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drm/amdgpu: give a fence param to ib_free
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cik_sdma.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
74a5d165
JX		 36#include "gca/gfx_7_2_enum.h"
37#include "gca/gfx_7_2_sh_mask.h"
a2e73f56
AD		 38
39#include "gmc/gmc_7_1_d.h"
40#include "gmc/gmc_7_1_sh_mask.h"
41
42#include "oss/oss_2_0_d.h"
43#include "oss/oss_2_0_sh_mask.h"
44
45static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
46{
47 SDMA0_REGISTER_OFFSET,
48 SDMA1_REGISTER_OFFSET
49};
50
51static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55
56MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
66
67u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
68
69/*
70 * sDMA - System DMA
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
76 *
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
83 * buffers.
84 */
85
86/**
87 * cik_sdma_init_microcode - load ucode images from disk
88 *
89 * @adev: amdgpu_device pointer
90 *
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
94 */
95static int cik_sdma_init_microcode(struct amdgpu_device *adev)
96{
97 const char *chip_name;
98 char fw_name[30];
c113ea1c 99 int err = 0, i;
a2e73f56
AD		 100
101 DRM_DEBUG("\n");
102
103 switch (adev->asic_type) {
104 case CHIP_BONAIRE:
105 chip_name = "bonaire";
106 break;
107 case CHIP_HAWAII:
108 chip_name = "hawaii";
109 break;
110 case CHIP_KAVERI:
111 chip_name = "kaveri";
112 break;
113 case CHIP_KABINI:
114 chip_name = "kabini";
115 break;
116 case CHIP_MULLINS:
117 chip_name = "mullins";
118 break;
119 default: BUG();
120 }
121
c113ea1c 122 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 123 if (i == 0)
124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
125 else
126 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
c113ea1c 127 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
a2e73f56
AD		 128 if (err)
129 goto out;
c113ea1c 130 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
a2e73f56
AD		 131 }
132out:
133 if (err) {
134 printk(KERN_ERR
135 "cik_sdma: Failed to load firmware \"%s\"\n",
136 fw_name);
c113ea1c
AD		 137 for (i = 0; i < adev->sdma.num_instances; i++) {
138 release_firmware(adev->sdma.instance[i].fw);
139 adev->sdma.instance[i].fw = NULL;
a2e73f56
AD		 140 }
141 }
142 return err;
143}
144
145/**
146 * cik_sdma_ring_get_rptr - get the current read pointer
147 *
148 * @ring: amdgpu ring pointer
149 *
150 * Get the current rptr from the hardware (CIK+).
151 */
152static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
153{
154 u32 rptr;
155
156 rptr = ring->adev->wb.wb[ring->rptr_offs];
157
158 return (rptr & 0x3fffc) >> 2;
159}
160
161/**
162 * cik_sdma_ring_get_wptr - get the current write pointer
163 *
164 * @ring: amdgpu ring pointer
165 *
166 * Get the current wptr from the hardware (CIK+).
167 */
168static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
169{
170 struct amdgpu_device *adev = ring->adev;
c113ea1c 171 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
a2e73f56
AD		 172
173 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
174}
175
176/**
177 * cik_sdma_ring_set_wptr - commit the write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Write the wptr back to the hardware (CIK+).
182 */
183static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
184{
185 struct amdgpu_device *adev = ring->adev;
c113ea1c 186 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
a2e73f56
AD		 187
188 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
189}
190
ac01db3d
JZ		 191static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
192{
c113ea1c 193 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ		 194 int i;
195
196 for (i = 0; i < count; i++)
197 if (sdma && sdma->burst_nop && (i == 0))
198 amdgpu_ring_write(ring, ring->nop |
199 SDMA_NOP_COUNT(count - 1));
200 else
201 amdgpu_ring_write(ring, ring->nop);
202}
203
a2e73f56
AD		 204/**
205 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
206 *
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
209 *
210 * Schedule an IB in the DMA ring (CIK).
211 */
212static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
213 struct amdgpu_ib *ib)
214{
4ff37a83 215 u32 extra_bits = ib->vm_id & 0xf;
a2e73f56
AD		 216 u32 next_rptr = ring->wptr + 5;
217
a2e73f56
AD		 218 while ((next_rptr & 7) != 4)
219 next_rptr++;
220
221 next_rptr += 4;
222 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
223 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
224 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
225 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
226 amdgpu_ring_write(ring, next_rptr);
227
a2e73f56 228 /* IB packet must end on a 8 DW boundary */
ac01db3d
JZ		 229 cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
230
a2e73f56
AD		 231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
234 amdgpu_ring_write(ring, ib->length_dw);
235
236}
237
238/**
d2edb07b 239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
a2e73f56
AD		 240 *
241 * @ring: amdgpu ring pointer
242 *
243 * Emit an hdp flush packet on the requested DMA ring.
244 */
d2edb07b 245static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 246{
247 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
249 u32 ref_and_mask;
250
c113ea1c 251 if (ring == &ring->adev->sdma.instance[0].ring)
a2e73f56
AD		 252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
253 else
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
255
256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */
261 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
262}
263
498dd97d
CZ		 264static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
265{
266 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
267 amdgpu_ring_write(ring, mmHDP_DEBUG0);
268 amdgpu_ring_write(ring, 1);
269}
270
a2e73f56
AD		 271/**
272 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
273 *
274 * @ring: amdgpu ring pointer
275 * @fence: amdgpu fence object
276 *
277 * Add a DMA fence packet to the ring to write
278 * the fence seq number and DMA trap packet to generate
279 * an interrupt if needed (CIK).
280 */
281static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 282 unsigned flags)
a2e73f56 283{
890ee23f 284 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
a2e73f56
AD		 285 /* write the fence */
286 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
287 amdgpu_ring_write(ring, lower_32_bits(addr));
288 amdgpu_ring_write(ring, upper_32_bits(addr));
289 amdgpu_ring_write(ring, lower_32_bits(seq));
290
291 /* optionally write high bits as well */
292 if (write64bit) {
293 addr += 4;
294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
295 amdgpu_ring_write(ring, lower_32_bits(addr));
296 amdgpu_ring_write(ring, upper_32_bits(addr));
297 amdgpu_ring_write(ring, upper_32_bits(seq));
298 }
299
300 /* generate an interrupt */
301 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
302}
303
a2e73f56
AD		 304/**
305 * cik_sdma_gfx_stop - stop the gfx async dma engines
306 *
307 * @adev: amdgpu_device pointer
308 *
309 * Stop the gfx async dma ring buffers (CIK).
310 */
311static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
312{
c113ea1c
AD		 313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
a2e73f56
AD		 315 u32 rb_cntl;
316 int i;
317
318 if ((adev->mman.buffer_funcs_ring == sdma0) ||
319 (adev->mman.buffer_funcs_ring == sdma1))
320 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
321
c113ea1c 322 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
324 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
327 }
328 sdma0->ready = false;
329 sdma1->ready = false;
330}
331
332/**
333 * cik_sdma_rlc_stop - stop the compute async dma engines
334 *
335 * @adev: amdgpu_device pointer
336 *
337 * Stop the compute async dma queues (CIK).
338 */
339static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
340{
341 /* XXX todo */
342}
343
344/**
345 * cik_sdma_enable - stop the async dma engines
346 *
347 * @adev: amdgpu_device pointer
348 * @enable: enable/disable the DMA MEs.
349 *
350 * Halt or unhalt the async dma engines (CIK).
351 */
352static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
353{
354 u32 me_cntl;
355 int i;
356
357 if (enable == false) {
358 cik_sdma_gfx_stop(adev);
359 cik_sdma_rlc_stop(adev);
360 }
361
c113ea1c 362 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 363 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
364 if (enable)
365 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
366 else
367 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
368 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
369 }
370}
371
372/**
373 * cik_sdma_gfx_resume - setup and start the async dma engines
374 *
375 * @adev: amdgpu_device pointer
376 *
377 * Set up the gfx DMA ring buffers and enable them (CIK).
378 * Returns 0 for success, error for failure.
379 */
380static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
381{
382 struct amdgpu_ring *ring;
383 u32 rb_cntl, ib_cntl;
384 u32 rb_bufsz;
385 u32 wb_offset;
386 int i, j, r;
387
c113ea1c
AD		 388 for (i = 0; i < adev->sdma.num_instances; i++) {
389 ring = &adev->sdma.instance[i].ring;
a2e73f56
AD		 390 wb_offset = (ring->rptr_offs * 4);
391
392 mutex_lock(&adev->srbm_mutex);
393 for (j = 0; j < 16; j++) {
394 cik_srbm_select(adev, 0, 0, 0, j);
395 /* SDMA GFX */
396 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
397 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
398 /* XXX SDMA RLC - todo */
399 }
400 cik_srbm_select(adev, 0, 0, 0, 0);
401 mutex_unlock(&adev->srbm_mutex);
402
2b3a765d
AD		 403 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
404 adev->gfx.config.gb_addr_config & 0x70);
405
a2e73f56
AD		 406 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
407 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
408
409 /* Set ring buffer size in dwords */
410 rb_bufsz = order_base_2(ring->ring_size / 4);
411 rb_cntl = rb_bufsz << 1;
412#ifdef __BIG_ENDIAN
454fc95e
AD		 413 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
414 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
a2e73f56
AD		 415#endif
416 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
417
418 /* Initialize the ring buffer's read and write pointers */
419 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
420 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
421
422 /* set the wb address whether it's enabled or not */
423 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
424 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
425 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
426 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
427
428 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
429
430 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
431 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
432
433 ring->wptr = 0;
434 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
435
436 /* enable DMA RB */
437 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
438 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
439
440 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
441#ifdef __BIG_ENDIAN
442 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
443#endif
444 /* enable DMA IBs */
445 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
446
447 ring->ready = true;
448
449 r = amdgpu_ring_test_ring(ring);
450 if (r) {
451 ring->ready = false;
452 return r;
453 }
454
455 if (adev->mman.buffer_funcs_ring == ring)
456 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
457 }
458
459 return 0;
460}
461
462/**
463 * cik_sdma_rlc_resume - setup and start the async dma engines
464 *
465 * @adev: amdgpu_device pointer
466 *
467 * Set up the compute DMA queues and enable them (CIK).
468 * Returns 0 for success, error for failure.
469 */
470static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
471{
472 /* XXX todo */
473 return 0;
474}
475
476/**
477 * cik_sdma_load_microcode - load the sDMA ME ucode
478 *
479 * @adev: amdgpu_device pointer
480 *
481 * Loads the sDMA0/1 ucode.
482 * Returns 0 for success, -EINVAL if the ucode is not available.
483 */
484static int cik_sdma_load_microcode(struct amdgpu_device *adev)
485{
486 const struct sdma_firmware_header_v1_0 *hdr;
487 const __le32 *fw_data;
488 u32 fw_size;
489 int i, j;
490
a2e73f56
AD		 491 /* halt the MEs */
492 cik_sdma_enable(adev, false);
493
c113ea1c
AD		 494 for (i = 0; i < adev->sdma.num_instances; i++) {
495 if (!adev->sdma.instance[i].fw)
496 return -EINVAL;
497 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
a2e73f56
AD		 498 amdgpu_ucode_print_sdma_hdr(&hdr->header);
499 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
c113ea1c
AD		 500 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
501 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
502 if (adev->sdma.instance[i].feature_version >= 20)
503 adev->sdma.instance[i].burst_nop = true;
a2e73f56 504 fw_data = (const __le32 *)
c113ea1c 505 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
a2e73f56
AD		 506 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
507 for (j = 0; j < fw_size; j++)
508 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
c113ea1c 509 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
a2e73f56
AD		 510 }
511
512 return 0;
513}
514
515/**
516 * cik_sdma_start - setup and start the async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Set up the DMA engines and enable them (CIK).
521 * Returns 0 for success, error for failure.
522 */
523static int cik_sdma_start(struct amdgpu_device *adev)
524{
525 int r;
526
527 r = cik_sdma_load_microcode(adev);
528 if (r)
529 return r;
530
531 /* unhalt the MEs */
532 cik_sdma_enable(adev, true);
533
534 /* start the gfx rings and rlc compute queues */
535 r = cik_sdma_gfx_resume(adev);
536 if (r)
537 return r;
538 r = cik_sdma_rlc_resume(adev);
539 if (r)
540 return r;
541
542 return 0;
543}
544
545/**
546 * cik_sdma_ring_test_ring - simple async dma engine test
547 *
548 * @ring: amdgpu_ring structure holding ring information
549 *
550 * Test the DMA engine by writing using it to write an
551 * value to memory. (CIK).
552 * Returns 0 for success, error for failure.
553 */
554static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
555{
556 struct amdgpu_device *adev = ring->adev;
557 unsigned i;
558 unsigned index;
559 int r;
560 u32 tmp;
561 u64 gpu_addr;
562
563 r = amdgpu_wb_get(adev, &index);
564 if (r) {
565 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
566 return r;
567 }
568
569 gpu_addr = adev->wb.gpu_addr + (index * 4);
570 tmp = 0xCAFEDEAD;
571 adev->wb.wb[index] = cpu_to_le32(tmp);
572
a27de35c 573 r = amdgpu_ring_alloc(ring, 5);
a2e73f56
AD		 574 if (r) {
575 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
576 amdgpu_wb_free(adev, index);
577 return r;
578 }
579 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
580 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
581 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
582 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
583 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 584 amdgpu_ring_commit(ring);
a2e73f56
AD		 585
586 for (i = 0; i < adev->usec_timeout; i++) {
587 tmp = le32_to_cpu(adev->wb.wb[index]);
588 if (tmp == 0xDEADBEEF)
589 break;
590 DRM_UDELAY(1);
591 }
592
593 if (i < adev->usec_timeout) {
594 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
595 } else {
596 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
597 ring->idx, tmp);
598 r = -EINVAL;
599 }
600 amdgpu_wb_free(adev, index);
601
602 return r;
603}
604
605/**
606 * cik_sdma_ring_test_ib - test an IB on the DMA engine
607 *
608 * @ring: amdgpu_ring structure holding ring information
609 *
610 * Test a simple IB in the DMA ring (CIK).
611 * Returns 0 on success, error on failure.
612 */
613static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
614{
615 struct amdgpu_device *adev = ring->adev;
616 struct amdgpu_ib ib;
1763552e 617 struct fence *f = NULL;
a2e73f56
AD		 618 unsigned i;
619 unsigned index;
620 int r;
621 u32 tmp = 0;
622 u64 gpu_addr;
623
624 r = amdgpu_wb_get(adev, &index);
625 if (r) {
626 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
627 return r;
628 }
629
630 gpu_addr = adev->wb.gpu_addr + (index * 4);
631 tmp = 0xCAFEDEAD;
632 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 633 memset(&ib, 0, sizeof(ib));
b07c60c0 634 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56 635 if (r) {
a2e73f56 636 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
0011fdaa 637 goto err0;
a2e73f56
AD		 638 }
639
640 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
641 ib.ptr[1] = lower_32_bits(gpu_addr);
642 ib.ptr[2] = upper_32_bits(gpu_addr);
643 ib.ptr[3] = 1;
644 ib.ptr[4] = 0xDEADBEEF;
645 ib.length_dw = 5;
336d1f5e 646 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
0011fdaa
CZ		 647 if (r)
648 goto err1;
a2e73f56 649
1763552e 650 r = fence_wait(f, false);
a2e73f56 651 if (r) {
a2e73f56 652 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
0011fdaa 653 goto err1;
a2e73f56
AD		 654 }
655 for (i = 0; i < adev->usec_timeout; i++) {
656 tmp = le32_to_cpu(adev->wb.wb[index]);
657 if (tmp == 0xDEADBEEF)
658 break;
659 DRM_UDELAY(1);
660 }
661 if (i < adev->usec_timeout) {
662 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
0011fdaa
CZ		 663 ring->idx, i);
664 goto err1;
a2e73f56
AD		 665 } else {
666 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
667 r = -EINVAL;
668 }
0011fdaa
CZ		 669
670err1:
281b4223 671 fence_put(f);
cc55c45d 672 amdgpu_ib_free(adev, &ib, NULL);
0011fdaa 673err0:
a2e73f56
AD		 674 amdgpu_wb_free(adev, index);
675 return r;
676}
677
678/**
679 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
680 *
681 * @ib: indirect buffer to fill with commands
682 * @pe: addr of the page entry
683 * @src: src addr to copy from
684 * @count: number of page entries to update
685 *
686 * Update PTEs by copying them from the GART using sDMA (CIK).
687 */
688static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
689 uint64_t pe, uint64_t src,
690 unsigned count)
691{
692 while (count) {
693 unsigned bytes = count * 8;
694 if (bytes > 0x1FFFF8)
695 bytes = 0x1FFFF8;
696
697 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
698 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
699 ib->ptr[ib->length_dw++] = bytes;
700 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
701 ib->ptr[ib->length_dw++] = lower_32_bits(src);
702 ib->ptr[ib->length_dw++] = upper_32_bits(src);
703 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
704 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
705
706 pe += bytes;
707 src += bytes;
708 count -= bytes / 8;
709 }
710}
711
712/**
713 * cik_sdma_vm_write_pages - update PTEs by writing them manually
714 *
715 * @ib: indirect buffer to fill with commands
716 * @pe: addr of the page entry
717 * @addr: dst addr to write into pe
718 * @count: number of page entries to update
719 * @incr: increase next addr by incr bytes
720 * @flags: access flags
721 *
722 * Update PTEs by writing them manually using sDMA (CIK).
723 */
724static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
b07c9d2a 725 const dma_addr_t *pages_addr, uint64_t pe,
a2e73f56
AD		 726 uint64_t addr, unsigned count,
727 uint32_t incr, uint32_t flags)
728{
729 uint64_t value;
730 unsigned ndw;
731
732 while (count) {
733 ndw = count * 2;
734 if (ndw > 0xFFFFE)
735 ndw = 0xFFFFE;
736
737 /* for non-physically contiguous pages (system) */
738 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
739 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
740 ib->ptr[ib->length_dw++] = pe;
741 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
742 ib->ptr[ib->length_dw++] = ndw;
743 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
b07c9d2a 744 value = amdgpu_vm_map_gart(pages_addr, addr);
a2e73f56
AD		 745 addr += incr;
746 value |= flags;
747 ib->ptr[ib->length_dw++] = value;
748 ib->ptr[ib->length_dw++] = upper_32_bits(value);
749 }
750 }
751}
752
753/**
754 * cik_sdma_vm_set_pages - update the page tables using sDMA
755 *
756 * @ib: indirect buffer to fill with commands
757 * @pe: addr of the page entry
758 * @addr: dst addr to write into pe
759 * @count: number of page entries to update
760 * @incr: increase next addr by incr bytes
761 * @flags: access flags
762 *
763 * Update the page tables using sDMA (CIK).
764 */
765static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
766 uint64_t pe,
767 uint64_t addr, unsigned count,
768 uint32_t incr, uint32_t flags)
769{
770 uint64_t value;
771 unsigned ndw;
772
773 while (count) {
774 ndw = count;
775 if (ndw > 0x7FFFF)
776 ndw = 0x7FFFF;
777
778 if (flags & AMDGPU_PTE_VALID)
779 value = addr;
780 else
781 value = 0;
782
783 /* for physically contiguous pages (vram) */
784 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
785 ib->ptr[ib->length_dw++] = pe; /* dst addr */
786 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
787 ib->ptr[ib->length_dw++] = flags; /* mask */
788 ib->ptr[ib->length_dw++] = 0;
789 ib->ptr[ib->length_dw++] = value; /* value */
790 ib->ptr[ib->length_dw++] = upper_32_bits(value);
791 ib->ptr[ib->length_dw++] = incr; /* increment size */
792 ib->ptr[ib->length_dw++] = 0;
793 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
794
795 pe += ndw * 8;
796 addr += ndw * incr;
797 count -= ndw;
798 }
799}
800
801/**
802 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
803 *
804 * @ib: indirect buffer to fill with padding
805 *
806 */
9e5d5309 807static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
a2e73f56 808{
9e5d5309 809 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ		 810 u32 pad_count;
811 int i;
812
813 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
814 for (i = 0; i < pad_count; i++)
815 if (sdma && sdma->burst_nop && (i == 0))
816 ib->ptr[ib->length_dw++] =
817 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
818 SDMA_NOP_COUNT(pad_count - 1);
819 else
820 ib->ptr[ib->length_dw++] =
821 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
a2e73f56
AD		 822}
823
824/**
00b7c4ff 825 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
a2e73f56
AD		 826 *
827 * @ring: amdgpu_ring pointer
a2e73f56 828 *
00b7c4ff 829 * Make sure all previous operations are completed (CIK).
a2e73f56 830 */
00b7c4ff 831static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
a2e73f56 832{
5c55db83
CZ		 833 uint32_t seq = ring->fence_drv.sync_seq;
834 uint64_t addr = ring->fence_drv.gpu_addr;
835
836 /* wait for idle */
837 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
838 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
839 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
840 SDMA_POLL_REG_MEM_EXTRA_M));
841 amdgpu_ring_write(ring, addr & 0xfffffffc);
842 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
843 amdgpu_ring_write(ring, seq); /* reference */
844 amdgpu_ring_write(ring, 0xfffffff); /* mask */
845 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
00b7c4ff 846}
5c55db83 847
00b7c4ff
CK		 848/**
849 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
850 *
851 * @ring: amdgpu_ring pointer
852 * @vm: amdgpu_vm pointer
853 *
854 * Update the page table base and flush the VM TLB
855 * using sDMA (CIK).
856 */
857static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
858 unsigned vm_id, uint64_t pd_addr)
859{
860 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
861 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
a2e73f56
AD		 862
863 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
864 if (vm_id < 8) {
865 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
866 } else {
867 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
868 }
869 amdgpu_ring_write(ring, pd_addr >> 12);
870
a2e73f56
AD		 871 /* flush TLB */
872 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
873 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
874 amdgpu_ring_write(ring, 1 << vm_id);
875
876 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
877 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
878 amdgpu_ring_write(ring, 0);
879 amdgpu_ring_write(ring, 0); /* reference */
880 amdgpu_ring_write(ring, 0); /* mask */
881 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
882}
883
884static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
885 bool enable)
886{
887 u32 orig, data;
888
889 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
890 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
891 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
892 } else {
893 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
894 data |= 0xff000000;
895 if (data != orig)
896 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
897
898 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
899 data |= 0xff000000;
900 if (data != orig)
901 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
902 }
903}
904
905static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
906 bool enable)
907{
908 u32 orig, data;
909
910 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
911 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
912 data |= 0x100;
913 if (orig != data)
914 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
915
916 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
917 data |= 0x100;
918 if (orig != data)
919 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
920 } else {
921 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
922 data &= ~0x100;
923 if (orig != data)
924 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
925
926 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
927 data &= ~0x100;
928 if (orig != data)
929 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
930 }
931}
932
5fc3aeeb 933static int cik_sdma_early_init(void *handle)
a2e73f56 934{
5fc3aeeb 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
936
c113ea1c
AD		 937 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
938
a2e73f56
AD		 939 cik_sdma_set_ring_funcs(adev);
940 cik_sdma_set_irq_funcs(adev);
941 cik_sdma_set_buffer_funcs(adev);
942 cik_sdma_set_vm_pte_funcs(adev);
943
944 return 0;
945}
946
5fc3aeeb 947static int cik_sdma_sw_init(void *handle)
a2e73f56
AD		 948{
949 struct amdgpu_ring *ring;
5fc3aeeb 950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 951 int r, i;
a2e73f56
AD		 952
953 r = cik_sdma_init_microcode(adev);
954 if (r) {
955 DRM_ERROR("Failed to load sdma firmware!\n");
956 return r;
957 }
958
959 /* SDMA trap event */
c113ea1c 960 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
a2e73f56
AD		 961 if (r)
962 return r;
963
964 /* SDMA Privileged inst */
c113ea1c 965 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
a2e73f56
AD		 966 if (r)
967 return r;
968
969 /* SDMA Privileged inst */
c113ea1c 970 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
a2e73f56
AD		 971 if (r)
972 return r;
973
c113ea1c
AD		 974 for (i = 0; i < adev->sdma.num_instances; i++) {
975 ring = &adev->sdma.instance[i].ring;
976 ring->ring_obj = NULL;
977 sprintf(ring->name, "sdma%d", i);
978 r = amdgpu_ring_init(adev, ring, 256 * 1024,
979 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
980 &adev->sdma.trap_irq,
981 (i == 0) ?
982 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
983 AMDGPU_RING_TYPE_SDMA);
984 if (r)
985 return r;
986 }
a2e73f56
AD		 987
988 return r;
989}
990
5fc3aeeb 991static int cik_sdma_sw_fini(void *handle)
a2e73f56 992{
5fc3aeeb 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 994 int i;
5fc3aeeb 995
c113ea1c
AD		 996 for (i = 0; i < adev->sdma.num_instances; i++)
997 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
a2e73f56
AD		 998
999 return 0;
1000}
1001
5fc3aeeb 1002static int cik_sdma_hw_init(void *handle)
a2e73f56
AD		 1003{
1004 int r;
5fc3aeeb 1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1006
1007 r = cik_sdma_start(adev);
1008 if (r)
1009 return r;
1010
1011 return r;
1012}
1013
5fc3aeeb 1014static int cik_sdma_hw_fini(void *handle)
a2e73f56 1015{
5fc3aeeb 1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
a2e73f56
AD		 1018 cik_sdma_enable(adev, false);
1019
1020 return 0;
1021}
1022
5fc3aeeb 1023static int cik_sdma_suspend(void *handle)
a2e73f56 1024{
5fc3aeeb 1025 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1026
1027 return cik_sdma_hw_fini(adev);
1028}
1029
5fc3aeeb 1030static int cik_sdma_resume(void *handle)
a2e73f56 1031{
5fc3aeeb 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1033
1034 return cik_sdma_hw_init(adev);
1035}
1036
5fc3aeeb 1037static bool cik_sdma_is_idle(void *handle)
a2e73f56 1038{
5fc3aeeb 1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1040 u32 tmp = RREG32(mmSRBM_STATUS2);
1041
1042 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1043 SRBM_STATUS2__SDMA1_BUSY_MASK))
1044 return false;
1045
1046 return true;
1047}
1048
5fc3aeeb 1049static int cik_sdma_wait_for_idle(void *handle)
a2e73f56
AD		 1050{
1051 unsigned i;
1052 u32 tmp;
5fc3aeeb 1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1054
1055 for (i = 0; i < adev->usec_timeout; i++) {
1056 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1057 SRBM_STATUS2__SDMA1_BUSY_MASK);
1058
1059 if (!tmp)
1060 return 0;
1061 udelay(1);
1062 }
1063 return -ETIMEDOUT;
1064}
1065
5fc3aeeb 1066static void cik_sdma_print_status(void *handle)
a2e73f56
AD		 1067{
1068 int i, j;
5fc3aeeb 1069 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1070
1071 dev_info(adev->dev, "CIK SDMA registers\n");
1072 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1073 RREG32(mmSRBM_STATUS2));
c113ea1c 1074 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 1075 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1076 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1077 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1078 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1079 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1080 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1081 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1082 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1083 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1084 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1085 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1086 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1087 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1088 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1089 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1090 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1091 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1092 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1093 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1094 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1095 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1096 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1097 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1098 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1099 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1100 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
2b3a765d
AD		 1101 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
1102 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
a2e73f56
AD		 1103 mutex_lock(&adev->srbm_mutex);
1104 for (j = 0; j < 16; j++) {
1105 cik_srbm_select(adev, 0, 0, 0, j);
1106 dev_info(adev->dev, " VM %d:\n", j);
1107 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1108 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1109 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1110 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1111 }
1112 cik_srbm_select(adev, 0, 0, 0, 0);
1113 mutex_unlock(&adev->srbm_mutex);
1114 }
1115}
1116
5fc3aeeb 1117static int cik_sdma_soft_reset(void *handle)
a2e73f56
AD		 1118{
1119 u32 srbm_soft_reset = 0;
5fc3aeeb 1120 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1121 u32 tmp = RREG32(mmSRBM_STATUS2);
1122
1123 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1124 /* sdma0 */
1125 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1126 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1127 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1128 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1129 }
1130 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1131 /* sdma1 */
1132 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1133 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1134 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1135 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1136 }
1137
1138 if (srbm_soft_reset) {
5fc3aeeb 1139 cik_sdma_print_status((void *)adev);
a2e73f56
AD		 1140
1141 tmp = RREG32(mmSRBM_SOFT_RESET);
1142 tmp |= srbm_soft_reset;
1143 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1144 WREG32(mmSRBM_SOFT_RESET, tmp);
1145 tmp = RREG32(mmSRBM_SOFT_RESET);
1146
1147 udelay(50);
1148
1149 tmp &= ~srbm_soft_reset;
1150 WREG32(mmSRBM_SOFT_RESET, tmp);
1151 tmp = RREG32(mmSRBM_SOFT_RESET);
1152
1153 /* Wait a little for things to settle down */
1154 udelay(50);
1155
5fc3aeeb 1156 cik_sdma_print_status((void *)adev);
a2e73f56
AD		 1157 }
1158
1159 return 0;
1160}
1161
1162static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1163 struct amdgpu_irq_src *src,
1164 unsigned type,
1165 enum amdgpu_interrupt_state state)
1166{
1167 u32 sdma_cntl;
1168
1169 switch (type) {
1170 case AMDGPU_SDMA_IRQ_TRAP0:
1171 switch (state) {
1172 case AMDGPU_IRQ_STATE_DISABLE:
1173 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1174 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1175 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1176 break;
1177 case AMDGPU_IRQ_STATE_ENABLE:
1178 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1179 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1180 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1181 break;
1182 default:
1183 break;
1184 }
1185 break;
1186 case AMDGPU_SDMA_IRQ_TRAP1:
1187 switch (state) {
1188 case AMDGPU_IRQ_STATE_DISABLE:
1189 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1190 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1191 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1192 break;
1193 case AMDGPU_IRQ_STATE_ENABLE:
1194 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1195 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1196 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1197 break;
1198 default:
1199 break;
1200 }
1201 break;
1202 default:
1203 break;
1204 }
1205 return 0;
1206}
1207
1208static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1209 struct amdgpu_irq_src *source,
1210 struct amdgpu_iv_entry *entry)
1211{
1212 u8 instance_id, queue_id;
1213
1214 instance_id = (entry->ring_id & 0x3) >> 0;
1215 queue_id = (entry->ring_id & 0xc) >> 2;
1216 DRM_DEBUG("IH: SDMA trap\n");
1217 switch (instance_id) {
1218 case 0:
1219 switch (queue_id) {
1220 case 0:
c113ea1c 1221 amdgpu_fence_process(&adev->sdma.instance[0].ring);
a2e73f56
AD		 1222 break;
1223 case 1:
1224 /* XXX compute */
1225 break;
1226 case 2:
1227 /* XXX compute */
1228 break;
1229 }
1230 break;
1231 case 1:
1232 switch (queue_id) {
1233 case 0:
c113ea1c 1234 amdgpu_fence_process(&adev->sdma.instance[1].ring);
a2e73f56
AD		 1235 break;
1236 case 1:
1237 /* XXX compute */
1238 break;
1239 case 2:
1240 /* XXX compute */
1241 break;
1242 }
1243 break;
1244 }
1245
1246 return 0;
1247}
1248
1249static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1250 struct amdgpu_irq_src *source,
1251 struct amdgpu_iv_entry *entry)
1252{
1253 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1254 schedule_work(&adev->reset_work);
1255 return 0;
1256}
1257
5fc3aeeb 1258static int cik_sdma_set_clockgating_state(void *handle,
1259 enum amd_clockgating_state state)
a2e73f56
AD		 1260{
1261 bool gate = false;
5fc3aeeb 1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 1263
5fc3aeeb 1264 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 1265 gate = true;
1266
1267 cik_enable_sdma_mgcg(adev, gate);
1268 cik_enable_sdma_mgls(adev, gate);
1269
1270 return 0;
1271}
1272
5fc3aeeb 1273static int cik_sdma_set_powergating_state(void *handle,
1274 enum amd_powergating_state state)
a2e73f56
AD		 1275{
1276 return 0;
1277}
1278
5fc3aeeb 1279const struct amd_ip_funcs cik_sdma_ip_funcs = {
a2e73f56
AD		 1280 .early_init = cik_sdma_early_init,
1281 .late_init = NULL,
1282 .sw_init = cik_sdma_sw_init,
1283 .sw_fini = cik_sdma_sw_fini,
1284 .hw_init = cik_sdma_hw_init,
1285 .hw_fini = cik_sdma_hw_fini,
1286 .suspend = cik_sdma_suspend,
1287 .resume = cik_sdma_resume,
1288 .is_idle = cik_sdma_is_idle,
1289 .wait_for_idle = cik_sdma_wait_for_idle,
1290 .soft_reset = cik_sdma_soft_reset,
1291 .print_status = cik_sdma_print_status,
1292 .set_clockgating_state = cik_sdma_set_clockgating_state,
1293 .set_powergating_state = cik_sdma_set_powergating_state,
1294};
1295
a2e73f56
AD		 1296static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1297 .get_rptr = cik_sdma_ring_get_rptr,
1298 .get_wptr = cik_sdma_ring_get_wptr,
1299 .set_wptr = cik_sdma_ring_set_wptr,
1300 .parse_cs = NULL,
1301 .emit_ib = cik_sdma_ring_emit_ib,
1302 .emit_fence = cik_sdma_ring_emit_fence,
00b7c4ff 1303 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
a2e73f56 1304 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
d2edb07b 1305 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
498dd97d 1306 .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
a2e73f56
AD		 1307 .test_ring = cik_sdma_ring_test_ring,
1308 .test_ib = cik_sdma_ring_test_ib,
ac01db3d 1309 .insert_nop = cik_sdma_ring_insert_nop,
9e5d5309 1310 .pad_ib = cik_sdma_ring_pad_ib,
a2e73f56
AD		 1311};
1312
1313static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1314{
c113ea1c
AD		 1315 int i;
1316
1317 for (i = 0; i < adev->sdma.num_instances; i++)
1318 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
a2e73f56
AD		 1319}
1320
1321static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1322 .set = cik_sdma_set_trap_irq_state,
1323 .process = cik_sdma_process_trap_irq,
1324};
1325
1326static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1327 .process = cik_sdma_process_illegal_inst_irq,
1328};
1329
1330static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1331{
c113ea1c
AD		 1332 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1333 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1334 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
a2e73f56
AD		 1335}
1336
1337/**
1338 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1339 *
1340 * @ring: amdgpu_ring structure holding ring information
1341 * @src_offset: src GPU address
1342 * @dst_offset: dst GPU address
1343 * @byte_count: number of bytes to xfer
1344 *
1345 * Copy GPU buffers using the DMA engine (CIK).
1346 * Used by the amdgpu ttm implementation to move pages if
1347 * registered as the asic copy callback.
1348 */
c7ae72c0 1349static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
a2e73f56
AD		 1350 uint64_t src_offset,
1351 uint64_t dst_offset,
1352 uint32_t byte_count)
1353{
c7ae72c0
CZ		 1354 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1355 ib->ptr[ib->length_dw++] = byte_count;
1356 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1357 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1358 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1359 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1360 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
a2e73f56
AD		 1361}
1362
1363/**
1364 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1365 *
1366 * @ring: amdgpu_ring structure holding ring information
1367 * @src_data: value to write to buffer
1368 * @dst_offset: dst GPU address
1369 * @byte_count: number of bytes to xfer
1370 *
1371 * Fill GPU buffers using the DMA engine (CIK).
1372 */
6e7a3840 1373static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
a2e73f56
AD		 1374 uint32_t src_data,
1375 uint64_t dst_offset,
1376 uint32_t byte_count)
1377{
6e7a3840
CZ		 1378 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1379 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1380 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1381 ib->ptr[ib->length_dw++] = src_data;
1382 ib->ptr[ib->length_dw++] = byte_count;
a2e73f56
AD		 1383}
1384
1385static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1386 .copy_max_bytes = 0x1fffff,
1387 .copy_num_dw = 7,
1388 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1389
1390 .fill_max_bytes = 0x1fffff,
1391 .fill_num_dw = 5,
1392 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1393};
1394
1395static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1396{
1397 if (adev->mman.buffer_funcs == NULL) {
1398 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
c113ea1c 1399 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
a2e73f56
AD		 1400 }
1401}
1402
1403static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1404 .copy_pte = cik_sdma_vm_copy_pte,
1405 .write_pte = cik_sdma_vm_write_pte,
1406 .set_pte_pde = cik_sdma_vm_set_pte_pde,
a2e73f56
AD		 1407};
1408
1409static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1410{
2d55e45a
CK		 1411 unsigned i;
1412
a2e73f56
AD		 1413 if (adev->vm_manager.vm_pte_funcs == NULL) {
1414 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
2d55e45a
CK		 1415 for (i = 0; i < adev->sdma.num_instances; i++)
1416 adev->vm_manager.vm_pte_rings[i] =
1417 &adev->sdma.instance[i].ring;
1418
1419 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
a2e73f56
AD		 1420 }
1421}
Linux kernel - Deliverables
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