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a2e73f56 AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "cikd.h" | |
30 | #include "cik.h" | |
31 | ||
32 | #include "bif/bif_4_1_d.h" | |
33 | #include "bif/bif_4_1_sh_mask.h" | |
34 | ||
35 | #include "gca/gfx_7_2_d.h" | |
74a5d165 JX |
36 | #include "gca/gfx_7_2_enum.h" |
37 | #include "gca/gfx_7_2_sh_mask.h" | |
a2e73f56 AD |
38 | |
39 | #include "gmc/gmc_7_1_d.h" | |
40 | #include "gmc/gmc_7_1_sh_mask.h" | |
41 | ||
42 | #include "oss/oss_2_0_d.h" | |
43 | #include "oss/oss_2_0_sh_mask.h" | |
44 | ||
45 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
46 | { | |
47 | SDMA0_REGISTER_OFFSET, | |
48 | SDMA1_REGISTER_OFFSET | |
49 | }; | |
50 | ||
51 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); | |
52 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); | |
53 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); | |
54 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); | |
55 | ||
56 | MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); | |
57 | MODULE_FIRMWARE("radeon/bonaire_sdma1.bin"); | |
58 | MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); | |
59 | MODULE_FIRMWARE("radeon/hawaii_sdma1.bin"); | |
60 | MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); | |
61 | MODULE_FIRMWARE("radeon/kaveri_sdma1.bin"); | |
62 | MODULE_FIRMWARE("radeon/kabini_sdma.bin"); | |
63 | MODULE_FIRMWARE("radeon/kabini_sdma1.bin"); | |
64 | MODULE_FIRMWARE("radeon/mullins_sdma.bin"); | |
65 | MODULE_FIRMWARE("radeon/mullins_sdma1.bin"); | |
66 | ||
67 | u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); | |
68 | ||
69 | /* | |
70 | * sDMA - System DMA | |
71 | * Starting with CIK, the GPU has new asynchronous | |
72 | * DMA engines. These engines are used for compute | |
73 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
74 | * and each one supports 1 ring buffer used for gfx | |
75 | * and 2 queues used for compute. | |
76 | * | |
77 | * The programming model is very similar to the CP | |
78 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
79 | * packet format that is different from the PM4 format | |
80 | * used by the CP. sDMA supports copying data, writing | |
81 | * embedded data, solid fills, and a number of other | |
82 | * things. It also has support for tiling/detiling of | |
83 | * buffers. | |
84 | */ | |
85 | ||
86 | /** | |
87 | * cik_sdma_init_microcode - load ucode images from disk | |
88 | * | |
89 | * @adev: amdgpu_device pointer | |
90 | * | |
91 | * Use the firmware interface to load the ucode images into | |
92 | * the driver (not loaded into hw). | |
93 | * Returns 0 on success, error on failure. | |
94 | */ | |
95 | static int cik_sdma_init_microcode(struct amdgpu_device *adev) | |
96 | { | |
97 | const char *chip_name; | |
98 | char fw_name[30]; | |
c113ea1c | 99 | int err = 0, i; |
a2e73f56 AD |
100 | |
101 | DRM_DEBUG("\n"); | |
102 | ||
103 | switch (adev->asic_type) { | |
104 | case CHIP_BONAIRE: | |
105 | chip_name = "bonaire"; | |
106 | break; | |
107 | case CHIP_HAWAII: | |
108 | chip_name = "hawaii"; | |
109 | break; | |
110 | case CHIP_KAVERI: | |
111 | chip_name = "kaveri"; | |
112 | break; | |
113 | case CHIP_KABINI: | |
114 | chip_name = "kabini"; | |
115 | break; | |
116 | case CHIP_MULLINS: | |
117 | chip_name = "mullins"; | |
118 | break; | |
119 | default: BUG(); | |
120 | } | |
121 | ||
c113ea1c | 122 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
123 | if (i == 0) |
124 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); | |
125 | else | |
126 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); | |
c113ea1c | 127 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
a2e73f56 AD |
128 | if (err) |
129 | goto out; | |
c113ea1c | 130 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
a2e73f56 AD |
131 | } |
132 | out: | |
133 | if (err) { | |
134 | printk(KERN_ERR | |
135 | "cik_sdma: Failed to load firmware \"%s\"\n", | |
136 | fw_name); | |
c113ea1c AD |
137 | for (i = 0; i < adev->sdma.num_instances; i++) { |
138 | release_firmware(adev->sdma.instance[i].fw); | |
139 | adev->sdma.instance[i].fw = NULL; | |
a2e73f56 AD |
140 | } |
141 | } | |
142 | return err; | |
143 | } | |
144 | ||
145 | /** | |
146 | * cik_sdma_ring_get_rptr - get the current read pointer | |
147 | * | |
148 | * @ring: amdgpu ring pointer | |
149 | * | |
150 | * Get the current rptr from the hardware (CIK+). | |
151 | */ | |
152 | static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) | |
153 | { | |
154 | u32 rptr; | |
155 | ||
156 | rptr = ring->adev->wb.wb[ring->rptr_offs]; | |
157 | ||
158 | return (rptr & 0x3fffc) >> 2; | |
159 | } | |
160 | ||
161 | /** | |
162 | * cik_sdma_ring_get_wptr - get the current write pointer | |
163 | * | |
164 | * @ring: amdgpu ring pointer | |
165 | * | |
166 | * Get the current wptr from the hardware (CIK+). | |
167 | */ | |
168 | static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) | |
169 | { | |
170 | struct amdgpu_device *adev = ring->adev; | |
c113ea1c | 171 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
a2e73f56 AD |
172 | |
173 | return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; | |
174 | } | |
175 | ||
176 | /** | |
177 | * cik_sdma_ring_set_wptr - commit the write pointer | |
178 | * | |
179 | * @ring: amdgpu ring pointer | |
180 | * | |
181 | * Write the wptr back to the hardware (CIK+). | |
182 | */ | |
183 | static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) | |
184 | { | |
185 | struct amdgpu_device *adev = ring->adev; | |
c113ea1c | 186 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
a2e73f56 AD |
187 | |
188 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); | |
189 | } | |
190 | ||
ac01db3d JZ |
191 | static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
192 | { | |
c113ea1c | 193 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
194 | int i; |
195 | ||
196 | for (i = 0; i < count; i++) | |
197 | if (sdma && sdma->burst_nop && (i == 0)) | |
198 | amdgpu_ring_write(ring, ring->nop | | |
199 | SDMA_NOP_COUNT(count - 1)); | |
200 | else | |
201 | amdgpu_ring_write(ring, ring->nop); | |
202 | } | |
203 | ||
a2e73f56 AD |
204 | /** |
205 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine | |
206 | * | |
207 | * @ring: amdgpu ring pointer | |
208 | * @ib: IB object to schedule | |
209 | * | |
210 | * Schedule an IB in the DMA ring (CIK). | |
211 | */ | |
212 | static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |
213 | struct amdgpu_ib *ib) | |
214 | { | |
215 | u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; | |
216 | u32 next_rptr = ring->wptr + 5; | |
217 | ||
a2e73f56 AD |
218 | while ((next_rptr & 7) != 4) |
219 | next_rptr++; | |
220 | ||
221 | next_rptr += 4; | |
222 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
223 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
224 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | |
225 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | |
226 | amdgpu_ring_write(ring, next_rptr); | |
227 | ||
a2e73f56 | 228 | /* IB packet must end on a 8 DW boundary */ |
ac01db3d JZ |
229 | cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); |
230 | ||
a2e73f56 AD |
231 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); |
232 | amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ | |
233 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); | |
234 | amdgpu_ring_write(ring, ib->length_dw); | |
235 | ||
236 | } | |
237 | ||
238 | /** | |
d2edb07b | 239 | * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
a2e73f56 AD |
240 | * |
241 | * @ring: amdgpu ring pointer | |
242 | * | |
243 | * Emit an hdp flush packet on the requested DMA ring. | |
244 | */ | |
d2edb07b | 245 | static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
a2e73f56 AD |
246 | { |
247 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | | |
248 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | |
249 | u32 ref_and_mask; | |
250 | ||
c113ea1c | 251 | if (ring == &ring->adev->sdma.instance[0].ring) |
a2e73f56 AD |
252 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; |
253 | else | |
254 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; | |
255 | ||
256 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
257 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
258 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
259 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
260 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
261 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
262 | } | |
263 | ||
264 | /** | |
265 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring | |
266 | * | |
267 | * @ring: amdgpu ring pointer | |
268 | * @fence: amdgpu fence object | |
269 | * | |
270 | * Add a DMA fence packet to the ring to write | |
271 | * the fence seq number and DMA trap packet to generate | |
272 | * an interrupt if needed (CIK). | |
273 | */ | |
274 | static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 275 | unsigned flags) |
a2e73f56 | 276 | { |
890ee23f | 277 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
a2e73f56 AD |
278 | /* write the fence */ |
279 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
280 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
281 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
282 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
283 | ||
284 | /* optionally write high bits as well */ | |
285 | if (write64bit) { | |
286 | addr += 4; | |
287 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
288 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
289 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
290 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
291 | } | |
292 | ||
293 | /* generate an interrupt */ | |
294 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); | |
295 | } | |
296 | ||
a2e73f56 AD |
297 | /** |
298 | * cik_sdma_gfx_stop - stop the gfx async dma engines | |
299 | * | |
300 | * @adev: amdgpu_device pointer | |
301 | * | |
302 | * Stop the gfx async dma ring buffers (CIK). | |
303 | */ | |
304 | static void cik_sdma_gfx_stop(struct amdgpu_device *adev) | |
305 | { | |
c113ea1c AD |
306 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
307 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
a2e73f56 AD |
308 | u32 rb_cntl; |
309 | int i; | |
310 | ||
311 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
312 | (adev->mman.buffer_funcs_ring == sdma1)) | |
313 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
314 | ||
c113ea1c | 315 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
316 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
317 | rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; | |
318 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
319 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); | |
320 | } | |
321 | sdma0->ready = false; | |
322 | sdma1->ready = false; | |
323 | } | |
324 | ||
325 | /** | |
326 | * cik_sdma_rlc_stop - stop the compute async dma engines | |
327 | * | |
328 | * @adev: amdgpu_device pointer | |
329 | * | |
330 | * Stop the compute async dma queues (CIK). | |
331 | */ | |
332 | static void cik_sdma_rlc_stop(struct amdgpu_device *adev) | |
333 | { | |
334 | /* XXX todo */ | |
335 | } | |
336 | ||
337 | /** | |
338 | * cik_sdma_enable - stop the async dma engines | |
339 | * | |
340 | * @adev: amdgpu_device pointer | |
341 | * @enable: enable/disable the DMA MEs. | |
342 | * | |
343 | * Halt or unhalt the async dma engines (CIK). | |
344 | */ | |
345 | static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) | |
346 | { | |
347 | u32 me_cntl; | |
348 | int i; | |
349 | ||
350 | if (enable == false) { | |
351 | cik_sdma_gfx_stop(adev); | |
352 | cik_sdma_rlc_stop(adev); | |
353 | } | |
354 | ||
c113ea1c | 355 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
356 | me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
357 | if (enable) | |
358 | me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; | |
359 | else | |
360 | me_cntl |= SDMA0_F32_CNTL__HALT_MASK; | |
361 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); | |
362 | } | |
363 | } | |
364 | ||
365 | /** | |
366 | * cik_sdma_gfx_resume - setup and start the async dma engines | |
367 | * | |
368 | * @adev: amdgpu_device pointer | |
369 | * | |
370 | * Set up the gfx DMA ring buffers and enable them (CIK). | |
371 | * Returns 0 for success, error for failure. | |
372 | */ | |
373 | static int cik_sdma_gfx_resume(struct amdgpu_device *adev) | |
374 | { | |
375 | struct amdgpu_ring *ring; | |
376 | u32 rb_cntl, ib_cntl; | |
377 | u32 rb_bufsz; | |
378 | u32 wb_offset; | |
379 | int i, j, r; | |
380 | ||
c113ea1c AD |
381 | for (i = 0; i < adev->sdma.num_instances; i++) { |
382 | ring = &adev->sdma.instance[i].ring; | |
a2e73f56 AD |
383 | wb_offset = (ring->rptr_offs * 4); |
384 | ||
385 | mutex_lock(&adev->srbm_mutex); | |
386 | for (j = 0; j < 16; j++) { | |
387 | cik_srbm_select(adev, 0, 0, 0, j); | |
388 | /* SDMA GFX */ | |
389 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
390 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
391 | /* XXX SDMA RLC - todo */ | |
392 | } | |
393 | cik_srbm_select(adev, 0, 0, 0, 0); | |
394 | mutex_unlock(&adev->srbm_mutex); | |
395 | ||
396 | WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); | |
397 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); | |
398 | ||
399 | /* Set ring buffer size in dwords */ | |
400 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
401 | rb_cntl = rb_bufsz << 1; | |
402 | #ifdef __BIG_ENDIAN | |
454fc95e AD |
403 | rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | |
404 | SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; | |
a2e73f56 AD |
405 | #endif |
406 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
407 | ||
408 | /* Initialize the ring buffer's read and write pointers */ | |
409 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
410 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
411 | ||
412 | /* set the wb address whether it's enabled or not */ | |
413 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
414 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
415 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
416 | ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); | |
417 | ||
418 | rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; | |
419 | ||
420 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
421 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
422 | ||
423 | ring->wptr = 0; | |
424 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); | |
425 | ||
426 | /* enable DMA RB */ | |
427 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], | |
428 | rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); | |
429 | ||
430 | ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; | |
431 | #ifdef __BIG_ENDIAN | |
432 | ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; | |
433 | #endif | |
434 | /* enable DMA IBs */ | |
435 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
436 | ||
437 | ring->ready = true; | |
438 | ||
439 | r = amdgpu_ring_test_ring(ring); | |
440 | if (r) { | |
441 | ring->ready = false; | |
442 | return r; | |
443 | } | |
444 | ||
445 | if (adev->mman.buffer_funcs_ring == ring) | |
446 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /** | |
453 | * cik_sdma_rlc_resume - setup and start the async dma engines | |
454 | * | |
455 | * @adev: amdgpu_device pointer | |
456 | * | |
457 | * Set up the compute DMA queues and enable them (CIK). | |
458 | * Returns 0 for success, error for failure. | |
459 | */ | |
460 | static int cik_sdma_rlc_resume(struct amdgpu_device *adev) | |
461 | { | |
462 | /* XXX todo */ | |
463 | return 0; | |
464 | } | |
465 | ||
466 | /** | |
467 | * cik_sdma_load_microcode - load the sDMA ME ucode | |
468 | * | |
469 | * @adev: amdgpu_device pointer | |
470 | * | |
471 | * Loads the sDMA0/1 ucode. | |
472 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
473 | */ | |
474 | static int cik_sdma_load_microcode(struct amdgpu_device *adev) | |
475 | { | |
476 | const struct sdma_firmware_header_v1_0 *hdr; | |
477 | const __le32 *fw_data; | |
478 | u32 fw_size; | |
479 | int i, j; | |
480 | ||
a2e73f56 AD |
481 | /* halt the MEs */ |
482 | cik_sdma_enable(adev, false); | |
483 | ||
c113ea1c AD |
484 | for (i = 0; i < adev->sdma.num_instances; i++) { |
485 | if (!adev->sdma.instance[i].fw) | |
486 | return -EINVAL; | |
487 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
a2e73f56 AD |
488 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
489 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
c113ea1c AD |
490 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); |
491 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
492 | if (adev->sdma.instance[i].feature_version >= 20) | |
493 | adev->sdma.instance[i].burst_nop = true; | |
a2e73f56 | 494 | fw_data = (const __le32 *) |
c113ea1c | 495 | (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
a2e73f56 AD |
496 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); |
497 | for (j = 0; j < fw_size; j++) | |
498 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
c113ea1c | 499 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
a2e73f56 AD |
500 | } |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
505 | /** | |
506 | * cik_sdma_start - setup and start the async dma engines | |
507 | * | |
508 | * @adev: amdgpu_device pointer | |
509 | * | |
510 | * Set up the DMA engines and enable them (CIK). | |
511 | * Returns 0 for success, error for failure. | |
512 | */ | |
513 | static int cik_sdma_start(struct amdgpu_device *adev) | |
514 | { | |
515 | int r; | |
516 | ||
517 | r = cik_sdma_load_microcode(adev); | |
518 | if (r) | |
519 | return r; | |
520 | ||
521 | /* unhalt the MEs */ | |
522 | cik_sdma_enable(adev, true); | |
523 | ||
524 | /* start the gfx rings and rlc compute queues */ | |
525 | r = cik_sdma_gfx_resume(adev); | |
526 | if (r) | |
527 | return r; | |
528 | r = cik_sdma_rlc_resume(adev); | |
529 | if (r) | |
530 | return r; | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | /** | |
536 | * cik_sdma_ring_test_ring - simple async dma engine test | |
537 | * | |
538 | * @ring: amdgpu_ring structure holding ring information | |
539 | * | |
540 | * Test the DMA engine by writing using it to write an | |
541 | * value to memory. (CIK). | |
542 | * Returns 0 for success, error for failure. | |
543 | */ | |
544 | static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) | |
545 | { | |
546 | struct amdgpu_device *adev = ring->adev; | |
547 | unsigned i; | |
548 | unsigned index; | |
549 | int r; | |
550 | u32 tmp; | |
551 | u64 gpu_addr; | |
552 | ||
553 | r = amdgpu_wb_get(adev, &index); | |
554 | if (r) { | |
555 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
556 | return r; | |
557 | } | |
558 | ||
559 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
560 | tmp = 0xCAFEDEAD; | |
561 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
562 | ||
a27de35c | 563 | r = amdgpu_ring_alloc(ring, 5); |
a2e73f56 AD |
564 | if (r) { |
565 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
566 | amdgpu_wb_free(adev, index); | |
567 | return r; | |
568 | } | |
569 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
570 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
571 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
572 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | |
573 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 574 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
575 | |
576 | for (i = 0; i < adev->usec_timeout; i++) { | |
577 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
578 | if (tmp == 0xDEADBEEF) | |
579 | break; | |
580 | DRM_UDELAY(1); | |
581 | } | |
582 | ||
583 | if (i < adev->usec_timeout) { | |
584 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
585 | } else { | |
586 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
587 | ring->idx, tmp); | |
588 | r = -EINVAL; | |
589 | } | |
590 | amdgpu_wb_free(adev, index); | |
591 | ||
592 | return r; | |
593 | } | |
594 | ||
595 | /** | |
596 | * cik_sdma_ring_test_ib - test an IB on the DMA engine | |
597 | * | |
598 | * @ring: amdgpu_ring structure holding ring information | |
599 | * | |
600 | * Test a simple IB in the DMA ring (CIK). | |
601 | * Returns 0 on success, error on failure. | |
602 | */ | |
603 | static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring) | |
604 | { | |
605 | struct amdgpu_device *adev = ring->adev; | |
606 | struct amdgpu_ib ib; | |
1763552e | 607 | struct fence *f = NULL; |
a2e73f56 AD |
608 | unsigned i; |
609 | unsigned index; | |
610 | int r; | |
611 | u32 tmp = 0; | |
612 | u64 gpu_addr; | |
613 | ||
614 | r = amdgpu_wb_get(adev, &index); | |
615 | if (r) { | |
616 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
617 | return r; | |
618 | } | |
619 | ||
620 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
621 | tmp = 0xCAFEDEAD; | |
622 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 623 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 624 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
a2e73f56 | 625 | if (r) { |
a2e73f56 | 626 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); |
0011fdaa | 627 | goto err0; |
a2e73f56 AD |
628 | } |
629 | ||
630 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
631 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
632 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
633 | ib.ptr[3] = 1; | |
634 | ib.ptr[4] = 0xDEADBEEF; | |
635 | ib.length_dw = 5; | |
e86f9cee CK |
636 | r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, |
637 | NULL, &f); | |
0011fdaa CZ |
638 | if (r) |
639 | goto err1; | |
a2e73f56 | 640 | |
1763552e | 641 | r = fence_wait(f, false); |
a2e73f56 | 642 | if (r) { |
a2e73f56 | 643 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); |
0011fdaa | 644 | goto err1; |
a2e73f56 AD |
645 | } |
646 | for (i = 0; i < adev->usec_timeout; i++) { | |
647 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
648 | if (tmp == 0xDEADBEEF) | |
649 | break; | |
650 | DRM_UDELAY(1); | |
651 | } | |
652 | if (i < adev->usec_timeout) { | |
653 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", | |
0011fdaa CZ |
654 | ring->idx, i); |
655 | goto err1; | |
a2e73f56 AD |
656 | } else { |
657 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
658 | r = -EINVAL; | |
659 | } | |
0011fdaa CZ |
660 | |
661 | err1: | |
281b4223 | 662 | fence_put(f); |
a2e73f56 | 663 | amdgpu_ib_free(adev, &ib); |
0011fdaa | 664 | err0: |
a2e73f56 AD |
665 | amdgpu_wb_free(adev, index); |
666 | return r; | |
667 | } | |
668 | ||
669 | /** | |
670 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART | |
671 | * | |
672 | * @ib: indirect buffer to fill with commands | |
673 | * @pe: addr of the page entry | |
674 | * @src: src addr to copy from | |
675 | * @count: number of page entries to update | |
676 | * | |
677 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
678 | */ | |
679 | static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, | |
680 | uint64_t pe, uint64_t src, | |
681 | unsigned count) | |
682 | { | |
683 | while (count) { | |
684 | unsigned bytes = count * 8; | |
685 | if (bytes > 0x1FFFF8) | |
686 | bytes = 0x1FFFF8; | |
687 | ||
688 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, | |
689 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
690 | ib->ptr[ib->length_dw++] = bytes; | |
691 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
692 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
693 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
694 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
695 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
696 | ||
697 | pe += bytes; | |
698 | src += bytes; | |
699 | count -= bytes / 8; | |
700 | } | |
701 | } | |
702 | ||
703 | /** | |
704 | * cik_sdma_vm_write_pages - update PTEs by writing them manually | |
705 | * | |
706 | * @ib: indirect buffer to fill with commands | |
707 | * @pe: addr of the page entry | |
708 | * @addr: dst addr to write into pe | |
709 | * @count: number of page entries to update | |
710 | * @incr: increase next addr by incr bytes | |
711 | * @flags: access flags | |
712 | * | |
713 | * Update PTEs by writing them manually using sDMA (CIK). | |
714 | */ | |
715 | static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, | |
b07c9d2a | 716 | const dma_addr_t *pages_addr, uint64_t pe, |
a2e73f56 AD |
717 | uint64_t addr, unsigned count, |
718 | uint32_t incr, uint32_t flags) | |
719 | { | |
720 | uint64_t value; | |
721 | unsigned ndw; | |
722 | ||
723 | while (count) { | |
724 | ndw = count * 2; | |
725 | if (ndw > 0xFFFFE) | |
726 | ndw = 0xFFFFE; | |
727 | ||
728 | /* for non-physically contiguous pages (system) */ | |
729 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | |
730 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
731 | ib->ptr[ib->length_dw++] = pe; | |
732 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
733 | ib->ptr[ib->length_dw++] = ndw; | |
734 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
b07c9d2a | 735 | value = amdgpu_vm_map_gart(pages_addr, addr); |
a2e73f56 AD |
736 | addr += incr; |
737 | value |= flags; | |
738 | ib->ptr[ib->length_dw++] = value; | |
739 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | /** | |
745 | * cik_sdma_vm_set_pages - update the page tables using sDMA | |
746 | * | |
747 | * @ib: indirect buffer to fill with commands | |
748 | * @pe: addr of the page entry | |
749 | * @addr: dst addr to write into pe | |
750 | * @count: number of page entries to update | |
751 | * @incr: increase next addr by incr bytes | |
752 | * @flags: access flags | |
753 | * | |
754 | * Update the page tables using sDMA (CIK). | |
755 | */ | |
756 | static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, | |
757 | uint64_t pe, | |
758 | uint64_t addr, unsigned count, | |
759 | uint32_t incr, uint32_t flags) | |
760 | { | |
761 | uint64_t value; | |
762 | unsigned ndw; | |
763 | ||
764 | while (count) { | |
765 | ndw = count; | |
766 | if (ndw > 0x7FFFF) | |
767 | ndw = 0x7FFFF; | |
768 | ||
769 | if (flags & AMDGPU_PTE_VALID) | |
770 | value = addr; | |
771 | else | |
772 | value = 0; | |
773 | ||
774 | /* for physically contiguous pages (vram) */ | |
775 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); | |
776 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
777 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
778 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
779 | ib->ptr[ib->length_dw++] = 0; | |
780 | ib->ptr[ib->length_dw++] = value; /* value */ | |
781 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
782 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
783 | ib->ptr[ib->length_dw++] = 0; | |
784 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ | |
785 | ||
786 | pe += ndw * 8; | |
787 | addr += ndw * incr; | |
788 | count -= ndw; | |
789 | } | |
790 | } | |
791 | ||
792 | /** | |
793 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw | |
794 | * | |
795 | * @ib: indirect buffer to fill with padding | |
796 | * | |
797 | */ | |
9e5d5309 | 798 | static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
a2e73f56 | 799 | { |
9e5d5309 | 800 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
801 | u32 pad_count; |
802 | int i; | |
803 | ||
804 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
805 | for (i = 0; i < pad_count; i++) | |
806 | if (sdma && sdma->burst_nop && (i == 0)) | |
807 | ib->ptr[ib->length_dw++] = | |
808 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | | |
809 | SDMA_NOP_COUNT(pad_count - 1); | |
810 | else | |
811 | ib->ptr[ib->length_dw++] = | |
812 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); | |
a2e73f56 AD |
813 | } |
814 | ||
815 | /** | |
816 | * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA | |
817 | * | |
818 | * @ring: amdgpu_ring pointer | |
819 | * @vm: amdgpu_vm pointer | |
820 | * | |
821 | * Update the page table base and flush the VM TLB | |
822 | * using sDMA (CIK). | |
823 | */ | |
824 | static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
825 | unsigned vm_id, uint64_t pd_addr) | |
826 | { | |
827 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | | |
828 | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ | |
829 | ||
830 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
831 | if (vm_id < 8) { | |
832 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
833 | } else { | |
834 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
835 | } | |
836 | amdgpu_ring_write(ring, pd_addr >> 12); | |
837 | ||
a2e73f56 AD |
838 | /* flush TLB */ |
839 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
840 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
841 | amdgpu_ring_write(ring, 1 << vm_id); | |
842 | ||
843 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
844 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
845 | amdgpu_ring_write(ring, 0); | |
846 | amdgpu_ring_write(ring, 0); /* reference */ | |
847 | amdgpu_ring_write(ring, 0); /* mask */ | |
848 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
849 | } | |
850 | ||
851 | static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, | |
852 | bool enable) | |
853 | { | |
854 | u32 orig, data; | |
855 | ||
856 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) { | |
857 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); | |
858 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); | |
859 | } else { | |
860 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); | |
861 | data |= 0xff000000; | |
862 | if (data != orig) | |
863 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); | |
864 | ||
865 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); | |
866 | data |= 0xff000000; | |
867 | if (data != orig) | |
868 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); | |
869 | } | |
870 | } | |
871 | ||
872 | static void cik_enable_sdma_mgls(struct amdgpu_device *adev, | |
873 | bool enable) | |
874 | { | |
875 | u32 orig, data; | |
876 | ||
877 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) { | |
878 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); | |
879 | data |= 0x100; | |
880 | if (orig != data) | |
881 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
882 | ||
883 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
884 | data |= 0x100; | |
885 | if (orig != data) | |
886 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
887 | } else { | |
888 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); | |
889 | data &= ~0x100; | |
890 | if (orig != data) | |
891 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
892 | ||
893 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
894 | data &= ~0x100; | |
895 | if (orig != data) | |
896 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
897 | } | |
898 | } | |
899 | ||
5fc3aeeb | 900 | static int cik_sdma_early_init(void *handle) |
a2e73f56 | 901 | { |
5fc3aeeb | 902 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
903 | ||
c113ea1c AD |
904 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; |
905 | ||
a2e73f56 AD |
906 | cik_sdma_set_ring_funcs(adev); |
907 | cik_sdma_set_irq_funcs(adev); | |
908 | cik_sdma_set_buffer_funcs(adev); | |
909 | cik_sdma_set_vm_pte_funcs(adev); | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
5fc3aeeb | 914 | static int cik_sdma_sw_init(void *handle) |
a2e73f56 AD |
915 | { |
916 | struct amdgpu_ring *ring; | |
5fc3aeeb | 917 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 918 | int r, i; |
a2e73f56 AD |
919 | |
920 | r = cik_sdma_init_microcode(adev); | |
921 | if (r) { | |
922 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
923 | return r; | |
924 | } | |
925 | ||
926 | /* SDMA trap event */ | |
c113ea1c | 927 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); |
a2e73f56 AD |
928 | if (r) |
929 | return r; | |
930 | ||
931 | /* SDMA Privileged inst */ | |
c113ea1c | 932 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); |
a2e73f56 AD |
933 | if (r) |
934 | return r; | |
935 | ||
936 | /* SDMA Privileged inst */ | |
c113ea1c | 937 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); |
a2e73f56 AD |
938 | if (r) |
939 | return r; | |
940 | ||
c113ea1c AD |
941 | for (i = 0; i < adev->sdma.num_instances; i++) { |
942 | ring = &adev->sdma.instance[i].ring; | |
943 | ring->ring_obj = NULL; | |
944 | sprintf(ring->name, "sdma%d", i); | |
945 | r = amdgpu_ring_init(adev, ring, 256 * 1024, | |
946 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, | |
947 | &adev->sdma.trap_irq, | |
948 | (i == 0) ? | |
949 | AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, | |
950 | AMDGPU_RING_TYPE_SDMA); | |
951 | if (r) | |
952 | return r; | |
953 | } | |
a2e73f56 AD |
954 | |
955 | return r; | |
956 | } | |
957 | ||
5fc3aeeb | 958 | static int cik_sdma_sw_fini(void *handle) |
a2e73f56 | 959 | { |
5fc3aeeb | 960 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 961 | int i; |
5fc3aeeb | 962 | |
c113ea1c AD |
963 | for (i = 0; i < adev->sdma.num_instances; i++) |
964 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
a2e73f56 AD |
965 | |
966 | return 0; | |
967 | } | |
968 | ||
5fc3aeeb | 969 | static int cik_sdma_hw_init(void *handle) |
a2e73f56 AD |
970 | { |
971 | int r; | |
5fc3aeeb | 972 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
973 | |
974 | r = cik_sdma_start(adev); | |
975 | if (r) | |
976 | return r; | |
977 | ||
978 | return r; | |
979 | } | |
980 | ||
5fc3aeeb | 981 | static int cik_sdma_hw_fini(void *handle) |
a2e73f56 | 982 | { |
5fc3aeeb | 983 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
984 | ||
a2e73f56 AD |
985 | cik_sdma_enable(adev, false); |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
5fc3aeeb | 990 | static int cik_sdma_suspend(void *handle) |
a2e73f56 | 991 | { |
5fc3aeeb | 992 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
993 | |
994 | return cik_sdma_hw_fini(adev); | |
995 | } | |
996 | ||
5fc3aeeb | 997 | static int cik_sdma_resume(void *handle) |
a2e73f56 | 998 | { |
5fc3aeeb | 999 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1000 | |
1001 | return cik_sdma_hw_init(adev); | |
1002 | } | |
1003 | ||
5fc3aeeb | 1004 | static bool cik_sdma_is_idle(void *handle) |
a2e73f56 | 1005 | { |
5fc3aeeb | 1006 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1007 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1008 | ||
1009 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1010 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1011 | return false; | |
1012 | ||
1013 | return true; | |
1014 | } | |
1015 | ||
5fc3aeeb | 1016 | static int cik_sdma_wait_for_idle(void *handle) |
a2e73f56 AD |
1017 | { |
1018 | unsigned i; | |
1019 | u32 tmp; | |
5fc3aeeb | 1020 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1021 | |
1022 | for (i = 0; i < adev->usec_timeout; i++) { | |
1023 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1024 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1025 | ||
1026 | if (!tmp) | |
1027 | return 0; | |
1028 | udelay(1); | |
1029 | } | |
1030 | return -ETIMEDOUT; | |
1031 | } | |
1032 | ||
5fc3aeeb | 1033 | static void cik_sdma_print_status(void *handle) |
a2e73f56 AD |
1034 | { |
1035 | int i, j; | |
5fc3aeeb | 1036 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1037 | |
1038 | dev_info(adev->dev, "CIK SDMA registers\n"); | |
1039 | dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", | |
1040 | RREG32(mmSRBM_STATUS2)); | |
c113ea1c | 1041 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
1042 | dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", |
1043 | i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); | |
1044 | dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n", | |
1045 | i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); | |
1046 | dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", | |
1047 | i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); | |
1048 | dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", | |
1049 | i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i])); | |
1050 | dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", | |
1051 | i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); | |
1052 | dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", | |
1053 | i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); | |
1054 | dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", | |
1055 | i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); | |
1056 | dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", | |
1057 | i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); | |
1058 | dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", | |
1059 | i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); | |
1060 | dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", | |
1061 | i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); | |
1062 | dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", | |
1063 | i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); | |
1064 | dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", | |
1065 | i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); | |
1066 | dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", | |
1067 | i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); | |
1068 | mutex_lock(&adev->srbm_mutex); | |
1069 | for (j = 0; j < 16; j++) { | |
1070 | cik_srbm_select(adev, 0, 0, 0, j); | |
1071 | dev_info(adev->dev, " VM %d:\n", j); | |
1072 | dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n", | |
1073 | RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); | |
1074 | dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n", | |
1075 | RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); | |
1076 | } | |
1077 | cik_srbm_select(adev, 0, 0, 0, 0); | |
1078 | mutex_unlock(&adev->srbm_mutex); | |
1079 | } | |
1080 | } | |
1081 | ||
5fc3aeeb | 1082 | static int cik_sdma_soft_reset(void *handle) |
a2e73f56 AD |
1083 | { |
1084 | u32 srbm_soft_reset = 0; | |
5fc3aeeb | 1085 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1086 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1087 | ||
1088 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1089 | /* sdma0 */ | |
1090 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1091 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1092 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1093 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1094 | } | |
1095 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1096 | /* sdma1 */ | |
1097 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1098 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1099 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1100 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1101 | } | |
1102 | ||
1103 | if (srbm_soft_reset) { | |
5fc3aeeb | 1104 | cik_sdma_print_status((void *)adev); |
a2e73f56 AD |
1105 | |
1106 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1107 | tmp |= srbm_soft_reset; | |
1108 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1109 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1110 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1111 | ||
1112 | udelay(50); | |
1113 | ||
1114 | tmp &= ~srbm_soft_reset; | |
1115 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1116 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1117 | ||
1118 | /* Wait a little for things to settle down */ | |
1119 | udelay(50); | |
1120 | ||
5fc3aeeb | 1121 | cik_sdma_print_status((void *)adev); |
a2e73f56 AD |
1122 | } |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, | |
1128 | struct amdgpu_irq_src *src, | |
1129 | unsigned type, | |
1130 | enum amdgpu_interrupt_state state) | |
1131 | { | |
1132 | u32 sdma_cntl; | |
1133 | ||
1134 | switch (type) { | |
1135 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1136 | switch (state) { | |
1137 | case AMDGPU_IRQ_STATE_DISABLE: | |
1138 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1139 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1140 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1141 | break; | |
1142 | case AMDGPU_IRQ_STATE_ENABLE: | |
1143 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1144 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1145 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1146 | break; | |
1147 | default: | |
1148 | break; | |
1149 | } | |
1150 | break; | |
1151 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1152 | switch (state) { | |
1153 | case AMDGPU_IRQ_STATE_DISABLE: | |
1154 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1155 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1156 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1157 | break; | |
1158 | case AMDGPU_IRQ_STATE_ENABLE: | |
1159 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1160 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1161 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1162 | break; | |
1163 | default: | |
1164 | break; | |
1165 | } | |
1166 | break; | |
1167 | default: | |
1168 | break; | |
1169 | } | |
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, | |
1174 | struct amdgpu_irq_src *source, | |
1175 | struct amdgpu_iv_entry *entry) | |
1176 | { | |
1177 | u8 instance_id, queue_id; | |
1178 | ||
1179 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1180 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1181 | DRM_DEBUG("IH: SDMA trap\n"); | |
1182 | switch (instance_id) { | |
1183 | case 0: | |
1184 | switch (queue_id) { | |
1185 | case 0: | |
c113ea1c | 1186 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
a2e73f56 AD |
1187 | break; |
1188 | case 1: | |
1189 | /* XXX compute */ | |
1190 | break; | |
1191 | case 2: | |
1192 | /* XXX compute */ | |
1193 | break; | |
1194 | } | |
1195 | break; | |
1196 | case 1: | |
1197 | switch (queue_id) { | |
1198 | case 0: | |
c113ea1c | 1199 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
a2e73f56 AD |
1200 | break; |
1201 | case 1: | |
1202 | /* XXX compute */ | |
1203 | break; | |
1204 | case 2: | |
1205 | /* XXX compute */ | |
1206 | break; | |
1207 | } | |
1208 | break; | |
1209 | } | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1215 | struct amdgpu_irq_src *source, | |
1216 | struct amdgpu_iv_entry *entry) | |
1217 | { | |
1218 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1219 | schedule_work(&adev->reset_work); | |
1220 | return 0; | |
1221 | } | |
1222 | ||
5fc3aeeb | 1223 | static int cik_sdma_set_clockgating_state(void *handle, |
1224 | enum amd_clockgating_state state) | |
a2e73f56 AD |
1225 | { |
1226 | bool gate = false; | |
5fc3aeeb | 1227 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 1228 | |
5fc3aeeb | 1229 | if (state == AMD_CG_STATE_GATE) |
a2e73f56 AD |
1230 | gate = true; |
1231 | ||
1232 | cik_enable_sdma_mgcg(adev, gate); | |
1233 | cik_enable_sdma_mgls(adev, gate); | |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
5fc3aeeb | 1238 | static int cik_sdma_set_powergating_state(void *handle, |
1239 | enum amd_powergating_state state) | |
a2e73f56 AD |
1240 | { |
1241 | return 0; | |
1242 | } | |
1243 | ||
5fc3aeeb | 1244 | const struct amd_ip_funcs cik_sdma_ip_funcs = { |
a2e73f56 AD |
1245 | .early_init = cik_sdma_early_init, |
1246 | .late_init = NULL, | |
1247 | .sw_init = cik_sdma_sw_init, | |
1248 | .sw_fini = cik_sdma_sw_fini, | |
1249 | .hw_init = cik_sdma_hw_init, | |
1250 | .hw_fini = cik_sdma_hw_fini, | |
1251 | .suspend = cik_sdma_suspend, | |
1252 | .resume = cik_sdma_resume, | |
1253 | .is_idle = cik_sdma_is_idle, | |
1254 | .wait_for_idle = cik_sdma_wait_for_idle, | |
1255 | .soft_reset = cik_sdma_soft_reset, | |
1256 | .print_status = cik_sdma_print_status, | |
1257 | .set_clockgating_state = cik_sdma_set_clockgating_state, | |
1258 | .set_powergating_state = cik_sdma_set_powergating_state, | |
1259 | }; | |
1260 | ||
a2e73f56 AD |
1261 | static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { |
1262 | .get_rptr = cik_sdma_ring_get_rptr, | |
1263 | .get_wptr = cik_sdma_ring_get_wptr, | |
1264 | .set_wptr = cik_sdma_ring_set_wptr, | |
1265 | .parse_cs = NULL, | |
1266 | .emit_ib = cik_sdma_ring_emit_ib, | |
1267 | .emit_fence = cik_sdma_ring_emit_fence, | |
a2e73f56 | 1268 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
d2edb07b | 1269 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
a2e73f56 AD |
1270 | .test_ring = cik_sdma_ring_test_ring, |
1271 | .test_ib = cik_sdma_ring_test_ib, | |
ac01db3d | 1272 | .insert_nop = cik_sdma_ring_insert_nop, |
9e5d5309 | 1273 | .pad_ib = cik_sdma_ring_pad_ib, |
a2e73f56 AD |
1274 | }; |
1275 | ||
1276 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) | |
1277 | { | |
c113ea1c AD |
1278 | int i; |
1279 | ||
1280 | for (i = 0; i < adev->sdma.num_instances; i++) | |
1281 | adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; | |
a2e73f56 AD |
1282 | } |
1283 | ||
1284 | static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { | |
1285 | .set = cik_sdma_set_trap_irq_state, | |
1286 | .process = cik_sdma_process_trap_irq, | |
1287 | }; | |
1288 | ||
1289 | static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { | |
1290 | .process = cik_sdma_process_illegal_inst_irq, | |
1291 | }; | |
1292 | ||
1293 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) | |
1294 | { | |
c113ea1c AD |
1295 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1296 | adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; | |
1297 | adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; | |
a2e73f56 AD |
1298 | } |
1299 | ||
1300 | /** | |
1301 | * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine | |
1302 | * | |
1303 | * @ring: amdgpu_ring structure holding ring information | |
1304 | * @src_offset: src GPU address | |
1305 | * @dst_offset: dst GPU address | |
1306 | * @byte_count: number of bytes to xfer | |
1307 | * | |
1308 | * Copy GPU buffers using the DMA engine (CIK). | |
1309 | * Used by the amdgpu ttm implementation to move pages if | |
1310 | * registered as the asic copy callback. | |
1311 | */ | |
c7ae72c0 | 1312 | static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, |
a2e73f56 AD |
1313 | uint64_t src_offset, |
1314 | uint64_t dst_offset, | |
1315 | uint32_t byte_count) | |
1316 | { | |
c7ae72c0 CZ |
1317 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); |
1318 | ib->ptr[ib->length_dw++] = byte_count; | |
1319 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1320 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1321 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1322 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1323 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
a2e73f56 AD |
1324 | } |
1325 | ||
1326 | /** | |
1327 | * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine | |
1328 | * | |
1329 | * @ring: amdgpu_ring structure holding ring information | |
1330 | * @src_data: value to write to buffer | |
1331 | * @dst_offset: dst GPU address | |
1332 | * @byte_count: number of bytes to xfer | |
1333 | * | |
1334 | * Fill GPU buffers using the DMA engine (CIK). | |
1335 | */ | |
6e7a3840 | 1336 | static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, |
a2e73f56 AD |
1337 | uint32_t src_data, |
1338 | uint64_t dst_offset, | |
1339 | uint32_t byte_count) | |
1340 | { | |
6e7a3840 CZ |
1341 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); |
1342 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1343 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1344 | ib->ptr[ib->length_dw++] = src_data; | |
1345 | ib->ptr[ib->length_dw++] = byte_count; | |
a2e73f56 AD |
1346 | } |
1347 | ||
1348 | static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { | |
1349 | .copy_max_bytes = 0x1fffff, | |
1350 | .copy_num_dw = 7, | |
1351 | .emit_copy_buffer = cik_sdma_emit_copy_buffer, | |
1352 | ||
1353 | .fill_max_bytes = 0x1fffff, | |
1354 | .fill_num_dw = 5, | |
1355 | .emit_fill_buffer = cik_sdma_emit_fill_buffer, | |
1356 | }; | |
1357 | ||
1358 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) | |
1359 | { | |
1360 | if (adev->mman.buffer_funcs == NULL) { | |
1361 | adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; | |
c113ea1c | 1362 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
a2e73f56 AD |
1363 | } |
1364 | } | |
1365 | ||
1366 | static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { | |
1367 | .copy_pte = cik_sdma_vm_copy_pte, | |
1368 | .write_pte = cik_sdma_vm_write_pte, | |
1369 | .set_pte_pde = cik_sdma_vm_set_pte_pde, | |
a2e73f56 AD |
1370 | }; |
1371 | ||
1372 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1373 | { | |
2d55e45a CK |
1374 | unsigned i; |
1375 | ||
a2e73f56 AD |
1376 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
1377 | adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; | |
2d55e45a CK |
1378 | for (i = 0; i < adev->sdma.num_instances; i++) |
1379 | adev->vm_manager.vm_pte_rings[i] = | |
1380 | &adev->sdma.instance[i].ring; | |
1381 | ||
1382 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
a2e73f56 AD |
1383 | } |
1384 | } |