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drm/amdgpu: don't enable/disable display twice on suspend/resume
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cz_dpm.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/seq_file.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_atombios.h"
30#include "vid.h"
31#include "vi_dpm.h"
32#include "amdgpu_dpm.h"
33#include "cz_dpm.h"
34#include "cz_ppsmc.h"
35#include "atom.h"
36
37#include "smu/smu_8_0_d.h"
38#include "smu/smu_8_0_sh_mask.h"
39#include "gca/gfx_8_0_d.h"
40#include "gca/gfx_8_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "bif/bif_5_1_d.h"
43#include "gfx_v8_0.h"
44
564ea790 45static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
b7a07769 46static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
564ea790 47
aaa36a97
AD		 48static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
49{
50 struct cz_ps *ps = rps->ps_priv;
51
52 return ps;
53}
54
55static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
56{
57 struct cz_power_info *pi = adev->pm.dpm.priv;
58
59 return pi;
60}
61
62static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
63 uint16_t voltage)
64{
65 uint16_t tmp = 6200 - voltage * 25;
66
67 return tmp;
68}
69
70static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
71 struct amdgpu_clock_and_voltage_limits *table)
72{
73 struct cz_power_info *pi = cz_get_pi(adev);
74 struct amdgpu_clock_voltage_dependency_table *dep_table =
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
76
77 if (dep_table->count > 0) {
78 table->sclk = dep_table->entries[dep_table->count - 1].clk;
79 table->vddc = cz_convert_8bit_index_to_voltage(adev,
80 dep_table->entries[dep_table->count - 1].v);
81 }
82
83 table->mclk = pi->sys_info.nbp_memory_clock[0];
84
85}
86
87union igp_info {
88 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
89 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
90 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
91 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
92};
93
94static int cz_parse_sys_info_table(struct amdgpu_device *adev)
95{
96 struct cz_power_info *pi = cz_get_pi(adev);
97 struct amdgpu_mode_info *mode_info = &adev->mode_info;
98 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
99 union igp_info *igp_info;
100 u8 frev, crev;
101 u16 data_offset;
102 int i = 0;
103
104 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
105 &frev, &crev, &data_offset)) {
106 igp_info = (union igp_info *)(mode_info->atom_context->bios +
107 data_offset);
108
109 if (crev != 9) {
110 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
111 return -EINVAL;
112 }
113 pi->sys_info.bootup_sclk =
114 le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
115 pi->sys_info.bootup_uma_clk =
116 le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
117 pi->sys_info.dentist_vco_freq =
118 le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
119 pi->sys_info.bootup_nb_voltage_index =
120 le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
121
122 if (igp_info->info_9.ucHtcTmpLmt == 0)
123 pi->sys_info.htc_tmp_lmt = 203;
124 else
125 pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
126
127 if (igp_info->info_9.ucHtcHystLmt == 0)
128 pi->sys_info.htc_hyst_lmt = 5;
129 else
130 pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
131
132 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
133 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
134 return -EINVAL;
135 }
136
137 if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
138 pi->enable_nb_ps_policy)
139 pi->sys_info.nb_dpm_enable = true;
140 else
141 pi->sys_info.nb_dpm_enable = false;
142
143 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
144 if (i < CZ_NUM_NBPMEMORY_CLOCK)
145 pi->sys_info.nbp_memory_clock[i] =
146 le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
147 pi->sys_info.nbp_n_clock[i] =
148 le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
149 }
150
151 for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
152 pi->sys_info.display_clock[i] =
153 le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
154
155 for (i = 0; i < CZ_NUM_NBPSTATES; i++)
156 pi->sys_info.nbp_voltage_index[i] =
157 le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
158
159 if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
160 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
161 pi->caps_enable_dfs_bypass = true;
162
163 pi->sys_info.uma_channel_number =
164 igp_info->info_9.ucUMAChannelNumber;
165
166 cz_construct_max_power_limits_table(adev,
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
168 }
169
170 return 0;
171}
172
173static void cz_patch_voltage_values(struct amdgpu_device *adev)
174{
175 int i;
176 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
178 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
180 struct amdgpu_clock_voltage_dependency_table *acp_table =
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
182
183 if (uvd_table->count) {
184 for (i = 0; i < uvd_table->count; i++)
185 uvd_table->entries[i].v =
186 cz_convert_8bit_index_to_voltage(adev,
187 uvd_table->entries[i].v);
188 }
189
190 if (vce_table->count) {
191 for (i = 0; i < vce_table->count; i++)
192 vce_table->entries[i].v =
193 cz_convert_8bit_index_to_voltage(adev,
194 vce_table->entries[i].v);
195 }
196
197 if (acp_table->count) {
198 for (i = 0; i < acp_table->count; i++)
199 acp_table->entries[i].v =
200 cz_convert_8bit_index_to_voltage(adev,
201 acp_table->entries[i].v);
202 }
203
204}
205
206static void cz_construct_boot_state(struct amdgpu_device *adev)
207{
208 struct cz_power_info *pi = cz_get_pi(adev);
209
210 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
211 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
212 pi->boot_pl.ds_divider_index = 0;
213 pi->boot_pl.ss_divider_index = 0;
214 pi->boot_pl.allow_gnb_slow = 1;
215 pi->boot_pl.force_nbp_state = 0;
216 pi->boot_pl.display_wm = 0;
217 pi->boot_pl.vce_wm = 0;
218
219}
220
221static void cz_patch_boot_state(struct amdgpu_device *adev,
222 struct cz_ps *ps)
223{
224 struct cz_power_info *pi = cz_get_pi(adev);
225
226 ps->num_levels = 1;
227 ps->levels[0] = pi->boot_pl;
228}
229
230union pplib_clock_info {
231 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
232 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
233 struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
234};
235
236static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
237 struct amdgpu_ps *rps, int index,
238 union pplib_clock_info *clock_info)
239{
240 struct cz_power_info *pi = cz_get_pi(adev);
241 struct cz_ps *ps = cz_get_ps(rps);
242 struct cz_pl *pl = &ps->levels[index];
243 struct amdgpu_clock_voltage_dependency_table *table =
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
245
246 pl->sclk = table->entries[clock_info->carrizo.index].clk;
247 pl->vddc_index = table->entries[clock_info->carrizo.index].v;
248
249 ps->num_levels = index + 1;
250
251 if (pi->caps_sclk_ds) {
252 pl->ds_divider_index = 5;
253 pl->ss_divider_index = 5;
254 }
255
256}
257
258static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
259 struct amdgpu_ps *rps,
260 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
261 u8 table_rev)
262{
263 struct cz_ps *ps = cz_get_ps(rps);
264
265 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
266 rps->class = le16_to_cpu(non_clock_info->usClassification);
267 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
268
269 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
270 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
271 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
272 } else {
273 rps->vclk = 0;
274 rps->dclk = 0;
275 }
276
277 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
278 adev->pm.dpm.boot_ps = rps;
279 cz_patch_boot_state(adev, ps);
280 }
281 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
282 adev->pm.dpm.uvd_ps = rps;
283
284}
285
286union power_info {
287 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
288 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
289 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
290 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
291 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
292};
293
294union pplib_power_state {
295 struct _ATOM_PPLIB_STATE v1;
296 struct _ATOM_PPLIB_STATE_V2 v2;
297};
298
299static int cz_parse_power_table(struct amdgpu_device *adev)
300{
301 struct amdgpu_mode_info *mode_info = &adev->mode_info;
302 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
303 union pplib_power_state *power_state;
304 int i, j, k, non_clock_array_index, clock_array_index;
305 union pplib_clock_info *clock_info;
306 struct _StateArray *state_array;
307 struct _ClockInfoArray *clock_info_array;
308 struct _NonClockInfoArray *non_clock_info_array;
309 union power_info *power_info;
310 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
311 u16 data_offset;
312 u8 frev, crev;
313 u8 *power_state_offset;
314 struct cz_ps *ps;
315
316 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
317 &frev, &crev, &data_offset))
318 return -EINVAL;
319 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
320
321 state_array = (struct _StateArray *)
322 (mode_info->atom_context->bios + data_offset +
323 le16_to_cpu(power_info->pplib.usStateArrayOffset));
324 clock_info_array = (struct _ClockInfoArray *)
325 (mode_info->atom_context->bios + data_offset +
326 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
327 non_clock_info_array = (struct _NonClockInfoArray *)
328 (mode_info->atom_context->bios + data_offset +
329 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
330
331 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
332 state_array->ucNumEntries, GFP_KERNEL);
333
334 if (!adev->pm.dpm.ps)
335 return -ENOMEM;
336
337 power_state_offset = (u8 *)state_array->states;
338 adev->pm.dpm.platform_caps =
339 le32_to_cpu(power_info->pplib.ulPlatformCaps);
340 adev->pm.dpm.backbias_response_time =
341 le16_to_cpu(power_info->pplib.usBackbiasTime);
342 adev->pm.dpm.voltage_response_time =
343 le16_to_cpu(power_info->pplib.usVoltageTime);
344
345 for (i = 0; i < state_array->ucNumEntries; i++) {
346 power_state = (union pplib_power_state *)power_state_offset;
347 non_clock_array_index = power_state->v2.nonClockInfoIndex;
348 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
349 &non_clock_info_array->nonClockInfo[non_clock_array_index];
350
351 ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
352 if (ps == NULL) {
353 kfree(adev->pm.dpm.ps);
354 return -ENOMEM;
355 }
356
357 adev->pm.dpm.ps[i].ps_priv = ps;
358 k = 0;
359 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
360 clock_array_index = power_state->v2.clockInfoIndex[j];
361 if (clock_array_index >= clock_info_array->ucNumEntries)
362 continue;
363 if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
364 break;
365 clock_info = (union pplib_clock_info *)
366 &clock_info_array->clockInfo[clock_array_index *
367 clock_info_array->ucEntrySize];
368 cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
369 k, clock_info);
370 k++;
371 }
372 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
373 non_clock_info,
374 non_clock_info_array->ucEntrySize);
375 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
376 }
377 adev->pm.dpm.num_ps = state_array->ucNumEntries;
378
379 return 0;
380}
381
382static int cz_process_firmware_header(struct amdgpu_device *adev)
383{
384 struct cz_power_info *pi = cz_get_pi(adev);
385 u32 tmp;
386 int ret;
387
388 ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
389 offsetof(struct SMU8_Firmware_Header,
390 DpmTable),
391 &tmp, pi->sram_end);
392
393 if (ret == 0)
394 pi->dpm_table_start = tmp;
395
396 return ret;
397}
398
399static int cz_dpm_init(struct amdgpu_device *adev)
400{
401 struct cz_power_info *pi;
402 int ret, i;
403
404 pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
405 if (NULL == pi)
406 return -ENOMEM;
407
408 adev->pm.dpm.priv = pi;
409
410 ret = amdgpu_get_platform_caps(adev);
411 if (ret)
412 return ret;
413
414 ret = amdgpu_parse_extended_power_table(adev);
415 if (ret)
416 return ret;
417
418 pi->sram_end = SMC_RAM_END;
419
420 /* set up DPM defaults */
421 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
422 pi->active_target[i] = CZ_AT_DFLT;
423
424 pi->mgcg_cgtt_local0 = 0x0;
425 pi->mgcg_cgtt_local1 = 0x0;
426 pi->clock_slow_down_step = 25000;
427 pi->skip_clock_slow_down = 1;
428 pi->enable_nb_ps_policy = 1;
429 pi->caps_power_containment = true;
430 pi->caps_cac = true;
431 pi->didt_enabled = false;
432 if (pi->didt_enabled) {
433 pi->caps_sq_ramping = true;
434 pi->caps_db_ramping = true;
435 pi->caps_td_ramping = true;
436 pi->caps_tcp_ramping = true;
437 }
438 pi->caps_sclk_ds = true;
439 pi->voting_clients = 0x00c00033;
440 pi->auto_thermal_throttling_enabled = true;
441 pi->bapm_enabled = false;
442 pi->disable_nb_ps3_in_battery = false;
443 pi->voltage_drop_threshold = 0;
444 pi->caps_sclk_throttle_low_notification = false;
445 pi->gfx_pg_threshold = 500;
446 pi->caps_fps = true;
447 /* uvd */
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
449 pi->caps_uvd_dpm = true;
450 /* vce */
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
452 pi->caps_vce_dpm = true;
453 /* acp */
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
455 pi->caps_acp_dpm = true;
456
457 pi->caps_stable_power_state = false;
458 pi->nb_dpm_enabled_by_driver = true;
459 pi->nb_dpm_enabled = false;
460 pi->caps_voltage_island = false;
461 /* flags which indicate need to upload pptable */
462 pi->need_pptable_upload = true;
463
464 ret = cz_parse_sys_info_table(adev);
465 if (ret)
466 return ret;
467
468 cz_patch_voltage_values(adev);
469 cz_construct_boot_state(adev);
470
471 ret = cz_parse_power_table(adev);
472 if (ret)
473 return ret;
474
475 ret = cz_process_firmware_header(adev);
476 if (ret)
477 return ret;
478
479 pi->dpm_enabled = true;
564ea790 480 pi->uvd_dynamic_pg = false;
aaa36a97
AD		 481
482 return 0;
483}
484
485static void cz_dpm_fini(struct amdgpu_device *adev)
486{
487 int i;
488
489 for (i = 0; i < adev->pm.dpm.num_ps; i++)
490 kfree(adev->pm.dpm.ps[i].ps_priv);
491
492 kfree(adev->pm.dpm.ps);
493 kfree(adev->pm.dpm.priv);
494 amdgpu_free_extended_power_table(adev);
495}
496
497static void
498cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
499 struct seq_file *m)
500{
501 struct amdgpu_clock_voltage_dependency_table *table =
502 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
503 u32 current_index =
504 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
505 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
506 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
507 u32 sclk, tmp;
508 u16 vddc;
509
510 if (current_index >= NUM_SCLK_LEVELS) {
511 seq_printf(m, "invalid dpm profile %d\n", current_index);
512 } else {
513 sclk = table->entries[current_index].clk;
514 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
515 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
516 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
517 vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
518 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
519 current_index, sclk, vddc);
520 }
521}
522
523static void cz_dpm_print_power_state(struct amdgpu_device *adev,
524 struct amdgpu_ps *rps)
525{
526 int i;
527 struct cz_ps *ps = cz_get_ps(rps);
528
529 amdgpu_dpm_print_class_info(rps->class, rps->class2);
530 amdgpu_dpm_print_cap_info(rps->caps);
531
532 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
533 for (i = 0; i < ps->num_levels; i++) {
534 struct cz_pl *pl = &ps->levels[i];
535
536 DRM_INFO("\t\tpower level %d sclk: %u vddc: %u\n",
537 i, pl->sclk,
538 cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
539 }
540
541 amdgpu_dpm_print_ps_status(adev, rps);
542}
543
544static void cz_dpm_set_funcs(struct amdgpu_device *adev);
545
5fc3aeeb 546static int cz_dpm_early_init(void *handle)
aaa36a97 547{
5fc3aeeb 548 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
549
aaa36a97
AD		 550 cz_dpm_set_funcs(adev);
551
552 return 0;
553}
554
564ea790 555
5fc3aeeb 556static int cz_dpm_late_init(void *handle)
564ea790 557{
5fc3aeeb 558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
559
564ea790
SJ		 560 /* powerdown unused blocks for now */
561 cz_dpm_powergate_uvd(adev, true);
b7a07769 562 cz_dpm_powergate_vce(adev, true);
564ea790
SJ		 563
564 return 0;
565}
566
5fc3aeeb 567static int cz_dpm_sw_init(void *handle)
aaa36a97 568{
5fc3aeeb 569 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 570 int ret = 0;
571 /* fix me to add thermal support TODO */
572
573 /* default to balanced state */
574 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
575 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
576 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
577 adev->pm.default_sclk = adev->clock.default_sclk;
578 adev->pm.default_mclk = adev->clock.default_mclk;
579 adev->pm.current_sclk = adev->clock.default_sclk;
580 adev->pm.current_mclk = adev->clock.default_mclk;
581 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
582
583 if (amdgpu_dpm == 0)
584 return 0;
585
586 mutex_lock(&adev->pm.mutex);
587 ret = cz_dpm_init(adev);
588 if (ret)
589 goto dpm_init_failed;
590
591 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
592 if (amdgpu_dpm == 1)
593 amdgpu_pm_print_power_states(adev);
594
595 ret = amdgpu_pm_sysfs_init(adev);
596 if (ret)
597 goto dpm_init_failed;
598
599 mutex_unlock(&adev->pm.mutex);
600 DRM_INFO("amdgpu: dpm initialized\n");
601
602 return 0;
603
604dpm_init_failed:
605 cz_dpm_fini(adev);
606 mutex_unlock(&adev->pm.mutex);
607 DRM_ERROR("amdgpu: dpm initialization failed\n");
608
609 return ret;
610}
611
5fc3aeeb 612static int cz_dpm_sw_fini(void *handle)
aaa36a97 613{
5fc3aeeb 614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
615
aaa36a97
AD		 616 mutex_lock(&adev->pm.mutex);
617 amdgpu_pm_sysfs_fini(adev);
618 cz_dpm_fini(adev);
619 mutex_unlock(&adev->pm.mutex);
620
621 return 0;
622}
623
624static void cz_reset_ap_mask(struct amdgpu_device *adev)
625{
626 struct cz_power_info *pi = cz_get_pi(adev);
627
628 pi->active_process_mask = 0;
629
630}
631
632static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
633 void **table)
634{
635 int ret = 0;
636
637 ret = cz_smu_download_pptable(adev, table);
638
639 return ret;
640}
641
642static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
643{
644 struct cz_power_info *pi = cz_get_pi(adev);
645 struct SMU8_Fusion_ClkTable *clock_table;
646 struct atom_clock_dividers dividers;
647 void *table = NULL;
648 uint8_t i = 0;
649 int ret = 0;
650
651 struct amdgpu_clock_voltage_dependency_table *vddc_table =
652 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
653 struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
654 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
655 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
656 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
657 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
658 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
659 struct amdgpu_clock_voltage_dependency_table *acp_table =
660 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
661
662 if (!pi->need_pptable_upload)
663 return 0;
664
665 ret = cz_dpm_download_pptable_from_smu(adev, &table);
666 if (ret) {
667 DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
668 return -EINVAL;
669 }
670
671 clock_table = (struct SMU8_Fusion_ClkTable *)table;
672 /* patch clock table */
673 if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
674 vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
675 uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
676 vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
677 acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
678 DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
679 return -EINVAL;
680 }
681
682 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
683
684 /* vddc sclk */
685 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
686 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
687 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
688 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
689 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
690 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
691 false, &dividers);
692 if (ret)
693 return ret;
694 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
695 (uint8_t)dividers.post_divider;
696
697 /* vddgfx sclk */
698 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
699 (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
700
701 /* acp breakdown */
702 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
703 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
704 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
705 (i < acp_table->count) ? acp_table->entries[i].clk : 0;
706 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
707 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
708 false, &dividers);
709 if (ret)
710 return ret;
711 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
712 (uint8_t)dividers.post_divider;
713
714 /* uvd breakdown */
715 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
716 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
717 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
718 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
719 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
720 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
721 false, &dividers);
722 if (ret)
723 return ret;
724 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
725 (uint8_t)dividers.post_divider;
726
727 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
728 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
729 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
730 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
731 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
732 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
733 false, &dividers);
734 if (ret)
735 return ret;
736 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
737 (uint8_t)dividers.post_divider;
738
739 /* vce breakdown */
740 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
741 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
742 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
743 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
744 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
745 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
746 false, &dividers);
747 if (ret)
748 return ret;
749 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
750 (uint8_t)dividers.post_divider;
751 }
752
753 /* its time to upload to SMU */
754 ret = cz_smu_upload_pptable(adev);
755 if (ret) {
756 DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
757 return ret;
758 }
759
760 return 0;
761}
762
763static void cz_init_sclk_limit(struct amdgpu_device *adev)
764{
765 struct cz_power_info *pi = cz_get_pi(adev);
766 struct amdgpu_clock_voltage_dependency_table *table =
767 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
768 uint32_t clock = 0, level;
769
770 if (!table || !table->count) {
771 DRM_ERROR("Invalid Voltage Dependency table.\n");
772 return;
773 }
774
775 pi->sclk_dpm.soft_min_clk = 0;
776 pi->sclk_dpm.hard_min_clk = 0;
777 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
778 level = cz_get_argument(adev);
779 if (level < table->count)
780 clock = table->entries[level].clk;
781 else {
782 DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
783 clock = table->entries[table->count - 1].clk;
784 }
785
786 pi->sclk_dpm.soft_max_clk = clock;
787 pi->sclk_dpm.hard_max_clk = clock;
788
789}
790
791static void cz_init_uvd_limit(struct amdgpu_device *adev)
792{
793 struct cz_power_info *pi = cz_get_pi(adev);
794 struct amdgpu_uvd_clock_voltage_dependency_table *table =
795 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
796 uint32_t clock = 0, level;
797
798 if (!table || !table->count) {
799 DRM_ERROR("Invalid Voltage Dependency table.\n");
800 return;
801 }
802
803 pi->uvd_dpm.soft_min_clk = 0;
804 pi->uvd_dpm.hard_min_clk = 0;
805 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
806 level = cz_get_argument(adev);
807 if (level < table->count)
808 clock = table->entries[level].vclk;
809 else {
810 DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
811 clock = table->entries[table->count - 1].vclk;
812 }
813
814 pi->uvd_dpm.soft_max_clk = clock;
815 pi->uvd_dpm.hard_max_clk = clock;
816
817}
818
819static void cz_init_vce_limit(struct amdgpu_device *adev)
820{
821 struct cz_power_info *pi = cz_get_pi(adev);
822 struct amdgpu_vce_clock_voltage_dependency_table *table =
823 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
824 uint32_t clock = 0, level;
825
826 if (!table || !table->count) {
827 DRM_ERROR("Invalid Voltage Dependency table.\n");
828 return;
829 }
830
b7a07769
SJ		 831 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
832 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
aaa36a97
AD		 833 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
834 level = cz_get_argument(adev);
835 if (level < table->count)
b7a07769 836 clock = table->entries[level].ecclk;
aaa36a97
AD		 837 else {
838 /* future BIOS would fix this error */
839 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
b7a07769 840 clock = table->entries[table->count - 1].ecclk;
aaa36a97
AD		 841 }
842
843 pi->vce_dpm.soft_max_clk = clock;
844 pi->vce_dpm.hard_max_clk = clock;
845
846}
847
848static void cz_init_acp_limit(struct amdgpu_device *adev)
849{
850 struct cz_power_info *pi = cz_get_pi(adev);
851 struct amdgpu_clock_voltage_dependency_table *table =
852 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
853 uint32_t clock = 0, level;
854
855 if (!table || !table->count) {
856 DRM_ERROR("Invalid Voltage Dependency table.\n");
857 return;
858 }
859
860 pi->acp_dpm.soft_min_clk = 0;
861 pi->acp_dpm.hard_min_clk = 0;
862 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
863 level = cz_get_argument(adev);
864 if (level < table->count)
865 clock = table->entries[level].clk;
866 else {
867 DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
868 clock = table->entries[table->count - 1].clk;
869 }
870
871 pi->acp_dpm.soft_max_clk = clock;
872 pi->acp_dpm.hard_max_clk = clock;
873
874}
875
876static void cz_init_pg_state(struct amdgpu_device *adev)
877{
878 struct cz_power_info *pi = cz_get_pi(adev);
879
880 pi->uvd_power_gated = false;
881 pi->vce_power_gated = false;
882 pi->acp_power_gated = false;
883
884}
885
886static void cz_init_sclk_threshold(struct amdgpu_device *adev)
887{
888 struct cz_power_info *pi = cz_get_pi(adev);
889
890 pi->low_sclk_interrupt_threshold = 0;
891
892}
893
894static void cz_dpm_setup_asic(struct amdgpu_device *adev)
895{
896 cz_reset_ap_mask(adev);
897 cz_dpm_upload_pptable_to_smu(adev);
898 cz_init_sclk_limit(adev);
899 cz_init_uvd_limit(adev);
900 cz_init_vce_limit(adev);
901 cz_init_acp_limit(adev);
902 cz_init_pg_state(adev);
903 cz_init_sclk_threshold(adev);
904
905}
906
907static bool cz_check_smu_feature(struct amdgpu_device *adev,
908 uint32_t feature)
909{
910 uint32_t smu_feature = 0;
911 int ret;
912
913 ret = cz_send_msg_to_smc_with_parameter(adev,
914 PPSMC_MSG_GetFeatureStatus, 0);
915 if (ret) {
916 DRM_ERROR("Failed to get SMU features from SMC.\n");
917 return false;
918 } else {
919 smu_feature = cz_get_argument(adev);
920 if (feature & smu_feature)
921 return true;
922 }
923
924 return false;
925}
926
927static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
928{
929 if (cz_check_smu_feature(adev,
930 SMU_EnabledFeatureScoreboard_SclkDpmOn))
931 return true;
932
933 return false;
934}
935
936static void cz_program_voting_clients(struct amdgpu_device *adev)
937{
938 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
939}
940
941static void cz_clear_voting_clients(struct amdgpu_device *adev)
942{
943 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
944}
945
946static int cz_start_dpm(struct amdgpu_device *adev)
947{
948 int ret = 0;
949
950 if (amdgpu_dpm) {
951 ret = cz_send_msg_to_smc_with_parameter(adev,
952 PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
953 if (ret) {
954 DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
955 return -EINVAL;
956 }
957 }
958
959 return 0;
960}
961
962static int cz_stop_dpm(struct amdgpu_device *adev)
963{
964 int ret = 0;
965
966 if (amdgpu_dpm && adev->pm.dpm_enabled) {
967 ret = cz_send_msg_to_smc_with_parameter(adev,
968 PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
969 if (ret) {
970 DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
971 return -EINVAL;
972 }
973 }
974
975 return 0;
976}
977
978static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
979 uint32_t clock, uint16_t msg)
980{
981 int i = 0;
982 struct amdgpu_clock_voltage_dependency_table *table =
983 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
984
985 switch (msg) {
986 case PPSMC_MSG_SetSclkSoftMin:
987 case PPSMC_MSG_SetSclkHardMin:
988 for (i = 0; i < table->count; i++)
989 if (clock <= table->entries[i].clk)
990 break;
991 if (i == table->count)
992 i = table->count - 1;
993 break;
994 case PPSMC_MSG_SetSclkSoftMax:
995 case PPSMC_MSG_SetSclkHardMax:
996 for (i = table->count - 1; i >= 0; i--)
997 if (clock >= table->entries[i].clk)
998 break;
999 if (i < 0)
1000 i = 0;
1001 break;
1002 default:
1003 break;
1004 }
1005
1006 return i;
1007}
1008
b7a07769
SJ		 1009static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1010 uint32_t clock, uint16_t msg)
1011{
1012 int i = 0;
1013 struct amdgpu_vce_clock_voltage_dependency_table *table =
1014 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1015
1016 if (table->count == 0)
1017 return 0;
1018
1019 switch (msg) {
1020 case PPSMC_MSG_SetEclkSoftMin:
1021 case PPSMC_MSG_SetEclkHardMin:
1022 for (i = 0; i < table->count-1; i++)
1023 if (clock <= table->entries[i].ecclk)
1024 break;
1025 break;
1026 case PPSMC_MSG_SetEclkSoftMax:
1027 case PPSMC_MSG_SetEclkHardMax:
1028 for (i = table->count - 1; i > 0; i--)
1029 if (clock >= table->entries[i].ecclk)
1030 break;
1031 break;
1032 default:
1033 break;
1034 }
1035
1036 return i;
1037}
1038
aaa36a97
AD		 1039static int cz_program_bootup_state(struct amdgpu_device *adev)
1040{
1041 struct cz_power_info *pi = cz_get_pi(adev);
1042 uint32_t soft_min_clk = 0;
1043 uint32_t soft_max_clk = 0;
1044 int ret = 0;
1045
1046 pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
1047 pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
1048
1049 soft_min_clk = cz_get_sclk_level(adev,
1050 pi->sclk_dpm.soft_min_clk,
1051 PPSMC_MSG_SetSclkSoftMin);
1052 soft_max_clk = cz_get_sclk_level(adev,
1053 pi->sclk_dpm.soft_max_clk,
1054 PPSMC_MSG_SetSclkSoftMax);
1055
1056 ret = cz_send_msg_to_smc_with_parameter(adev,
1057 PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
1058 if (ret)
1059 return -EINVAL;
1060
1061 ret = cz_send_msg_to_smc_with_parameter(adev,
1062 PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
1063 if (ret)
1064 return -EINVAL;
1065
1066 return 0;
1067}
1068
1069/* TODO */
1070static int cz_disable_cgpg(struct amdgpu_device *adev)
1071{
1072 return 0;
1073}
1074
1075/* TODO */
1076static int cz_enable_cgpg(struct amdgpu_device *adev)
1077{
1078 return 0;
1079}
1080
1081/* TODO */
1082static int cz_program_pt_config_registers(struct amdgpu_device *adev)
1083{
1084 return 0;
1085}
1086
1087static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
1088{
1089 struct cz_power_info *pi = cz_get_pi(adev);
1090 uint32_t reg = 0;
1091
1092 if (pi->caps_sq_ramping) {
1093 reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
1094 if (enable)
1095 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1096 else
1097 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1098 WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
1099 }
1100 if (pi->caps_db_ramping) {
1101 reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
1102 if (enable)
1103 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
1104 else
1105 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
1106 WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
1107 }
1108 if (pi->caps_td_ramping) {
1109 reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
1110 if (enable)
1111 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
1112 else
1113 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
1114 WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
1115 }
1116 if (pi->caps_tcp_ramping) {
1117 reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
1118 if (enable)
1119 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1120 else
1121 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1122 WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
1123 }
1124
1125}
1126
1127static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
1128{
1129 struct cz_power_info *pi = cz_get_pi(adev);
1130 int ret;
1131
1132 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
1133 pi->caps_td_ramping || pi->caps_tcp_ramping) {
1134 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
1135 ret = cz_disable_cgpg(adev);
1136 if (ret) {
1137 DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
1138 return -EINVAL;
1139 }
1140 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
1141 }
1142
1143 ret = cz_program_pt_config_registers(adev);
1144 if (ret) {
1145 DRM_ERROR("Di/Dt config failed\n");
1146 return -EINVAL;
1147 }
1148 cz_do_enable_didt(adev, enable);
1149
1150 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
1151 ret = cz_enable_cgpg(adev);
1152 if (ret) {
1153 DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
1154 return -EINVAL;
1155 }
1156 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1157 }
1158 }
1159
1160 return 0;
1161}
1162
1163/* TODO */
1164static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
1165{
1166}
1167
1168static void cz_update_current_ps(struct amdgpu_device *adev,
1169 struct amdgpu_ps *rps)
1170{
1171 struct cz_power_info *pi = cz_get_pi(adev);
1172 struct cz_ps *ps = cz_get_ps(rps);
1173
1174 pi->current_ps = *ps;
1175 pi->current_rps = *rps;
1176 pi->current_rps.ps_priv = ps;
1177
1178}
1179
1180static void cz_update_requested_ps(struct amdgpu_device *adev,
1181 struct amdgpu_ps *rps)
1182{
1183 struct cz_power_info *pi = cz_get_pi(adev);
1184 struct cz_ps *ps = cz_get_ps(rps);
1185
1186 pi->requested_ps = *ps;
1187 pi->requested_rps = *rps;
1188 pi->requested_rps.ps_priv = ps;
1189
1190}
1191
1192/* PP arbiter support needed TODO */
1193static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1194 struct amdgpu_ps *new_rps,
1195 struct amdgpu_ps *old_rps)
1196{
1197 struct cz_ps *ps = cz_get_ps(new_rps);
1198 struct cz_power_info *pi = cz_get_pi(adev);
1199 struct amdgpu_clock_and_voltage_limits *limits =
1200 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1201 /* 10kHz memory clock */
1202 uint32_t mclk = 0;
1203
1204 ps->force_high = false;
1205 ps->need_dfs_bypass = true;
1206 pi->video_start = new_rps->dclk || new_rps->vclk ||
1207 new_rps->evclk || new_rps->ecclk;
1208
1209 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1210 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1211 pi->battery_state = true;
1212 else
1213 pi->battery_state = false;
1214
1215 if (pi->caps_stable_power_state)
1216 mclk = limits->mclk;
1217
1218 if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
1219 ps->force_high = true;
1220
1221}
1222
1223static int cz_dpm_enable(struct amdgpu_device *adev)
1224{
1225 int ret = 0;
1226
1227 /* renable will hang up SMU, so check first */
1228 if (cz_check_for_dpm_enabled(adev))
1229 return -EINVAL;
1230
1231 cz_program_voting_clients(adev);
1232
1233 ret = cz_start_dpm(adev);
1234 if (ret) {
1235 DRM_ERROR("Carrizo DPM enable failed\n");
1236 return -EINVAL;
1237 }
1238
1239 ret = cz_program_bootup_state(adev);
1240 if (ret) {
1241 DRM_ERROR("Carrizo bootup state program failed\n");
1242 return -EINVAL;
1243 }
1244
1245 ret = cz_enable_didt(adev, true);
1246 if (ret) {
1247 DRM_ERROR("Carrizo enable di/dt failed\n");
1248 return -EINVAL;
1249 }
1250
1251 cz_reset_acp_boot_level(adev);
1252
1253 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1254
1255 return 0;
1256}
1257
5fc3aeeb 1258static int cz_dpm_hw_init(void *handle)
aaa36a97 1259{
5fc3aeeb 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
46651cc5 1261 int ret = 0;
aaa36a97
AD		 1262
1263 mutex_lock(&adev->pm.mutex);
1264
05188312
AD		 1265 /* smu init only needs to be called at startup, not resume.
1266 * It should be in sw_init, but requires the fw info gathered
1267 * in sw_init from other IP modules.
1268 */
aaa36a97
AD		 1269 ret = cz_smu_init(adev);
1270 if (ret) {
1271 DRM_ERROR("amdgpu: smc initialization failed\n");
1272 mutex_unlock(&adev->pm.mutex);
1273 return ret;
1274 }
1275
1276 /* do the actual fw loading */
1277 ret = cz_smu_start(adev);
1278 if (ret) {
1279 DRM_ERROR("amdgpu: smc start failed\n");
1280 mutex_unlock(&adev->pm.mutex);
1281 return ret;
1282 }
1283
46651cc5
SJ		 1284 if (!amdgpu_dpm) {
1285 adev->pm.dpm_enabled = false;
1286 mutex_unlock(&adev->pm.mutex);
1287 return ret;
1288 }
1289
aaa36a97
AD		 1290 /* cz dpm setup asic */
1291 cz_dpm_setup_asic(adev);
1292
1293 /* cz dpm enable */
1294 ret = cz_dpm_enable(adev);
1295 if (ret)
1296 adev->pm.dpm_enabled = false;
1297 else
1298 adev->pm.dpm_enabled = true;
1299
1300 mutex_unlock(&adev->pm.mutex);
1301
1302 return 0;
1303}
1304
1305static int cz_dpm_disable(struct amdgpu_device *adev)
1306{
1307 int ret = 0;
1308
1309 if (!cz_check_for_dpm_enabled(adev))
1310 return -EINVAL;
1311
1312 ret = cz_enable_didt(adev, false);
1313 if (ret) {
1314 DRM_ERROR("Carrizo disable di/dt failed\n");
1315 return -EINVAL;
1316 }
1317
564ea790
SJ		 1318 /* powerup blocks */
1319 cz_dpm_powergate_uvd(adev, false);
b7a07769 1320 cz_dpm_powergate_vce(adev, false);
564ea790 1321
aaa36a97
AD		 1322 cz_clear_voting_clients(adev);
1323 cz_stop_dpm(adev);
1324 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1325
1326 return 0;
1327}
1328
5fc3aeeb 1329static int cz_dpm_hw_fini(void *handle)
aaa36a97
AD		 1330{
1331 int ret = 0;
5fc3aeeb 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1333
1334 mutex_lock(&adev->pm.mutex);
1335
05188312
AD		 1336 /* smu fini only needs to be called at teardown, not suspend.
1337 * It should be in sw_fini, but we put it here for symmetry
1338 * with smu init.
1339 */
aaa36a97
AD		 1340 cz_smu_fini(adev);
1341
1342 if (adev->pm.dpm_enabled) {
1343 ret = cz_dpm_disable(adev);
aaa36a97
AD		 1344
1345 adev->pm.dpm.current_ps =
1346 adev->pm.dpm.requested_ps =
1347 adev->pm.dpm.boot_ps;
1348 }
1349
1350 adev->pm.dpm_enabled = false;
1351
1352 mutex_unlock(&adev->pm.mutex);
1353
10457457 1354 return ret;
aaa36a97
AD		 1355}
1356
5fc3aeeb 1357static int cz_dpm_suspend(void *handle)
aaa36a97
AD		 1358{
1359 int ret = 0;
5fc3aeeb 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1361
1362 if (adev->pm.dpm_enabled) {
1363 mutex_lock(&adev->pm.mutex);
1364
1365 ret = cz_dpm_disable(adev);
aaa36a97
AD		 1366
1367 adev->pm.dpm.current_ps =
1368 adev->pm.dpm.requested_ps =
1369 adev->pm.dpm.boot_ps;
1370
1371 mutex_unlock(&adev->pm.mutex);
1372 }
1373
10457457 1374 return ret;
aaa36a97
AD		 1375}
1376
5fc3aeeb 1377static int cz_dpm_resume(void *handle)
aaa36a97
AD		 1378{
1379 int ret = 0;
5fc3aeeb 1380 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1381
1382 mutex_lock(&adev->pm.mutex);
aaa36a97
AD		 1383
1384 /* do the actual fw loading */
1385 ret = cz_smu_start(adev);
1386 if (ret) {
1387 DRM_ERROR("amdgpu: smc start failed\n");
1388 mutex_unlock(&adev->pm.mutex);
1389 return ret;
1390 }
1391
46651cc5
SJ		 1392 if (!amdgpu_dpm) {
1393 adev->pm.dpm_enabled = false;
1394 mutex_unlock(&adev->pm.mutex);
1395 return ret;
1396 }
1397
aaa36a97
AD		 1398 /* cz dpm setup asic */
1399 cz_dpm_setup_asic(adev);
1400
1401 /* cz dpm enable */
1402 ret = cz_dpm_enable(adev);
1403 if (ret)
1404 adev->pm.dpm_enabled = false;
1405 else
1406 adev->pm.dpm_enabled = true;
1407
1408 mutex_unlock(&adev->pm.mutex);
1409 /* upon resume, re-compute the clocks */
1410 if (adev->pm.dpm_enabled)
1411 amdgpu_pm_compute_clocks(adev);
1412
1413 return 0;
1414}
1415
5fc3aeeb 1416static int cz_dpm_set_clockgating_state(void *handle,
1417 enum amd_clockgating_state state)
aaa36a97
AD		 1418{
1419 return 0;
1420}
1421
5fc3aeeb 1422static int cz_dpm_set_powergating_state(void *handle,
1423 enum amd_powergating_state state)
aaa36a97
AD		 1424{
1425 return 0;
1426}
1427
1428/* borrowed from KV, need future unify */
1429static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1430{
1431 int actual_temp = 0;
1432 uint32_t temp = RREG32_SMC(0xC0300E0C);
1433
1434 if (temp)
1435 actual_temp = 1000 * ((temp / 8) - 49);
1436
1437 return actual_temp;
1438}
1439
1440static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
1441{
1442 struct cz_power_info *pi = cz_get_pi(adev);
1443 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1444 struct amdgpu_ps *new_ps = &requested_ps;
1445
1446 cz_update_requested_ps(adev, new_ps);
1447 cz_apply_state_adjust_rules(adev, &pi->requested_rps,
1448 &pi->current_rps);
1449
1450 return 0;
1451}
1452
1453static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
1454{
1455 struct cz_power_info *pi = cz_get_pi(adev);
1456 struct amdgpu_clock_and_voltage_limits *limits =
1457 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1458 uint32_t clock, stable_ps_clock = 0;
1459
1460 clock = pi->sclk_dpm.soft_min_clk;
1461
1462 if (pi->caps_stable_power_state) {
1463 stable_ps_clock = limits->sclk * 75 / 100;
1464 if (clock < stable_ps_clock)
1465 clock = stable_ps_clock;
1466 }
1467
1468 if (clock != pi->sclk_dpm.soft_min_clk) {
1469 pi->sclk_dpm.soft_min_clk = clock;
1470 cz_send_msg_to_smc_with_parameter(adev,
1471 PPSMC_MSG_SetSclkSoftMin,
1472 cz_get_sclk_level(adev, clock,
1473 PPSMC_MSG_SetSclkSoftMin));
1474 }
1475
1476 if (pi->caps_stable_power_state &&
1477 pi->sclk_dpm.soft_max_clk != clock) {
1478 pi->sclk_dpm.soft_max_clk = clock;
1479 cz_send_msg_to_smc_with_parameter(adev,
1480 PPSMC_MSG_SetSclkSoftMax,
1481 cz_get_sclk_level(adev, clock,
1482 PPSMC_MSG_SetSclkSoftMax));
1483 } else {
1484 cz_send_msg_to_smc_with_parameter(adev,
1485 PPSMC_MSG_SetSclkSoftMax,
1486 cz_get_sclk_level(adev,
1487 pi->sclk_dpm.soft_max_clk,
1488 PPSMC_MSG_SetSclkSoftMax));
1489 }
1490
1491 return 0;
1492}
1493
1494static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
1495{
1496 int ret = 0;
1497 struct cz_power_info *pi = cz_get_pi(adev);
1498
1499 if (pi->caps_sclk_ds) {
1500 cz_send_msg_to_smc_with_parameter(adev,
1501 PPSMC_MSG_SetMinDeepSleepSclk,
1502 CZ_MIN_DEEP_SLEEP_SCLK);
1503 }
1504
1505 return ret;
1506}
1507
1508/* ?? without dal support, is this still needed in setpowerstate list*/
1509static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
1510{
1511 int ret = 0;
1512 struct cz_power_info *pi = cz_get_pi(adev);
1513
1514 cz_send_msg_to_smc_with_parameter(adev,
1515 PPSMC_MSG_SetWatermarkFrequency,
1516 pi->sclk_dpm.soft_max_clk);
1517
1518 return ret;
1519}
1520
1521static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
1522{
1523 int ret = 0;
1524 struct cz_power_info *pi = cz_get_pi(adev);
1525
1526 /* also depend on dal NBPStateDisableRequired */
1527 if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
1528 ret = cz_send_msg_to_smc_with_parameter(adev,
1529 PPSMC_MSG_EnableAllSmuFeatures,
1530 NB_DPM_MASK);
1531 if (ret) {
1532 DRM_ERROR("amdgpu: nb dpm enable failed\n");
1533 return ret;
1534 }
1535 pi->nb_dpm_enabled = true;
1536 }
1537
1538 return ret;
1539}
1540
1541static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
1542 bool enable)
1543{
1544 if (enable)
1545 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
1546 else
1547 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
1548
1549}
1550
1551static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
1552{
1553 int ret = 0;
1554 struct cz_power_info *pi = cz_get_pi(adev);
1555 struct cz_ps *ps = &pi->requested_ps;
1556
1557 if (pi->sys_info.nb_dpm_enable) {
1558 if (ps->force_high)
1559 cz_dpm_nbdpm_lm_pstate_enable(adev, true);
1560 else
1561 cz_dpm_nbdpm_lm_pstate_enable(adev, false);
1562 }
1563
1564 return ret;
1565}
1566
1567/* with dpm enabled */
1568static int cz_dpm_set_power_state(struct amdgpu_device *adev)
1569{
1570 int ret = 0;
1571
1572 cz_dpm_update_sclk_limit(adev);
1573 cz_dpm_set_deep_sleep_sclk_threshold(adev);
1574 cz_dpm_set_watermark_threshold(adev);
1575 cz_dpm_enable_nbdpm(adev);
1576 cz_dpm_update_low_memory_pstate(adev);
1577
1578 return ret;
1579}
1580
1581static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
1582{
1583 struct cz_power_info *pi = cz_get_pi(adev);
1584 struct amdgpu_ps *ps = &pi->requested_rps;
1585
1586 cz_update_current_ps(adev, ps);
1587
1588}
1589
1590static int cz_dpm_force_highest(struct amdgpu_device *adev)
1591{
1592 struct cz_power_info *pi = cz_get_pi(adev);
1593 int ret = 0;
1594
1595 if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
1596 pi->sclk_dpm.soft_min_clk =
1597 pi->sclk_dpm.soft_max_clk;
1598 ret = cz_send_msg_to_smc_with_parameter(adev,
1599 PPSMC_MSG_SetSclkSoftMin,
1600 cz_get_sclk_level(adev,
1601 pi->sclk_dpm.soft_min_clk,
1602 PPSMC_MSG_SetSclkSoftMin));
1603 if (ret)
1604 return ret;
1605 }
1606
1607 return ret;
1608}
1609
1610static int cz_dpm_force_lowest(struct amdgpu_device *adev)
1611{
1612 struct cz_power_info *pi = cz_get_pi(adev);
1613 int ret = 0;
1614
1615 if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
1616 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
1617 ret = cz_send_msg_to_smc_with_parameter(adev,
1618 PPSMC_MSG_SetSclkSoftMax,
1619 cz_get_sclk_level(adev,
1620 pi->sclk_dpm.soft_max_clk,
1621 PPSMC_MSG_SetSclkSoftMax));
1622 if (ret)
1623 return ret;
1624 }
1625
1626 return ret;
1627}
1628
1629static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
1630{
1631 struct cz_power_info *pi = cz_get_pi(adev);
1632
1633 if (!pi->max_sclk_level) {
1634 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
1635 pi->max_sclk_level = cz_get_argument(adev) + 1;
1636 }
1637
1638 if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1639 DRM_ERROR("Invalid max sclk level!\n");
1640 return -EINVAL;
1641 }
1642
1643 return pi->max_sclk_level;
1644}
1645
1646static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1647{
1648 struct cz_power_info *pi = cz_get_pi(adev);
1649 struct amdgpu_clock_voltage_dependency_table *dep_table =
1650 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1651 uint32_t level = 0;
1652 int ret = 0;
1653
1654 pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
1655 level = cz_dpm_get_max_sclk_level(adev) - 1;
1656 if (level < dep_table->count)
1657 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
1658 else
1659 pi->sclk_dpm.soft_max_clk =
1660 dep_table->entries[dep_table->count - 1].clk;
1661
1662 /* get min/max sclk soft value
1663 * notify SMU to execute */
1664 ret = cz_send_msg_to_smc_with_parameter(adev,
1665 PPSMC_MSG_SetSclkSoftMin,
1666 cz_get_sclk_level(adev,
1667 pi->sclk_dpm.soft_min_clk,
1668 PPSMC_MSG_SetSclkSoftMin));
1669 if (ret)
1670 return ret;
1671
1672 ret = cz_send_msg_to_smc_with_parameter(adev,
1673 PPSMC_MSG_SetSclkSoftMax,
1674 cz_get_sclk_level(adev,
1675 pi->sclk_dpm.soft_max_clk,
1676 PPSMC_MSG_SetSclkSoftMax));
1677 if (ret)
1678 return ret;
1679
1680 DRM_INFO("DPM unforce state min=%d, max=%d.\n",
1681 pi->sclk_dpm.soft_min_clk,
1682 pi->sclk_dpm.soft_max_clk);
1683
1684 return 0;
1685}
1686
1687static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1688 enum amdgpu_dpm_forced_level level)
1689{
1690 int ret = 0;
1691
1692 switch (level) {
1693 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
1694 ret = cz_dpm_force_highest(adev);
1695 if (ret)
1696 return ret;
1697 break;
1698 case AMDGPU_DPM_FORCED_LEVEL_LOW:
1699 ret = cz_dpm_force_lowest(adev);
1700 if (ret)
1701 return ret;
1702 break;
1703 case AMDGPU_DPM_FORCED_LEVEL_AUTO:
1704 ret = cz_dpm_unforce_dpm_levels(adev);
1705 if (ret)
1706 return ret;
1707 break;
1708 default:
1709 break;
1710 }
1711
1712 return ret;
1713}
1714
1715/* fix me, display configuration change lists here
1716 * mostly dal related*/
1717static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
1718{
1719}
1720
1721static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
1722{
1723 struct cz_power_info *pi = cz_get_pi(adev);
1724 struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
1725
1726 if (low)
1727 return requested_state->levels[0].sclk;
1728 else
1729 return requested_state->levels[requested_state->num_levels - 1].sclk;
1730
1731}
1732
1733static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
1734{
1735 struct cz_power_info *pi = cz_get_pi(adev);
1736
1737 return pi->sys_info.bootup_uma_clk;
1738}
1739
564ea790
SJ		 1740static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1741{
1742 struct cz_power_info *pi = cz_get_pi(adev);
1743 int ret = 0;
1744
1745 if (enable && pi->caps_uvd_dpm ) {
1746 pi->dpm_flags |= DPMFlags_UVD_Enabled;
1747 DRM_DEBUG("UVD DPM Enabled.\n");
1748
1749 ret = cz_send_msg_to_smc_with_parameter(adev,
1750 PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK);
1751 } else {
1752 pi->dpm_flags &= ~DPMFlags_UVD_Enabled;
1753 DRM_DEBUG("UVD DPM Stopped\n");
1754
1755 ret = cz_send_msg_to_smc_with_parameter(adev,
1756 PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK);
1757 }
1758
1759 return ret;
1760}
1761
1762static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1763{
1764 return cz_enable_uvd_dpm(adev, !gate);
1765}
1766
1767
1768static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1769{
1770 struct cz_power_info *pi = cz_get_pi(adev);
1771 int ret;
1772
1773 if (pi->uvd_power_gated == gate)
1774 return;
1775
1776 pi->uvd_power_gated = gate;
1777
1778 if (gate) {
1779 if (pi->caps_uvd_pg) {
1780 /* disable clockgating so we can properly shut down the block */
5fc3aeeb 1781 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1782 AMD_CG_STATE_UNGATE);
564ea790 1783 /* shutdown the UVD block */
5fc3aeeb 1784 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1785 AMD_PG_STATE_GATE);
564ea790
SJ		 1786 /* XXX: check for errors */
1787 }
1788 cz_update_uvd_dpm(adev, gate);
1789 if (pi->caps_uvd_pg)
1790 /* power off the UVD block */
1791 cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
1792 } else {
1793 if (pi->caps_uvd_pg) {
1794 /* power on the UVD block */
1795 if (pi->uvd_dynamic_pg)
1796 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
1797 else
1798 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
1799 /* re-init the UVD block */
5fc3aeeb 1800 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1801 AMD_PG_STATE_UNGATE);
564ea790 1802 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
5fc3aeeb 1803 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1804 AMD_CG_STATE_GATE);
564ea790
SJ		 1805 /* XXX: check for errors */
1806 }
1807 cz_update_uvd_dpm(adev, gate);
1808 }
1809}
1810
b7a07769
SJ		 1811static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1812{
1813 struct cz_power_info *pi = cz_get_pi(adev);
1814 int ret = 0;
1815
1816 if (enable && pi->caps_vce_dpm) {
1817 pi->dpm_flags |= DPMFlags_VCE_Enabled;
1818 DRM_DEBUG("VCE DPM Enabled.\n");
1819
1820 ret = cz_send_msg_to_smc_with_parameter(adev,
1821 PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
1822
1823 } else {
1824 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
1825 DRM_DEBUG("VCE DPM Stopped\n");
1826
1827 ret = cz_send_msg_to_smc_with_parameter(adev,
1828 PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
1829 }
1830
1831 return ret;
1832}
1833
1834static int cz_update_vce_dpm(struct amdgpu_device *adev)
1835{
1836 struct cz_power_info *pi = cz_get_pi(adev);
1837 struct amdgpu_vce_clock_voltage_dependency_table *table =
1838 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1839
1840 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1841 if (pi->caps_stable_power_state) {
1842 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
1843
1844 } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
1845 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
1846 }
1847
1848 cz_send_msg_to_smc_with_parameter(adev,
1849 PPSMC_MSG_SetEclkHardMin,
1850 cz_get_eclk_level(adev,
1851 pi->vce_dpm.hard_min_clk,
1852 PPSMC_MSG_SetEclkHardMin));
1853 return 0;
1854}
1855
1856static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1857{
1858 struct cz_power_info *pi = cz_get_pi(adev);
1859
1860 if (pi->caps_vce_pg) {
1861 if (pi->vce_power_gated != gate) {
1862 if (gate) {
1863 /* disable clockgating so we can properly shut down the block */
1864 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1865 AMD_CG_STATE_UNGATE);
1866 /* shutdown the VCE block */
1867 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1868 AMD_PG_STATE_GATE);
1869
1870 cz_enable_vce_dpm(adev, false);
1871 /* TODO: to figure out why vce can't be poweroff. */
1872 /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
1873 pi->vce_power_gated = true;
1874 } else {
1875 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
1876 pi->vce_power_gated = false;
1877
1878 /* re-init the VCE block */
1879 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1880 AMD_PG_STATE_UNGATE);
1881 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1882 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1883 AMD_CG_STATE_GATE);
1884
1885 cz_update_vce_dpm(adev);
1886 cz_enable_vce_dpm(adev, true);
1887 }
1888 } else {
1889 if (! pi->vce_power_gated) {
1890 cz_update_vce_dpm(adev);
1891 }
1892 }
1893 } else { /*pi->caps_vce_pg*/
1894 cz_update_vce_dpm(adev);
1895 cz_enable_vce_dpm(adev, true);
1896 }
1897
1898 return;
1899}
1900
5fc3aeeb 1901const struct amd_ip_funcs cz_dpm_ip_funcs = {
aaa36a97 1902 .early_init = cz_dpm_early_init,
564ea790 1903 .late_init = cz_dpm_late_init,
aaa36a97
AD		 1904 .sw_init = cz_dpm_sw_init,
1905 .sw_fini = cz_dpm_sw_fini,
1906 .hw_init = cz_dpm_hw_init,
1907 .hw_fini = cz_dpm_hw_fini,
1908 .suspend = cz_dpm_suspend,
1909 .resume = cz_dpm_resume,
1910 .is_idle = NULL,
1911 .wait_for_idle = NULL,
1912 .soft_reset = NULL,
1913 .print_status = NULL,
1914 .set_clockgating_state = cz_dpm_set_clockgating_state,
1915 .set_powergating_state = cz_dpm_set_powergating_state,
1916};
1917
1918static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
1919 .get_temperature = cz_dpm_get_temperature,
1920 .pre_set_power_state = cz_dpm_pre_set_power_state,
1921 .set_power_state = cz_dpm_set_power_state,
1922 .post_set_power_state = cz_dpm_post_set_power_state,
1923 .display_configuration_changed = cz_dpm_display_configuration_changed,
1924 .get_sclk = cz_dpm_get_sclk,
1925 .get_mclk = cz_dpm_get_mclk,
1926 .print_power_state = cz_dpm_print_power_state,
1927 .debugfs_print_current_performance_level =
1928 cz_dpm_debugfs_print_current_performance_level,
1929 .force_performance_level = cz_dpm_force_dpm_level,
1930 .vblank_too_short = NULL,
564ea790 1931 .powergate_uvd = cz_dpm_powergate_uvd,
b7a07769 1932 .powergate_vce = cz_dpm_powergate_vce,
aaa36a97
AD		 1933};
1934
1935static void cz_dpm_set_funcs(struct amdgpu_device *adev)
1936{
1937 if (NULL == adev->pm.funcs)
1938 adev->pm.funcs = &cz_dpm_funcs;
1939}
Linux kernel - Deliverables
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