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drm/amdgpu/cz: implement voltage validation properly
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cz_dpm.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/seq_file.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_atombios.h"
30#include "vid.h"
31#include "vi_dpm.h"
32#include "amdgpu_dpm.h"
33#include "cz_dpm.h"
34#include "cz_ppsmc.h"
35#include "atom.h"
36
37#include "smu/smu_8_0_d.h"
38#include "smu/smu_8_0_sh_mask.h"
39#include "gca/gfx_8_0_d.h"
40#include "gca/gfx_8_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "bif/bif_5_1_d.h"
43#include "gfx_v8_0.h"
44
564ea790 45static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
b7a07769 46static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
564ea790 47
aaa36a97
AD		 48static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
49{
50 struct cz_ps *ps = rps->ps_priv;
51
52 return ps;
53}
54
55static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
56{
57 struct cz_power_info *pi = adev->pm.dpm.priv;
58
59 return pi;
60}
61
62static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
63 uint16_t voltage)
64{
65 uint16_t tmp = 6200 - voltage * 25;
66
67 return tmp;
68}
69
70static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
71 struct amdgpu_clock_and_voltage_limits *table)
72{
73 struct cz_power_info *pi = cz_get_pi(adev);
74 struct amdgpu_clock_voltage_dependency_table *dep_table =
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
76
77 if (dep_table->count > 0) {
78 table->sclk = dep_table->entries[dep_table->count - 1].clk;
79 table->vddc = cz_convert_8bit_index_to_voltage(adev,
80 dep_table->entries[dep_table->count - 1].v);
81 }
82
83 table->mclk = pi->sys_info.nbp_memory_clock[0];
84
85}
86
87union igp_info {
88 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
89 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
90 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
91 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
92};
93
94static int cz_parse_sys_info_table(struct amdgpu_device *adev)
95{
96 struct cz_power_info *pi = cz_get_pi(adev);
97 struct amdgpu_mode_info *mode_info = &adev->mode_info;
98 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
99 union igp_info *igp_info;
100 u8 frev, crev;
101 u16 data_offset;
102 int i = 0;
103
104 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
105 &frev, &crev, &data_offset)) {
106 igp_info = (union igp_info *)(mode_info->atom_context->bios +
107 data_offset);
108
109 if (crev != 9) {
110 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
111 return -EINVAL;
112 }
113 pi->sys_info.bootup_sclk =
114 le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
115 pi->sys_info.bootup_uma_clk =
116 le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
117 pi->sys_info.dentist_vco_freq =
118 le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
119 pi->sys_info.bootup_nb_voltage_index =
120 le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
121
122 if (igp_info->info_9.ucHtcTmpLmt == 0)
123 pi->sys_info.htc_tmp_lmt = 203;
124 else
125 pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
126
127 if (igp_info->info_9.ucHtcHystLmt == 0)
128 pi->sys_info.htc_hyst_lmt = 5;
129 else
130 pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
131
132 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
133 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
134 return -EINVAL;
135 }
136
137 if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
138 pi->enable_nb_ps_policy)
139 pi->sys_info.nb_dpm_enable = true;
140 else
141 pi->sys_info.nb_dpm_enable = false;
142
143 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
144 if (i < CZ_NUM_NBPMEMORY_CLOCK)
145 pi->sys_info.nbp_memory_clock[i] =
146 le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
147 pi->sys_info.nbp_n_clock[i] =
148 le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
149 }
150
151 for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
152 pi->sys_info.display_clock[i] =
153 le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
154
155 for (i = 0; i < CZ_NUM_NBPSTATES; i++)
156 pi->sys_info.nbp_voltage_index[i] =
157 le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
158
159 if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
160 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
161 pi->caps_enable_dfs_bypass = true;
162
163 pi->sys_info.uma_channel_number =
164 igp_info->info_9.ucUMAChannelNumber;
165
166 cz_construct_max_power_limits_table(adev,
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
168 }
169
170 return 0;
171}
172
173static void cz_patch_voltage_values(struct amdgpu_device *adev)
174{
175 int i;
176 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
178 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
180 struct amdgpu_clock_voltage_dependency_table *acp_table =
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
182
183 if (uvd_table->count) {
184 for (i = 0; i < uvd_table->count; i++)
185 uvd_table->entries[i].v =
186 cz_convert_8bit_index_to_voltage(adev,
187 uvd_table->entries[i].v);
188 }
189
190 if (vce_table->count) {
191 for (i = 0; i < vce_table->count; i++)
192 vce_table->entries[i].v =
193 cz_convert_8bit_index_to_voltage(adev,
194 vce_table->entries[i].v);
195 }
196
197 if (acp_table->count) {
198 for (i = 0; i < acp_table->count; i++)
199 acp_table->entries[i].v =
200 cz_convert_8bit_index_to_voltage(adev,
201 acp_table->entries[i].v);
202 }
203
204}
205
206static void cz_construct_boot_state(struct amdgpu_device *adev)
207{
208 struct cz_power_info *pi = cz_get_pi(adev);
209
210 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
211 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
212 pi->boot_pl.ds_divider_index = 0;
213 pi->boot_pl.ss_divider_index = 0;
214 pi->boot_pl.allow_gnb_slow = 1;
215 pi->boot_pl.force_nbp_state = 0;
216 pi->boot_pl.display_wm = 0;
217 pi->boot_pl.vce_wm = 0;
218
219}
220
221static void cz_patch_boot_state(struct amdgpu_device *adev,
222 struct cz_ps *ps)
223{
224 struct cz_power_info *pi = cz_get_pi(adev);
225
226 ps->num_levels = 1;
227 ps->levels[0] = pi->boot_pl;
228}
229
230union pplib_clock_info {
231 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
232 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
233 struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
234};
235
236static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
237 struct amdgpu_ps *rps, int index,
238 union pplib_clock_info *clock_info)
239{
240 struct cz_power_info *pi = cz_get_pi(adev);
241 struct cz_ps *ps = cz_get_ps(rps);
242 struct cz_pl *pl = &ps->levels[index];
243 struct amdgpu_clock_voltage_dependency_table *table =
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
245
246 pl->sclk = table->entries[clock_info->carrizo.index].clk;
247 pl->vddc_index = table->entries[clock_info->carrizo.index].v;
248
249 ps->num_levels = index + 1;
250
251 if (pi->caps_sclk_ds) {
252 pl->ds_divider_index = 5;
253 pl->ss_divider_index = 5;
254 }
255
256}
257
258static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
259 struct amdgpu_ps *rps,
260 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
261 u8 table_rev)
262{
263 struct cz_ps *ps = cz_get_ps(rps);
264
265 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
266 rps->class = le16_to_cpu(non_clock_info->usClassification);
267 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
268
269 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
270 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
271 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
272 } else {
273 rps->vclk = 0;
274 rps->dclk = 0;
275 }
276
277 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
278 adev->pm.dpm.boot_ps = rps;
279 cz_patch_boot_state(adev, ps);
280 }
281 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
282 adev->pm.dpm.uvd_ps = rps;
283
284}
285
286union power_info {
287 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
288 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
289 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
290 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
291 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
292};
293
294union pplib_power_state {
295 struct _ATOM_PPLIB_STATE v1;
296 struct _ATOM_PPLIB_STATE_V2 v2;
297};
298
299static int cz_parse_power_table(struct amdgpu_device *adev)
300{
301 struct amdgpu_mode_info *mode_info = &adev->mode_info;
302 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
303 union pplib_power_state *power_state;
304 int i, j, k, non_clock_array_index, clock_array_index;
305 union pplib_clock_info *clock_info;
306 struct _StateArray *state_array;
307 struct _ClockInfoArray *clock_info_array;
308 struct _NonClockInfoArray *non_clock_info_array;
309 union power_info *power_info;
310 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
311 u16 data_offset;
312 u8 frev, crev;
313 u8 *power_state_offset;
314 struct cz_ps *ps;
315
316 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
317 &frev, &crev, &data_offset))
318 return -EINVAL;
319 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
320
321 state_array = (struct _StateArray *)
322 (mode_info->atom_context->bios + data_offset +
323 le16_to_cpu(power_info->pplib.usStateArrayOffset));
324 clock_info_array = (struct _ClockInfoArray *)
325 (mode_info->atom_context->bios + data_offset +
326 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
327 non_clock_info_array = (struct _NonClockInfoArray *)
328 (mode_info->atom_context->bios + data_offset +
329 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
330
331 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
332 state_array->ucNumEntries, GFP_KERNEL);
333
334 if (!adev->pm.dpm.ps)
335 return -ENOMEM;
336
337 power_state_offset = (u8 *)state_array->states;
338 adev->pm.dpm.platform_caps =
339 le32_to_cpu(power_info->pplib.ulPlatformCaps);
340 adev->pm.dpm.backbias_response_time =
341 le16_to_cpu(power_info->pplib.usBackbiasTime);
342 adev->pm.dpm.voltage_response_time =
343 le16_to_cpu(power_info->pplib.usVoltageTime);
344
345 for (i = 0; i < state_array->ucNumEntries; i++) {
346 power_state = (union pplib_power_state *)power_state_offset;
347 non_clock_array_index = power_state->v2.nonClockInfoIndex;
348 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
349 &non_clock_info_array->nonClockInfo[non_clock_array_index];
350
351 ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
352 if (ps == NULL) {
353 kfree(adev->pm.dpm.ps);
354 return -ENOMEM;
355 }
356
357 adev->pm.dpm.ps[i].ps_priv = ps;
358 k = 0;
359 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
360 clock_array_index = power_state->v2.clockInfoIndex[j];
361 if (clock_array_index >= clock_info_array->ucNumEntries)
362 continue;
363 if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
364 break;
365 clock_info = (union pplib_clock_info *)
366 &clock_info_array->clockInfo[clock_array_index *
367 clock_info_array->ucEntrySize];
368 cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
369 k, clock_info);
370 k++;
371 }
372 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
373 non_clock_info,
374 non_clock_info_array->ucEntrySize);
375 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
376 }
377 adev->pm.dpm.num_ps = state_array->ucNumEntries;
378
379 return 0;
380}
381
382static int cz_process_firmware_header(struct amdgpu_device *adev)
383{
384 struct cz_power_info *pi = cz_get_pi(adev);
385 u32 tmp;
386 int ret;
387
388 ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
389 offsetof(struct SMU8_Firmware_Header,
390 DpmTable),
391 &tmp, pi->sram_end);
392
393 if (ret == 0)
394 pi->dpm_table_start = tmp;
395
396 return ret;
397}
398
399static int cz_dpm_init(struct amdgpu_device *adev)
400{
401 struct cz_power_info *pi;
402 int ret, i;
403
404 pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
405 if (NULL == pi)
406 return -ENOMEM;
407
408 adev->pm.dpm.priv = pi;
409
410 ret = amdgpu_get_platform_caps(adev);
411 if (ret)
412 return ret;
413
414 ret = amdgpu_parse_extended_power_table(adev);
415 if (ret)
416 return ret;
417
418 pi->sram_end = SMC_RAM_END;
419
420 /* set up DPM defaults */
421 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
422 pi->active_target[i] = CZ_AT_DFLT;
423
424 pi->mgcg_cgtt_local0 = 0x0;
425 pi->mgcg_cgtt_local1 = 0x0;
426 pi->clock_slow_down_step = 25000;
427 pi->skip_clock_slow_down = 1;
9dcabece 428 pi->enable_nb_ps_policy = 0;
aaa36a97
AD		 429 pi->caps_power_containment = true;
430 pi->caps_cac = true;
431 pi->didt_enabled = false;
432 if (pi->didt_enabled) {
433 pi->caps_sq_ramping = true;
434 pi->caps_db_ramping = true;
435 pi->caps_td_ramping = true;
436 pi->caps_tcp_ramping = true;
437 }
438 pi->caps_sclk_ds = true;
439 pi->voting_clients = 0x00c00033;
440 pi->auto_thermal_throttling_enabled = true;
441 pi->bapm_enabled = false;
442 pi->disable_nb_ps3_in_battery = false;
443 pi->voltage_drop_threshold = 0;
444 pi->caps_sclk_throttle_low_notification = false;
445 pi->gfx_pg_threshold = 500;
446 pi->caps_fps = true;
447 /* uvd */
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
449 pi->caps_uvd_dpm = true;
450 /* vce */
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
452 pi->caps_vce_dpm = true;
453 /* acp */
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
455 pi->caps_acp_dpm = true;
456
457 pi->caps_stable_power_state = false;
458 pi->nb_dpm_enabled_by_driver = true;
459 pi->nb_dpm_enabled = false;
460 pi->caps_voltage_island = false;
461 /* flags which indicate need to upload pptable */
462 pi->need_pptable_upload = true;
463
464 ret = cz_parse_sys_info_table(adev);
465 if (ret)
466 return ret;
467
468 cz_patch_voltage_values(adev);
469 cz_construct_boot_state(adev);
470
471 ret = cz_parse_power_table(adev);
472 if (ret)
473 return ret;
474
475 ret = cz_process_firmware_header(adev);
476 if (ret)
477 return ret;
478
479 pi->dpm_enabled = true;
564ea790 480 pi->uvd_dynamic_pg = false;
aaa36a97
AD		 481
482 return 0;
483}
484
485static void cz_dpm_fini(struct amdgpu_device *adev)
486{
487 int i;
488
489 for (i = 0; i < adev->pm.dpm.num_ps; i++)
490 kfree(adev->pm.dpm.ps[i].ps_priv);
491
492 kfree(adev->pm.dpm.ps);
493 kfree(adev->pm.dpm.priv);
494 amdgpu_free_extended_power_table(adev);
495}
496
f2d52cd4
AD		 497#define ixSMUSVI_NB_CURRENTVID 0xD8230044
498#define CURRENT_NB_VID_MASK 0xff000000
499#define CURRENT_NB_VID__SHIFT 24
500#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
501#define CURRENT_GFX_VID_MASK 0xff000000
502#define CURRENT_GFX_VID__SHIFT 24
503
aaa36a97
AD		 504static void
505cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
506 struct seq_file *m)
507{
508 struct amdgpu_clock_voltage_dependency_table *table =
509 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
510 u32 current_index =
511 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
512 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
513 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
514 u32 sclk, tmp;
f2d52cd4 515 u16 vddnb, vddgfx;
aaa36a97
AD		 516
517 if (current_index >= NUM_SCLK_LEVELS) {
518 seq_printf(m, "invalid dpm profile %d\n", current_index);
519 } else {
520 sclk = table->entries[current_index].clk;
f2d52cd4
AD		 521 tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
522 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
523 vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
524 tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
525 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
526 vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
527 seq_printf(m, "power level %d sclk: %u vddnb: %u vddgfx: %u\n",
528 current_index, sclk, vddnb, vddgfx);
aaa36a97
AD		 529 }
530}
531
532static void cz_dpm_print_power_state(struct amdgpu_device *adev,
533 struct amdgpu_ps *rps)
534{
535 int i;
536 struct cz_ps *ps = cz_get_ps(rps);
537
538 amdgpu_dpm_print_class_info(rps->class, rps->class2);
539 amdgpu_dpm_print_cap_info(rps->caps);
540
541 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
542 for (i = 0; i < ps->num_levels; i++) {
543 struct cz_pl *pl = &ps->levels[i];
544
545 DRM_INFO("\t\tpower level %d sclk: %u vddc: %u\n",
546 i, pl->sclk,
547 cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
548 }
549
550 amdgpu_dpm_print_ps_status(adev, rps);
551}
552
553static void cz_dpm_set_funcs(struct amdgpu_device *adev);
554
5fc3aeeb 555static int cz_dpm_early_init(void *handle)
aaa36a97 556{
5fc3aeeb 557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
558
aaa36a97
AD		 559 cz_dpm_set_funcs(adev);
560
561 return 0;
562}
563
564ea790 564
5fc3aeeb 565static int cz_dpm_late_init(void *handle)
564ea790 566{
5fc3aeeb 567 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
568
6d8db6ce
SJ		 569 if (amdgpu_dpm) {
570 /* powerdown unused blocks for now */
571 cz_dpm_powergate_uvd(adev, true);
572 cz_dpm_powergate_vce(adev, true);
573 }
564ea790
SJ		 574
575 return 0;
576}
577
5fc3aeeb 578static int cz_dpm_sw_init(void *handle)
aaa36a97 579{
5fc3aeeb 580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 581 int ret = 0;
582 /* fix me to add thermal support TODO */
583
584 /* default to balanced state */
585 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
586 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
587 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
588 adev->pm.default_sclk = adev->clock.default_sclk;
589 adev->pm.default_mclk = adev->clock.default_mclk;
590 adev->pm.current_sclk = adev->clock.default_sclk;
591 adev->pm.current_mclk = adev->clock.default_mclk;
592 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
593
594 if (amdgpu_dpm == 0)
595 return 0;
596
597 mutex_lock(&adev->pm.mutex);
598 ret = cz_dpm_init(adev);
599 if (ret)
600 goto dpm_init_failed;
601
602 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
603 if (amdgpu_dpm == 1)
604 amdgpu_pm_print_power_states(adev);
605
606 ret = amdgpu_pm_sysfs_init(adev);
607 if (ret)
608 goto dpm_init_failed;
609
610 mutex_unlock(&adev->pm.mutex);
611 DRM_INFO("amdgpu: dpm initialized\n");
612
613 return 0;
614
615dpm_init_failed:
616 cz_dpm_fini(adev);
617 mutex_unlock(&adev->pm.mutex);
618 DRM_ERROR("amdgpu: dpm initialization failed\n");
619
620 return ret;
621}
622
5fc3aeeb 623static int cz_dpm_sw_fini(void *handle)
aaa36a97 624{
5fc3aeeb 625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
626
aaa36a97
AD		 627 mutex_lock(&adev->pm.mutex);
628 amdgpu_pm_sysfs_fini(adev);
629 cz_dpm_fini(adev);
630 mutex_unlock(&adev->pm.mutex);
631
632 return 0;
633}
634
635static void cz_reset_ap_mask(struct amdgpu_device *adev)
636{
637 struct cz_power_info *pi = cz_get_pi(adev);
638
639 pi->active_process_mask = 0;
640
641}
642
643static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
644 void **table)
645{
646 int ret = 0;
647
648 ret = cz_smu_download_pptable(adev, table);
649
650 return ret;
651}
652
653static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
654{
655 struct cz_power_info *pi = cz_get_pi(adev);
656 struct SMU8_Fusion_ClkTable *clock_table;
657 struct atom_clock_dividers dividers;
658 void *table = NULL;
659 uint8_t i = 0;
660 int ret = 0;
661
662 struct amdgpu_clock_voltage_dependency_table *vddc_table =
663 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
664 struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
665 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
666 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
667 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
668 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
669 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
670 struct amdgpu_clock_voltage_dependency_table *acp_table =
671 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
672
673 if (!pi->need_pptable_upload)
674 return 0;
675
676 ret = cz_dpm_download_pptable_from_smu(adev, &table);
677 if (ret) {
678 DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
679 return -EINVAL;
680 }
681
682 clock_table = (struct SMU8_Fusion_ClkTable *)table;
683 /* patch clock table */
684 if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
685 vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
686 uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
687 vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
688 acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
689 DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
690 return -EINVAL;
691 }
692
693 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
694
695 /* vddc sclk */
696 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
697 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
698 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
699 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
700 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
701 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
702 false, &dividers);
703 if (ret)
704 return ret;
705 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
706 (uint8_t)dividers.post_divider;
707
708 /* vddgfx sclk */
709 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
710 (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
711
712 /* acp breakdown */
713 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
714 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
715 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
716 (i < acp_table->count) ? acp_table->entries[i].clk : 0;
717 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
718 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
719 false, &dividers);
720 if (ret)
721 return ret;
722 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
723 (uint8_t)dividers.post_divider;
724
725 /* uvd breakdown */
726 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
727 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
728 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
729 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
730 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
731 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
732 false, &dividers);
733 if (ret)
734 return ret;
735 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
736 (uint8_t)dividers.post_divider;
737
738 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
739 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
740 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
741 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
742 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
743 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
744 false, &dividers);
745 if (ret)
746 return ret;
747 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
748 (uint8_t)dividers.post_divider;
749
750 /* vce breakdown */
751 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
752 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
753 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
754 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
755 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
756 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
757 false, &dividers);
758 if (ret)
759 return ret;
760 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
761 (uint8_t)dividers.post_divider;
762 }
763
764 /* its time to upload to SMU */
765 ret = cz_smu_upload_pptable(adev);
766 if (ret) {
767 DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
768 return ret;
769 }
770
771 return 0;
772}
773
774static void cz_init_sclk_limit(struct amdgpu_device *adev)
775{
776 struct cz_power_info *pi = cz_get_pi(adev);
777 struct amdgpu_clock_voltage_dependency_table *table =
778 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
779 uint32_t clock = 0, level;
780
781 if (!table || !table->count) {
782 DRM_ERROR("Invalid Voltage Dependency table.\n");
783 return;
784 }
785
786 pi->sclk_dpm.soft_min_clk = 0;
787 pi->sclk_dpm.hard_min_clk = 0;
788 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
789 level = cz_get_argument(adev);
790 if (level < table->count)
791 clock = table->entries[level].clk;
792 else {
793 DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
794 clock = table->entries[table->count - 1].clk;
795 }
796
797 pi->sclk_dpm.soft_max_clk = clock;
798 pi->sclk_dpm.hard_max_clk = clock;
799
800}
801
802static void cz_init_uvd_limit(struct amdgpu_device *adev)
803{
804 struct cz_power_info *pi = cz_get_pi(adev);
805 struct amdgpu_uvd_clock_voltage_dependency_table *table =
806 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
807 uint32_t clock = 0, level;
808
809 if (!table || !table->count) {
810 DRM_ERROR("Invalid Voltage Dependency table.\n");
811 return;
812 }
813
814 pi->uvd_dpm.soft_min_clk = 0;
815 pi->uvd_dpm.hard_min_clk = 0;
816 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
817 level = cz_get_argument(adev);
818 if (level < table->count)
819 clock = table->entries[level].vclk;
820 else {
821 DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
822 clock = table->entries[table->count - 1].vclk;
823 }
824
825 pi->uvd_dpm.soft_max_clk = clock;
826 pi->uvd_dpm.hard_max_clk = clock;
827
828}
829
830static void cz_init_vce_limit(struct amdgpu_device *adev)
831{
832 struct cz_power_info *pi = cz_get_pi(adev);
833 struct amdgpu_vce_clock_voltage_dependency_table *table =
834 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
835 uint32_t clock = 0, level;
836
837 if (!table || !table->count) {
838 DRM_ERROR("Invalid Voltage Dependency table.\n");
839 return;
840 }
841
b7a07769
SJ		 842 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
843 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
aaa36a97
AD		 844 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
845 level = cz_get_argument(adev);
846 if (level < table->count)
b7a07769 847 clock = table->entries[level].ecclk;
aaa36a97
AD		 848 else {
849 /* future BIOS would fix this error */
850 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
b7a07769 851 clock = table->entries[table->count - 1].ecclk;
aaa36a97
AD		 852 }
853
854 pi->vce_dpm.soft_max_clk = clock;
855 pi->vce_dpm.hard_max_clk = clock;
856
857}
858
859static void cz_init_acp_limit(struct amdgpu_device *adev)
860{
861 struct cz_power_info *pi = cz_get_pi(adev);
862 struct amdgpu_clock_voltage_dependency_table *table =
863 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
864 uint32_t clock = 0, level;
865
866 if (!table || !table->count) {
867 DRM_ERROR("Invalid Voltage Dependency table.\n");
868 return;
869 }
870
871 pi->acp_dpm.soft_min_clk = 0;
872 pi->acp_dpm.hard_min_clk = 0;
873 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
874 level = cz_get_argument(adev);
875 if (level < table->count)
876 clock = table->entries[level].clk;
877 else {
878 DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
879 clock = table->entries[table->count - 1].clk;
880 }
881
882 pi->acp_dpm.soft_max_clk = clock;
883 pi->acp_dpm.hard_max_clk = clock;
884
885}
886
887static void cz_init_pg_state(struct amdgpu_device *adev)
888{
889 struct cz_power_info *pi = cz_get_pi(adev);
890
891 pi->uvd_power_gated = false;
892 pi->vce_power_gated = false;
893 pi->acp_power_gated = false;
894
895}
896
897static void cz_init_sclk_threshold(struct amdgpu_device *adev)
898{
899 struct cz_power_info *pi = cz_get_pi(adev);
900
901 pi->low_sclk_interrupt_threshold = 0;
902
903}
904
905static void cz_dpm_setup_asic(struct amdgpu_device *adev)
906{
907 cz_reset_ap_mask(adev);
908 cz_dpm_upload_pptable_to_smu(adev);
909 cz_init_sclk_limit(adev);
910 cz_init_uvd_limit(adev);
911 cz_init_vce_limit(adev);
912 cz_init_acp_limit(adev);
913 cz_init_pg_state(adev);
914 cz_init_sclk_threshold(adev);
915
916}
917
918static bool cz_check_smu_feature(struct amdgpu_device *adev,
919 uint32_t feature)
920{
921 uint32_t smu_feature = 0;
922 int ret;
923
924 ret = cz_send_msg_to_smc_with_parameter(adev,
925 PPSMC_MSG_GetFeatureStatus, 0);
926 if (ret) {
927 DRM_ERROR("Failed to get SMU features from SMC.\n");
928 return false;
929 } else {
930 smu_feature = cz_get_argument(adev);
931 if (feature & smu_feature)
932 return true;
933 }
934
935 return false;
936}
937
938static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
939{
940 if (cz_check_smu_feature(adev,
941 SMU_EnabledFeatureScoreboard_SclkDpmOn))
942 return true;
943
944 return false;
945}
946
947static void cz_program_voting_clients(struct amdgpu_device *adev)
948{
949 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
950}
951
952static void cz_clear_voting_clients(struct amdgpu_device *adev)
953{
954 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
955}
956
957static int cz_start_dpm(struct amdgpu_device *adev)
958{
959 int ret = 0;
960
961 if (amdgpu_dpm) {
962 ret = cz_send_msg_to_smc_with_parameter(adev,
963 PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
964 if (ret) {
965 DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
966 return -EINVAL;
967 }
968 }
969
970 return 0;
971}
972
973static int cz_stop_dpm(struct amdgpu_device *adev)
974{
975 int ret = 0;
976
977 if (amdgpu_dpm && adev->pm.dpm_enabled) {
978 ret = cz_send_msg_to_smc_with_parameter(adev,
979 PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
980 if (ret) {
981 DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
982 return -EINVAL;
983 }
984 }
985
986 return 0;
987}
988
989static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
990 uint32_t clock, uint16_t msg)
991{
992 int i = 0;
993 struct amdgpu_clock_voltage_dependency_table *table =
994 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
995
996 switch (msg) {
997 case PPSMC_MSG_SetSclkSoftMin:
998 case PPSMC_MSG_SetSclkHardMin:
999 for (i = 0; i < table->count; i++)
1000 if (clock <= table->entries[i].clk)
1001 break;
1002 if (i == table->count)
1003 i = table->count - 1;
1004 break;
1005 case PPSMC_MSG_SetSclkSoftMax:
1006 case PPSMC_MSG_SetSclkHardMax:
1007 for (i = table->count - 1; i >= 0; i--)
1008 if (clock >= table->entries[i].clk)
1009 break;
1010 if (i < 0)
1011 i = 0;
1012 break;
1013 default:
1014 break;
1015 }
1016
1017 return i;
1018}
1019
b7a07769
SJ		 1020static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1021 uint32_t clock, uint16_t msg)
1022{
1023 int i = 0;
1024 struct amdgpu_vce_clock_voltage_dependency_table *table =
1025 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1026
1027 if (table->count == 0)
1028 return 0;
1029
1030 switch (msg) {
1031 case PPSMC_MSG_SetEclkSoftMin:
1032 case PPSMC_MSG_SetEclkHardMin:
1033 for (i = 0; i < table->count-1; i++)
1034 if (clock <= table->entries[i].ecclk)
1035 break;
1036 break;
1037 case PPSMC_MSG_SetEclkSoftMax:
1038 case PPSMC_MSG_SetEclkHardMax:
1039 for (i = table->count - 1; i > 0; i--)
1040 if (clock >= table->entries[i].ecclk)
1041 break;
1042 break;
1043 default:
1044 break;
1045 }
1046
1047 return i;
1048}
1049
aaa36a97
AD		 1050static int cz_program_bootup_state(struct amdgpu_device *adev)
1051{
1052 struct cz_power_info *pi = cz_get_pi(adev);
1053 uint32_t soft_min_clk = 0;
1054 uint32_t soft_max_clk = 0;
1055 int ret = 0;
1056
1057 pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
1058 pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
1059
1060 soft_min_clk = cz_get_sclk_level(adev,
1061 pi->sclk_dpm.soft_min_clk,
1062 PPSMC_MSG_SetSclkSoftMin);
1063 soft_max_clk = cz_get_sclk_level(adev,
1064 pi->sclk_dpm.soft_max_clk,
1065 PPSMC_MSG_SetSclkSoftMax);
1066
1067 ret = cz_send_msg_to_smc_with_parameter(adev,
1068 PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
1069 if (ret)
1070 return -EINVAL;
1071
1072 ret = cz_send_msg_to_smc_with_parameter(adev,
1073 PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
1074 if (ret)
1075 return -EINVAL;
1076
1077 return 0;
1078}
1079
1080/* TODO */
1081static int cz_disable_cgpg(struct amdgpu_device *adev)
1082{
1083 return 0;
1084}
1085
1086/* TODO */
1087static int cz_enable_cgpg(struct amdgpu_device *adev)
1088{
1089 return 0;
1090}
1091
1092/* TODO */
1093static int cz_program_pt_config_registers(struct amdgpu_device *adev)
1094{
1095 return 0;
1096}
1097
1098static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
1099{
1100 struct cz_power_info *pi = cz_get_pi(adev);
1101 uint32_t reg = 0;
1102
1103 if (pi->caps_sq_ramping) {
1104 reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
1105 if (enable)
1106 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1107 else
1108 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1109 WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
1110 }
1111 if (pi->caps_db_ramping) {
1112 reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
1113 if (enable)
1114 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
1115 else
1116 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
1117 WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
1118 }
1119 if (pi->caps_td_ramping) {
1120 reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
1121 if (enable)
1122 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
1123 else
1124 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
1125 WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
1126 }
1127 if (pi->caps_tcp_ramping) {
1128 reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
1129 if (enable)
1130 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1131 else
1132 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1133 WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
1134 }
1135
1136}
1137
1138static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
1139{
1140 struct cz_power_info *pi = cz_get_pi(adev);
1141 int ret;
1142
1143 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
1144 pi->caps_td_ramping || pi->caps_tcp_ramping) {
1145 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
1146 ret = cz_disable_cgpg(adev);
1147 if (ret) {
1148 DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
1149 return -EINVAL;
1150 }
1151 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
1152 }
1153
1154 ret = cz_program_pt_config_registers(adev);
1155 if (ret) {
1156 DRM_ERROR("Di/Dt config failed\n");
1157 return -EINVAL;
1158 }
1159 cz_do_enable_didt(adev, enable);
1160
1161 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
1162 ret = cz_enable_cgpg(adev);
1163 if (ret) {
1164 DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
1165 return -EINVAL;
1166 }
1167 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1168 }
1169 }
1170
1171 return 0;
1172}
1173
1174/* TODO */
1175static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
1176{
1177}
1178
1179static void cz_update_current_ps(struct amdgpu_device *adev,
1180 struct amdgpu_ps *rps)
1181{
1182 struct cz_power_info *pi = cz_get_pi(adev);
1183 struct cz_ps *ps = cz_get_ps(rps);
1184
1185 pi->current_ps = *ps;
1186 pi->current_rps = *rps;
1187 pi->current_rps.ps_priv = ps;
1188
1189}
1190
1191static void cz_update_requested_ps(struct amdgpu_device *adev,
1192 struct amdgpu_ps *rps)
1193{
1194 struct cz_power_info *pi = cz_get_pi(adev);
1195 struct cz_ps *ps = cz_get_ps(rps);
1196
1197 pi->requested_ps = *ps;
1198 pi->requested_rps = *rps;
1199 pi->requested_rps.ps_priv = ps;
1200
1201}
1202
1203/* PP arbiter support needed TODO */
1204static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1205 struct amdgpu_ps *new_rps,
1206 struct amdgpu_ps *old_rps)
1207{
1208 struct cz_ps *ps = cz_get_ps(new_rps);
1209 struct cz_power_info *pi = cz_get_pi(adev);
1210 struct amdgpu_clock_and_voltage_limits *limits =
1211 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1212 /* 10kHz memory clock */
1213 uint32_t mclk = 0;
1214
1215 ps->force_high = false;
1216 ps->need_dfs_bypass = true;
1217 pi->video_start = new_rps->dclk || new_rps->vclk ||
1218 new_rps->evclk || new_rps->ecclk;
1219
1220 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1221 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1222 pi->battery_state = true;
1223 else
1224 pi->battery_state = false;
1225
1226 if (pi->caps_stable_power_state)
1227 mclk = limits->mclk;
1228
1229 if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
1230 ps->force_high = true;
1231
1232}
1233
1234static int cz_dpm_enable(struct amdgpu_device *adev)
1235{
1236 int ret = 0;
1237
1238 /* renable will hang up SMU, so check first */
1239 if (cz_check_for_dpm_enabled(adev))
1240 return -EINVAL;
1241
1242 cz_program_voting_clients(adev);
1243
1244 ret = cz_start_dpm(adev);
1245 if (ret) {
1246 DRM_ERROR("Carrizo DPM enable failed\n");
1247 return -EINVAL;
1248 }
1249
1250 ret = cz_program_bootup_state(adev);
1251 if (ret) {
1252 DRM_ERROR("Carrizo bootup state program failed\n");
1253 return -EINVAL;
1254 }
1255
1256 ret = cz_enable_didt(adev, true);
1257 if (ret) {
1258 DRM_ERROR("Carrizo enable di/dt failed\n");
1259 return -EINVAL;
1260 }
1261
1262 cz_reset_acp_boot_level(adev);
1263
1264 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1265
1266 return 0;
1267}
1268
5fc3aeeb 1269static int cz_dpm_hw_init(void *handle)
aaa36a97 1270{
5fc3aeeb 1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
46651cc5 1272 int ret = 0;
aaa36a97
AD		 1273
1274 mutex_lock(&adev->pm.mutex);
1275
05188312
AD		 1276 /* smu init only needs to be called at startup, not resume.
1277 * It should be in sw_init, but requires the fw info gathered
1278 * in sw_init from other IP modules.
1279 */
aaa36a97
AD		 1280 ret = cz_smu_init(adev);
1281 if (ret) {
1282 DRM_ERROR("amdgpu: smc initialization failed\n");
1283 mutex_unlock(&adev->pm.mutex);
1284 return ret;
1285 }
1286
1287 /* do the actual fw loading */
1288 ret = cz_smu_start(adev);
1289 if (ret) {
1290 DRM_ERROR("amdgpu: smc start failed\n");
1291 mutex_unlock(&adev->pm.mutex);
1292 return ret;
1293 }
1294
46651cc5
SJ		 1295 if (!amdgpu_dpm) {
1296 adev->pm.dpm_enabled = false;
1297 mutex_unlock(&adev->pm.mutex);
1298 return ret;
1299 }
1300
aaa36a97
AD		 1301 /* cz dpm setup asic */
1302 cz_dpm_setup_asic(adev);
1303
1304 /* cz dpm enable */
1305 ret = cz_dpm_enable(adev);
1306 if (ret)
1307 adev->pm.dpm_enabled = false;
1308 else
1309 adev->pm.dpm_enabled = true;
1310
1311 mutex_unlock(&adev->pm.mutex);
1312
1313 return 0;
1314}
1315
1316static int cz_dpm_disable(struct amdgpu_device *adev)
1317{
1318 int ret = 0;
1319
1320 if (!cz_check_for_dpm_enabled(adev))
1321 return -EINVAL;
1322
1323 ret = cz_enable_didt(adev, false);
1324 if (ret) {
1325 DRM_ERROR("Carrizo disable di/dt failed\n");
1326 return -EINVAL;
1327 }
1328
564ea790
SJ		 1329 /* powerup blocks */
1330 cz_dpm_powergate_uvd(adev, false);
b7a07769 1331 cz_dpm_powergate_vce(adev, false);
564ea790 1332
aaa36a97
AD		 1333 cz_clear_voting_clients(adev);
1334 cz_stop_dpm(adev);
1335 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1336
1337 return 0;
1338}
1339
5fc3aeeb 1340static int cz_dpm_hw_fini(void *handle)
aaa36a97
AD		 1341{
1342 int ret = 0;
5fc3aeeb 1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1344
1345 mutex_lock(&adev->pm.mutex);
1346
05188312
AD		 1347 /* smu fini only needs to be called at teardown, not suspend.
1348 * It should be in sw_fini, but we put it here for symmetry
1349 * with smu init.
1350 */
aaa36a97
AD		 1351 cz_smu_fini(adev);
1352
1353 if (adev->pm.dpm_enabled) {
1354 ret = cz_dpm_disable(adev);
aaa36a97
AD		 1355
1356 adev->pm.dpm.current_ps =
1357 adev->pm.dpm.requested_ps =
1358 adev->pm.dpm.boot_ps;
1359 }
1360
1361 adev->pm.dpm_enabled = false;
1362
1363 mutex_unlock(&adev->pm.mutex);
1364
10457457 1365 return ret;
aaa36a97
AD		 1366}
1367
5fc3aeeb 1368static int cz_dpm_suspend(void *handle)
aaa36a97
AD		 1369{
1370 int ret = 0;
5fc3aeeb 1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1372
1373 if (adev->pm.dpm_enabled) {
1374 mutex_lock(&adev->pm.mutex);
1375
1376 ret = cz_dpm_disable(adev);
aaa36a97
AD		 1377
1378 adev->pm.dpm.current_ps =
1379 adev->pm.dpm.requested_ps =
1380 adev->pm.dpm.boot_ps;
1381
1382 mutex_unlock(&adev->pm.mutex);
1383 }
1384
10457457 1385 return ret;
aaa36a97
AD		 1386}
1387
5fc3aeeb 1388static int cz_dpm_resume(void *handle)
aaa36a97
AD		 1389{
1390 int ret = 0;
5fc3aeeb 1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1392
1393 mutex_lock(&adev->pm.mutex);
aaa36a97
AD		 1394
1395 /* do the actual fw loading */
1396 ret = cz_smu_start(adev);
1397 if (ret) {
1398 DRM_ERROR("amdgpu: smc start failed\n");
1399 mutex_unlock(&adev->pm.mutex);
1400 return ret;
1401 }
1402
46651cc5
SJ		 1403 if (!amdgpu_dpm) {
1404 adev->pm.dpm_enabled = false;
1405 mutex_unlock(&adev->pm.mutex);
1406 return ret;
1407 }
1408
aaa36a97
AD		 1409 /* cz dpm setup asic */
1410 cz_dpm_setup_asic(adev);
1411
1412 /* cz dpm enable */
1413 ret = cz_dpm_enable(adev);
1414 if (ret)
1415 adev->pm.dpm_enabled = false;
1416 else
1417 adev->pm.dpm_enabled = true;
1418
1419 mutex_unlock(&adev->pm.mutex);
1420 /* upon resume, re-compute the clocks */
1421 if (adev->pm.dpm_enabled)
1422 amdgpu_pm_compute_clocks(adev);
1423
1424 return 0;
1425}
1426
5fc3aeeb 1427static int cz_dpm_set_clockgating_state(void *handle,
1428 enum amd_clockgating_state state)
aaa36a97
AD		 1429{
1430 return 0;
1431}
1432
5fc3aeeb 1433static int cz_dpm_set_powergating_state(void *handle,
1434 enum amd_powergating_state state)
aaa36a97
AD		 1435{
1436 return 0;
1437}
1438
1439/* borrowed from KV, need future unify */
1440static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1441{
1442 int actual_temp = 0;
1443 uint32_t temp = RREG32_SMC(0xC0300E0C);
1444
1445 if (temp)
1446 actual_temp = 1000 * ((temp / 8) - 49);
1447
1448 return actual_temp;
1449}
1450
1451static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
1452{
1453 struct cz_power_info *pi = cz_get_pi(adev);
1454 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1455 struct amdgpu_ps *new_ps = &requested_ps;
1456
1457 cz_update_requested_ps(adev, new_ps);
1458 cz_apply_state_adjust_rules(adev, &pi->requested_rps,
1459 &pi->current_rps);
1460
1461 return 0;
1462}
1463
1464static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
1465{
1466 struct cz_power_info *pi = cz_get_pi(adev);
1467 struct amdgpu_clock_and_voltage_limits *limits =
1468 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1469 uint32_t clock, stable_ps_clock = 0;
1470
1471 clock = pi->sclk_dpm.soft_min_clk;
1472
1473 if (pi->caps_stable_power_state) {
1474 stable_ps_clock = limits->sclk * 75 / 100;
1475 if (clock < stable_ps_clock)
1476 clock = stable_ps_clock;
1477 }
1478
1479 if (clock != pi->sclk_dpm.soft_min_clk) {
1480 pi->sclk_dpm.soft_min_clk = clock;
1481 cz_send_msg_to_smc_with_parameter(adev,
1482 PPSMC_MSG_SetSclkSoftMin,
1483 cz_get_sclk_level(adev, clock,
1484 PPSMC_MSG_SetSclkSoftMin));
1485 }
1486
1487 if (pi->caps_stable_power_state &&
1488 pi->sclk_dpm.soft_max_clk != clock) {
1489 pi->sclk_dpm.soft_max_clk = clock;
1490 cz_send_msg_to_smc_with_parameter(adev,
1491 PPSMC_MSG_SetSclkSoftMax,
1492 cz_get_sclk_level(adev, clock,
1493 PPSMC_MSG_SetSclkSoftMax));
1494 } else {
1495 cz_send_msg_to_smc_with_parameter(adev,
1496 PPSMC_MSG_SetSclkSoftMax,
1497 cz_get_sclk_level(adev,
1498 pi->sclk_dpm.soft_max_clk,
1499 PPSMC_MSG_SetSclkSoftMax));
1500 }
1501
1502 return 0;
1503}
1504
1505static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
1506{
1507 int ret = 0;
1508 struct cz_power_info *pi = cz_get_pi(adev);
1509
1510 if (pi->caps_sclk_ds) {
1511 cz_send_msg_to_smc_with_parameter(adev,
1512 PPSMC_MSG_SetMinDeepSleepSclk,
1513 CZ_MIN_DEEP_SLEEP_SCLK);
1514 }
1515
1516 return ret;
1517}
1518
1519/* ?? without dal support, is this still needed in setpowerstate list*/
1520static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
1521{
1522 int ret = 0;
1523 struct cz_power_info *pi = cz_get_pi(adev);
1524
1525 cz_send_msg_to_smc_with_parameter(adev,
1526 PPSMC_MSG_SetWatermarkFrequency,
1527 pi->sclk_dpm.soft_max_clk);
1528
1529 return ret;
1530}
1531
1532static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
1533{
1534 int ret = 0;
1535 struct cz_power_info *pi = cz_get_pi(adev);
1536
1537 /* also depend on dal NBPStateDisableRequired */
1538 if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
1539 ret = cz_send_msg_to_smc_with_parameter(adev,
1540 PPSMC_MSG_EnableAllSmuFeatures,
1541 NB_DPM_MASK);
1542 if (ret) {
1543 DRM_ERROR("amdgpu: nb dpm enable failed\n");
1544 return ret;
1545 }
1546 pi->nb_dpm_enabled = true;
1547 }
1548
1549 return ret;
1550}
1551
1552static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
1553 bool enable)
1554{
1555 if (enable)
1556 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
1557 else
1558 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
1559
1560}
1561
1562static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
1563{
1564 int ret = 0;
1565 struct cz_power_info *pi = cz_get_pi(adev);
1566 struct cz_ps *ps = &pi->requested_ps;
1567
1568 if (pi->sys_info.nb_dpm_enable) {
1569 if (ps->force_high)
1570 cz_dpm_nbdpm_lm_pstate_enable(adev, true);
1571 else
1572 cz_dpm_nbdpm_lm_pstate_enable(adev, false);
1573 }
1574
1575 return ret;
1576}
1577
1578/* with dpm enabled */
1579static int cz_dpm_set_power_state(struct amdgpu_device *adev)
1580{
1581 int ret = 0;
1582
1583 cz_dpm_update_sclk_limit(adev);
1584 cz_dpm_set_deep_sleep_sclk_threshold(adev);
1585 cz_dpm_set_watermark_threshold(adev);
1586 cz_dpm_enable_nbdpm(adev);
1587 cz_dpm_update_low_memory_pstate(adev);
1588
1589 return ret;
1590}
1591
1592static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
1593{
1594 struct cz_power_info *pi = cz_get_pi(adev);
1595 struct amdgpu_ps *ps = &pi->requested_rps;
1596
1597 cz_update_current_ps(adev, ps);
1598
1599}
1600
1601static int cz_dpm_force_highest(struct amdgpu_device *adev)
1602{
1603 struct cz_power_info *pi = cz_get_pi(adev);
1604 int ret = 0;
1605
1606 if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
1607 pi->sclk_dpm.soft_min_clk =
1608 pi->sclk_dpm.soft_max_clk;
1609 ret = cz_send_msg_to_smc_with_parameter(adev,
1610 PPSMC_MSG_SetSclkSoftMin,
1611 cz_get_sclk_level(adev,
1612 pi->sclk_dpm.soft_min_clk,
1613 PPSMC_MSG_SetSclkSoftMin));
1614 if (ret)
1615 return ret;
1616 }
1617
1618 return ret;
1619}
1620
1621static int cz_dpm_force_lowest(struct amdgpu_device *adev)
1622{
1623 struct cz_power_info *pi = cz_get_pi(adev);
1624 int ret = 0;
1625
1626 if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
1627 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
1628 ret = cz_send_msg_to_smc_with_parameter(adev,
1629 PPSMC_MSG_SetSclkSoftMax,
1630 cz_get_sclk_level(adev,
1631 pi->sclk_dpm.soft_max_clk,
1632 PPSMC_MSG_SetSclkSoftMax));
1633 if (ret)
1634 return ret;
1635 }
1636
1637 return ret;
1638}
1639
1640static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
1641{
1642 struct cz_power_info *pi = cz_get_pi(adev);
1643
1644 if (!pi->max_sclk_level) {
1645 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
1646 pi->max_sclk_level = cz_get_argument(adev) + 1;
1647 }
1648
1649 if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1650 DRM_ERROR("Invalid max sclk level!\n");
1651 return -EINVAL;
1652 }
1653
1654 return pi->max_sclk_level;
1655}
1656
1657static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1658{
1659 struct cz_power_info *pi = cz_get_pi(adev);
1660 struct amdgpu_clock_voltage_dependency_table *dep_table =
1661 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1662 uint32_t level = 0;
1663 int ret = 0;
1664
1665 pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
1666 level = cz_dpm_get_max_sclk_level(adev) - 1;
1667 if (level < dep_table->count)
1668 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
1669 else
1670 pi->sclk_dpm.soft_max_clk =
1671 dep_table->entries[dep_table->count - 1].clk;
1672
1673 /* get min/max sclk soft value
1674 * notify SMU to execute */
1675 ret = cz_send_msg_to_smc_with_parameter(adev,
1676 PPSMC_MSG_SetSclkSoftMin,
1677 cz_get_sclk_level(adev,
1678 pi->sclk_dpm.soft_min_clk,
1679 PPSMC_MSG_SetSclkSoftMin));
1680 if (ret)
1681 return ret;
1682
1683 ret = cz_send_msg_to_smc_with_parameter(adev,
1684 PPSMC_MSG_SetSclkSoftMax,
1685 cz_get_sclk_level(adev,
1686 pi->sclk_dpm.soft_max_clk,
1687 PPSMC_MSG_SetSclkSoftMax));
1688 if (ret)
1689 return ret;
1690
1a45e8a1
AD		 1691 DRM_DEBUG("DPM unforce state min=%d, max=%d.\n",
1692 pi->sclk_dpm.soft_min_clk,
1693 pi->sclk_dpm.soft_max_clk);
aaa36a97
AD		 1694
1695 return 0;
1696}
1697
1698static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
85cfe096 1699 enum amdgpu_dpm_forced_level level)
aaa36a97
AD		 1700{
1701 int ret = 0;
1702
1703 switch (level) {
1704 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
85cfe096
AD		 1705 ret = cz_dpm_unforce_dpm_levels(adev);
1706 if (ret)
1707 return ret;
aaa36a97
AD		 1708 ret = cz_dpm_force_highest(adev);
1709 if (ret)
1710 return ret;
1711 break;
1712 case AMDGPU_DPM_FORCED_LEVEL_LOW:
85cfe096
AD		 1713 ret = cz_dpm_unforce_dpm_levels(adev);
1714 if (ret)
1715 return ret;
aaa36a97
AD		 1716 ret = cz_dpm_force_lowest(adev);
1717 if (ret)
1718 return ret;
1719 break;
1720 case AMDGPU_DPM_FORCED_LEVEL_AUTO:
1721 ret = cz_dpm_unforce_dpm_levels(adev);
1722 if (ret)
1723 return ret;
1724 break;
1725 default:
1726 break;
1727 }
1728
58829aa6
AD		 1729 adev->pm.dpm.forced_level = level;
1730
aaa36a97
AD		 1731 return ret;
1732}
1733
1734/* fix me, display configuration change lists here
1735 * mostly dal related*/
1736static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
1737{
1738}
1739
1740static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
1741{
1742 struct cz_power_info *pi = cz_get_pi(adev);
1743 struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
1744
1745 if (low)
1746 return requested_state->levels[0].sclk;
1747 else
1748 return requested_state->levels[requested_state->num_levels - 1].sclk;
1749
1750}
1751
1752static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
1753{
1754 struct cz_power_info *pi = cz_get_pi(adev);
1755
1756 return pi->sys_info.bootup_uma_clk;
1757}
1758
564ea790
SJ		 1759static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1760{
1761 struct cz_power_info *pi = cz_get_pi(adev);
1762 int ret = 0;
1763
1764 if (enable && pi->caps_uvd_dpm ) {
1765 pi->dpm_flags |= DPMFlags_UVD_Enabled;
1766 DRM_DEBUG("UVD DPM Enabled.\n");
1767
1768 ret = cz_send_msg_to_smc_with_parameter(adev,
1769 PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK);
1770 } else {
1771 pi->dpm_flags &= ~DPMFlags_UVD_Enabled;
1772 DRM_DEBUG("UVD DPM Stopped\n");
1773
1774 ret = cz_send_msg_to_smc_with_parameter(adev,
1775 PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK);
1776 }
1777
1778 return ret;
1779}
1780
1781static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1782{
1783 return cz_enable_uvd_dpm(adev, !gate);
1784}
1785
1786
1787static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1788{
1789 struct cz_power_info *pi = cz_get_pi(adev);
1790 int ret;
1791
1792 if (pi->uvd_power_gated == gate)
1793 return;
1794
1795 pi->uvd_power_gated = gate;
1796
1797 if (gate) {
1798 if (pi->caps_uvd_pg) {
1799 /* disable clockgating so we can properly shut down the block */
5fc3aeeb 1800 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1801 AMD_CG_STATE_UNGATE);
564ea790 1802 /* shutdown the UVD block */
5fc3aeeb 1803 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1804 AMD_PG_STATE_GATE);
564ea790
SJ		 1805 /* XXX: check for errors */
1806 }
1807 cz_update_uvd_dpm(adev, gate);
1808 if (pi->caps_uvd_pg)
1809 /* power off the UVD block */
1810 cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
1811 } else {
1812 if (pi->caps_uvd_pg) {
1813 /* power on the UVD block */
1814 if (pi->uvd_dynamic_pg)
1815 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
1816 else
1817 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
1818 /* re-init the UVD block */
5fc3aeeb 1819 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1820 AMD_PG_STATE_UNGATE);
564ea790 1821 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
5fc3aeeb 1822 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1823 AMD_CG_STATE_GATE);
564ea790
SJ		 1824 /* XXX: check for errors */
1825 }
1826 cz_update_uvd_dpm(adev, gate);
1827 }
1828}
1829
b7a07769
SJ		 1830static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1831{
1832 struct cz_power_info *pi = cz_get_pi(adev);
1833 int ret = 0;
1834
1835 if (enable && pi->caps_vce_dpm) {
1836 pi->dpm_flags |= DPMFlags_VCE_Enabled;
1837 DRM_DEBUG("VCE DPM Enabled.\n");
1838
1839 ret = cz_send_msg_to_smc_with_parameter(adev,
1840 PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
1841
1842 } else {
1843 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
1844 DRM_DEBUG("VCE DPM Stopped\n");
1845
1846 ret = cz_send_msg_to_smc_with_parameter(adev,
1847 PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
1848 }
1849
1850 return ret;
1851}
1852
1853static int cz_update_vce_dpm(struct amdgpu_device *adev)
1854{
1855 struct cz_power_info *pi = cz_get_pi(adev);
1856 struct amdgpu_vce_clock_voltage_dependency_table *table =
1857 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1858
1859 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1860 if (pi->caps_stable_power_state) {
1861 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
1862
1863 } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
1864 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
1865 }
1866
1867 cz_send_msg_to_smc_with_parameter(adev,
1868 PPSMC_MSG_SetEclkHardMin,
1869 cz_get_eclk_level(adev,
1870 pi->vce_dpm.hard_min_clk,
1871 PPSMC_MSG_SetEclkHardMin));
1872 return 0;
1873}
1874
1875static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1876{
1877 struct cz_power_info *pi = cz_get_pi(adev);
1878
1879 if (pi->caps_vce_pg) {
1880 if (pi->vce_power_gated != gate) {
1881 if (gate) {
1882 /* disable clockgating so we can properly shut down the block */
1883 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1884 AMD_CG_STATE_UNGATE);
1885 /* shutdown the VCE block */
1886 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1887 AMD_PG_STATE_GATE);
1888
1889 cz_enable_vce_dpm(adev, false);
1890 /* TODO: to figure out why vce can't be poweroff. */
1891 /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
1892 pi->vce_power_gated = true;
1893 } else {
1894 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
1895 pi->vce_power_gated = false;
1896
1897 /* re-init the VCE block */
1898 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1899 AMD_PG_STATE_UNGATE);
1900 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1901 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1902 AMD_CG_STATE_GATE);
1903
1904 cz_update_vce_dpm(adev);
1905 cz_enable_vce_dpm(adev, true);
1906 }
1907 } else {
1908 if (! pi->vce_power_gated) {
1909 cz_update_vce_dpm(adev);
1910 }
1911 }
1912 } else { /*pi->caps_vce_pg*/
1913 cz_update_vce_dpm(adev);
1914 cz_enable_vce_dpm(adev, true);
1915 }
1916
1917 return;
1918}
1919
5fc3aeeb 1920const struct amd_ip_funcs cz_dpm_ip_funcs = {
aaa36a97 1921 .early_init = cz_dpm_early_init,
564ea790 1922 .late_init = cz_dpm_late_init,
aaa36a97
AD		 1923 .sw_init = cz_dpm_sw_init,
1924 .sw_fini = cz_dpm_sw_fini,
1925 .hw_init = cz_dpm_hw_init,
1926 .hw_fini = cz_dpm_hw_fini,
1927 .suspend = cz_dpm_suspend,
1928 .resume = cz_dpm_resume,
1929 .is_idle = NULL,
1930 .wait_for_idle = NULL,
1931 .soft_reset = NULL,
1932 .print_status = NULL,
1933 .set_clockgating_state = cz_dpm_set_clockgating_state,
1934 .set_powergating_state = cz_dpm_set_powergating_state,
1935};
1936
1937static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
1938 .get_temperature = cz_dpm_get_temperature,
1939 .pre_set_power_state = cz_dpm_pre_set_power_state,
1940 .set_power_state = cz_dpm_set_power_state,
1941 .post_set_power_state = cz_dpm_post_set_power_state,
1942 .display_configuration_changed = cz_dpm_display_configuration_changed,
1943 .get_sclk = cz_dpm_get_sclk,
1944 .get_mclk = cz_dpm_get_mclk,
1945 .print_power_state = cz_dpm_print_power_state,
1946 .debugfs_print_current_performance_level =
1947 cz_dpm_debugfs_print_current_performance_level,
1948 .force_performance_level = cz_dpm_force_dpm_level,
1949 .vblank_too_short = NULL,
564ea790 1950 .powergate_uvd = cz_dpm_powergate_uvd,
b7a07769 1951 .powergate_vce = cz_dpm_powergate_vce,
aaa36a97
AD		 1952};
1953
1954static void cz_dpm_set_funcs(struct amdgpu_device *adev)
1955{
1956 if (NULL == adev->pm.funcs)
1957 adev->pm.funcs = &cz_dpm_funcs;
1958}
Linux kernel - Deliverables
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