Commit | Line | Data |
---|---|---|
aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include "drmP.h" | |
24 | #include "amdgpu.h" | |
25 | #include "amdgpu_pm.h" | |
26 | #include "amdgpu_i2c.h" | |
27 | #include "vid.h" | |
28 | #include "atom.h" | |
29 | #include "amdgpu_atombios.h" | |
30 | #include "atombios_crtc.h" | |
31 | #include "atombios_encoders.h" | |
32 | #include "amdgpu_pll.h" | |
33 | #include "amdgpu_connectors.h" | |
34 | ||
35 | #include "dce/dce_10_0_d.h" | |
36 | #include "dce/dce_10_0_sh_mask.h" | |
37 | #include "dce/dce_10_0_enum.h" | |
38 | #include "oss/oss_3_0_d.h" | |
39 | #include "oss/oss_3_0_sh_mask.h" | |
40 | #include "gmc/gmc_8_1_d.h" | |
41 | #include "gmc/gmc_8_1_sh_mask.h" | |
42 | ||
43 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); | |
44 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); | |
45 | ||
46 | static const u32 crtc_offsets[] = | |
47 | { | |
48 | CRTC0_REGISTER_OFFSET, | |
49 | CRTC1_REGISTER_OFFSET, | |
50 | CRTC2_REGISTER_OFFSET, | |
51 | CRTC3_REGISTER_OFFSET, | |
52 | CRTC4_REGISTER_OFFSET, | |
53 | CRTC5_REGISTER_OFFSET, | |
54 | CRTC6_REGISTER_OFFSET | |
55 | }; | |
56 | ||
57 | static const u32 hpd_offsets[] = | |
58 | { | |
59 | HPD0_REGISTER_OFFSET, | |
60 | HPD1_REGISTER_OFFSET, | |
61 | HPD2_REGISTER_OFFSET, | |
62 | HPD3_REGISTER_OFFSET, | |
63 | HPD4_REGISTER_OFFSET, | |
64 | HPD5_REGISTER_OFFSET | |
65 | }; | |
66 | ||
67 | static const uint32_t dig_offsets[] = { | |
68 | DIG0_REGISTER_OFFSET, | |
69 | DIG1_REGISTER_OFFSET, | |
70 | DIG2_REGISTER_OFFSET, | |
71 | DIG3_REGISTER_OFFSET, | |
72 | DIG4_REGISTER_OFFSET, | |
73 | DIG5_REGISTER_OFFSET, | |
74 | DIG6_REGISTER_OFFSET | |
75 | }; | |
76 | ||
77 | static const struct { | |
78 | uint32_t reg; | |
79 | uint32_t vblank; | |
80 | uint32_t vline; | |
81 | uint32_t hpd; | |
82 | ||
83 | } interrupt_status_offsets[] = { { | |
84 | .reg = mmDISP_INTERRUPT_STATUS, | |
85 | .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, | |
86 | .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, | |
87 | .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK | |
88 | }, { | |
89 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, | |
90 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, | |
91 | .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, | |
92 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK | |
93 | }, { | |
94 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, | |
95 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, | |
96 | .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, | |
97 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK | |
98 | }, { | |
99 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, | |
100 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, | |
101 | .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, | |
102 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK | |
103 | }, { | |
104 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, | |
105 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, | |
106 | .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, | |
107 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK | |
108 | }, { | |
109 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, | |
110 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, | |
111 | .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, | |
112 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK | |
113 | } }; | |
114 | ||
115 | static const u32 golden_settings_tonga_a11[] = | |
116 | { | |
117 | mmDCI_CLK_CNTL, 0x00000080, 0x00000000, | |
118 | mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, | |
119 | mmFBC_MISC, 0x1f311fff, 0x12300000, | |
120 | mmHDMI_CONTROL, 0x31000111, 0x00000011, | |
121 | }; | |
122 | ||
5732a94f AD |
123 | static const u32 tonga_mgcg_cgcg_init[] = |
124 | { | |
125 | mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, | |
126 | mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, | |
127 | }; | |
128 | ||
84390860 DZ |
129 | static const u32 golden_settings_fiji_a10[] = |
130 | { | |
131 | mmDCI_CLK_CNTL, 0x00000080, 0x00000000, | |
132 | mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, | |
133 | mmFBC_MISC, 0x1f311fff, 0x12300000, | |
134 | mmHDMI_CONTROL, 0x31000111, 0x00000011, | |
135 | }; | |
136 | ||
137 | static const u32 fiji_mgcg_cgcg_init[] = | |
138 | { | |
139 | mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, | |
140 | mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, | |
141 | }; | |
142 | ||
aaa36a97 AD |
143 | static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) |
144 | { | |
145 | switch (adev->asic_type) { | |
84390860 DZ |
146 | case CHIP_FIJI: |
147 | amdgpu_program_register_sequence(adev, | |
148 | fiji_mgcg_cgcg_init, | |
149 | (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); | |
150 | amdgpu_program_register_sequence(adev, | |
151 | golden_settings_fiji_a10, | |
152 | (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); | |
153 | break; | |
aaa36a97 | 154 | case CHIP_TONGA: |
5732a94f AD |
155 | amdgpu_program_register_sequence(adev, |
156 | tonga_mgcg_cgcg_init, | |
157 | (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); | |
aaa36a97 AD |
158 | amdgpu_program_register_sequence(adev, |
159 | golden_settings_tonga_a11, | |
160 | (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); | |
161 | break; | |
162 | default: | |
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, | |
168 | u32 block_offset, u32 reg) | |
169 | { | |
170 | unsigned long flags; | |
171 | u32 r; | |
172 | ||
173 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); | |
174 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); | |
175 | r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); | |
176 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); | |
177 | ||
178 | return r; | |
179 | } | |
180 | ||
181 | static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, | |
182 | u32 block_offset, u32 reg, u32 v) | |
183 | { | |
184 | unsigned long flags; | |
185 | ||
186 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); | |
187 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); | |
188 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); | |
189 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); | |
190 | } | |
191 | ||
192 | static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) | |
193 | { | |
194 | if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & | |
195 | CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) | |
196 | return true; | |
197 | else | |
198 | return false; | |
199 | } | |
200 | ||
201 | static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) | |
202 | { | |
203 | u32 pos1, pos2; | |
204 | ||
205 | pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
206 | pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
207 | ||
208 | if (pos1 != pos2) | |
209 | return true; | |
210 | else | |
211 | return false; | |
212 | } | |
213 | ||
214 | /** | |
215 | * dce_v10_0_vblank_wait - vblank wait asic callback. | |
216 | * | |
217 | * @adev: amdgpu_device pointer | |
218 | * @crtc: crtc to wait for vblank on | |
219 | * | |
220 | * Wait for vblank on the requested crtc (evergreen+). | |
221 | */ | |
222 | static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) | |
223 | { | |
224 | unsigned i = 0; | |
225 | ||
226 | if (crtc >= adev->mode_info.num_crtc) | |
227 | return; | |
228 | ||
229 | if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) | |
230 | return; | |
231 | ||
232 | /* depending on when we hit vblank, we may be close to active; if so, | |
233 | * wait for another frame. | |
234 | */ | |
235 | while (dce_v10_0_is_in_vblank(adev, crtc)) { | |
236 | if (i++ % 100 == 0) { | |
237 | if (!dce_v10_0_is_counter_moving(adev, crtc)) | |
238 | break; | |
239 | } | |
240 | } | |
241 | ||
242 | while (!dce_v10_0_is_in_vblank(adev, crtc)) { | |
243 | if (i++ % 100 == 0) { | |
244 | if (!dce_v10_0_is_counter_moving(adev, crtc)) | |
245 | break; | |
246 | } | |
247 | } | |
248 | } | |
249 | ||
250 | static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
251 | { | |
252 | if (crtc >= adev->mode_info.num_crtc) | |
253 | return 0; | |
254 | else | |
255 | return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); | |
256 | } | |
257 | ||
f6c7aba4 MD |
258 | static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) |
259 | { | |
260 | unsigned i; | |
261 | ||
262 | /* Enable pflip interrupts */ | |
263 | for (i = 0; i < adev->mode_info.num_crtc; i++) | |
264 | amdgpu_irq_get(adev, &adev->pageflip_irq, i); | |
265 | } | |
266 | ||
267 | static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) | |
268 | { | |
269 | unsigned i; | |
270 | ||
271 | /* Disable pflip interrupts */ | |
272 | for (i = 0; i < adev->mode_info.num_crtc; i++) | |
273 | amdgpu_irq_put(adev, &adev->pageflip_irq, i); | |
274 | } | |
275 | ||
aaa36a97 AD |
276 | /** |
277 | * dce_v10_0_page_flip - pageflip callback. | |
278 | * | |
279 | * @adev: amdgpu_device pointer | |
280 | * @crtc_id: crtc to cleanup pageflip on | |
281 | * @crtc_base: new address of the crtc (GPU MC address) | |
282 | * | |
283 | * Does the actual pageflip (evergreen+). | |
284 | * During vblank we take the crtc lock and wait for the update_pending | |
285 | * bit to go high, when it does, we release the lock, and allow the | |
286 | * double buffered update to take place. | |
287 | * Returns the current update pending status. | |
288 | */ | |
289 | static void dce_v10_0_page_flip(struct amdgpu_device *adev, | |
290 | int crtc_id, u64 crtc_base) | |
291 | { | |
292 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; | |
293 | u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); | |
294 | int i; | |
295 | ||
296 | /* Lock the graphics update lock */ | |
297 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); | |
298 | WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); | |
299 | ||
300 | /* update the scanout addresses */ | |
301 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
302 | upper_32_bits(crtc_base)); | |
303 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
304 | lower_32_bits(crtc_base)); | |
305 | ||
306 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
307 | upper_32_bits(crtc_base)); | |
308 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
309 | lower_32_bits(crtc_base)); | |
310 | ||
311 | /* Wait for update_pending to go high. */ | |
312 | for (i = 0; i < adev->usec_timeout; i++) { | |
313 | if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & | |
314 | GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) | |
315 | break; | |
316 | udelay(1); | |
317 | } | |
318 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); | |
319 | ||
320 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
321 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); | |
322 | WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); | |
323 | } | |
324 | ||
325 | static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
326 | u32 *vbl, u32 *position) | |
327 | { | |
328 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) | |
329 | return -EINVAL; | |
330 | ||
331 | *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); | |
332 | *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | /** | |
338 | * dce_v10_0_hpd_sense - hpd sense callback. | |
339 | * | |
340 | * @adev: amdgpu_device pointer | |
341 | * @hpd: hpd (hotplug detect) pin | |
342 | * | |
343 | * Checks if a digital monitor is connected (evergreen+). | |
344 | * Returns true if connected, false if not connected. | |
345 | */ | |
346 | static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, | |
347 | enum amdgpu_hpd_id hpd) | |
348 | { | |
349 | int idx; | |
350 | bool connected = false; | |
351 | ||
352 | switch (hpd) { | |
353 | case AMDGPU_HPD_1: | |
354 | idx = 0; | |
355 | break; | |
356 | case AMDGPU_HPD_2: | |
357 | idx = 1; | |
358 | break; | |
359 | case AMDGPU_HPD_3: | |
360 | idx = 2; | |
361 | break; | |
362 | case AMDGPU_HPD_4: | |
363 | idx = 3; | |
364 | break; | |
365 | case AMDGPU_HPD_5: | |
366 | idx = 4; | |
367 | break; | |
368 | case AMDGPU_HPD_6: | |
369 | idx = 5; | |
370 | break; | |
371 | default: | |
372 | return connected; | |
373 | } | |
374 | ||
375 | if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & | |
376 | DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) | |
377 | connected = true; | |
378 | ||
379 | return connected; | |
380 | } | |
381 | ||
382 | /** | |
383 | * dce_v10_0_hpd_set_polarity - hpd set polarity callback. | |
384 | * | |
385 | * @adev: amdgpu_device pointer | |
386 | * @hpd: hpd (hotplug detect) pin | |
387 | * | |
388 | * Set the polarity of the hpd pin (evergreen+). | |
389 | */ | |
390 | static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, | |
391 | enum amdgpu_hpd_id hpd) | |
392 | { | |
393 | u32 tmp; | |
394 | bool connected = dce_v10_0_hpd_sense(adev, hpd); | |
395 | int idx; | |
396 | ||
397 | switch (hpd) { | |
398 | case AMDGPU_HPD_1: | |
399 | idx = 0; | |
400 | break; | |
401 | case AMDGPU_HPD_2: | |
402 | idx = 1; | |
403 | break; | |
404 | case AMDGPU_HPD_3: | |
405 | idx = 2; | |
406 | break; | |
407 | case AMDGPU_HPD_4: | |
408 | idx = 3; | |
409 | break; | |
410 | case AMDGPU_HPD_5: | |
411 | idx = 4; | |
412 | break; | |
413 | case AMDGPU_HPD_6: | |
414 | idx = 5; | |
415 | break; | |
416 | default: | |
417 | return; | |
418 | } | |
419 | ||
420 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); | |
421 | if (connected) | |
422 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); | |
423 | else | |
424 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); | |
425 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); | |
426 | } | |
427 | ||
428 | /** | |
429 | * dce_v10_0_hpd_init - hpd setup callback. | |
430 | * | |
431 | * @adev: amdgpu_device pointer | |
432 | * | |
433 | * Setup the hpd pins used by the card (evergreen+). | |
434 | * Enable the pin, set the polarity, and enable the hpd interrupts. | |
435 | */ | |
436 | static void dce_v10_0_hpd_init(struct amdgpu_device *adev) | |
437 | { | |
438 | struct drm_device *dev = adev->ddev; | |
439 | struct drm_connector *connector; | |
440 | u32 tmp; | |
441 | int idx; | |
442 | ||
443 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
444 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
445 | ||
446 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || | |
447 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { | |
448 | /* don't try to enable hpd on eDP or LVDS avoid breaking the | |
449 | * aux dp channel on imac and help (but not completely fix) | |
450 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 | |
451 | * also avoid interrupt storms during dpms. | |
452 | */ | |
453 | continue; | |
454 | } | |
455 | ||
456 | switch (amdgpu_connector->hpd.hpd) { | |
457 | case AMDGPU_HPD_1: | |
458 | idx = 0; | |
459 | break; | |
460 | case AMDGPU_HPD_2: | |
461 | idx = 1; | |
462 | break; | |
463 | case AMDGPU_HPD_3: | |
464 | idx = 2; | |
465 | break; | |
466 | case AMDGPU_HPD_4: | |
467 | idx = 3; | |
468 | break; | |
469 | case AMDGPU_HPD_5: | |
470 | idx = 4; | |
471 | break; | |
472 | case AMDGPU_HPD_6: | |
473 | idx = 5; | |
474 | break; | |
475 | default: | |
476 | continue; | |
477 | } | |
478 | ||
479 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); | |
480 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); | |
481 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); | |
482 | ||
483 | tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); | |
484 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, | |
485 | DC_HPD_CONNECT_INT_DELAY, | |
486 | AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); | |
487 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, | |
488 | DC_HPD_DISCONNECT_INT_DELAY, | |
489 | AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); | |
490 | WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); | |
491 | ||
492 | dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); | |
493 | amdgpu_irq_get(adev, &adev->hpd_irq, | |
494 | amdgpu_connector->hpd.hpd); | |
495 | } | |
496 | } | |
497 | ||
498 | /** | |
499 | * dce_v10_0_hpd_fini - hpd tear down callback. | |
500 | * | |
501 | * @adev: amdgpu_device pointer | |
502 | * | |
503 | * Tear down the hpd pins used by the card (evergreen+). | |
504 | * Disable the hpd interrupts. | |
505 | */ | |
506 | static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) | |
507 | { | |
508 | struct drm_device *dev = adev->ddev; | |
509 | struct drm_connector *connector; | |
510 | u32 tmp; | |
511 | int idx; | |
512 | ||
513 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
514 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
515 | ||
516 | switch (amdgpu_connector->hpd.hpd) { | |
517 | case AMDGPU_HPD_1: | |
518 | idx = 0; | |
519 | break; | |
520 | case AMDGPU_HPD_2: | |
521 | idx = 1; | |
522 | break; | |
523 | case AMDGPU_HPD_3: | |
524 | idx = 2; | |
525 | break; | |
526 | case AMDGPU_HPD_4: | |
527 | idx = 3; | |
528 | break; | |
529 | case AMDGPU_HPD_5: | |
530 | idx = 4; | |
531 | break; | |
532 | case AMDGPU_HPD_6: | |
533 | idx = 5; | |
534 | break; | |
535 | default: | |
536 | continue; | |
537 | } | |
538 | ||
539 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); | |
540 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); | |
541 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); | |
542 | ||
543 | amdgpu_irq_put(adev, &adev->hpd_irq, | |
544 | amdgpu_connector->hpd.hpd); | |
545 | } | |
546 | } | |
547 | ||
548 | static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) | |
549 | { | |
550 | return mmDC_GPIO_HPD_A; | |
551 | } | |
552 | ||
553 | static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) | |
554 | { | |
555 | u32 crtc_hung = 0; | |
556 | u32 crtc_status[6]; | |
557 | u32 i, j, tmp; | |
558 | ||
559 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
560 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); | |
561 | if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { | |
562 | crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
563 | crtc_hung |= (1 << i); | |
564 | } | |
565 | } | |
566 | ||
567 | for (j = 0; j < 10; j++) { | |
568 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
569 | if (crtc_hung & (1 << i)) { | |
570 | tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
571 | if (tmp != crtc_status[i]) | |
572 | crtc_hung &= ~(1 << i); | |
573 | } | |
574 | } | |
575 | if (crtc_hung == 0) | |
576 | return false; | |
577 | udelay(100); | |
578 | } | |
579 | ||
580 | return true; | |
581 | } | |
582 | ||
583 | static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, | |
584 | struct amdgpu_mode_mc_save *save) | |
585 | { | |
586 | u32 crtc_enabled, tmp; | |
587 | int i; | |
588 | ||
589 | save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); | |
590 | save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); | |
591 | ||
592 | /* disable VGA render */ | |
593 | tmp = RREG32(mmVGA_RENDER_CONTROL); | |
594 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); | |
595 | WREG32(mmVGA_RENDER_CONTROL, tmp); | |
596 | ||
597 | /* blank the display controllers */ | |
598 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
599 | crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), | |
600 | CRTC_CONTROL, CRTC_MASTER_EN); | |
601 | if (crtc_enabled) { | |
602 | #if 0 | |
603 | u32 frame_count; | |
604 | int j; | |
605 | ||
606 | save->crtc_enabled[i] = true; | |
607 | tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); | |
608 | if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { | |
609 | amdgpu_display_vblank_wait(adev, i); | |
610 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
611 | tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); | |
612 | WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); | |
613 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
614 | } | |
615 | /* wait for the next frame */ | |
616 | frame_count = amdgpu_display_vblank_get_counter(adev, i); | |
617 | for (j = 0; j < adev->usec_timeout; j++) { | |
618 | if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) | |
619 | break; | |
620 | udelay(1); | |
621 | } | |
622 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); | |
623 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { | |
624 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); | |
625 | WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); | |
626 | } | |
627 | tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); | |
628 | if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { | |
629 | tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); | |
630 | WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); | |
631 | } | |
632 | #else | |
633 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ | |
634 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
635 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); | |
636 | tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); | |
637 | WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); | |
638 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
639 | save->crtc_enabled[i] = false; | |
640 | /* ***** */ | |
641 | #endif | |
642 | } else { | |
643 | save->crtc_enabled[i] = false; | |
644 | } | |
645 | } | |
646 | } | |
647 | ||
648 | static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, | |
649 | struct amdgpu_mode_mc_save *save) | |
650 | { | |
651 | u32 tmp, frame_count; | |
652 | int i, j; | |
653 | ||
654 | /* update crtc base addresses */ | |
655 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
656 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], | |
657 | upper_32_bits(adev->mc.vram_start)); | |
658 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], | |
659 | upper_32_bits(adev->mc.vram_start)); | |
660 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], | |
661 | (u32)adev->mc.vram_start); | |
662 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], | |
663 | (u32)adev->mc.vram_start); | |
664 | ||
665 | if (save->crtc_enabled[i]) { | |
666 | tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); | |
667 | if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { | |
668 | tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); | |
669 | WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); | |
670 | } | |
671 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); | |
672 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { | |
673 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); | |
674 | WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); | |
675 | } | |
676 | tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); | |
677 | if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { | |
678 | tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); | |
679 | WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); | |
680 | } | |
681 | for (j = 0; j < adev->usec_timeout; j++) { | |
682 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); | |
683 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) | |
684 | break; | |
685 | udelay(1); | |
686 | } | |
687 | tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); | |
688 | tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); | |
689 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
690 | WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); | |
691 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
692 | /* wait for the next frame */ | |
693 | frame_count = amdgpu_display_vblank_get_counter(adev, i); | |
694 | for (j = 0; j < adev->usec_timeout; j++) { | |
695 | if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) | |
696 | break; | |
697 | udelay(1); | |
698 | } | |
699 | } | |
700 | } | |
701 | ||
702 | WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); | |
703 | WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); | |
704 | ||
705 | /* Unlock vga access */ | |
706 | WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); | |
707 | mdelay(1); | |
708 | WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); | |
709 | } | |
710 | ||
711 | static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, | |
712 | bool render) | |
713 | { | |
714 | u32 tmp; | |
715 | ||
716 | /* Lockout access through VGA aperture*/ | |
717 | tmp = RREG32(mmVGA_HDP_CONTROL); | |
718 | if (render) | |
719 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); | |
720 | else | |
721 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); | |
722 | WREG32(mmVGA_HDP_CONTROL, tmp); | |
723 | ||
724 | /* disable VGA render */ | |
725 | tmp = RREG32(mmVGA_RENDER_CONTROL); | |
726 | if (render) | |
727 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); | |
728 | else | |
729 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); | |
730 | WREG32(mmVGA_RENDER_CONTROL, tmp); | |
731 | } | |
732 | ||
733 | static void dce_v10_0_program_fmt(struct drm_encoder *encoder) | |
734 | { | |
735 | struct drm_device *dev = encoder->dev; | |
736 | struct amdgpu_device *adev = dev->dev_private; | |
737 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
738 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); | |
739 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); | |
740 | int bpc = 0; | |
741 | u32 tmp = 0; | |
742 | enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; | |
743 | ||
744 | if (connector) { | |
745 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
746 | bpc = amdgpu_connector_get_monitor_bpc(connector); | |
747 | dither = amdgpu_connector->dither; | |
748 | } | |
749 | ||
750 | /* LVDS/eDP FMT is set up by atom */ | |
751 | if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
752 | return; | |
753 | ||
754 | /* not needed for analog */ | |
755 | if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || | |
756 | (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) | |
757 | return; | |
758 | ||
759 | if (bpc == 0) | |
760 | return; | |
761 | ||
762 | switch (bpc) { | |
763 | case 6: | |
764 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { | |
765 | /* XXX sort out optimal dither settings */ | |
766 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); | |
767 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); | |
768 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); | |
769 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); | |
770 | } else { | |
771 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); | |
772 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); | |
773 | } | |
774 | break; | |
775 | case 8: | |
776 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { | |
777 | /* XXX sort out optimal dither settings */ | |
778 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); | |
779 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); | |
780 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); | |
781 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); | |
782 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); | |
783 | } else { | |
784 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); | |
785 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); | |
786 | } | |
787 | break; | |
788 | case 10: | |
789 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { | |
790 | /* XXX sort out optimal dither settings */ | |
791 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); | |
792 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); | |
793 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); | |
794 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); | |
795 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); | |
796 | } else { | |
797 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); | |
798 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); | |
799 | } | |
800 | break; | |
801 | default: | |
802 | /* not needed */ | |
803 | break; | |
804 | } | |
805 | ||
806 | WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
807 | } | |
808 | ||
809 | ||
810 | /* display watermark setup */ | |
811 | /** | |
812 | * dce_v10_0_line_buffer_adjust - Set up the line buffer | |
813 | * | |
814 | * @adev: amdgpu_device pointer | |
815 | * @amdgpu_crtc: the selected display controller | |
816 | * @mode: the current display mode on the selected display | |
817 | * controller | |
818 | * | |
819 | * Setup up the line buffer allocation for | |
820 | * the selected display controller (CIK). | |
821 | * Returns the line buffer size in pixels. | |
822 | */ | |
823 | static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, | |
824 | struct amdgpu_crtc *amdgpu_crtc, | |
825 | struct drm_display_mode *mode) | |
826 | { | |
827 | u32 tmp, buffer_alloc, i, mem_cfg; | |
828 | u32 pipe_offset = amdgpu_crtc->crtc_id; | |
829 | /* | |
830 | * Line Buffer Setup | |
831 | * There are 6 line buffers, one for each display controllers. | |
832 | * There are 3 partitions per LB. Select the number of partitions | |
833 | * to enable based on the display width. For display widths larger | |
834 | * than 4096, you need use to use 2 display controllers and combine | |
835 | * them using the stereo blender. | |
836 | */ | |
837 | if (amdgpu_crtc->base.enabled && mode) { | |
838 | if (mode->crtc_hdisplay < 1920) { | |
839 | mem_cfg = 1; | |
840 | buffer_alloc = 2; | |
841 | } else if (mode->crtc_hdisplay < 2560) { | |
842 | mem_cfg = 2; | |
843 | buffer_alloc = 2; | |
844 | } else if (mode->crtc_hdisplay < 4096) { | |
845 | mem_cfg = 0; | |
2f7d10b3 | 846 | buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; |
aaa36a97 AD |
847 | } else { |
848 | DRM_DEBUG_KMS("Mode too big for LB!\n"); | |
849 | mem_cfg = 0; | |
2f7d10b3 | 850 | buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; |
aaa36a97 AD |
851 | } |
852 | } else { | |
853 | mem_cfg = 1; | |
854 | buffer_alloc = 0; | |
855 | } | |
856 | ||
857 | tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); | |
858 | tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); | |
859 | WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); | |
860 | ||
861 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); | |
862 | tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); | |
863 | WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); | |
864 | ||
865 | for (i = 0; i < adev->usec_timeout; i++) { | |
866 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); | |
867 | if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) | |
868 | break; | |
869 | udelay(1); | |
870 | } | |
871 | ||
872 | if (amdgpu_crtc->base.enabled && mode) { | |
873 | switch (mem_cfg) { | |
874 | case 0: | |
875 | default: | |
876 | return 4096 * 2; | |
877 | case 1: | |
878 | return 1920 * 2; | |
879 | case 2: | |
880 | return 2560 * 2; | |
881 | } | |
882 | } | |
883 | ||
884 | /* controller not enabled, so no lb used */ | |
885 | return 0; | |
886 | } | |
887 | ||
888 | /** | |
889 | * cik_get_number_of_dram_channels - get the number of dram channels | |
890 | * | |
891 | * @adev: amdgpu_device pointer | |
892 | * | |
893 | * Look up the number of video ram channels (CIK). | |
894 | * Used for display watermark bandwidth calculations | |
895 | * Returns the number of dram channels | |
896 | */ | |
897 | static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) | |
898 | { | |
899 | u32 tmp = RREG32(mmMC_SHARED_CHMAP); | |
900 | ||
901 | switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { | |
902 | case 0: | |
903 | default: | |
904 | return 1; | |
905 | case 1: | |
906 | return 2; | |
907 | case 2: | |
908 | return 4; | |
909 | case 3: | |
910 | return 8; | |
911 | case 4: | |
912 | return 3; | |
913 | case 5: | |
914 | return 6; | |
915 | case 6: | |
916 | return 10; | |
917 | case 7: | |
918 | return 12; | |
919 | case 8: | |
920 | return 16; | |
921 | } | |
922 | } | |
923 | ||
924 | struct dce10_wm_params { | |
925 | u32 dram_channels; /* number of dram channels */ | |
926 | u32 yclk; /* bandwidth per dram data pin in kHz */ | |
927 | u32 sclk; /* engine clock in kHz */ | |
928 | u32 disp_clk; /* display clock in kHz */ | |
929 | u32 src_width; /* viewport width */ | |
930 | u32 active_time; /* active display time in ns */ | |
931 | u32 blank_time; /* blank time in ns */ | |
932 | bool interlaced; /* mode is interlaced */ | |
933 | fixed20_12 vsc; /* vertical scale ratio */ | |
934 | u32 num_heads; /* number of active crtcs */ | |
935 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ | |
936 | u32 lb_size; /* line buffer allocated to pipe */ | |
937 | u32 vtaps; /* vertical scaler taps */ | |
938 | }; | |
939 | ||
940 | /** | |
941 | * dce_v10_0_dram_bandwidth - get the dram bandwidth | |
942 | * | |
943 | * @wm: watermark calculation data | |
944 | * | |
945 | * Calculate the raw dram bandwidth (CIK). | |
946 | * Used for display watermark bandwidth calculations | |
947 | * Returns the dram bandwidth in MBytes/s | |
948 | */ | |
949 | static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) | |
950 | { | |
951 | /* Calculate raw DRAM Bandwidth */ | |
952 | fixed20_12 dram_efficiency; /* 0.7 */ | |
953 | fixed20_12 yclk, dram_channels, bandwidth; | |
954 | fixed20_12 a; | |
955 | ||
956 | a.full = dfixed_const(1000); | |
957 | yclk.full = dfixed_const(wm->yclk); | |
958 | yclk.full = dfixed_div(yclk, a); | |
959 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
960 | a.full = dfixed_const(10); | |
961 | dram_efficiency.full = dfixed_const(7); | |
962 | dram_efficiency.full = dfixed_div(dram_efficiency, a); | |
963 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
964 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); | |
965 | ||
966 | return dfixed_trunc(bandwidth); | |
967 | } | |
968 | ||
969 | /** | |
970 | * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display | |
971 | * | |
972 | * @wm: watermark calculation data | |
973 | * | |
974 | * Calculate the dram bandwidth used for display (CIK). | |
975 | * Used for display watermark bandwidth calculations | |
976 | * Returns the dram bandwidth for display in MBytes/s | |
977 | */ | |
978 | static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) | |
979 | { | |
980 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
981 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ | |
982 | fixed20_12 yclk, dram_channels, bandwidth; | |
983 | fixed20_12 a; | |
984 | ||
985 | a.full = dfixed_const(1000); | |
986 | yclk.full = dfixed_const(wm->yclk); | |
987 | yclk.full = dfixed_div(yclk, a); | |
988 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
989 | a.full = dfixed_const(10); | |
990 | disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ | |
991 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); | |
992 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
993 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); | |
994 | ||
995 | return dfixed_trunc(bandwidth); | |
996 | } | |
997 | ||
998 | /** | |
999 | * dce_v10_0_data_return_bandwidth - get the data return bandwidth | |
1000 | * | |
1001 | * @wm: watermark calculation data | |
1002 | * | |
1003 | * Calculate the data return bandwidth used for display (CIK). | |
1004 | * Used for display watermark bandwidth calculations | |
1005 | * Returns the data return bandwidth in MBytes/s | |
1006 | */ | |
1007 | static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) | |
1008 | { | |
1009 | /* Calculate the display Data return Bandwidth */ | |
1010 | fixed20_12 return_efficiency; /* 0.8 */ | |
1011 | fixed20_12 sclk, bandwidth; | |
1012 | fixed20_12 a; | |
1013 | ||
1014 | a.full = dfixed_const(1000); | |
1015 | sclk.full = dfixed_const(wm->sclk); | |
1016 | sclk.full = dfixed_div(sclk, a); | |
1017 | a.full = dfixed_const(10); | |
1018 | return_efficiency.full = dfixed_const(8); | |
1019 | return_efficiency.full = dfixed_div(return_efficiency, a); | |
1020 | a.full = dfixed_const(32); | |
1021 | bandwidth.full = dfixed_mul(a, sclk); | |
1022 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency); | |
1023 | ||
1024 | return dfixed_trunc(bandwidth); | |
1025 | } | |
1026 | ||
1027 | /** | |
1028 | * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth | |
1029 | * | |
1030 | * @wm: watermark calculation data | |
1031 | * | |
1032 | * Calculate the dmif bandwidth used for display (CIK). | |
1033 | * Used for display watermark bandwidth calculations | |
1034 | * Returns the dmif bandwidth in MBytes/s | |
1035 | */ | |
1036 | static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) | |
1037 | { | |
1038 | /* Calculate the DMIF Request Bandwidth */ | |
1039 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ | |
1040 | fixed20_12 disp_clk, bandwidth; | |
1041 | fixed20_12 a, b; | |
1042 | ||
1043 | a.full = dfixed_const(1000); | |
1044 | disp_clk.full = dfixed_const(wm->disp_clk); | |
1045 | disp_clk.full = dfixed_div(disp_clk, a); | |
1046 | a.full = dfixed_const(32); | |
1047 | b.full = dfixed_mul(a, disp_clk); | |
1048 | ||
1049 | a.full = dfixed_const(10); | |
1050 | disp_clk_request_efficiency.full = dfixed_const(8); | |
1051 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); | |
1052 | ||
1053 | bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); | |
1054 | ||
1055 | return dfixed_trunc(bandwidth); | |
1056 | } | |
1057 | ||
1058 | /** | |
1059 | * dce_v10_0_available_bandwidth - get the min available bandwidth | |
1060 | * | |
1061 | * @wm: watermark calculation data | |
1062 | * | |
1063 | * Calculate the min available bandwidth used for display (CIK). | |
1064 | * Used for display watermark bandwidth calculations | |
1065 | * Returns the min available bandwidth in MBytes/s | |
1066 | */ | |
1067 | static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) | |
1068 | { | |
1069 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ | |
1070 | u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); | |
1071 | u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); | |
1072 | u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); | |
1073 | ||
1074 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); | |
1075 | } | |
1076 | ||
1077 | /** | |
1078 | * dce_v10_0_average_bandwidth - get the average available bandwidth | |
1079 | * | |
1080 | * @wm: watermark calculation data | |
1081 | * | |
1082 | * Calculate the average available bandwidth used for display (CIK). | |
1083 | * Used for display watermark bandwidth calculations | |
1084 | * Returns the average available bandwidth in MBytes/s | |
1085 | */ | |
1086 | static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) | |
1087 | { | |
1088 | /* Calculate the display mode Average Bandwidth | |
1089 | * DisplayMode should contain the source and destination dimensions, | |
1090 | * timing, etc. | |
1091 | */ | |
1092 | fixed20_12 bpp; | |
1093 | fixed20_12 line_time; | |
1094 | fixed20_12 src_width; | |
1095 | fixed20_12 bandwidth; | |
1096 | fixed20_12 a; | |
1097 | ||
1098 | a.full = dfixed_const(1000); | |
1099 | line_time.full = dfixed_const(wm->active_time + wm->blank_time); | |
1100 | line_time.full = dfixed_div(line_time, a); | |
1101 | bpp.full = dfixed_const(wm->bytes_per_pixel); | |
1102 | src_width.full = dfixed_const(wm->src_width); | |
1103 | bandwidth.full = dfixed_mul(src_width, bpp); | |
1104 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc); | |
1105 | bandwidth.full = dfixed_div(bandwidth, line_time); | |
1106 | ||
1107 | return dfixed_trunc(bandwidth); | |
1108 | } | |
1109 | ||
1110 | /** | |
1111 | * dce_v10_0_latency_watermark - get the latency watermark | |
1112 | * | |
1113 | * @wm: watermark calculation data | |
1114 | * | |
1115 | * Calculate the latency watermark (CIK). | |
1116 | * Used for display watermark bandwidth calculations | |
1117 | * Returns the latency watermark in ns | |
1118 | */ | |
1119 | static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) | |
1120 | { | |
1121 | /* First calculate the latency in ns */ | |
1122 | u32 mc_latency = 2000; /* 2000 ns. */ | |
1123 | u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); | |
1124 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; | |
1125 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; | |
1126 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ | |
1127 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + | |
1128 | (wm->num_heads * cursor_line_pair_return_time); | |
1129 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; | |
1130 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; | |
1131 | u32 tmp, dmif_size = 12288; | |
1132 | fixed20_12 a, b, c; | |
1133 | ||
1134 | if (wm->num_heads == 0) | |
1135 | return 0; | |
1136 | ||
1137 | a.full = dfixed_const(2); | |
1138 | b.full = dfixed_const(1); | |
1139 | if ((wm->vsc.full > a.full) || | |
1140 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || | |
1141 | (wm->vtaps >= 5) || | |
1142 | ((wm->vsc.full >= a.full) && wm->interlaced)) | |
1143 | max_src_lines_per_dst_line = 4; | |
1144 | else | |
1145 | max_src_lines_per_dst_line = 2; | |
1146 | ||
1147 | a.full = dfixed_const(available_bandwidth); | |
1148 | b.full = dfixed_const(wm->num_heads); | |
1149 | a.full = dfixed_div(a, b); | |
1150 | ||
1151 | b.full = dfixed_const(mc_latency + 512); | |
1152 | c.full = dfixed_const(wm->disp_clk); | |
1153 | b.full = dfixed_div(b, c); | |
1154 | ||
1155 | c.full = dfixed_const(dmif_size); | |
1156 | b.full = dfixed_div(c, b); | |
1157 | ||
1158 | tmp = min(dfixed_trunc(a), dfixed_trunc(b)); | |
1159 | ||
1160 | b.full = dfixed_const(1000); | |
1161 | c.full = dfixed_const(wm->disp_clk); | |
1162 | b.full = dfixed_div(c, b); | |
1163 | c.full = dfixed_const(wm->bytes_per_pixel); | |
1164 | b.full = dfixed_mul(b, c); | |
1165 | ||
1166 | lb_fill_bw = min(tmp, dfixed_trunc(b)); | |
1167 | ||
1168 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | |
1169 | b.full = dfixed_const(1000); | |
1170 | c.full = dfixed_const(lb_fill_bw); | |
1171 | b.full = dfixed_div(c, b); | |
1172 | a.full = dfixed_div(a, b); | |
1173 | line_fill_time = dfixed_trunc(a); | |
1174 | ||
1175 | if (line_fill_time < wm->active_time) | |
1176 | return latency; | |
1177 | else | |
1178 | return latency + (line_fill_time - wm->active_time); | |
1179 | ||
1180 | } | |
1181 | ||
1182 | /** | |
1183 | * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check | |
1184 | * average and available dram bandwidth | |
1185 | * | |
1186 | * @wm: watermark calculation data | |
1187 | * | |
1188 | * Check if the display average bandwidth fits in the display | |
1189 | * dram bandwidth (CIK). | |
1190 | * Used for display watermark bandwidth calculations | |
1191 | * Returns true if the display fits, false if not. | |
1192 | */ | |
1193 | static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) | |
1194 | { | |
1195 | if (dce_v10_0_average_bandwidth(wm) <= | |
1196 | (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) | |
1197 | return true; | |
1198 | else | |
1199 | return false; | |
1200 | } | |
1201 | ||
1202 | /** | |
1203 | * dce_v10_0_average_bandwidth_vs_available_bandwidth - check | |
1204 | * average and available bandwidth | |
1205 | * | |
1206 | * @wm: watermark calculation data | |
1207 | * | |
1208 | * Check if the display average bandwidth fits in the display | |
1209 | * available bandwidth (CIK). | |
1210 | * Used for display watermark bandwidth calculations | |
1211 | * Returns true if the display fits, false if not. | |
1212 | */ | |
1213 | static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) | |
1214 | { | |
1215 | if (dce_v10_0_average_bandwidth(wm) <= | |
1216 | (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) | |
1217 | return true; | |
1218 | else | |
1219 | return false; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * dce_v10_0_check_latency_hiding - check latency hiding | |
1224 | * | |
1225 | * @wm: watermark calculation data | |
1226 | * | |
1227 | * Check latency hiding (CIK). | |
1228 | * Used for display watermark bandwidth calculations | |
1229 | * Returns true if the display fits, false if not. | |
1230 | */ | |
1231 | static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) | |
1232 | { | |
1233 | u32 lb_partitions = wm->lb_size / wm->src_width; | |
1234 | u32 line_time = wm->active_time + wm->blank_time; | |
1235 | u32 latency_tolerant_lines; | |
1236 | u32 latency_hiding; | |
1237 | fixed20_12 a; | |
1238 | ||
1239 | a.full = dfixed_const(1); | |
1240 | if (wm->vsc.full > a.full) | |
1241 | latency_tolerant_lines = 1; | |
1242 | else { | |
1243 | if (lb_partitions <= (wm->vtaps + 1)) | |
1244 | latency_tolerant_lines = 1; | |
1245 | else | |
1246 | latency_tolerant_lines = 2; | |
1247 | } | |
1248 | ||
1249 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); | |
1250 | ||
1251 | if (dce_v10_0_latency_watermark(wm) <= latency_hiding) | |
1252 | return true; | |
1253 | else | |
1254 | return false; | |
1255 | } | |
1256 | ||
1257 | /** | |
1258 | * dce_v10_0_program_watermarks - program display watermarks | |
1259 | * | |
1260 | * @adev: amdgpu_device pointer | |
1261 | * @amdgpu_crtc: the selected display controller | |
1262 | * @lb_size: line buffer size | |
1263 | * @num_heads: number of display controllers in use | |
1264 | * | |
1265 | * Calculate and program the display watermarks for the | |
1266 | * selected display controller (CIK). | |
1267 | */ | |
1268 | static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, | |
1269 | struct amdgpu_crtc *amdgpu_crtc, | |
1270 | u32 lb_size, u32 num_heads) | |
1271 | { | |
1272 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; | |
1273 | struct dce10_wm_params wm_low, wm_high; | |
1274 | u32 pixel_period; | |
1275 | u32 line_time = 0; | |
1276 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | |
1277 | u32 tmp, wm_mask; | |
1278 | ||
1279 | if (amdgpu_crtc->base.enabled && num_heads && mode) { | |
1280 | pixel_period = 1000000 / (u32)mode->clock; | |
1281 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | |
1282 | ||
1283 | /* watermark for high clocks */ | |
1284 | if (adev->pm.dpm_enabled) { | |
1285 | wm_high.yclk = | |
1286 | amdgpu_dpm_get_mclk(adev, false) * 10; | |
1287 | wm_high.sclk = | |
1288 | amdgpu_dpm_get_sclk(adev, false) * 10; | |
1289 | } else { | |
1290 | wm_high.yclk = adev->pm.current_mclk * 10; | |
1291 | wm_high.sclk = adev->pm.current_sclk * 10; | |
1292 | } | |
1293 | ||
1294 | wm_high.disp_clk = mode->clock; | |
1295 | wm_high.src_width = mode->crtc_hdisplay; | |
1296 | wm_high.active_time = mode->crtc_hdisplay * pixel_period; | |
1297 | wm_high.blank_time = line_time - wm_high.active_time; | |
1298 | wm_high.interlaced = false; | |
1299 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1300 | wm_high.interlaced = true; | |
1301 | wm_high.vsc = amdgpu_crtc->vsc; | |
1302 | wm_high.vtaps = 1; | |
1303 | if (amdgpu_crtc->rmx_type != RMX_OFF) | |
1304 | wm_high.vtaps = 2; | |
1305 | wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
1306 | wm_high.lb_size = lb_size; | |
1307 | wm_high.dram_channels = cik_get_number_of_dram_channels(adev); | |
1308 | wm_high.num_heads = num_heads; | |
1309 | ||
1310 | /* set for high clocks */ | |
1311 | latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); | |
1312 | ||
1313 | /* possibly force display priority to high */ | |
1314 | /* should really do this at mode validation time... */ | |
1315 | if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || | |
1316 | !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || | |
1317 | !dce_v10_0_check_latency_hiding(&wm_high) || | |
1318 | (adev->mode_info.disp_priority == 2)) { | |
1319 | DRM_DEBUG_KMS("force priority to high\n"); | |
1320 | } | |
1321 | ||
1322 | /* watermark for low clocks */ | |
1323 | if (adev->pm.dpm_enabled) { | |
1324 | wm_low.yclk = | |
1325 | amdgpu_dpm_get_mclk(adev, true) * 10; | |
1326 | wm_low.sclk = | |
1327 | amdgpu_dpm_get_sclk(adev, true) * 10; | |
1328 | } else { | |
1329 | wm_low.yclk = adev->pm.current_mclk * 10; | |
1330 | wm_low.sclk = adev->pm.current_sclk * 10; | |
1331 | } | |
1332 | ||
1333 | wm_low.disp_clk = mode->clock; | |
1334 | wm_low.src_width = mode->crtc_hdisplay; | |
1335 | wm_low.active_time = mode->crtc_hdisplay * pixel_period; | |
1336 | wm_low.blank_time = line_time - wm_low.active_time; | |
1337 | wm_low.interlaced = false; | |
1338 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1339 | wm_low.interlaced = true; | |
1340 | wm_low.vsc = amdgpu_crtc->vsc; | |
1341 | wm_low.vtaps = 1; | |
1342 | if (amdgpu_crtc->rmx_type != RMX_OFF) | |
1343 | wm_low.vtaps = 2; | |
1344 | wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
1345 | wm_low.lb_size = lb_size; | |
1346 | wm_low.dram_channels = cik_get_number_of_dram_channels(adev); | |
1347 | wm_low.num_heads = num_heads; | |
1348 | ||
1349 | /* set for low clocks */ | |
1350 | latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); | |
1351 | ||
1352 | /* possibly force display priority to high */ | |
1353 | /* should really do this at mode validation time... */ | |
1354 | if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || | |
1355 | !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || | |
1356 | !dce_v10_0_check_latency_hiding(&wm_low) || | |
1357 | (adev->mode_info.disp_priority == 2)) { | |
1358 | DRM_DEBUG_KMS("force priority to high\n"); | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | /* select wm A */ | |
1363 | wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); | |
1364 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); | |
1365 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1366 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); | |
1367 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); | |
1368 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); | |
1369 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1370 | /* select wm B */ | |
1371 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); | |
1372 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1373 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); | |
be9fd2e9 | 1374 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); |
aaa36a97 AD |
1375 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); |
1376 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1377 | /* restore original selection */ | |
1378 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); | |
1379 | ||
1380 | /* save values for DPM */ | |
1381 | amdgpu_crtc->line_time = line_time; | |
1382 | amdgpu_crtc->wm_high = latency_watermark_a; | |
1383 | amdgpu_crtc->wm_low = latency_watermark_b; | |
1384 | } | |
1385 | ||
1386 | /** | |
1387 | * dce_v10_0_bandwidth_update - program display watermarks | |
1388 | * | |
1389 | * @adev: amdgpu_device pointer | |
1390 | * | |
1391 | * Calculate and program the display watermarks and line | |
1392 | * buffer allocation (CIK). | |
1393 | */ | |
1394 | static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) | |
1395 | { | |
1396 | struct drm_display_mode *mode = NULL; | |
1397 | u32 num_heads = 0, lb_size; | |
1398 | int i; | |
1399 | ||
1400 | amdgpu_update_display_priority(adev); | |
1401 | ||
1402 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
1403 | if (adev->mode_info.crtcs[i]->base.enabled) | |
1404 | num_heads++; | |
1405 | } | |
1406 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
1407 | mode = &adev->mode_info.crtcs[i]->base.mode; | |
1408 | lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); | |
1409 | dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], | |
1410 | lb_size, num_heads); | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) | |
1415 | { | |
1416 | int i; | |
1417 | u32 offset, tmp; | |
1418 | ||
1419 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1420 | offset = adev->mode_info.audio.pin[i].offset; | |
1421 | tmp = RREG32_AUDIO_ENDPT(offset, | |
1422 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); | |
1423 | if (((tmp & | |
1424 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> | |
1425 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) | |
1426 | adev->mode_info.audio.pin[i].connected = false; | |
1427 | else | |
1428 | adev->mode_info.audio.pin[i].connected = true; | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) | |
1433 | { | |
1434 | int i; | |
1435 | ||
1436 | dce_v10_0_audio_get_connected_pins(adev); | |
1437 | ||
1438 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1439 | if (adev->mode_info.audio.pin[i].connected) | |
1440 | return &adev->mode_info.audio.pin[i]; | |
1441 | } | |
1442 | DRM_ERROR("No connected audio pins found!\n"); | |
1443 | return NULL; | |
1444 | } | |
1445 | ||
1446 | static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) | |
1447 | { | |
1448 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1449 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1450 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1451 | u32 tmp; | |
1452 | ||
1453 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1454 | return; | |
1455 | ||
1456 | tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); | |
1457 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); | |
1458 | WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); | |
1459 | } | |
1460 | ||
1461 | static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, | |
1462 | struct drm_display_mode *mode) | |
1463 | { | |
1464 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1465 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1466 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1467 | struct drm_connector *connector; | |
1468 | struct amdgpu_connector *amdgpu_connector = NULL; | |
1469 | u32 tmp; | |
1470 | int interlace = 0; | |
1471 | ||
1472 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1473 | return; | |
1474 | ||
1475 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
1476 | if (connector->encoder == encoder) { | |
1477 | amdgpu_connector = to_amdgpu_connector(connector); | |
1478 | break; | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | if (!amdgpu_connector) { | |
1483 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
1484 | return; | |
1485 | } | |
1486 | ||
1487 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1488 | interlace = 1; | |
1489 | if (connector->latency_present[interlace]) { | |
1490 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1491 | VIDEO_LIPSYNC, connector->video_latency[interlace]); | |
1492 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1493 | AUDIO_LIPSYNC, connector->audio_latency[interlace]); | |
1494 | } else { | |
1495 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1496 | VIDEO_LIPSYNC, 0); | |
1497 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1498 | AUDIO_LIPSYNC, 0); | |
1499 | } | |
1500 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, | |
1501 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); | |
1502 | } | |
1503 | ||
1504 | static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) | |
1505 | { | |
1506 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1507 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1508 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1509 | struct drm_connector *connector; | |
1510 | struct amdgpu_connector *amdgpu_connector = NULL; | |
1511 | u32 tmp; | |
1512 | u8 *sadb = NULL; | |
1513 | int sad_count; | |
1514 | ||
1515 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1516 | return; | |
1517 | ||
1518 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
1519 | if (connector->encoder == encoder) { | |
1520 | amdgpu_connector = to_amdgpu_connector(connector); | |
1521 | break; | |
1522 | } | |
1523 | } | |
1524 | ||
1525 | if (!amdgpu_connector) { | |
1526 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
1527 | return; | |
1528 | } | |
1529 | ||
1530 | sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); | |
1531 | if (sad_count < 0) { | |
1532 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); | |
1533 | sad_count = 0; | |
1534 | } | |
1535 | ||
1536 | /* program the speaker allocation */ | |
1537 | tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, | |
1538 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); | |
1539 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1540 | DP_CONNECTION, 0); | |
1541 | /* set HDMI mode */ | |
1542 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1543 | HDMI_CONNECTION, 1); | |
1544 | if (sad_count) | |
1545 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1546 | SPEAKER_ALLOCATION, sadb[0]); | |
1547 | else | |
1548 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1549 | SPEAKER_ALLOCATION, 5); /* stereo */ | |
1550 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, | |
1551 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); | |
1552 | ||
1553 | kfree(sadb); | |
1554 | } | |
1555 | ||
1556 | static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) | |
1557 | { | |
1558 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1559 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1560 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1561 | struct drm_connector *connector; | |
1562 | struct amdgpu_connector *amdgpu_connector = NULL; | |
1563 | struct cea_sad *sads; | |
1564 | int i, sad_count; | |
1565 | ||
1566 | static const u16 eld_reg_to_type[][2] = { | |
1567 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
1568 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
1569 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
1570 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
1571 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
1572 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
1573 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
1574 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
1575 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
1576 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
1577 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
1578 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
1579 | }; | |
1580 | ||
1581 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1582 | return; | |
1583 | ||
1584 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
1585 | if (connector->encoder == encoder) { | |
1586 | amdgpu_connector = to_amdgpu_connector(connector); | |
1587 | break; | |
1588 | } | |
1589 | } | |
1590 | ||
1591 | if (!amdgpu_connector) { | |
1592 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
1593 | return; | |
1594 | } | |
1595 | ||
1596 | sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); | |
1597 | if (sad_count <= 0) { | |
1598 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); | |
1599 | return; | |
1600 | } | |
1601 | BUG_ON(!sads); | |
1602 | ||
1603 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { | |
1604 | u32 tmp = 0; | |
1605 | u8 stereo_freqs = 0; | |
1606 | int max_channels = -1; | |
1607 | int j; | |
1608 | ||
1609 | for (j = 0; j < sad_count; j++) { | |
1610 | struct cea_sad *sad = &sads[j]; | |
1611 | ||
1612 | if (sad->format == eld_reg_to_type[i][1]) { | |
1613 | if (sad->channels > max_channels) { | |
1614 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1615 | MAX_CHANNELS, sad->channels); | |
1616 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1617 | DESCRIPTOR_BYTE_2, sad->byte2); | |
1618 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1619 | SUPPORTED_FREQUENCIES, sad->freq); | |
1620 | max_channels = sad->channels; | |
1621 | } | |
1622 | ||
1623 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) | |
1624 | stereo_freqs |= sad->freq; | |
1625 | else | |
1626 | break; | |
1627 | } | |
1628 | } | |
1629 | ||
1630 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1631 | SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); | |
1632 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); | |
1633 | } | |
1634 | ||
1635 | kfree(sads); | |
1636 | } | |
1637 | ||
1638 | static void dce_v10_0_audio_enable(struct amdgpu_device *adev, | |
1639 | struct amdgpu_audio_pin *pin, | |
1640 | bool enable) | |
1641 | { | |
1642 | if (!pin) | |
1643 | return; | |
1644 | ||
1645 | WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | |
1646 | enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); | |
1647 | } | |
1648 | ||
1649 | static const u32 pin_offsets[] = | |
1650 | { | |
1651 | AUD0_REGISTER_OFFSET, | |
1652 | AUD1_REGISTER_OFFSET, | |
1653 | AUD2_REGISTER_OFFSET, | |
1654 | AUD3_REGISTER_OFFSET, | |
1655 | AUD4_REGISTER_OFFSET, | |
1656 | AUD5_REGISTER_OFFSET, | |
1657 | AUD6_REGISTER_OFFSET, | |
1658 | }; | |
1659 | ||
1660 | static int dce_v10_0_audio_init(struct amdgpu_device *adev) | |
1661 | { | |
1662 | int i; | |
1663 | ||
1664 | if (!amdgpu_audio) | |
1665 | return 0; | |
1666 | ||
1667 | adev->mode_info.audio.enabled = true; | |
1668 | ||
1669 | adev->mode_info.audio.num_pins = 7; | |
1670 | ||
1671 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1672 | adev->mode_info.audio.pin[i].channels = -1; | |
1673 | adev->mode_info.audio.pin[i].rate = -1; | |
1674 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
1675 | adev->mode_info.audio.pin[i].status_bits = 0; | |
1676 | adev->mode_info.audio.pin[i].category_code = 0; | |
1677 | adev->mode_info.audio.pin[i].connected = false; | |
1678 | adev->mode_info.audio.pin[i].offset = pin_offsets[i]; | |
1679 | adev->mode_info.audio.pin[i].id = i; | |
1680 | /* disable audio. it will be set up later */ | |
1681 | /* XXX remove once we switch to ip funcs */ | |
1682 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
1683 | } | |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | static void dce_v10_0_audio_fini(struct amdgpu_device *adev) | |
1689 | { | |
1690 | int i; | |
1691 | ||
1692 | if (!adev->mode_info.audio.enabled) | |
1693 | return; | |
1694 | ||
1695 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) | |
1696 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
1697 | ||
1698 | adev->mode_info.audio.enabled = false; | |
1699 | } | |
1700 | ||
1701 | /* | |
1702 | * update the N and CTS parameters for a given pixel clock rate | |
1703 | */ | |
1704 | static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
1705 | { | |
1706 | struct drm_device *dev = encoder->dev; | |
1707 | struct amdgpu_device *adev = dev->dev_private; | |
1708 | struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); | |
1709 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1710 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1711 | u32 tmp; | |
1712 | ||
1713 | tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); | |
1714 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); | |
1715 | WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); | |
1716 | tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); | |
1717 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); | |
1718 | WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); | |
1719 | ||
1720 | tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); | |
1721 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); | |
1722 | WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); | |
1723 | tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); | |
1724 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); | |
1725 | WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); | |
1726 | ||
1727 | tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); | |
1728 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); | |
1729 | WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); | |
1730 | tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); | |
1731 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); | |
1732 | WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); | |
1733 | ||
1734 | } | |
1735 | ||
1736 | /* | |
1737 | * build a HDMI Video Info Frame | |
1738 | */ | |
1739 | static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, | |
1740 | void *buffer, size_t size) | |
1741 | { | |
1742 | struct drm_device *dev = encoder->dev; | |
1743 | struct amdgpu_device *adev = dev->dev_private; | |
1744 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1745 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1746 | uint8_t *frame = buffer + 3; | |
1747 | uint8_t *header = buffer; | |
1748 | ||
1749 | WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, | |
1750 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); | |
1751 | WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, | |
1752 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); | |
1753 | WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, | |
1754 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); | |
1755 | WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, | |
1756 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); | |
1757 | } | |
1758 | ||
1759 | static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |
1760 | { | |
1761 | struct drm_device *dev = encoder->dev; | |
1762 | struct amdgpu_device *adev = dev->dev_private; | |
1763 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1764 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1765 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); | |
1766 | u32 dto_phase = 24 * 1000; | |
1767 | u32 dto_modulo = clock; | |
1768 | u32 tmp; | |
1769 | ||
1770 | if (!dig || !dig->afmt) | |
1771 | return; | |
1772 | ||
1773 | /* XXX two dtos; generally use dto0 for hdmi */ | |
1774 | /* Express [24MHz / target pixel clock] as an exact rational | |
1775 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
1776 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
1777 | */ | |
1778 | tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); | |
1779 | tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, | |
1780 | amdgpu_crtc->crtc_id); | |
1781 | WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); | |
1782 | WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); | |
1783 | WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); | |
1784 | } | |
1785 | ||
1786 | /* | |
1787 | * update the info frames with the data from the current display mode | |
1788 | */ | |
1789 | static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, | |
1790 | struct drm_display_mode *mode) | |
1791 | { | |
1792 | struct drm_device *dev = encoder->dev; | |
1793 | struct amdgpu_device *adev = dev->dev_private; | |
1794 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1795 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1796 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); | |
1797 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; | |
1798 | struct hdmi_avi_infoframe frame; | |
1799 | ssize_t err; | |
1800 | u32 tmp; | |
1801 | int bpc = 8; | |
1802 | ||
1803 | if (!dig || !dig->afmt) | |
1804 | return; | |
1805 | ||
1806 | /* Silent, r600_hdmi_enable will raise WARN for us */ | |
1807 | if (!dig->afmt->enabled) | |
1808 | return; | |
1809 | ||
1810 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ | |
1811 | if (encoder->crtc) { | |
1812 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); | |
1813 | bpc = amdgpu_crtc->bpc; | |
1814 | } | |
1815 | ||
1816 | /* disable audio prior to setting up hw */ | |
1817 | dig->afmt->pin = dce_v10_0_audio_get_pin(adev); | |
1818 | dce_v10_0_audio_enable(adev, dig->afmt->pin, false); | |
1819 | ||
1820 | dce_v10_0_audio_set_dto(encoder, mode->clock); | |
1821 | ||
1822 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); | |
1823 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); | |
1824 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ | |
1825 | ||
1826 | WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); | |
1827 | ||
1828 | tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); | |
1829 | switch (bpc) { | |
1830 | case 0: | |
1831 | case 6: | |
1832 | case 8: | |
1833 | case 16: | |
1834 | default: | |
1835 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); | |
1836 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); | |
1837 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", | |
1838 | connector->name, bpc); | |
1839 | break; | |
1840 | case 10: | |
1841 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); | |
1842 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); | |
1843 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", | |
1844 | connector->name); | |
1845 | break; | |
1846 | case 12: | |
1847 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); | |
1848 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); | |
1849 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", | |
1850 | connector->name); | |
1851 | break; | |
1852 | } | |
1853 | WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); | |
1854 | ||
1855 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); | |
1856 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ | |
1857 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ | |
1858 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ | |
1859 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1860 | ||
1861 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); | |
1862 | /* enable audio info frames (frames won't be set until audio is enabled) */ | |
1863 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); | |
1864 | /* required for audio info values to be updated */ | |
1865 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); | |
1866 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); | |
1867 | ||
1868 | tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); | |
1869 | /* required for audio info values to be updated */ | |
1870 | tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); | |
1871 | WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); | |
1872 | ||
1873 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); | |
1874 | /* anything other than 0 */ | |
1875 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); | |
1876 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); | |
1877 | ||
1878 | WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ | |
1879 | ||
1880 | tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); | |
1881 | /* set the default audio delay */ | |
1882 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); | |
1883 | /* should be suffient for all audio modes and small enough for all hblanks */ | |
1884 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); | |
1885 | WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1886 | ||
1887 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); | |
1888 | /* allow 60958 channel status fields to be updated */ | |
1889 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); | |
1890 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1891 | ||
1892 | tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); | |
1893 | if (bpc > 8) | |
1894 | /* clear SW CTS value */ | |
1895 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); | |
1896 | else | |
1897 | /* select SW CTS value */ | |
1898 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); | |
1899 | /* allow hw to sent ACR packets when required */ | |
1900 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); | |
1901 | WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1902 | ||
1903 | dce_v10_0_afmt_update_ACR(encoder, mode->clock); | |
1904 | ||
1905 | tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); | |
1906 | tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); | |
1907 | WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); | |
1908 | ||
1909 | tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); | |
1910 | tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); | |
1911 | WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); | |
1912 | ||
1913 | tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); | |
1914 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); | |
1915 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); | |
1916 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); | |
1917 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); | |
1918 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); | |
1919 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); | |
1920 | WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); | |
1921 | ||
1922 | dce_v10_0_audio_write_speaker_allocation(encoder); | |
1923 | ||
1924 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, | |
1925 | (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); | |
1926 | ||
1927 | dce_v10_0_afmt_audio_select_pin(encoder); | |
1928 | dce_v10_0_audio_write_sad_regs(encoder); | |
1929 | dce_v10_0_audio_write_latency_fields(encoder, mode); | |
1930 | ||
1931 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); | |
1932 | if (err < 0) { | |
1933 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
1934 | return; | |
1935 | } | |
1936 | ||
1937 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
1938 | if (err < 0) { | |
1939 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
1940 | return; | |
1941 | } | |
1942 | ||
1943 | dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); | |
1944 | ||
1945 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); | |
1946 | /* enable AVI info frames */ | |
1947 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); | |
1948 | /* required for audio info values to be updated */ | |
1949 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); | |
1950 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); | |
1951 | ||
1952 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); | |
1953 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); | |
1954 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); | |
1955 | ||
1956 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); | |
1957 | /* send audio packets */ | |
1958 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); | |
1959 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1960 | ||
1961 | WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); | |
1962 | WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); | |
1963 | WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); | |
1964 | WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); | |
1965 | ||
1966 | /* enable audio after to setting up hw */ | |
1967 | dce_v10_0_audio_enable(adev, dig->afmt->pin, true); | |
1968 | } | |
1969 | ||
1970 | static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) | |
1971 | { | |
1972 | struct drm_device *dev = encoder->dev; | |
1973 | struct amdgpu_device *adev = dev->dev_private; | |
1974 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1975 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1976 | ||
1977 | if (!dig || !dig->afmt) | |
1978 | return; | |
1979 | ||
1980 | /* Silent, r600_hdmi_enable will raise WARN for us */ | |
1981 | if (enable && dig->afmt->enabled) | |
1982 | return; | |
1983 | if (!enable && !dig->afmt->enabled) | |
1984 | return; | |
1985 | ||
1986 | if (!enable && dig->afmt->pin) { | |
1987 | dce_v10_0_audio_enable(adev, dig->afmt->pin, false); | |
1988 | dig->afmt->pin = NULL; | |
1989 | } | |
1990 | ||
1991 | dig->afmt->enabled = enable; | |
1992 | ||
1993 | DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", | |
1994 | enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); | |
1995 | } | |
1996 | ||
1997 | static void dce_v10_0_afmt_init(struct amdgpu_device *adev) | |
1998 | { | |
1999 | int i; | |
2000 | ||
2001 | for (i = 0; i < adev->mode_info.num_dig; i++) | |
2002 | adev->mode_info.afmt[i] = NULL; | |
2003 | ||
2004 | /* DCE10 has audio blocks tied to DIG encoders */ | |
2005 | for (i = 0; i < adev->mode_info.num_dig; i++) { | |
2006 | adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); | |
2007 | if (adev->mode_info.afmt[i]) { | |
2008 | adev->mode_info.afmt[i]->offset = dig_offsets[i]; | |
2009 | adev->mode_info.afmt[i]->id = i; | |
2010 | } | |
2011 | } | |
2012 | } | |
2013 | ||
2014 | static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) | |
2015 | { | |
2016 | int i; | |
2017 | ||
2018 | for (i = 0; i < adev->mode_info.num_dig; i++) { | |
2019 | kfree(adev->mode_info.afmt[i]); | |
2020 | adev->mode_info.afmt[i] = NULL; | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | static const u32 vga_control_regs[6] = | |
2025 | { | |
2026 | mmD1VGA_CONTROL, | |
2027 | mmD2VGA_CONTROL, | |
2028 | mmD3VGA_CONTROL, | |
2029 | mmD4VGA_CONTROL, | |
2030 | mmD5VGA_CONTROL, | |
2031 | mmD6VGA_CONTROL, | |
2032 | }; | |
2033 | ||
2034 | static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) | |
2035 | { | |
2036 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2037 | struct drm_device *dev = crtc->dev; | |
2038 | struct amdgpu_device *adev = dev->dev_private; | |
2039 | u32 vga_control; | |
2040 | ||
2041 | vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; | |
2042 | if (enable) | |
2043 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); | |
2044 | else | |
2045 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); | |
2046 | } | |
2047 | ||
2048 | static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) | |
2049 | { | |
2050 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2051 | struct drm_device *dev = crtc->dev; | |
2052 | struct amdgpu_device *adev = dev->dev_private; | |
2053 | ||
2054 | if (enable) | |
2055 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); | |
2056 | else | |
2057 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); | |
2058 | } | |
2059 | ||
aaa36a97 AD |
2060 | static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, |
2061 | struct drm_framebuffer *fb, | |
2062 | int x, int y, int atomic) | |
2063 | { | |
2064 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2065 | struct drm_device *dev = crtc->dev; | |
2066 | struct amdgpu_device *adev = dev->dev_private; | |
2067 | struct amdgpu_framebuffer *amdgpu_fb; | |
2068 | struct drm_framebuffer *target_fb; | |
2069 | struct drm_gem_object *obj; | |
2070 | struct amdgpu_bo *rbo; | |
2071 | uint64_t fb_location, tiling_flags; | |
2072 | uint32_t fb_format, fb_pitch_pixels; | |
aaa36a97 | 2073 | u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); |
fbd76d59 | 2074 | u32 pipe_config; |
aaa36a97 AD |
2075 | u32 tmp, viewport_w, viewport_h; |
2076 | int r; | |
2077 | bool bypass_lut = false; | |
2078 | ||
2079 | /* no fb bound */ | |
2080 | if (!atomic && !crtc->primary->fb) { | |
2081 | DRM_DEBUG_KMS("No FB bound\n"); | |
2082 | return 0; | |
2083 | } | |
2084 | ||
2085 | if (atomic) { | |
2086 | amdgpu_fb = to_amdgpu_framebuffer(fb); | |
2087 | target_fb = fb; | |
2088 | } | |
2089 | else { | |
2090 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
2091 | target_fb = crtc->primary->fb; | |
2092 | } | |
2093 | ||
2094 | /* If atomic, assume fb object is pinned & idle & fenced and | |
2095 | * just update base pointers | |
2096 | */ | |
2097 | obj = amdgpu_fb->obj; | |
2098 | rbo = gem_to_amdgpu_bo(obj); | |
2099 | r = amdgpu_bo_reserve(rbo, false); | |
2100 | if (unlikely(r != 0)) | |
2101 | return r; | |
2102 | ||
2103 | if (atomic) | |
2104 | fb_location = amdgpu_bo_gpu_offset(rbo); | |
2105 | else { | |
2106 | r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); | |
2107 | if (unlikely(r != 0)) { | |
2108 | amdgpu_bo_unreserve(rbo); | |
2109 | return -EINVAL; | |
2110 | } | |
2111 | } | |
2112 | ||
2113 | amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); | |
2114 | amdgpu_bo_unreserve(rbo); | |
2115 | ||
fbd76d59 MO |
2116 | pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); |
2117 | ||
aaa36a97 AD |
2118 | switch (target_fb->pixel_format) { |
2119 | case DRM_FORMAT_C8: | |
2120 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); | |
2121 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); | |
2122 | break; | |
2123 | case DRM_FORMAT_XRGB4444: | |
2124 | case DRM_FORMAT_ARGB4444: | |
2125 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2126 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); | |
2127 | #ifdef __BIG_ENDIAN | |
2128 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2129 | ENDIAN_8IN16); | |
2130 | #endif | |
2131 | break; | |
2132 | case DRM_FORMAT_XRGB1555: | |
2133 | case DRM_FORMAT_ARGB1555: | |
2134 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2135 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); | |
2136 | #ifdef __BIG_ENDIAN | |
2137 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2138 | ENDIAN_8IN16); | |
2139 | #endif | |
2140 | break; | |
2141 | case DRM_FORMAT_BGRX5551: | |
2142 | case DRM_FORMAT_BGRA5551: | |
2143 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2144 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); | |
2145 | #ifdef __BIG_ENDIAN | |
2146 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2147 | ENDIAN_8IN16); | |
2148 | #endif | |
2149 | break; | |
2150 | case DRM_FORMAT_RGB565: | |
2151 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2152 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); | |
2153 | #ifdef __BIG_ENDIAN | |
2154 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2155 | ENDIAN_8IN16); | |
2156 | #endif | |
2157 | break; | |
2158 | case DRM_FORMAT_XRGB8888: | |
2159 | case DRM_FORMAT_ARGB8888: | |
2160 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); | |
2161 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); | |
2162 | #ifdef __BIG_ENDIAN | |
2163 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2164 | ENDIAN_8IN32); | |
2165 | #endif | |
2166 | break; | |
2167 | case DRM_FORMAT_XRGB2101010: | |
2168 | case DRM_FORMAT_ARGB2101010: | |
2169 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); | |
2170 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); | |
2171 | #ifdef __BIG_ENDIAN | |
2172 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2173 | ENDIAN_8IN32); | |
2174 | #endif | |
2175 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | |
2176 | bypass_lut = true; | |
2177 | break; | |
2178 | case DRM_FORMAT_BGRX1010102: | |
2179 | case DRM_FORMAT_BGRA1010102: | |
2180 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); | |
2181 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); | |
2182 | #ifdef __BIG_ENDIAN | |
2183 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2184 | ENDIAN_8IN32); | |
2185 | #endif | |
2186 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | |
2187 | bypass_lut = true; | |
2188 | break; | |
2189 | default: | |
2190 | DRM_ERROR("Unsupported screen format %s\n", | |
2191 | drm_get_format_name(target_fb->pixel_format)); | |
2192 | return -EINVAL; | |
2193 | } | |
2194 | ||
fbd76d59 MO |
2195 | if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { |
2196 | unsigned bankw, bankh, mtaspect, tile_split, num_banks; | |
aaa36a97 | 2197 | |
fbd76d59 MO |
2198 | bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); |
2199 | bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); | |
2200 | mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); | |
2201 | tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); | |
2202 | num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); | |
aaa36a97 | 2203 | |
aaa36a97 AD |
2204 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); |
2205 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, | |
2206 | ARRAY_2D_TILED_THIN1); | |
2207 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, | |
2208 | tile_split); | |
2209 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); | |
2210 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); | |
2211 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, | |
2212 | mtaspect); | |
2213 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, | |
2214 | ADDR_SURF_MICRO_TILING_DISPLAY); | |
fbd76d59 | 2215 | } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { |
aaa36a97 AD |
2216 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, |
2217 | ARRAY_1D_TILED_THIN1); | |
2218 | } | |
2219 | ||
aaa36a97 AD |
2220 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, |
2221 | pipe_config); | |
2222 | ||
2223 | dce_v10_0_vga_enable(crtc, false); | |
2224 | ||
2225 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
2226 | upper_32_bits(fb_location)); | |
2227 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
2228 | upper_32_bits(fb_location)); | |
2229 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
2230 | (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); | |
2231 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
2232 | (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); | |
2233 | WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); | |
2234 | WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); | |
2235 | ||
2236 | /* | |
2237 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT | |
2238 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to | |
2239 | * retain the full precision throughout the pipeline. | |
2240 | */ | |
2241 | tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); | |
2242 | if (bypass_lut) | |
2243 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); | |
2244 | else | |
2245 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); | |
2246 | WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); | |
2247 | ||
2248 | if (bypass_lut) | |
2249 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); | |
2250 | ||
2251 | WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); | |
2252 | WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); | |
2253 | WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); | |
2254 | WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); | |
2255 | WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); | |
2256 | WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); | |
2257 | ||
2258 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); | |
2259 | WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); | |
2260 | ||
2261 | dce_v10_0_grph_enable(crtc, true); | |
2262 | ||
2263 | WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, | |
2264 | target_fb->height); | |
2265 | ||
2266 | x &= ~3; | |
2267 | y &= ~1; | |
2268 | WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, | |
2269 | (x << 16) | y); | |
2270 | viewport_w = crtc->mode.hdisplay; | |
2271 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | |
2272 | WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, | |
2273 | (viewport_w << 16) | viewport_h); | |
2274 | ||
2275 | /* pageflip setup */ | |
2276 | /* make sure flip is at vb rather than hb */ | |
2277 | tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); | |
2278 | tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, | |
2279 | GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); | |
2280 | WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2281 | ||
2282 | /* set pageflip to happen only at start of vblank interval (front porch) */ | |
2283 | WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); | |
2284 | ||
2285 | if (!atomic && fb && fb != crtc->primary->fb) { | |
2286 | amdgpu_fb = to_amdgpu_framebuffer(fb); | |
2287 | rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); | |
2288 | r = amdgpu_bo_reserve(rbo, false); | |
2289 | if (unlikely(r != 0)) | |
2290 | return r; | |
2291 | amdgpu_bo_unpin(rbo); | |
2292 | amdgpu_bo_unreserve(rbo); | |
2293 | } | |
2294 | ||
2295 | /* Bytes per pixel may have changed */ | |
2296 | dce_v10_0_bandwidth_update(adev); | |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
2301 | static void dce_v10_0_set_interleave(struct drm_crtc *crtc, | |
2302 | struct drm_display_mode *mode) | |
2303 | { | |
2304 | struct drm_device *dev = crtc->dev; | |
2305 | struct amdgpu_device *adev = dev->dev_private; | |
2306 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2307 | u32 tmp; | |
2308 | ||
2309 | tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); | |
2310 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2311 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); | |
2312 | else | |
2313 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); | |
2314 | WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); | |
2315 | } | |
2316 | ||
2317 | static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) | |
2318 | { | |
2319 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2320 | struct drm_device *dev = crtc->dev; | |
2321 | struct amdgpu_device *adev = dev->dev_private; | |
2322 | int i; | |
2323 | u32 tmp; | |
2324 | ||
2325 | DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); | |
2326 | ||
2327 | tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); | |
2328 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); | |
2329 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); | |
2330 | WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2331 | ||
2332 | tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); | |
2333 | tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); | |
2334 | WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2335 | ||
2336 | tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); | |
2337 | tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); | |
2338 | WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2339 | ||
2340 | tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); | |
2341 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); | |
2342 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); | |
2343 | WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2344 | ||
2345 | WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); | |
2346 | ||
2347 | WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); | |
2348 | WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); | |
2349 | WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); | |
2350 | ||
2351 | WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); | |
2352 | WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); | |
2353 | WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); | |
2354 | ||
2355 | WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); | |
2356 | WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); | |
2357 | ||
2358 | WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); | |
2359 | for (i = 0; i < 256; i++) { | |
2360 | WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, | |
2361 | (amdgpu_crtc->lut_r[i] << 20) | | |
2362 | (amdgpu_crtc->lut_g[i] << 10) | | |
2363 | (amdgpu_crtc->lut_b[i] << 0)); | |
2364 | } | |
2365 | ||
2366 | tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); | |
2367 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); | |
2368 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); | |
2369 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); | |
2370 | WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2371 | ||
2372 | tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); | |
2373 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); | |
2374 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); | |
2375 | WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2376 | ||
2377 | tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); | |
2378 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); | |
2379 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); | |
2380 | WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2381 | ||
2382 | tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); | |
2383 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); | |
2384 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); | |
2385 | WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2386 | ||
2387 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ | |
2388 | WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); | |
2389 | /* XXX this only needs to be programmed once per crtc at startup, | |
2390 | * not sure where the best place for it is | |
2391 | */ | |
2392 | tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); | |
2393 | tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); | |
2394 | WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2395 | } | |
2396 | ||
2397 | static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) | |
2398 | { | |
2399 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
2400 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
2401 | ||
2402 | switch (amdgpu_encoder->encoder_id) { | |
2403 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2404 | if (dig->linkb) | |
2405 | return 1; | |
2406 | else | |
2407 | return 0; | |
2408 | break; | |
2409 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2410 | if (dig->linkb) | |
2411 | return 3; | |
2412 | else | |
2413 | return 2; | |
2414 | break; | |
2415 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2416 | if (dig->linkb) | |
2417 | return 5; | |
2418 | else | |
2419 | return 4; | |
2420 | break; | |
2421 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: | |
2422 | return 6; | |
2423 | break; | |
2424 | default: | |
2425 | DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); | |
2426 | return 0; | |
2427 | } | |
2428 | } | |
2429 | ||
2430 | /** | |
2431 | * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. | |
2432 | * | |
2433 | * @crtc: drm crtc | |
2434 | * | |
2435 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors | |
2436 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP | |
2437 | * monitors a dedicated PPLL must be used. If a particular board has | |
2438 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming | |
2439 | * as there is no need to program the PLL itself. If we are not able to | |
2440 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to | |
2441 | * avoid messing up an existing monitor. | |
2442 | * | |
2443 | * Asic specific PLL information | |
2444 | * | |
2445 | * DCE 10.x | |
2446 | * Tonga | |
2447 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) | |
2448 | * CI | |
2449 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
2450 | * | |
2451 | */ | |
2452 | static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) | |
2453 | { | |
2454 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2455 | struct drm_device *dev = crtc->dev; | |
2456 | struct amdgpu_device *adev = dev->dev_private; | |
2457 | u32 pll_in_use; | |
2458 | int pll; | |
2459 | ||
2460 | if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { | |
2461 | if (adev->clock.dp_extclk) | |
2462 | /* skip PPLL programming if using ext clock */ | |
2463 | return ATOM_PPLL_INVALID; | |
2464 | else { | |
2465 | /* use the same PPLL for all DP monitors */ | |
2466 | pll = amdgpu_pll_get_shared_dp_ppll(crtc); | |
2467 | if (pll != ATOM_PPLL_INVALID) | |
2468 | return pll; | |
2469 | } | |
2470 | } else { | |
2471 | /* use the same PPLL for all monitors with the same clock */ | |
2472 | pll = amdgpu_pll_get_shared_nondp_ppll(crtc); | |
2473 | if (pll != ATOM_PPLL_INVALID) | |
2474 | return pll; | |
2475 | } | |
2476 | ||
2477 | /* DCE10 has PPLL0, PPLL1, and PPLL2 */ | |
2478 | pll_in_use = amdgpu_pll_get_use_mask(crtc); | |
2479 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | |
2480 | return ATOM_PPLL2; | |
2481 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | |
2482 | return ATOM_PPLL1; | |
2483 | if (!(pll_in_use & (1 << ATOM_PPLL0))) | |
2484 | return ATOM_PPLL0; | |
2485 | DRM_ERROR("unable to allocate a PPLL\n"); | |
2486 | return ATOM_PPLL_INVALID; | |
2487 | } | |
2488 | ||
2489 | static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) | |
2490 | { | |
2491 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2492 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2493 | uint32_t cur_lock; | |
2494 | ||
2495 | cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); | |
2496 | if (lock) | |
2497 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); | |
2498 | else | |
2499 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); | |
2500 | WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); | |
2501 | } | |
2502 | ||
2503 | static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) | |
2504 | { | |
2505 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2506 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2507 | u32 tmp; | |
2508 | ||
2509 | tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); | |
2510 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); | |
2511 | WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2512 | } | |
2513 | ||
2514 | static void dce_v10_0_show_cursor(struct drm_crtc *crtc) | |
2515 | { | |
2516 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2517 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2518 | u32 tmp; | |
2519 | ||
2520 | tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); | |
2521 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); | |
2522 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); | |
2523 | WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2524 | } | |
2525 | ||
2526 | static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, | |
2527 | uint64_t gpu_addr) | |
2528 | { | |
2529 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2530 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2531 | ||
2532 | WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
2533 | upper_32_bits(gpu_addr)); | |
2534 | WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
2535 | lower_32_bits(gpu_addr)); | |
2536 | } | |
2537 | ||
2538 | static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, | |
2539 | int x, int y) | |
2540 | { | |
2541 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2542 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2543 | int xorigin = 0, yorigin = 0; | |
2544 | ||
2545 | /* avivo cursor are offset into the total surface */ | |
2546 | x += crtc->x; | |
2547 | y += crtc->y; | |
2548 | DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); | |
2549 | ||
2550 | if (x < 0) { | |
2551 | xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); | |
2552 | x = 0; | |
2553 | } | |
2554 | if (y < 0) { | |
2555 | yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); | |
2556 | y = 0; | |
2557 | } | |
2558 | ||
2559 | dce_v10_0_lock_cursor(crtc, true); | |
2560 | WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); | |
2561 | WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); | |
2562 | WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, | |
2563 | ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); | |
2564 | dce_v10_0_lock_cursor(crtc, false); | |
2565 | ||
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc, | |
2570 | struct drm_file *file_priv, | |
2571 | uint32_t handle, | |
2572 | uint32_t width, | |
2573 | uint32_t height) | |
2574 | { | |
2575 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2576 | struct drm_gem_object *obj; | |
2577 | struct amdgpu_bo *robj; | |
2578 | uint64_t gpu_addr; | |
2579 | int ret; | |
2580 | ||
2581 | if (!handle) { | |
2582 | /* turn off cursor */ | |
2583 | dce_v10_0_hide_cursor(crtc); | |
2584 | obj = NULL; | |
2585 | goto unpin; | |
2586 | } | |
2587 | ||
2588 | if ((width > amdgpu_crtc->max_cursor_width) || | |
2589 | (height > amdgpu_crtc->max_cursor_height)) { | |
2590 | DRM_ERROR("bad cursor width or height %d x %d\n", width, height); | |
2591 | return -EINVAL; | |
2592 | } | |
2593 | ||
2594 | obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); | |
2595 | if (!obj) { | |
2596 | DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); | |
2597 | return -ENOENT; | |
2598 | } | |
2599 | ||
2600 | robj = gem_to_amdgpu_bo(obj); | |
2601 | ret = amdgpu_bo_reserve(robj, false); | |
2602 | if (unlikely(ret != 0)) | |
2603 | goto fail; | |
2604 | ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, | |
7e5a547f | 2605 | 0, 0, &gpu_addr); |
aaa36a97 AD |
2606 | amdgpu_bo_unreserve(robj); |
2607 | if (ret) | |
2608 | goto fail; | |
2609 | ||
2610 | amdgpu_crtc->cursor_width = width; | |
2611 | amdgpu_crtc->cursor_height = height; | |
2612 | ||
2613 | dce_v10_0_lock_cursor(crtc, true); | |
2614 | dce_v10_0_set_cursor(crtc, obj, gpu_addr); | |
2615 | dce_v10_0_show_cursor(crtc); | |
2616 | dce_v10_0_lock_cursor(crtc, false); | |
2617 | ||
2618 | unpin: | |
2619 | if (amdgpu_crtc->cursor_bo) { | |
2620 | robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2621 | ret = amdgpu_bo_reserve(robj, false); | |
2622 | if (likely(ret == 0)) { | |
2623 | amdgpu_bo_unpin(robj); | |
2624 | amdgpu_bo_unreserve(robj); | |
2625 | } | |
2626 | drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); | |
2627 | } | |
2628 | ||
2629 | amdgpu_crtc->cursor_bo = obj; | |
2630 | return 0; | |
2631 | fail: | |
2632 | drm_gem_object_unreference_unlocked(obj); | |
2633 | ||
2634 | return ret; | |
2635 | } | |
2636 | ||
2637 | static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
2638 | u16 *blue, uint32_t start, uint32_t size) | |
2639 | { | |
2640 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2641 | int end = (start + size > 256) ? 256 : start + size, i; | |
2642 | ||
2643 | /* userspace palettes are always correct as is */ | |
2644 | for (i = start; i < end; i++) { | |
2645 | amdgpu_crtc->lut_r[i] = red[i] >> 6; | |
2646 | amdgpu_crtc->lut_g[i] = green[i] >> 6; | |
2647 | amdgpu_crtc->lut_b[i] = blue[i] >> 6; | |
2648 | } | |
2649 | dce_v10_0_crtc_load_lut(crtc); | |
2650 | } | |
2651 | ||
2652 | static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) | |
2653 | { | |
2654 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2655 | ||
2656 | drm_crtc_cleanup(crtc); | |
2657 | destroy_workqueue(amdgpu_crtc->pflip_queue); | |
2658 | kfree(amdgpu_crtc); | |
2659 | } | |
2660 | ||
2661 | static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { | |
2662 | .cursor_set = dce_v10_0_crtc_cursor_set, | |
2663 | .cursor_move = dce_v10_0_crtc_cursor_move, | |
2664 | .gamma_set = dce_v10_0_crtc_gamma_set, | |
2665 | .set_config = amdgpu_crtc_set_config, | |
2666 | .destroy = dce_v10_0_crtc_destroy, | |
2667 | .page_flip = amdgpu_crtc_page_flip, | |
2668 | }; | |
2669 | ||
2670 | static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2671 | { | |
2672 | struct drm_device *dev = crtc->dev; | |
2673 | struct amdgpu_device *adev = dev->dev_private; | |
2674 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
5e6775ab | 2675 | unsigned type; |
aaa36a97 AD |
2676 | |
2677 | switch (mode) { | |
2678 | case DRM_MODE_DPMS_ON: | |
2679 | amdgpu_crtc->enabled = true; | |
2680 | amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); | |
2681 | dce_v10_0_vga_enable(crtc, true); | |
2682 | amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); | |
2683 | dce_v10_0_vga_enable(crtc, false); | |
f6c7aba4 | 2684 | /* Make sure VBLANK and PFLIP interrupts are still enabled */ |
5e6775ab MD |
2685 | type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); |
2686 | amdgpu_irq_update(adev, &adev->crtc_irq, type); | |
f6c7aba4 | 2687 | amdgpu_irq_update(adev, &adev->pageflip_irq, type); |
aaa36a97 AD |
2688 | drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); |
2689 | dce_v10_0_crtc_load_lut(crtc); | |
2690 | break; | |
2691 | case DRM_MODE_DPMS_STANDBY: | |
2692 | case DRM_MODE_DPMS_SUSPEND: | |
2693 | case DRM_MODE_DPMS_OFF: | |
2694 | drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); | |
2695 | if (amdgpu_crtc->enabled) { | |
2696 | dce_v10_0_vga_enable(crtc, true); | |
2697 | amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); | |
2698 | dce_v10_0_vga_enable(crtc, false); | |
2699 | } | |
2700 | amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); | |
2701 | amdgpu_crtc->enabled = false; | |
2702 | break; | |
2703 | } | |
2704 | /* adjust pm to dpms */ | |
2705 | amdgpu_pm_compute_clocks(adev); | |
2706 | } | |
2707 | ||
2708 | static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) | |
2709 | { | |
2710 | /* disable crtc pair power gating before programming */ | |
2711 | amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); | |
2712 | amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); | |
2713 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
2714 | } | |
2715 | ||
2716 | static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) | |
2717 | { | |
2718 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); | |
2719 | amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); | |
2720 | } | |
2721 | ||
2722 | static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) | |
2723 | { | |
2724 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2725 | struct drm_device *dev = crtc->dev; | |
2726 | struct amdgpu_device *adev = dev->dev_private; | |
2727 | struct amdgpu_atom_ss ss; | |
2728 | int i; | |
2729 | ||
2730 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
2731 | if (crtc->primary->fb) { | |
2732 | int r; | |
2733 | struct amdgpu_framebuffer *amdgpu_fb; | |
2734 | struct amdgpu_bo *rbo; | |
2735 | ||
2736 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
2737 | rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); | |
2738 | r = amdgpu_bo_reserve(rbo, false); | |
2739 | if (unlikely(r)) | |
2740 | DRM_ERROR("failed to reserve rbo before unpin\n"); | |
2741 | else { | |
2742 | amdgpu_bo_unpin(rbo); | |
2743 | amdgpu_bo_unreserve(rbo); | |
2744 | } | |
2745 | } | |
2746 | /* disable the GRPH */ | |
2747 | dce_v10_0_grph_enable(crtc, false); | |
2748 | ||
2749 | amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); | |
2750 | ||
2751 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
2752 | if (adev->mode_info.crtcs[i] && | |
2753 | adev->mode_info.crtcs[i]->enabled && | |
2754 | i != amdgpu_crtc->crtc_id && | |
2755 | amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { | |
2756 | /* one other crtc is using this pll don't turn | |
2757 | * off the pll | |
2758 | */ | |
2759 | goto done; | |
2760 | } | |
2761 | } | |
2762 | ||
2763 | switch (amdgpu_crtc->pll_id) { | |
2764 | case ATOM_PPLL0: | |
2765 | case ATOM_PPLL1: | |
2766 | case ATOM_PPLL2: | |
2767 | /* disable the ppll */ | |
2768 | amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, | |
2769 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); | |
2770 | break; | |
2771 | default: | |
2772 | break; | |
2773 | } | |
2774 | done: | |
2775 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; | |
2776 | amdgpu_crtc->adjusted_clock = 0; | |
2777 | amdgpu_crtc->encoder = NULL; | |
2778 | amdgpu_crtc->connector = NULL; | |
2779 | } | |
2780 | ||
2781 | static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, | |
2782 | struct drm_display_mode *mode, | |
2783 | struct drm_display_mode *adjusted_mode, | |
2784 | int x, int y, struct drm_framebuffer *old_fb) | |
2785 | { | |
2786 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2787 | ||
2788 | if (!amdgpu_crtc->adjusted_clock) | |
2789 | return -EINVAL; | |
2790 | ||
2791 | amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); | |
2792 | amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); | |
2793 | dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
2794 | amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); | |
2795 | amdgpu_atombios_crtc_scaler_setup(crtc); | |
2796 | /* update the hw version fpr dpm */ | |
2797 | amdgpu_crtc->hw_mode = *adjusted_mode; | |
2798 | ||
2799 | return 0; | |
2800 | } | |
2801 | ||
2802 | static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, | |
2803 | const struct drm_display_mode *mode, | |
2804 | struct drm_display_mode *adjusted_mode) | |
2805 | { | |
2806 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2807 | struct drm_device *dev = crtc->dev; | |
2808 | struct drm_encoder *encoder; | |
2809 | ||
2810 | /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ | |
2811 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2812 | if (encoder->crtc == crtc) { | |
2813 | amdgpu_crtc->encoder = encoder; | |
2814 | amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); | |
2815 | break; | |
2816 | } | |
2817 | } | |
2818 | if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { | |
2819 | amdgpu_crtc->encoder = NULL; | |
2820 | amdgpu_crtc->connector = NULL; | |
2821 | return false; | |
2822 | } | |
2823 | if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) | |
2824 | return false; | |
2825 | if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) | |
2826 | return false; | |
2827 | /* pick pll */ | |
2828 | amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); | |
2829 | /* if we can't get a PPLL for a non-DP encoder, fail */ | |
2830 | if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && | |
2831 | !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) | |
2832 | return false; | |
2833 | ||
2834 | return true; | |
2835 | } | |
2836 | ||
2837 | static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
2838 | struct drm_framebuffer *old_fb) | |
2839 | { | |
2840 | return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
2841 | } | |
2842 | ||
2843 | static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, | |
2844 | struct drm_framebuffer *fb, | |
2845 | int x, int y, enum mode_set_atomic state) | |
2846 | { | |
2847 | return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); | |
2848 | } | |
2849 | ||
2850 | static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { | |
2851 | .dpms = dce_v10_0_crtc_dpms, | |
2852 | .mode_fixup = dce_v10_0_crtc_mode_fixup, | |
2853 | .mode_set = dce_v10_0_crtc_mode_set, | |
2854 | .mode_set_base = dce_v10_0_crtc_set_base, | |
2855 | .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, | |
2856 | .prepare = dce_v10_0_crtc_prepare, | |
2857 | .commit = dce_v10_0_crtc_commit, | |
2858 | .load_lut = dce_v10_0_crtc_load_lut, | |
2859 | .disable = dce_v10_0_crtc_disable, | |
2860 | }; | |
2861 | ||
2862 | static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) | |
2863 | { | |
2864 | struct amdgpu_crtc *amdgpu_crtc; | |
2865 | int i; | |
2866 | ||
2867 | amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + | |
2868 | (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
2869 | if (amdgpu_crtc == NULL) | |
2870 | return -ENOMEM; | |
2871 | ||
2872 | drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); | |
2873 | ||
2874 | drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); | |
2875 | amdgpu_crtc->crtc_id = index; | |
2876 | amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); | |
2877 | adev->mode_info.crtcs[index] = amdgpu_crtc; | |
2878 | ||
2879 | amdgpu_crtc->max_cursor_width = 128; | |
2880 | amdgpu_crtc->max_cursor_height = 128; | |
2881 | adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; | |
2882 | adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; | |
2883 | ||
2884 | for (i = 0; i < 256; i++) { | |
2885 | amdgpu_crtc->lut_r[i] = i << 2; | |
2886 | amdgpu_crtc->lut_g[i] = i << 2; | |
2887 | amdgpu_crtc->lut_b[i] = i << 2; | |
2888 | } | |
2889 | ||
2890 | switch (amdgpu_crtc->crtc_id) { | |
2891 | case 0: | |
2892 | default: | |
2893 | amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; | |
2894 | break; | |
2895 | case 1: | |
2896 | amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; | |
2897 | break; | |
2898 | case 2: | |
2899 | amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; | |
2900 | break; | |
2901 | case 3: | |
2902 | amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; | |
2903 | break; | |
2904 | case 4: | |
2905 | amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; | |
2906 | break; | |
2907 | case 5: | |
2908 | amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; | |
2909 | break; | |
2910 | } | |
2911 | ||
2912 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; | |
2913 | amdgpu_crtc->adjusted_clock = 0; | |
2914 | amdgpu_crtc->encoder = NULL; | |
2915 | amdgpu_crtc->connector = NULL; | |
2916 | drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); | |
2917 | ||
2918 | return 0; | |
2919 | } | |
2920 | ||
5fc3aeeb | 2921 | static int dce_v10_0_early_init(void *handle) |
aaa36a97 | 2922 | { |
5fc3aeeb | 2923 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2924 | ||
aaa36a97 AD |
2925 | adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; |
2926 | adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; | |
2927 | ||
2928 | dce_v10_0_set_display_funcs(adev); | |
2929 | dce_v10_0_set_irq_funcs(adev); | |
2930 | ||
2931 | switch (adev->asic_type) { | |
84390860 | 2932 | case CHIP_FIJI: |
aaa36a97 AD |
2933 | case CHIP_TONGA: |
2934 | adev->mode_info.num_crtc = 6; /* XXX 7??? */ | |
2935 | adev->mode_info.num_hpd = 6; | |
2936 | adev->mode_info.num_dig = 7; | |
2937 | break; | |
2938 | default: | |
2939 | /* FIXME: not supported yet */ | |
2940 | return -EINVAL; | |
2941 | } | |
2942 | ||
2943 | return 0; | |
2944 | } | |
2945 | ||
5fc3aeeb | 2946 | static int dce_v10_0_sw_init(void *handle) |
aaa36a97 AD |
2947 | { |
2948 | int r, i; | |
5fc3aeeb | 2949 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
2950 | |
2951 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
2952 | r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); | |
2953 | if (r) | |
2954 | return r; | |
2955 | } | |
2956 | ||
2957 | for (i = 8; i < 20; i += 2) { | |
2958 | r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); | |
2959 | if (r) | |
2960 | return r; | |
2961 | } | |
2962 | ||
2963 | /* HPD hotplug */ | |
2964 | r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); | |
2965 | if (r) | |
2966 | return r; | |
2967 | ||
2968 | adev->mode_info.mode_config_initialized = true; | |
2969 | ||
2970 | adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; | |
2971 | ||
2972 | adev->ddev->mode_config.max_width = 16384; | |
2973 | adev->ddev->mode_config.max_height = 16384; | |
2974 | ||
2975 | adev->ddev->mode_config.preferred_depth = 24; | |
2976 | adev->ddev->mode_config.prefer_shadow = 1; | |
2977 | ||
2978 | adev->ddev->mode_config.fb_base = adev->mc.aper_base; | |
2979 | ||
2980 | r = amdgpu_modeset_create_props(adev); | |
2981 | if (r) | |
2982 | return r; | |
2983 | ||
2984 | adev->ddev->mode_config.max_width = 16384; | |
2985 | adev->ddev->mode_config.max_height = 16384; | |
2986 | ||
2987 | /* allocate crtcs */ | |
2988 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
2989 | r = dce_v10_0_crtc_init(adev, i); | |
2990 | if (r) | |
2991 | return r; | |
2992 | } | |
2993 | ||
2994 | if (amdgpu_atombios_get_connector_info_from_object_table(adev)) | |
2995 | amdgpu_print_display_setup(adev->ddev); | |
2996 | else | |
2997 | return -EINVAL; | |
2998 | ||
2999 | /* setup afmt */ | |
3000 | dce_v10_0_afmt_init(adev); | |
3001 | ||
3002 | r = dce_v10_0_audio_init(adev); | |
3003 | if (r) | |
3004 | return r; | |
3005 | ||
3006 | drm_kms_helper_poll_init(adev->ddev); | |
3007 | ||
3008 | return r; | |
3009 | } | |
3010 | ||
5fc3aeeb | 3011 | static int dce_v10_0_sw_fini(void *handle) |
aaa36a97 | 3012 | { |
5fc3aeeb | 3013 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3014 | ||
aaa36a97 AD |
3015 | kfree(adev->mode_info.bios_hardcoded_edid); |
3016 | ||
3017 | drm_kms_helper_poll_fini(adev->ddev); | |
3018 | ||
3019 | dce_v10_0_audio_fini(adev); | |
3020 | ||
3021 | dce_v10_0_afmt_fini(adev); | |
3022 | ||
3023 | drm_mode_config_cleanup(adev->ddev); | |
3024 | adev->mode_info.mode_config_initialized = false; | |
3025 | ||
3026 | return 0; | |
3027 | } | |
3028 | ||
5fc3aeeb | 3029 | static int dce_v10_0_hw_init(void *handle) |
aaa36a97 AD |
3030 | { |
3031 | int i; | |
5fc3aeeb | 3032 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3033 | |
3034 | dce_v10_0_init_golden_registers(adev); | |
3035 | ||
3036 | /* init dig PHYs, disp eng pll */ | |
3037 | amdgpu_atombios_encoder_init_dig(adev); | |
3038 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); | |
3039 | ||
3040 | /* initialize hpd */ | |
3041 | dce_v10_0_hpd_init(adev); | |
3042 | ||
3043 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
3044 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
3045 | } | |
3046 | ||
f6c7aba4 MD |
3047 | dce_v10_0_pageflip_interrupt_init(adev); |
3048 | ||
aaa36a97 AD |
3049 | return 0; |
3050 | } | |
3051 | ||
5fc3aeeb | 3052 | static int dce_v10_0_hw_fini(void *handle) |
aaa36a97 AD |
3053 | { |
3054 | int i; | |
5fc3aeeb | 3055 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3056 | |
3057 | dce_v10_0_hpd_fini(adev); | |
3058 | ||
3059 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
3060 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
3061 | } | |
3062 | ||
f6c7aba4 MD |
3063 | dce_v10_0_pageflip_interrupt_fini(adev); |
3064 | ||
aaa36a97 AD |
3065 | return 0; |
3066 | } | |
3067 | ||
5fc3aeeb | 3068 | static int dce_v10_0_suspend(void *handle) |
aaa36a97 | 3069 | { |
5fc3aeeb | 3070 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 | 3071 | |
aaa36a97 AD |
3072 | amdgpu_atombios_scratch_regs_save(adev); |
3073 | ||
3074 | dce_v10_0_hpd_fini(adev); | |
3075 | ||
f6c7aba4 MD |
3076 | dce_v10_0_pageflip_interrupt_fini(adev); |
3077 | ||
aaa36a97 AD |
3078 | return 0; |
3079 | } | |
3080 | ||
5fc3aeeb | 3081 | static int dce_v10_0_resume(void *handle) |
aaa36a97 | 3082 | { |
5fc3aeeb | 3083 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3084 | |
3085 | dce_v10_0_init_golden_registers(adev); | |
3086 | ||
3087 | amdgpu_atombios_scratch_regs_restore(adev); | |
3088 | ||
3089 | /* init dig PHYs, disp eng pll */ | |
3090 | amdgpu_atombios_encoder_init_dig(adev); | |
3091 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); | |
3092 | /* turn on the BL */ | |
3093 | if (adev->mode_info.bl_encoder) { | |
3094 | u8 bl_level = amdgpu_display_backlight_get_level(adev, | |
3095 | adev->mode_info.bl_encoder); | |
3096 | amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, | |
3097 | bl_level); | |
3098 | } | |
3099 | ||
3100 | /* initialize hpd */ | |
3101 | dce_v10_0_hpd_init(adev); | |
3102 | ||
f6c7aba4 MD |
3103 | dce_v10_0_pageflip_interrupt_init(adev); |
3104 | ||
aaa36a97 AD |
3105 | return 0; |
3106 | } | |
3107 | ||
5fc3aeeb | 3108 | static bool dce_v10_0_is_idle(void *handle) |
aaa36a97 | 3109 | { |
aaa36a97 AD |
3110 | return true; |
3111 | } | |
3112 | ||
5fc3aeeb | 3113 | static int dce_v10_0_wait_for_idle(void *handle) |
aaa36a97 | 3114 | { |
aaa36a97 AD |
3115 | return 0; |
3116 | } | |
3117 | ||
5fc3aeeb | 3118 | static void dce_v10_0_print_status(void *handle) |
aaa36a97 | 3119 | { |
5fc3aeeb | 3120 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3121 | ||
aaa36a97 AD |
3122 | dev_info(adev->dev, "DCE 10.x registers\n"); |
3123 | /* XXX todo */ | |
3124 | } | |
3125 | ||
5fc3aeeb | 3126 | static int dce_v10_0_soft_reset(void *handle) |
aaa36a97 AD |
3127 | { |
3128 | u32 srbm_soft_reset = 0, tmp; | |
5fc3aeeb | 3129 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3130 | |
3131 | if (dce_v10_0_is_display_hung(adev)) | |
3132 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; | |
3133 | ||
3134 | if (srbm_soft_reset) { | |
5fc3aeeb | 3135 | dce_v10_0_print_status((void *)adev); |
aaa36a97 AD |
3136 | |
3137 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
3138 | tmp |= srbm_soft_reset; | |
3139 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
3140 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
3141 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
3142 | ||
3143 | udelay(50); | |
3144 | ||
3145 | tmp &= ~srbm_soft_reset; | |
3146 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
3147 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
3148 | ||
3149 | /* Wait a little for things to settle down */ | |
3150 | udelay(50); | |
5fc3aeeb | 3151 | dce_v10_0_print_status((void *)adev); |
aaa36a97 AD |
3152 | } |
3153 | return 0; | |
3154 | } | |
3155 | ||
3156 | static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, | |
3157 | int crtc, | |
3158 | enum amdgpu_interrupt_state state) | |
3159 | { | |
3160 | u32 lb_interrupt_mask; | |
3161 | ||
3162 | if (crtc >= adev->mode_info.num_crtc) { | |
3163 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3164 | return; | |
3165 | } | |
3166 | ||
3167 | switch (state) { | |
3168 | case AMDGPU_IRQ_STATE_DISABLE: | |
3169 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3170 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3171 | VBLANK_INTERRUPT_MASK, 0); | |
3172 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3173 | break; | |
3174 | case AMDGPU_IRQ_STATE_ENABLE: | |
3175 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3176 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3177 | VBLANK_INTERRUPT_MASK, 1); | |
3178 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3179 | break; | |
3180 | default: | |
3181 | break; | |
3182 | } | |
3183 | } | |
3184 | ||
3185 | static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, | |
3186 | int crtc, | |
3187 | enum amdgpu_interrupt_state state) | |
3188 | { | |
3189 | u32 lb_interrupt_mask; | |
3190 | ||
3191 | if (crtc >= adev->mode_info.num_crtc) { | |
3192 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3193 | return; | |
3194 | } | |
3195 | ||
3196 | switch (state) { | |
3197 | case AMDGPU_IRQ_STATE_DISABLE: | |
3198 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3199 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3200 | VLINE_INTERRUPT_MASK, 0); | |
3201 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3202 | break; | |
3203 | case AMDGPU_IRQ_STATE_ENABLE: | |
3204 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3205 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3206 | VLINE_INTERRUPT_MASK, 1); | |
3207 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3208 | break; | |
3209 | default: | |
3210 | break; | |
3211 | } | |
3212 | } | |
3213 | ||
3214 | static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, | |
3215 | struct amdgpu_irq_src *source, | |
3216 | unsigned hpd, | |
3217 | enum amdgpu_interrupt_state state) | |
3218 | { | |
3219 | u32 tmp; | |
3220 | ||
3221 | if (hpd >= adev->mode_info.num_hpd) { | |
3222 | DRM_DEBUG("invalid hdp %d\n", hpd); | |
3223 | return 0; | |
3224 | } | |
3225 | ||
3226 | switch (state) { | |
3227 | case AMDGPU_IRQ_STATE_DISABLE: | |
3228 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); | |
3229 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); | |
3230 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); | |
3231 | break; | |
3232 | case AMDGPU_IRQ_STATE_ENABLE: | |
3233 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); | |
3234 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); | |
3235 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); | |
3236 | break; | |
3237 | default: | |
3238 | break; | |
3239 | } | |
3240 | ||
3241 | return 0; | |
3242 | } | |
3243 | ||
3244 | static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, | |
3245 | struct amdgpu_irq_src *source, | |
3246 | unsigned type, | |
3247 | enum amdgpu_interrupt_state state) | |
3248 | { | |
3249 | switch (type) { | |
3250 | case AMDGPU_CRTC_IRQ_VBLANK1: | |
3251 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); | |
3252 | break; | |
3253 | case AMDGPU_CRTC_IRQ_VBLANK2: | |
3254 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); | |
3255 | break; | |
3256 | case AMDGPU_CRTC_IRQ_VBLANK3: | |
3257 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); | |
3258 | break; | |
3259 | case AMDGPU_CRTC_IRQ_VBLANK4: | |
3260 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); | |
3261 | break; | |
3262 | case AMDGPU_CRTC_IRQ_VBLANK5: | |
3263 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); | |
3264 | break; | |
3265 | case AMDGPU_CRTC_IRQ_VBLANK6: | |
3266 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); | |
3267 | break; | |
3268 | case AMDGPU_CRTC_IRQ_VLINE1: | |
3269 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); | |
3270 | break; | |
3271 | case AMDGPU_CRTC_IRQ_VLINE2: | |
3272 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); | |
3273 | break; | |
3274 | case AMDGPU_CRTC_IRQ_VLINE3: | |
3275 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); | |
3276 | break; | |
3277 | case AMDGPU_CRTC_IRQ_VLINE4: | |
3278 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); | |
3279 | break; | |
3280 | case AMDGPU_CRTC_IRQ_VLINE5: | |
3281 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); | |
3282 | break; | |
3283 | case AMDGPU_CRTC_IRQ_VLINE6: | |
3284 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); | |
3285 | break; | |
3286 | default: | |
3287 | break; | |
3288 | } | |
3289 | return 0; | |
3290 | } | |
3291 | ||
3292 | static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, | |
3293 | struct amdgpu_irq_src *src, | |
3294 | unsigned type, | |
3295 | enum amdgpu_interrupt_state state) | |
3296 | { | |
3297 | u32 reg, reg_block; | |
3298 | /* now deal with page flip IRQ */ | |
3299 | switch (type) { | |
3300 | case AMDGPU_PAGEFLIP_IRQ_D1: | |
3301 | reg_block = CRTC0_REGISTER_OFFSET; | |
3302 | break; | |
3303 | case AMDGPU_PAGEFLIP_IRQ_D2: | |
3304 | reg_block = CRTC1_REGISTER_OFFSET; | |
3305 | break; | |
3306 | case AMDGPU_PAGEFLIP_IRQ_D3: | |
3307 | reg_block = CRTC2_REGISTER_OFFSET; | |
3308 | break; | |
3309 | case AMDGPU_PAGEFLIP_IRQ_D4: | |
3310 | reg_block = CRTC3_REGISTER_OFFSET; | |
3311 | break; | |
3312 | case AMDGPU_PAGEFLIP_IRQ_D5: | |
3313 | reg_block = CRTC4_REGISTER_OFFSET; | |
3314 | break; | |
3315 | case AMDGPU_PAGEFLIP_IRQ_D6: | |
3316 | reg_block = CRTC5_REGISTER_OFFSET; | |
3317 | break; | |
3318 | default: | |
3319 | DRM_ERROR("invalid pageflip crtc %d\n", type); | |
3320 | return -EINVAL; | |
3321 | } | |
3322 | ||
3323 | reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); | |
3324 | if (state == AMDGPU_IRQ_STATE_DISABLE) | |
3325 | WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); | |
3326 | else | |
3327 | WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); | |
3328 | ||
3329 | return 0; | |
3330 | } | |
3331 | ||
3332 | static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, | |
3333 | struct amdgpu_irq_src *source, | |
3334 | struct amdgpu_iv_entry *entry) | |
3335 | { | |
3336 | int reg_block; | |
3337 | unsigned long flags; | |
3338 | unsigned crtc_id; | |
3339 | struct amdgpu_crtc *amdgpu_crtc; | |
3340 | struct amdgpu_flip_work *works; | |
3341 | ||
3342 | crtc_id = (entry->src_id - 8) >> 1; | |
3343 | amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; | |
3344 | ||
3345 | /* ack the interrupt */ | |
3346 | switch(crtc_id){ | |
3347 | case AMDGPU_PAGEFLIP_IRQ_D1: | |
3348 | reg_block = CRTC0_REGISTER_OFFSET; | |
3349 | break; | |
3350 | case AMDGPU_PAGEFLIP_IRQ_D2: | |
3351 | reg_block = CRTC1_REGISTER_OFFSET; | |
3352 | break; | |
3353 | case AMDGPU_PAGEFLIP_IRQ_D3: | |
3354 | reg_block = CRTC2_REGISTER_OFFSET; | |
3355 | break; | |
3356 | case AMDGPU_PAGEFLIP_IRQ_D4: | |
3357 | reg_block = CRTC3_REGISTER_OFFSET; | |
3358 | break; | |
3359 | case AMDGPU_PAGEFLIP_IRQ_D5: | |
3360 | reg_block = CRTC4_REGISTER_OFFSET; | |
3361 | break; | |
3362 | case AMDGPU_PAGEFLIP_IRQ_D6: | |
3363 | reg_block = CRTC5_REGISTER_OFFSET; | |
3364 | break; | |
3365 | default: | |
3366 | DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); | |
3367 | return -EINVAL; | |
3368 | } | |
3369 | ||
3370 | if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) | |
3371 | WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); | |
3372 | ||
3373 | /* IRQ could occur when in initial stage */ | |
3374 | if (amdgpu_crtc == NULL) | |
3375 | return 0; | |
3376 | ||
3377 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
3378 | works = amdgpu_crtc->pflip_works; | |
3379 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { | |
3380 | DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " | |
3381 | "AMDGPU_FLIP_SUBMITTED(%d)\n", | |
3382 | amdgpu_crtc->pflip_status, | |
3383 | AMDGPU_FLIP_SUBMITTED); | |
3384 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
3385 | return 0; | |
3386 | } | |
3387 | ||
3388 | /* page flip completed. clean up */ | |
3389 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; | |
3390 | amdgpu_crtc->pflip_works = NULL; | |
3391 | ||
3392 | /* wakeup usersapce */ | |
3393 | if (works->event) | |
3394 | drm_send_vblank_event(adev->ddev, crtc_id, works->event); | |
3395 | ||
3396 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
3397 | ||
3398 | drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); | |
aaa36a97 AD |
3399 | queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); |
3400 | ||
3401 | return 0; | |
3402 | } | |
3403 | ||
3404 | static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, | |
3405 | int hpd) | |
3406 | { | |
3407 | u32 tmp; | |
3408 | ||
3409 | if (hpd >= adev->mode_info.num_hpd) { | |
3410 | DRM_DEBUG("invalid hdp %d\n", hpd); | |
3411 | return; | |
3412 | } | |
3413 | ||
3414 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); | |
3415 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); | |
3416 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); | |
3417 | } | |
3418 | ||
3419 | static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, | |
3420 | int crtc) | |
3421 | { | |
3422 | u32 tmp; | |
3423 | ||
3424 | if (crtc >= adev->mode_info.num_crtc) { | |
3425 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3426 | return; | |
3427 | } | |
3428 | ||
3429 | tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); | |
3430 | tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); | |
3431 | WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); | |
3432 | } | |
3433 | ||
3434 | static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, | |
3435 | int crtc) | |
3436 | { | |
3437 | u32 tmp; | |
3438 | ||
3439 | if (crtc >= adev->mode_info.num_crtc) { | |
3440 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3441 | return; | |
3442 | } | |
3443 | ||
3444 | tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); | |
3445 | tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); | |
3446 | WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); | |
3447 | } | |
3448 | ||
3449 | static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, | |
3450 | struct amdgpu_irq_src *source, | |
3451 | struct amdgpu_iv_entry *entry) | |
3452 | { | |
3453 | unsigned crtc = entry->src_id - 1; | |
3454 | uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); | |
3455 | unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); | |
3456 | ||
3457 | switch (entry->src_data) { | |
3458 | case 0: /* vblank */ | |
bd833144 | 3459 | if (disp_int & interrupt_status_offsets[crtc].vblank) |
aaa36a97 | 3460 | dce_v10_0_crtc_vblank_int_ack(adev, crtc); |
bd833144 MK |
3461 | else |
3462 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); | |
3463 | ||
3464 | if (amdgpu_irq_enabled(adev, source, irq_type)) { | |
3465 | drm_handle_vblank(adev->ddev, crtc); | |
aaa36a97 | 3466 | } |
bd833144 MK |
3467 | DRM_DEBUG("IH: D%d vblank\n", crtc + 1); |
3468 | ||
aaa36a97 AD |
3469 | break; |
3470 | case 1: /* vline */ | |
bd833144 | 3471 | if (disp_int & interrupt_status_offsets[crtc].vline) |
aaa36a97 | 3472 | dce_v10_0_crtc_vline_int_ack(adev, crtc); |
bd833144 MK |
3473 | else |
3474 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); | |
3475 | ||
3476 | DRM_DEBUG("IH: D%d vline\n", crtc + 1); | |
3477 | ||
aaa36a97 AD |
3478 | break; |
3479 | default: | |
3480 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); | |
3481 | break; | |
3482 | } | |
3483 | ||
3484 | return 0; | |
3485 | } | |
3486 | ||
3487 | static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, | |
3488 | struct amdgpu_irq_src *source, | |
3489 | struct amdgpu_iv_entry *entry) | |
3490 | { | |
3491 | uint32_t disp_int, mask; | |
3492 | unsigned hpd; | |
3493 | ||
3494 | if (entry->src_data >= adev->mode_info.num_hpd) { | |
3495 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); | |
3496 | return 0; | |
3497 | } | |
3498 | ||
3499 | hpd = entry->src_data; | |
3500 | disp_int = RREG32(interrupt_status_offsets[hpd].reg); | |
3501 | mask = interrupt_status_offsets[hpd].hpd; | |
3502 | ||
3503 | if (disp_int & mask) { | |
3504 | dce_v10_0_hpd_int_ack(adev, hpd); | |
3505 | schedule_work(&adev->hotplug_work); | |
3506 | DRM_DEBUG("IH: HPD%d\n", hpd + 1); | |
3507 | } | |
3508 | ||
3509 | return 0; | |
3510 | } | |
3511 | ||
5fc3aeeb | 3512 | static int dce_v10_0_set_clockgating_state(void *handle, |
3513 | enum amd_clockgating_state state) | |
aaa36a97 AD |
3514 | { |
3515 | return 0; | |
3516 | } | |
3517 | ||
5fc3aeeb | 3518 | static int dce_v10_0_set_powergating_state(void *handle, |
3519 | enum amd_powergating_state state) | |
aaa36a97 AD |
3520 | { |
3521 | return 0; | |
3522 | } | |
3523 | ||
5fc3aeeb | 3524 | const struct amd_ip_funcs dce_v10_0_ip_funcs = { |
aaa36a97 AD |
3525 | .early_init = dce_v10_0_early_init, |
3526 | .late_init = NULL, | |
3527 | .sw_init = dce_v10_0_sw_init, | |
3528 | .sw_fini = dce_v10_0_sw_fini, | |
3529 | .hw_init = dce_v10_0_hw_init, | |
3530 | .hw_fini = dce_v10_0_hw_fini, | |
3531 | .suspend = dce_v10_0_suspend, | |
3532 | .resume = dce_v10_0_resume, | |
3533 | .is_idle = dce_v10_0_is_idle, | |
3534 | .wait_for_idle = dce_v10_0_wait_for_idle, | |
3535 | .soft_reset = dce_v10_0_soft_reset, | |
3536 | .print_status = dce_v10_0_print_status, | |
3537 | .set_clockgating_state = dce_v10_0_set_clockgating_state, | |
3538 | .set_powergating_state = dce_v10_0_set_powergating_state, | |
3539 | }; | |
3540 | ||
3541 | static void | |
3542 | dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, | |
3543 | struct drm_display_mode *mode, | |
3544 | struct drm_display_mode *adjusted_mode) | |
3545 | { | |
3546 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3547 | ||
3548 | amdgpu_encoder->pixel_clock = adjusted_mode->clock; | |
3549 | ||
3550 | /* need to call this here rather than in prepare() since we need some crtc info */ | |
3551 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
3552 | ||
3553 | /* set scaler clears this on some chips */ | |
3554 | dce_v10_0_set_interleave(encoder->crtc, mode); | |
3555 | ||
3556 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { | |
3557 | dce_v10_0_afmt_enable(encoder, true); | |
3558 | dce_v10_0_afmt_setmode(encoder, adjusted_mode); | |
3559 | } | |
3560 | } | |
3561 | ||
3562 | static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) | |
3563 | { | |
3564 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
3565 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3566 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); | |
3567 | ||
3568 | if ((amdgpu_encoder->active_device & | |
3569 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || | |
3570 | (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != | |
3571 | ENCODER_OBJECT_ID_NONE)) { | |
3572 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
3573 | if (dig) { | |
3574 | dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); | |
3575 | if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) | |
3576 | dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; | |
3577 | } | |
3578 | } | |
3579 | ||
3580 | amdgpu_atombios_scratch_regs_lock(adev, true); | |
3581 | ||
3582 | if (connector) { | |
3583 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
3584 | ||
3585 | /* select the clock/data port if it uses a router */ | |
3586 | if (amdgpu_connector->router.cd_valid) | |
3587 | amdgpu_i2c_router_select_cd_port(amdgpu_connector); | |
3588 | ||
3589 | /* turn eDP panel on for mode set */ | |
3590 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
3591 | amdgpu_atombios_encoder_set_edp_panel_power(connector, | |
3592 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
3593 | } | |
3594 | ||
3595 | /* this is needed for the pll/ss setup to work correctly in some cases */ | |
3596 | amdgpu_atombios_encoder_set_crtc_source(encoder); | |
3597 | /* set up the FMT blocks */ | |
3598 | dce_v10_0_program_fmt(encoder); | |
3599 | } | |
3600 | ||
3601 | static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) | |
3602 | { | |
3603 | struct drm_device *dev = encoder->dev; | |
3604 | struct amdgpu_device *adev = dev->dev_private; | |
3605 | ||
3606 | /* need to call this here as we need the crtc set up */ | |
3607 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | |
3608 | amdgpu_atombios_scratch_regs_lock(adev, false); | |
3609 | } | |
3610 | ||
3611 | static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) | |
3612 | { | |
3613 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3614 | struct amdgpu_encoder_atom_dig *dig; | |
3615 | ||
3616 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
3617 | ||
3618 | if (amdgpu_atombios_encoder_is_digital(encoder)) { | |
3619 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) | |
3620 | dce_v10_0_afmt_enable(encoder, false); | |
3621 | dig = amdgpu_encoder->enc_priv; | |
3622 | dig->dig_encoder = -1; | |
3623 | } | |
3624 | amdgpu_encoder->active_device = 0; | |
3625 | } | |
3626 | ||
3627 | /* these are handled by the primary encoders */ | |
3628 | static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) | |
3629 | { | |
3630 | ||
3631 | } | |
3632 | ||
3633 | static void dce_v10_0_ext_commit(struct drm_encoder *encoder) | |
3634 | { | |
3635 | ||
3636 | } | |
3637 | ||
3638 | static void | |
3639 | dce_v10_0_ext_mode_set(struct drm_encoder *encoder, | |
3640 | struct drm_display_mode *mode, | |
3641 | struct drm_display_mode *adjusted_mode) | |
3642 | { | |
3643 | ||
3644 | } | |
3645 | ||
3646 | static void dce_v10_0_ext_disable(struct drm_encoder *encoder) | |
3647 | { | |
3648 | ||
3649 | } | |
3650 | ||
3651 | static void | |
3652 | dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) | |
3653 | { | |
3654 | ||
3655 | } | |
3656 | ||
3657 | static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder, | |
3658 | const struct drm_display_mode *mode, | |
3659 | struct drm_display_mode *adjusted_mode) | |
3660 | { | |
3661 | return true; | |
3662 | } | |
3663 | ||
3664 | static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { | |
3665 | .dpms = dce_v10_0_ext_dpms, | |
3666 | .mode_fixup = dce_v10_0_ext_mode_fixup, | |
3667 | .prepare = dce_v10_0_ext_prepare, | |
3668 | .mode_set = dce_v10_0_ext_mode_set, | |
3669 | .commit = dce_v10_0_ext_commit, | |
3670 | .disable = dce_v10_0_ext_disable, | |
3671 | /* no detect for TMDS/LVDS yet */ | |
3672 | }; | |
3673 | ||
3674 | static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { | |
3675 | .dpms = amdgpu_atombios_encoder_dpms, | |
3676 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, | |
3677 | .prepare = dce_v10_0_encoder_prepare, | |
3678 | .mode_set = dce_v10_0_encoder_mode_set, | |
3679 | .commit = dce_v10_0_encoder_commit, | |
3680 | .disable = dce_v10_0_encoder_disable, | |
3681 | .detect = amdgpu_atombios_encoder_dig_detect, | |
3682 | }; | |
3683 | ||
3684 | static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { | |
3685 | .dpms = amdgpu_atombios_encoder_dpms, | |
3686 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, | |
3687 | .prepare = dce_v10_0_encoder_prepare, | |
3688 | .mode_set = dce_v10_0_encoder_mode_set, | |
3689 | .commit = dce_v10_0_encoder_commit, | |
3690 | .detect = amdgpu_atombios_encoder_dac_detect, | |
3691 | }; | |
3692 | ||
3693 | static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) | |
3694 | { | |
3695 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3696 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
3697 | amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); | |
3698 | kfree(amdgpu_encoder->enc_priv); | |
3699 | drm_encoder_cleanup(encoder); | |
3700 | kfree(amdgpu_encoder); | |
3701 | } | |
3702 | ||
3703 | static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { | |
3704 | .destroy = dce_v10_0_encoder_destroy, | |
3705 | }; | |
3706 | ||
3707 | static void dce_v10_0_encoder_add(struct amdgpu_device *adev, | |
3708 | uint32_t encoder_enum, | |
3709 | uint32_t supported_device, | |
3710 | u16 caps) | |
3711 | { | |
3712 | struct drm_device *dev = adev->ddev; | |
3713 | struct drm_encoder *encoder; | |
3714 | struct amdgpu_encoder *amdgpu_encoder; | |
3715 | ||
3716 | /* see if we already added it */ | |
3717 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3718 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3719 | if (amdgpu_encoder->encoder_enum == encoder_enum) { | |
3720 | amdgpu_encoder->devices |= supported_device; | |
3721 | return; | |
3722 | } | |
3723 | ||
3724 | } | |
3725 | ||
3726 | /* add a new one */ | |
3727 | amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); | |
3728 | if (!amdgpu_encoder) | |
3729 | return; | |
3730 | ||
3731 | encoder = &amdgpu_encoder->base; | |
3732 | switch (adev->mode_info.num_crtc) { | |
3733 | case 1: | |
3734 | encoder->possible_crtcs = 0x1; | |
3735 | break; | |
3736 | case 2: | |
3737 | default: | |
3738 | encoder->possible_crtcs = 0x3; | |
3739 | break; | |
3740 | case 4: | |
3741 | encoder->possible_crtcs = 0xf; | |
3742 | break; | |
3743 | case 6: | |
3744 | encoder->possible_crtcs = 0x3f; | |
3745 | break; | |
3746 | } | |
3747 | ||
3748 | amdgpu_encoder->enc_priv = NULL; | |
3749 | ||
3750 | amdgpu_encoder->encoder_enum = encoder_enum; | |
3751 | amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
3752 | amdgpu_encoder->devices = supported_device; | |
3753 | amdgpu_encoder->rmx_type = RMX_OFF; | |
3754 | amdgpu_encoder->underscan_type = UNDERSCAN_OFF; | |
3755 | amdgpu_encoder->is_ext_encoder = false; | |
3756 | amdgpu_encoder->caps = caps; | |
3757 | ||
3758 | switch (amdgpu_encoder->encoder_id) { | |
3759 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
3760 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
3761 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3762 | DRM_MODE_ENCODER_DAC); | |
3763 | drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); | |
3764 | break; | |
3765 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
3766 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
3767 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
3768 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
3769 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: | |
3770 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
3771 | amdgpu_encoder->rmx_type = RMX_FULL; | |
3772 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3773 | DRM_MODE_ENCODER_LVDS); | |
3774 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); | |
3775 | } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { | |
3776 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3777 | DRM_MODE_ENCODER_DAC); | |
3778 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); | |
3779 | } else { | |
3780 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3781 | DRM_MODE_ENCODER_TMDS); | |
3782 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); | |
3783 | } | |
3784 | drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); | |
3785 | break; | |
3786 | case ENCODER_OBJECT_ID_SI170B: | |
3787 | case ENCODER_OBJECT_ID_CH7303: | |
3788 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: | |
3789 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: | |
3790 | case ENCODER_OBJECT_ID_TITFP513: | |
3791 | case ENCODER_OBJECT_ID_VT1623: | |
3792 | case ENCODER_OBJECT_ID_HDMI_SI1930: | |
3793 | case ENCODER_OBJECT_ID_TRAVIS: | |
3794 | case ENCODER_OBJECT_ID_NUTMEG: | |
3795 | /* these are handled by the primary encoders */ | |
3796 | amdgpu_encoder->is_ext_encoder = true; | |
3797 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
3798 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3799 | DRM_MODE_ENCODER_LVDS); | |
3800 | else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) | |
3801 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3802 | DRM_MODE_ENCODER_DAC); | |
3803 | else | |
3804 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3805 | DRM_MODE_ENCODER_TMDS); | |
3806 | drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); | |
3807 | break; | |
3808 | } | |
3809 | } | |
3810 | ||
3811 | static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { | |
3812 | .set_vga_render_state = &dce_v10_0_set_vga_render_state, | |
3813 | .bandwidth_update = &dce_v10_0_bandwidth_update, | |
3814 | .vblank_get_counter = &dce_v10_0_vblank_get_counter, | |
3815 | .vblank_wait = &dce_v10_0_vblank_wait, | |
3816 | .is_display_hung = &dce_v10_0_is_display_hung, | |
3817 | .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, | |
3818 | .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, | |
3819 | .hpd_sense = &dce_v10_0_hpd_sense, | |
3820 | .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, | |
3821 | .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, | |
3822 | .page_flip = &dce_v10_0_page_flip, | |
3823 | .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, | |
3824 | .add_encoder = &dce_v10_0_encoder_add, | |
3825 | .add_connector = &amdgpu_connector_add, | |
3826 | .stop_mc_access = &dce_v10_0_stop_mc_access, | |
3827 | .resume_mc_access = &dce_v10_0_resume_mc_access, | |
3828 | }; | |
3829 | ||
3830 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) | |
3831 | { | |
3832 | if (adev->mode_info.funcs == NULL) | |
3833 | adev->mode_info.funcs = &dce_v10_0_display_funcs; | |
3834 | } | |
3835 | ||
3836 | static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { | |
3837 | .set = dce_v10_0_set_crtc_irq_state, | |
3838 | .process = dce_v10_0_crtc_irq, | |
3839 | }; | |
3840 | ||
3841 | static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { | |
3842 | .set = dce_v10_0_set_pageflip_irq_state, | |
3843 | .process = dce_v10_0_pageflip_irq, | |
3844 | }; | |
3845 | ||
3846 | static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { | |
3847 | .set = dce_v10_0_set_hpd_irq_state, | |
3848 | .process = dce_v10_0_hpd_irq, | |
3849 | }; | |
3850 | ||
3851 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) | |
3852 | { | |
3853 | adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; | |
3854 | adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; | |
3855 | ||
3856 | adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; | |
3857 | adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; | |
3858 | ||
3859 | adev->hpd_irq.num_types = AMDGPU_HPD_LAST; | |
3860 | adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; | |
3861 | } |