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Merge remote-tracking branch 'sound-asoc/for-next'
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v10_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_10_0_d.h"
36#include "dce/dce_10_0_sh_mask.h"
37#include "dce/dce_10_0_enum.h"
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42
43static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
44static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
45
46static const u32 crtc_offsets[] =
47{
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55};
56
57static const u32 hpd_offsets[] =
58{
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65};
66
67static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET
75};
76
77static const struct {
78 uint32_t reg;
79 uint32_t vblank;
80 uint32_t vline;
81 uint32_t hpd;
82
83} interrupt_status_offsets[] = { {
84 .reg = mmDISP_INTERRUPT_STATUS,
85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
88}, {
89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
93}, {
94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
98}, {
99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
103}, {
104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
108}, {
109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
113} };
114
115static const u32 golden_settings_tonga_a11[] =
116{
117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
119 mmFBC_MISC, 0x1f311fff, 0x12300000,
120 mmHDMI_CONTROL, 0x31000111, 0x00000011,
121};
122
5732a94f
AD		 123static const u32 tonga_mgcg_cgcg_init[] =
124{
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
84390860
DZ		 129static const u32 golden_settings_fiji_a10[] =
130{
131 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
132 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
133 mmFBC_MISC, 0x1f311fff, 0x12300000,
134 mmHDMI_CONTROL, 0x31000111, 0x00000011,
135};
136
137static const u32 fiji_mgcg_cgcg_init[] =
138{
139 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
140 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
141};
142
aaa36a97
AD		 143static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
144{
145 switch (adev->asic_type) {
84390860
DZ		 146 case CHIP_FIJI:
147 amdgpu_program_register_sequence(adev,
148 fiji_mgcg_cgcg_init,
149 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
150 amdgpu_program_register_sequence(adev,
151 golden_settings_fiji_a10,
152 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
153 break;
aaa36a97 154 case CHIP_TONGA:
5732a94f
AD		 155 amdgpu_program_register_sequence(adev,
156 tonga_mgcg_cgcg_init,
157 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
aaa36a97
AD		 158 amdgpu_program_register_sequence(adev,
159 golden_settings_tonga_a11,
160 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
161 break;
162 default:
163 break;
164 }
165}
166
167static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
168 u32 block_offset, u32 reg)
169{
170 unsigned long flags;
171 u32 r;
172
173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
177
178 return r;
179}
180
181static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
182 u32 block_offset, u32 reg, u32 v)
183{
184 unsigned long flags;
185
186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
190}
191
192static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
193{
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
196 return true;
197 else
198 return false;
199}
200
201static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
202{
203 u32 pos1, pos2;
204
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
207
208 if (pos1 != pos2)
209 return true;
210 else
211 return false;
212}
213
214/**
215 * dce_v10_0_vblank_wait - vblank wait asic callback.
216 *
217 * @adev: amdgpu_device pointer
218 * @crtc: crtc to wait for vblank on
219 *
220 * Wait for vblank on the requested crtc (evergreen+).
221 */
222static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
223{
224 unsigned i = 0;
225
226 if (crtc >= adev->mode_info.num_crtc)
227 return;
228
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
230 return;
231
232 /* depending on when we hit vblank, we may be close to active; if so,
233 * wait for another frame.
234 */
235 while (dce_v10_0_is_in_vblank(adev, crtc)) {
236 if (i++ % 100 == 0) {
237 if (!dce_v10_0_is_counter_moving(adev, crtc))
238 break;
239 }
240 }
241
242 while (!dce_v10_0_is_in_vblank(adev, crtc)) {
243 if (i++ % 100 == 0) {
244 if (!dce_v10_0_is_counter_moving(adev, crtc))
245 break;
246 }
247 }
248}
249
250static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
251{
252 if (crtc >= adev->mode_info.num_crtc)
253 return 0;
254 else
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
256}
257
f6c7aba4
MD		 258static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
259{
260 unsigned i;
261
262 /* Enable pflip interrupts */
263 for (i = 0; i < adev->mode_info.num_crtc; i++)
264 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
265}
266
267static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
268{
269 unsigned i;
270
271 /* Disable pflip interrupts */
272 for (i = 0; i < adev->mode_info.num_crtc; i++)
273 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
274}
275
aaa36a97
AD		 276/**
277 * dce_v10_0_page_flip - pageflip callback.
278 *
279 * @adev: amdgpu_device pointer
280 * @crtc_id: crtc to cleanup pageflip on
281 * @crtc_base: new address of the crtc (GPU MC address)
282 *
0eaaacab
AD		 283 * Triggers the actual pageflip by updating the primary
284 * surface base address.
aaa36a97
AD		 285 */
286static void dce_v10_0_page_flip(struct amdgpu_device *adev,
cb9e59d7 287 int crtc_id, u64 crtc_base, bool async)
aaa36a97
AD		 288{
289 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
cb9e59d7 290 u32 tmp;
aaa36a97 291
cb9e59d7
AD		 292 /* flip at hsync for async, default is vsync */
293 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
294 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
295 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
296 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
0eaaacab 297 /* update the primary scanout address */
aaa36a97
AD		 298 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
299 upper_32_bits(crtc_base));
0eaaacab 300 /* writing to the low address triggers the update */
aaa36a97
AD		 301 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
302 lower_32_bits(crtc_base));
0eaaacab
AD		 303 /* post the write */
304 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
aaa36a97
AD		 305}
306
307static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
308 u32 *vbl, u32 *position)
309{
310 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
311 return -EINVAL;
312
313 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
314 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
315
316 return 0;
317}
318
319/**
320 * dce_v10_0_hpd_sense - hpd sense callback.
321 *
322 * @adev: amdgpu_device pointer
323 * @hpd: hpd (hotplug detect) pin
324 *
325 * Checks if a digital monitor is connected (evergreen+).
326 * Returns true if connected, false if not connected.
327 */
328static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
329 enum amdgpu_hpd_id hpd)
330{
331 int idx;
332 bool connected = false;
333
334 switch (hpd) {
335 case AMDGPU_HPD_1:
336 idx = 0;
337 break;
338 case AMDGPU_HPD_2:
339 idx = 1;
340 break;
341 case AMDGPU_HPD_3:
342 idx = 2;
343 break;
344 case AMDGPU_HPD_4:
345 idx = 3;
346 break;
347 case AMDGPU_HPD_5:
348 idx = 4;
349 break;
350 case AMDGPU_HPD_6:
351 idx = 5;
352 break;
353 default:
354 return connected;
355 }
356
357 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
358 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
359 connected = true;
360
361 return connected;
362}
363
364/**
365 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
366 *
367 * @adev: amdgpu_device pointer
368 * @hpd: hpd (hotplug detect) pin
369 *
370 * Set the polarity of the hpd pin (evergreen+).
371 */
372static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
373 enum amdgpu_hpd_id hpd)
374{
375 u32 tmp;
376 bool connected = dce_v10_0_hpd_sense(adev, hpd);
377 int idx;
378
379 switch (hpd) {
380 case AMDGPU_HPD_1:
381 idx = 0;
382 break;
383 case AMDGPU_HPD_2:
384 idx = 1;
385 break;
386 case AMDGPU_HPD_3:
387 idx = 2;
388 break;
389 case AMDGPU_HPD_4:
390 idx = 3;
391 break;
392 case AMDGPU_HPD_5:
393 idx = 4;
394 break;
395 case AMDGPU_HPD_6:
396 idx = 5;
397 break;
398 default:
399 return;
400 }
401
402 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
403 if (connected)
404 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
405 else
406 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
407 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
408}
409
410/**
411 * dce_v10_0_hpd_init - hpd setup callback.
412 *
413 * @adev: amdgpu_device pointer
414 *
415 * Setup the hpd pins used by the card (evergreen+).
416 * Enable the pin, set the polarity, and enable the hpd interrupts.
417 */
418static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
419{
420 struct drm_device *dev = adev->ddev;
421 struct drm_connector *connector;
422 u32 tmp;
423 int idx;
424
425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
427
428 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
429 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
430 /* don't try to enable hpd on eDP or LVDS avoid breaking the
431 * aux dp channel on imac and help (but not completely fix)
432 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
433 * also avoid interrupt storms during dpms.
434 */
435 continue;
436 }
437
438 switch (amdgpu_connector->hpd.hpd) {
439 case AMDGPU_HPD_1:
440 idx = 0;
441 break;
442 case AMDGPU_HPD_2:
443 idx = 1;
444 break;
445 case AMDGPU_HPD_3:
446 idx = 2;
447 break;
448 case AMDGPU_HPD_4:
449 idx = 3;
450 break;
451 case AMDGPU_HPD_5:
452 idx = 4;
453 break;
454 case AMDGPU_HPD_6:
455 idx = 5;
456 break;
457 default:
458 continue;
459 }
460
461 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
462 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
463 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
464
465 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
466 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
467 DC_HPD_CONNECT_INT_DELAY,
468 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
469 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
470 DC_HPD_DISCONNECT_INT_DELAY,
471 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
472 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
473
474 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
475 amdgpu_irq_get(adev, &adev->hpd_irq,
476 amdgpu_connector->hpd.hpd);
477 }
478}
479
480/**
481 * dce_v10_0_hpd_fini - hpd tear down callback.
482 *
483 * @adev: amdgpu_device pointer
484 *
485 * Tear down the hpd pins used by the card (evergreen+).
486 * Disable the hpd interrupts.
487 */
488static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
489{
490 struct drm_device *dev = adev->ddev;
491 struct drm_connector *connector;
492 u32 tmp;
493 int idx;
494
495 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
496 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
497
498 switch (amdgpu_connector->hpd.hpd) {
499 case AMDGPU_HPD_1:
500 idx = 0;
501 break;
502 case AMDGPU_HPD_2:
503 idx = 1;
504 break;
505 case AMDGPU_HPD_3:
506 idx = 2;
507 break;
508 case AMDGPU_HPD_4:
509 idx = 3;
510 break;
511 case AMDGPU_HPD_5:
512 idx = 4;
513 break;
514 case AMDGPU_HPD_6:
515 idx = 5;
516 break;
517 default:
518 continue;
519 }
520
521 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
522 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
523 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
524
525 amdgpu_irq_put(adev, &adev->hpd_irq,
526 amdgpu_connector->hpd.hpd);
527 }
528}
529
530static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
531{
532 return mmDC_GPIO_HPD_A;
533}
534
535static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
536{
537 u32 crtc_hung = 0;
538 u32 crtc_status[6];
539 u32 i, j, tmp;
540
541 for (i = 0; i < adev->mode_info.num_crtc; i++) {
542 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
543 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
544 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
545 crtc_hung |= (1 << i);
546 }
547 }
548
549 for (j = 0; j < 10; j++) {
550 for (i = 0; i < adev->mode_info.num_crtc; i++) {
551 if (crtc_hung & (1 << i)) {
552 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
553 if (tmp != crtc_status[i])
554 crtc_hung &= ~(1 << i);
555 }
556 }
557 if (crtc_hung == 0)
558 return false;
559 udelay(100);
560 }
561
562 return true;
563}
564
565static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
566 struct amdgpu_mode_mc_save *save)
567{
568 u32 crtc_enabled, tmp;
569 int i;
570
571 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
572 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
573
574 /* disable VGA render */
575 tmp = RREG32(mmVGA_RENDER_CONTROL);
576 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
577 WREG32(mmVGA_RENDER_CONTROL, tmp);
578
579 /* blank the display controllers */
580 for (i = 0; i < adev->mode_info.num_crtc; i++) {
581 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
582 CRTC_CONTROL, CRTC_MASTER_EN);
583 if (crtc_enabled) {
584#if 0
585 u32 frame_count;
586 int j;
587
588 save->crtc_enabled[i] = true;
589 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
590 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
591 amdgpu_display_vblank_wait(adev, i);
592 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
593 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
594 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
595 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
596 }
597 /* wait for the next frame */
598 frame_count = amdgpu_display_vblank_get_counter(adev, i);
599 for (j = 0; j < adev->usec_timeout; j++) {
600 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
601 break;
602 udelay(1);
603 }
604 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
605 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
606 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
607 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
608 }
609 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
610 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
611 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
612 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
613 }
614#else
615 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
616 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
617 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
618 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
619 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
620 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
621 save->crtc_enabled[i] = false;
622 /* ***** */
623#endif
624 } else {
625 save->crtc_enabled[i] = false;
626 }
627 }
628}
629
630static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
631 struct amdgpu_mode_mc_save *save)
632{
633 u32 tmp, frame_count;
634 int i, j;
635
636 /* update crtc base addresses */
637 for (i = 0; i < adev->mode_info.num_crtc; i++) {
638 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
639 upper_32_bits(adev->mc.vram_start));
640 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
641 upper_32_bits(adev->mc.vram_start));
642 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
643 (u32)adev->mc.vram_start);
644 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
645 (u32)adev->mc.vram_start);
646
647 if (save->crtc_enabled[i]) {
648 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
3fd4b751
MD		 649 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
650 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
aaa36a97
AD		 651 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
652 }
653 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
654 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
655 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
656 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
657 }
658 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
659 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
660 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
661 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
662 }
663 for (j = 0; j < adev->usec_timeout; j++) {
664 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
665 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
666 break;
667 udelay(1);
668 }
669 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
670 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
671 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
672 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
673 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
674 /* wait for the next frame */
675 frame_count = amdgpu_display_vblank_get_counter(adev, i);
676 for (j = 0; j < adev->usec_timeout; j++) {
677 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
678 break;
679 udelay(1);
680 }
681 }
682 }
683
684 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
685 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
686
687 /* Unlock vga access */
688 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
689 mdelay(1);
690 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
691}
692
693static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
694 bool render)
695{
696 u32 tmp;
697
698 /* Lockout access through VGA aperture*/
699 tmp = RREG32(mmVGA_HDP_CONTROL);
700 if (render)
701 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
702 else
703 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
704 WREG32(mmVGA_HDP_CONTROL, tmp);
705
706 /* disable VGA render */
707 tmp = RREG32(mmVGA_RENDER_CONTROL);
708 if (render)
709 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
710 else
711 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
712 WREG32(mmVGA_RENDER_CONTROL, tmp);
713}
714
83c9b025
ED		 715static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
716{
717 int num_crtc = 0;
718
719 switch (adev->asic_type) {
720 case CHIP_FIJI:
721 case CHIP_TONGA:
722 num_crtc = 6;
723 break;
724 default:
725 num_crtc = 0;
726 }
727 return num_crtc;
728}
729
730void dce_v10_0_disable_dce(struct amdgpu_device *adev)
731{
732 /*Disable VGA render and enabled crtc, if has DCE engine*/
733 if (amdgpu_atombios_has_dce_engine_info(adev)) {
734 u32 tmp;
735 int crtc_enabled, i;
736
737 dce_v10_0_set_vga_render_state(adev, false);
738
739 /*Disable crtc*/
740 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
741 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
742 CRTC_CONTROL, CRTC_MASTER_EN);
743 if (crtc_enabled) {
744 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
745 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
746 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
747 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
748 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
749 }
750 }
751 }
752}
753
aaa36a97
AD		 754static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
755{
756 struct drm_device *dev = encoder->dev;
757 struct amdgpu_device *adev = dev->dev_private;
758 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
759 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
760 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
761 int bpc = 0;
762 u32 tmp = 0;
763 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
764
765 if (connector) {
766 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
767 bpc = amdgpu_connector_get_monitor_bpc(connector);
768 dither = amdgpu_connector->dither;
769 }
770
771 /* LVDS/eDP FMT is set up by atom */
772 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
773 return;
774
775 /* not needed for analog */
776 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
777 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
778 return;
779
780 if (bpc == 0)
781 return;
782
783 switch (bpc) {
784 case 6:
785 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
786 /* XXX sort out optimal dither settings */
787 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
788 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
789 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
790 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
791 } else {
792 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
793 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
794 }
795 break;
796 case 8:
797 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
798 /* XXX sort out optimal dither settings */
799 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
800 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
801 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
802 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
803 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
804 } else {
805 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
806 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
807 }
808 break;
809 case 10:
810 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
811 /* XXX sort out optimal dither settings */
812 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
813 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
814 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
815 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
816 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
817 } else {
818 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
819 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
820 }
821 break;
822 default:
823 /* not needed */
824 break;
825 }
826
827 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
828}
829
830
831/* display watermark setup */
832/**
833 * dce_v10_0_line_buffer_adjust - Set up the line buffer
834 *
835 * @adev: amdgpu_device pointer
836 * @amdgpu_crtc: the selected display controller
837 * @mode: the current display mode on the selected display
838 * controller
839 *
840 * Setup up the line buffer allocation for
841 * the selected display controller (CIK).
842 * Returns the line buffer size in pixels.
843 */
844static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
845 struct amdgpu_crtc *amdgpu_crtc,
846 struct drm_display_mode *mode)
847{
848 u32 tmp, buffer_alloc, i, mem_cfg;
849 u32 pipe_offset = amdgpu_crtc->crtc_id;
850 /*
851 * Line Buffer Setup
852 * There are 6 line buffers, one for each display controllers.
853 * There are 3 partitions per LB. Select the number of partitions
854 * to enable based on the display width. For display widths larger
855 * than 4096, you need use to use 2 display controllers and combine
856 * them using the stereo blender.
857 */
858 if (amdgpu_crtc->base.enabled && mode) {
859 if (mode->crtc_hdisplay < 1920) {
860 mem_cfg = 1;
861 buffer_alloc = 2;
862 } else if (mode->crtc_hdisplay < 2560) {
863 mem_cfg = 2;
864 buffer_alloc = 2;
865 } else if (mode->crtc_hdisplay < 4096) {
866 mem_cfg = 0;
2f7d10b3 867 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 868 } else {
869 DRM_DEBUG_KMS("Mode too big for LB!\n");
870 mem_cfg = 0;
2f7d10b3 871 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 872 }
873 } else {
874 mem_cfg = 1;
875 buffer_alloc = 0;
876 }
877
878 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
879 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
880 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
881
882 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
883 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
884 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
885
886 for (i = 0; i < adev->usec_timeout; i++) {
887 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
888 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
889 break;
890 udelay(1);
891 }
892
893 if (amdgpu_crtc->base.enabled && mode) {
894 switch (mem_cfg) {
895 case 0:
896 default:
897 return 4096 * 2;
898 case 1:
899 return 1920 * 2;
900 case 2:
901 return 2560 * 2;
902 }
903 }
904
905 /* controller not enabled, so no lb used */
906 return 0;
907}
908
909/**
910 * cik_get_number_of_dram_channels - get the number of dram channels
911 *
912 * @adev: amdgpu_device pointer
913 *
914 * Look up the number of video ram channels (CIK).
915 * Used for display watermark bandwidth calculations
916 * Returns the number of dram channels
917 */
918static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
919{
920 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
921
922 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
923 case 0:
924 default:
925 return 1;
926 case 1:
927 return 2;
928 case 2:
929 return 4;
930 case 3:
931 return 8;
932 case 4:
933 return 3;
934 case 5:
935 return 6;
936 case 6:
937 return 10;
938 case 7:
939 return 12;
940 case 8:
941 return 16;
942 }
943}
944
945struct dce10_wm_params {
946 u32 dram_channels; /* number of dram channels */
947 u32 yclk; /* bandwidth per dram data pin in kHz */
948 u32 sclk; /* engine clock in kHz */
949 u32 disp_clk; /* display clock in kHz */
950 u32 src_width; /* viewport width */
951 u32 active_time; /* active display time in ns */
952 u32 blank_time; /* blank time in ns */
953 bool interlaced; /* mode is interlaced */
954 fixed20_12 vsc; /* vertical scale ratio */
955 u32 num_heads; /* number of active crtcs */
956 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
957 u32 lb_size; /* line buffer allocated to pipe */
958 u32 vtaps; /* vertical scaler taps */
959};
960
961/**
962 * dce_v10_0_dram_bandwidth - get the dram bandwidth
963 *
964 * @wm: watermark calculation data
965 *
966 * Calculate the raw dram bandwidth (CIK).
967 * Used for display watermark bandwidth calculations
968 * Returns the dram bandwidth in MBytes/s
969 */
970static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
971{
972 /* Calculate raw DRAM Bandwidth */
973 fixed20_12 dram_efficiency; /* 0.7 */
974 fixed20_12 yclk, dram_channels, bandwidth;
975 fixed20_12 a;
976
977 a.full = dfixed_const(1000);
978 yclk.full = dfixed_const(wm->yclk);
979 yclk.full = dfixed_div(yclk, a);
980 dram_channels.full = dfixed_const(wm->dram_channels * 4);
981 a.full = dfixed_const(10);
982 dram_efficiency.full = dfixed_const(7);
983 dram_efficiency.full = dfixed_div(dram_efficiency, a);
984 bandwidth.full = dfixed_mul(dram_channels, yclk);
985 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
986
987 return dfixed_trunc(bandwidth);
988}
989
990/**
991 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
992 *
993 * @wm: watermark calculation data
994 *
995 * Calculate the dram bandwidth used for display (CIK).
996 * Used for display watermark bandwidth calculations
997 * Returns the dram bandwidth for display in MBytes/s
998 */
999static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1000{
1001 /* Calculate DRAM Bandwidth and the part allocated to display. */
1002 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1003 fixed20_12 yclk, dram_channels, bandwidth;
1004 fixed20_12 a;
1005
1006 a.full = dfixed_const(1000);
1007 yclk.full = dfixed_const(wm->yclk);
1008 yclk.full = dfixed_div(yclk, a);
1009 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1010 a.full = dfixed_const(10);
1011 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1012 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1013 bandwidth.full = dfixed_mul(dram_channels, yclk);
1014 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1015
1016 return dfixed_trunc(bandwidth);
1017}
1018
1019/**
1020 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
1021 *
1022 * @wm: watermark calculation data
1023 *
1024 * Calculate the data return bandwidth used for display (CIK).
1025 * Used for display watermark bandwidth calculations
1026 * Returns the data return bandwidth in MBytes/s
1027 */
1028static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
1029{
1030 /* Calculate the display Data return Bandwidth */
1031 fixed20_12 return_efficiency; /* 0.8 */
1032 fixed20_12 sclk, bandwidth;
1033 fixed20_12 a;
1034
1035 a.full = dfixed_const(1000);
1036 sclk.full = dfixed_const(wm->sclk);
1037 sclk.full = dfixed_div(sclk, a);
1038 a.full = dfixed_const(10);
1039 return_efficiency.full = dfixed_const(8);
1040 return_efficiency.full = dfixed_div(return_efficiency, a);
1041 a.full = dfixed_const(32);
1042 bandwidth.full = dfixed_mul(a, sclk);
1043 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1044
1045 return dfixed_trunc(bandwidth);
1046}
1047
1048/**
1049 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1050 *
1051 * @wm: watermark calculation data
1052 *
1053 * Calculate the dmif bandwidth used for display (CIK).
1054 * Used for display watermark bandwidth calculations
1055 * Returns the dmif bandwidth in MBytes/s
1056 */
1057static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1058{
1059 /* Calculate the DMIF Request Bandwidth */
1060 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1061 fixed20_12 disp_clk, bandwidth;
1062 fixed20_12 a, b;
1063
1064 a.full = dfixed_const(1000);
1065 disp_clk.full = dfixed_const(wm->disp_clk);
1066 disp_clk.full = dfixed_div(disp_clk, a);
1067 a.full = dfixed_const(32);
1068 b.full = dfixed_mul(a, disp_clk);
1069
1070 a.full = dfixed_const(10);
1071 disp_clk_request_efficiency.full = dfixed_const(8);
1072 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1073
1074 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1075
1076 return dfixed_trunc(bandwidth);
1077}
1078
1079/**
1080 * dce_v10_0_available_bandwidth - get the min available bandwidth
1081 *
1082 * @wm: watermark calculation data
1083 *
1084 * Calculate the min available bandwidth used for display (CIK).
1085 * Used for display watermark bandwidth calculations
1086 * Returns the min available bandwidth in MBytes/s
1087 */
1088static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1089{
1090 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1091 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1092 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1093 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1094
1095 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1096}
1097
1098/**
1099 * dce_v10_0_average_bandwidth - get the average available bandwidth
1100 *
1101 * @wm: watermark calculation data
1102 *
1103 * Calculate the average available bandwidth used for display (CIK).
1104 * Used for display watermark bandwidth calculations
1105 * Returns the average available bandwidth in MBytes/s
1106 */
1107static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1108{
1109 /* Calculate the display mode Average Bandwidth
1110 * DisplayMode should contain the source and destination dimensions,
1111 * timing, etc.
1112 */
1113 fixed20_12 bpp;
1114 fixed20_12 line_time;
1115 fixed20_12 src_width;
1116 fixed20_12 bandwidth;
1117 fixed20_12 a;
1118
1119 a.full = dfixed_const(1000);
1120 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1121 line_time.full = dfixed_div(line_time, a);
1122 bpp.full = dfixed_const(wm->bytes_per_pixel);
1123 src_width.full = dfixed_const(wm->src_width);
1124 bandwidth.full = dfixed_mul(src_width, bpp);
1125 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1126 bandwidth.full = dfixed_div(bandwidth, line_time);
1127
1128 return dfixed_trunc(bandwidth);
1129}
1130
1131/**
1132 * dce_v10_0_latency_watermark - get the latency watermark
1133 *
1134 * @wm: watermark calculation data
1135 *
1136 * Calculate the latency watermark (CIK).
1137 * Used for display watermark bandwidth calculations
1138 * Returns the latency watermark in ns
1139 */
1140static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1141{
1142 /* First calculate the latency in ns */
1143 u32 mc_latency = 2000; /* 2000 ns. */
1144 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1145 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1146 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1147 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1148 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1149 (wm->num_heads * cursor_line_pair_return_time);
1150 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1151 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1152 u32 tmp, dmif_size = 12288;
1153 fixed20_12 a, b, c;
1154
1155 if (wm->num_heads == 0)
1156 return 0;
1157
1158 a.full = dfixed_const(2);
1159 b.full = dfixed_const(1);
1160 if ((wm->vsc.full > a.full) ||
1161 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1162 (wm->vtaps >= 5) ||
1163 ((wm->vsc.full >= a.full) && wm->interlaced))
1164 max_src_lines_per_dst_line = 4;
1165 else
1166 max_src_lines_per_dst_line = 2;
1167
1168 a.full = dfixed_const(available_bandwidth);
1169 b.full = dfixed_const(wm->num_heads);
1170 a.full = dfixed_div(a, b);
1171
1172 b.full = dfixed_const(mc_latency + 512);
1173 c.full = dfixed_const(wm->disp_clk);
1174 b.full = dfixed_div(b, c);
1175
1176 c.full = dfixed_const(dmif_size);
1177 b.full = dfixed_div(c, b);
1178
1179 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1180
1181 b.full = dfixed_const(1000);
1182 c.full = dfixed_const(wm->disp_clk);
1183 b.full = dfixed_div(c, b);
1184 c.full = dfixed_const(wm->bytes_per_pixel);
1185 b.full = dfixed_mul(b, c);
1186
1187 lb_fill_bw = min(tmp, dfixed_trunc(b));
1188
1189 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1190 b.full = dfixed_const(1000);
1191 c.full = dfixed_const(lb_fill_bw);
1192 b.full = dfixed_div(c, b);
1193 a.full = dfixed_div(a, b);
1194 line_fill_time = dfixed_trunc(a);
1195
1196 if (line_fill_time < wm->active_time)
1197 return latency;
1198 else
1199 return latency + (line_fill_time - wm->active_time);
1200
1201}
1202
1203/**
1204 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1205 * average and available dram bandwidth
1206 *
1207 * @wm: watermark calculation data
1208 *
1209 * Check if the display average bandwidth fits in the display
1210 * dram bandwidth (CIK).
1211 * Used for display watermark bandwidth calculations
1212 * Returns true if the display fits, false if not.
1213 */
1214static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1215{
1216 if (dce_v10_0_average_bandwidth(wm) <=
1217 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1218 return true;
1219 else
1220 return false;
1221}
1222
1223/**
1224 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1225 * average and available bandwidth
1226 *
1227 * @wm: watermark calculation data
1228 *
1229 * Check if the display average bandwidth fits in the display
1230 * available bandwidth (CIK).
1231 * Used for display watermark bandwidth calculations
1232 * Returns true if the display fits, false if not.
1233 */
1234static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1235{
1236 if (dce_v10_0_average_bandwidth(wm) <=
1237 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1238 return true;
1239 else
1240 return false;
1241}
1242
1243/**
1244 * dce_v10_0_check_latency_hiding - check latency hiding
1245 *
1246 * @wm: watermark calculation data
1247 *
1248 * Check latency hiding (CIK).
1249 * Used for display watermark bandwidth calculations
1250 * Returns true if the display fits, false if not.
1251 */
1252static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1253{
1254 u32 lb_partitions = wm->lb_size / wm->src_width;
1255 u32 line_time = wm->active_time + wm->blank_time;
1256 u32 latency_tolerant_lines;
1257 u32 latency_hiding;
1258 fixed20_12 a;
1259
1260 a.full = dfixed_const(1);
1261 if (wm->vsc.full > a.full)
1262 latency_tolerant_lines = 1;
1263 else {
1264 if (lb_partitions <= (wm->vtaps + 1))
1265 latency_tolerant_lines = 1;
1266 else
1267 latency_tolerant_lines = 2;
1268 }
1269
1270 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1271
1272 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1273 return true;
1274 else
1275 return false;
1276}
1277
1278/**
1279 * dce_v10_0_program_watermarks - program display watermarks
1280 *
1281 * @adev: amdgpu_device pointer
1282 * @amdgpu_crtc: the selected display controller
1283 * @lb_size: line buffer size
1284 * @num_heads: number of display controllers in use
1285 *
1286 * Calculate and program the display watermarks for the
1287 * selected display controller (CIK).
1288 */
1289static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1290 struct amdgpu_crtc *amdgpu_crtc,
1291 u32 lb_size, u32 num_heads)
1292{
1293 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1294 struct dce10_wm_params wm_low, wm_high;
1295 u32 pixel_period;
1296 u32 line_time = 0;
1297 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1298 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
aaa36a97
AD		 1299
1300 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1301 pixel_period = 1000000 / (u32)mode->clock;
1302 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1303
1304 /* watermark for high clocks */
1305 if (adev->pm.dpm_enabled) {
1306 wm_high.yclk =
1307 amdgpu_dpm_get_mclk(adev, false) * 10;
1308 wm_high.sclk =
1309 amdgpu_dpm_get_sclk(adev, false) * 10;
1310 } else {
1311 wm_high.yclk = adev->pm.current_mclk * 10;
1312 wm_high.sclk = adev->pm.current_sclk * 10;
1313 }
1314
1315 wm_high.disp_clk = mode->clock;
1316 wm_high.src_width = mode->crtc_hdisplay;
1317 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1318 wm_high.blank_time = line_time - wm_high.active_time;
1319 wm_high.interlaced = false;
1320 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1321 wm_high.interlaced = true;
1322 wm_high.vsc = amdgpu_crtc->vsc;
1323 wm_high.vtaps = 1;
1324 if (amdgpu_crtc->rmx_type != RMX_OFF)
1325 wm_high.vtaps = 2;
1326 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1327 wm_high.lb_size = lb_size;
1328 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1329 wm_high.num_heads = num_heads;
1330
1331 /* set for high clocks */
1332 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1333
1334 /* possibly force display priority to high */
1335 /* should really do this at mode validation time... */
1336 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1337 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1338 !dce_v10_0_check_latency_hiding(&wm_high) ||
1339 (adev->mode_info.disp_priority == 2)) {
1340 DRM_DEBUG_KMS("force priority to high\n");
1341 }
1342
1343 /* watermark for low clocks */
1344 if (adev->pm.dpm_enabled) {
1345 wm_low.yclk =
1346 amdgpu_dpm_get_mclk(adev, true) * 10;
1347 wm_low.sclk =
1348 amdgpu_dpm_get_sclk(adev, true) * 10;
1349 } else {
1350 wm_low.yclk = adev->pm.current_mclk * 10;
1351 wm_low.sclk = adev->pm.current_sclk * 10;
1352 }
1353
1354 wm_low.disp_clk = mode->clock;
1355 wm_low.src_width = mode->crtc_hdisplay;
1356 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1357 wm_low.blank_time = line_time - wm_low.active_time;
1358 wm_low.interlaced = false;
1359 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1360 wm_low.interlaced = true;
1361 wm_low.vsc = amdgpu_crtc->vsc;
1362 wm_low.vtaps = 1;
1363 if (amdgpu_crtc->rmx_type != RMX_OFF)
1364 wm_low.vtaps = 2;
1365 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1366 wm_low.lb_size = lb_size;
1367 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1368 wm_low.num_heads = num_heads;
1369
1370 /* set for low clocks */
1371 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1372
1373 /* possibly force display priority to high */
1374 /* should really do this at mode validation time... */
1375 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1376 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1377 !dce_v10_0_check_latency_hiding(&wm_low) ||
1378 (adev->mode_info.disp_priority == 2)) {
1379 DRM_DEBUG_KMS("force priority to high\n");
1380 }
8e36f9d3 1381 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
aaa36a97
AD		 1382 }
1383
1384 /* select wm A */
1385 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1386 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1387 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1388 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1389 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1390 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1391 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1392 /* select wm B */
1393 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1394 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1395 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
be9fd2e9 1396 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
aaa36a97
AD		 1397 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1398 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1399 /* restore original selection */
1400 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1401
1402 /* save values for DPM */
1403 amdgpu_crtc->line_time = line_time;
1404 amdgpu_crtc->wm_high = latency_watermark_a;
1405 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1406 /* Save number of lines the linebuffer leads before the scanout */
1407 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
aaa36a97
AD		 1408}
1409
1410/**
1411 * dce_v10_0_bandwidth_update - program display watermarks
1412 *
1413 * @adev: amdgpu_device pointer
1414 *
1415 * Calculate and program the display watermarks and line
1416 * buffer allocation (CIK).
1417 */
1418static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1419{
1420 struct drm_display_mode *mode = NULL;
1421 u32 num_heads = 0, lb_size;
1422 int i;
1423
1424 amdgpu_update_display_priority(adev);
1425
1426 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1427 if (adev->mode_info.crtcs[i]->base.enabled)
1428 num_heads++;
1429 }
1430 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1431 mode = &adev->mode_info.crtcs[i]->base.mode;
1432 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1433 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1434 lb_size, num_heads);
1435 }
1436}
1437
1438static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1439{
1440 int i;
1441 u32 offset, tmp;
1442
1443 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1444 offset = adev->mode_info.audio.pin[i].offset;
1445 tmp = RREG32_AUDIO_ENDPT(offset,
1446 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1447 if (((tmp &
1448 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1449 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1450 adev->mode_info.audio.pin[i].connected = false;
1451 else
1452 adev->mode_info.audio.pin[i].connected = true;
1453 }
1454}
1455
1456static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1457{
1458 int i;
1459
1460 dce_v10_0_audio_get_connected_pins(adev);
1461
1462 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1463 if (adev->mode_info.audio.pin[i].connected)
1464 return &adev->mode_info.audio.pin[i];
1465 }
1466 DRM_ERROR("No connected audio pins found!\n");
1467 return NULL;
1468}
1469
1470static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1471{
1472 struct amdgpu_device *adev = encoder->dev->dev_private;
1473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1475 u32 tmp;
1476
1477 if (!dig || !dig->afmt || !dig->afmt->pin)
1478 return;
1479
1480 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1481 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1482 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1483}
1484
1485static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1486 struct drm_display_mode *mode)
1487{
1488 struct amdgpu_device *adev = encoder->dev->dev_private;
1489 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1490 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1491 struct drm_connector *connector;
1492 struct amdgpu_connector *amdgpu_connector = NULL;
1493 u32 tmp;
1494 int interlace = 0;
1495
1496 if (!dig || !dig->afmt || !dig->afmt->pin)
1497 return;
1498
1499 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1500 if (connector->encoder == encoder) {
1501 amdgpu_connector = to_amdgpu_connector(connector);
1502 break;
1503 }
1504 }
1505
1506 if (!amdgpu_connector) {
1507 DRM_ERROR("Couldn't find encoder's connector\n");
1508 return;
1509 }
1510
1511 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1512 interlace = 1;
1513 if (connector->latency_present[interlace]) {
1514 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1515 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1516 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1517 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1518 } else {
1519 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1520 VIDEO_LIPSYNC, 0);
1521 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1522 AUDIO_LIPSYNC, 0);
1523 }
1524 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1525 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1526}
1527
1528static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1529{
1530 struct amdgpu_device *adev = encoder->dev->dev_private;
1531 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1532 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1533 struct drm_connector *connector;
1534 struct amdgpu_connector *amdgpu_connector = NULL;
1535 u32 tmp;
1536 u8 *sadb = NULL;
1537 int sad_count;
1538
1539 if (!dig || !dig->afmt || !dig->afmt->pin)
1540 return;
1541
1542 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1543 if (connector->encoder == encoder) {
1544 amdgpu_connector = to_amdgpu_connector(connector);
1545 break;
1546 }
1547 }
1548
1549 if (!amdgpu_connector) {
1550 DRM_ERROR("Couldn't find encoder's connector\n");
1551 return;
1552 }
1553
1554 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1555 if (sad_count < 0) {
1556 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1557 sad_count = 0;
1558 }
1559
1560 /* program the speaker allocation */
1561 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1562 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1563 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1564 DP_CONNECTION, 0);
1565 /* set HDMI mode */
1566 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1567 HDMI_CONNECTION, 1);
1568 if (sad_count)
1569 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1570 SPEAKER_ALLOCATION, sadb[0]);
1571 else
1572 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1573 SPEAKER_ALLOCATION, 5); /* stereo */
1574 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1575 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1576
1577 kfree(sadb);
1578}
1579
1580static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1581{
1582 struct amdgpu_device *adev = encoder->dev->dev_private;
1583 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1584 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1585 struct drm_connector *connector;
1586 struct amdgpu_connector *amdgpu_connector = NULL;
1587 struct cea_sad *sads;
1588 int i, sad_count;
1589
1590 static const u16 eld_reg_to_type[][2] = {
1591 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1592 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1593 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1594 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1595 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1596 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1597 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1598 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1599 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1600 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1601 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1602 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1603 };
1604
1605 if (!dig || !dig->afmt || !dig->afmt->pin)
1606 return;
1607
1608 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1609 if (connector->encoder == encoder) {
1610 amdgpu_connector = to_amdgpu_connector(connector);
1611 break;
1612 }
1613 }
1614
1615 if (!amdgpu_connector) {
1616 DRM_ERROR("Couldn't find encoder's connector\n");
1617 return;
1618 }
1619
1620 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1621 if (sad_count <= 0) {
1622 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1623 return;
1624 }
1625 BUG_ON(!sads);
1626
1627 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1628 u32 tmp = 0;
1629 u8 stereo_freqs = 0;
1630 int max_channels = -1;
1631 int j;
1632
1633 for (j = 0; j < sad_count; j++) {
1634 struct cea_sad *sad = &sads[j];
1635
1636 if (sad->format == eld_reg_to_type[i][1]) {
1637 if (sad->channels > max_channels) {
1638 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1639 MAX_CHANNELS, sad->channels);
1640 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1641 DESCRIPTOR_BYTE_2, sad->byte2);
1642 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1643 SUPPORTED_FREQUENCIES, sad->freq);
1644 max_channels = sad->channels;
1645 }
1646
1647 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1648 stereo_freqs |= sad->freq;
1649 else
1650 break;
1651 }
1652 }
1653
1654 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1655 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1656 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1657 }
1658
1659 kfree(sads);
1660}
1661
1662static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1663 struct amdgpu_audio_pin *pin,
1664 bool enable)
1665{
1666 if (!pin)
1667 return;
1668
1669 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1670 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1671}
1672
1673static const u32 pin_offsets[] =
1674{
1675 AUD0_REGISTER_OFFSET,
1676 AUD1_REGISTER_OFFSET,
1677 AUD2_REGISTER_OFFSET,
1678 AUD3_REGISTER_OFFSET,
1679 AUD4_REGISTER_OFFSET,
1680 AUD5_REGISTER_OFFSET,
1681 AUD6_REGISTER_OFFSET,
1682};
1683
1684static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1685{
1686 int i;
1687
1688 if (!amdgpu_audio)
1689 return 0;
1690
1691 adev->mode_info.audio.enabled = true;
1692
1693 adev->mode_info.audio.num_pins = 7;
1694
1695 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1696 adev->mode_info.audio.pin[i].channels = -1;
1697 adev->mode_info.audio.pin[i].rate = -1;
1698 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1699 adev->mode_info.audio.pin[i].status_bits = 0;
1700 adev->mode_info.audio.pin[i].category_code = 0;
1701 adev->mode_info.audio.pin[i].connected = false;
1702 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1703 adev->mode_info.audio.pin[i].id = i;
1704 /* disable audio. it will be set up later */
1705 /* XXX remove once we switch to ip funcs */
1706 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1707 }
1708
1709 return 0;
1710}
1711
1712static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1713{
1714 int i;
1715
441ce96f
TSD		 1716 if (!amdgpu_audio)
1717 return;
1718
aaa36a97
AD		 1719 if (!adev->mode_info.audio.enabled)
1720 return;
1721
1722 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1723 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1724
1725 adev->mode_info.audio.enabled = false;
1726}
1727
1728/*
1729 * update the N and CTS parameters for a given pixel clock rate
1730 */
1731static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1732{
1733 struct drm_device *dev = encoder->dev;
1734 struct amdgpu_device *adev = dev->dev_private;
1735 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1736 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1737 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1738 u32 tmp;
1739
1740 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1741 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1742 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1743 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1744 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1745 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1746
1747 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1748 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1749 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1750 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1751 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1752 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1753
1754 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1755 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1756 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1757 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1758 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1759 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1760
1761}
1762
1763/*
1764 * build a HDMI Video Info Frame
1765 */
1766static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1767 void *buffer, size_t size)
1768{
1769 struct drm_device *dev = encoder->dev;
1770 struct amdgpu_device *adev = dev->dev_private;
1771 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1772 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1773 uint8_t *frame = buffer + 3;
1774 uint8_t *header = buffer;
1775
1776 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1777 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1778 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1779 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1780 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1781 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1782 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1783 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1784}
1785
1786static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1787{
1788 struct drm_device *dev = encoder->dev;
1789 struct amdgpu_device *adev = dev->dev_private;
1790 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1791 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1792 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1793 u32 dto_phase = 24 * 1000;
1794 u32 dto_modulo = clock;
1795 u32 tmp;
1796
1797 if (!dig || !dig->afmt)
1798 return;
1799
1800 /* XXX two dtos; generally use dto0 for hdmi */
1801 /* Express [24MHz / target pixel clock] as an exact rational
1802 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1803 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1804 */
1805 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1806 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1807 amdgpu_crtc->crtc_id);
1808 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1809 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1810 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1811}
1812
1813/*
1814 * update the info frames with the data from the current display mode
1815 */
1816static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1817 struct drm_display_mode *mode)
1818{
1819 struct drm_device *dev = encoder->dev;
1820 struct amdgpu_device *adev = dev->dev_private;
1821 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1822 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1823 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1824 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1825 struct hdmi_avi_infoframe frame;
1826 ssize_t err;
1827 u32 tmp;
1828 int bpc = 8;
1829
1830 if (!dig || !dig->afmt)
1831 return;
1832
1833 /* Silent, r600_hdmi_enable will raise WARN for us */
1834 if (!dig->afmt->enabled)
1835 return;
1836
1837 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1838 if (encoder->crtc) {
1839 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1840 bpc = amdgpu_crtc->bpc;
1841 }
1842
1843 /* disable audio prior to setting up hw */
1844 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1845 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1846
1847 dce_v10_0_audio_set_dto(encoder, mode->clock);
1848
1849 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1850 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1851 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1852
1853 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1854
1855 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1856 switch (bpc) {
1857 case 0:
1858 case 6:
1859 case 8:
1860 case 16:
1861 default:
1862 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1863 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1864 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1865 connector->name, bpc);
1866 break;
1867 case 10:
1868 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1869 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1870 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1871 connector->name);
1872 break;
1873 case 12:
1874 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1875 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1876 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1877 connector->name);
1878 break;
1879 }
1880 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1881
1882 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1883 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1884 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1885 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1886 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1887
1888 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1889 /* enable audio info frames (frames won't be set until audio is enabled) */
1890 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1891 /* required for audio info values to be updated */
1892 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1893 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1894
1895 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1896 /* required for audio info values to be updated */
1897 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1898 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1899
1900 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1901 /* anything other than 0 */
1902 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1903 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1904
1905 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1906
1907 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1908 /* set the default audio delay */
1909 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1910 /* should be suffient for all audio modes and small enough for all hblanks */
1911 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1912 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1913
1914 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1915 /* allow 60958 channel status fields to be updated */
1916 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1917 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1918
1919 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1920 if (bpc > 8)
1921 /* clear SW CTS value */
1922 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1923 else
1924 /* select SW CTS value */
1925 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1926 /* allow hw to sent ACR packets when required */
1927 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1928 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1929
1930 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1931
1932 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1933 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1934 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1935
1936 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1937 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1938 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1939
1940 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1941 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1942 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1943 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1944 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1945 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1946 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1947 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1948
1949 dce_v10_0_audio_write_speaker_allocation(encoder);
1950
1951 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1952 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1953
1954 dce_v10_0_afmt_audio_select_pin(encoder);
1955 dce_v10_0_audio_write_sad_regs(encoder);
1956 dce_v10_0_audio_write_latency_fields(encoder, mode);
1957
1958 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1959 if (err < 0) {
1960 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1961 return;
1962 }
1963
1964 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1965 if (err < 0) {
1966 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1967 return;
1968 }
1969
1970 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1971
1972 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1973 /* enable AVI info frames */
1974 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1975 /* required for audio info values to be updated */
1976 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1977 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1978
1979 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1980 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1981 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1982
1983 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1984 /* send audio packets */
1985 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1986 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1987
1988 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1989 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1990 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1991 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1992
1993 /* enable audio after to setting up hw */
1994 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1995}
1996
1997static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1998{
1999 struct drm_device *dev = encoder->dev;
2000 struct amdgpu_device *adev = dev->dev_private;
2001 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2002 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2003
2004 if (!dig || !dig->afmt)
2005 return;
2006
2007 /* Silent, r600_hdmi_enable will raise WARN for us */
2008 if (enable && dig->afmt->enabled)
2009 return;
2010 if (!enable && !dig->afmt->enabled)
2011 return;
2012
2013 if (!enable && dig->afmt->pin) {
2014 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
2015 dig->afmt->pin = NULL;
2016 }
2017
2018 dig->afmt->enabled = enable;
2019
2020 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2021 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2022}
2023
720a6ce3 2024static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
aaa36a97
AD		 2025{
2026 int i;
2027
2028 for (i = 0; i < adev->mode_info.num_dig; i++)
2029 adev->mode_info.afmt[i] = NULL;
2030
2031 /* DCE10 has audio blocks tied to DIG encoders */
2032 for (i = 0; i < adev->mode_info.num_dig; i++) {
2033 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2034 if (adev->mode_info.afmt[i]) {
2035 adev->mode_info.afmt[i]->offset = dig_offsets[i];
2036 adev->mode_info.afmt[i]->id = i;
720a6ce3
TSD		 2037 } else {
2038 int j;
2039 for (j = 0; j < i; j++) {
2040 kfree(adev->mode_info.afmt[j]);
2041 adev->mode_info.afmt[j] = NULL;
2042 }
2043 return -ENOMEM;
aaa36a97
AD		 2044 }
2045 }
720a6ce3 2046 return 0;
aaa36a97
AD		 2047}
2048
2049static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
2050{
2051 int i;
2052
2053 for (i = 0; i < adev->mode_info.num_dig; i++) {
2054 kfree(adev->mode_info.afmt[i]);
2055 adev->mode_info.afmt[i] = NULL;
2056 }
2057}
2058
2059static const u32 vga_control_regs[6] =
2060{
2061 mmD1VGA_CONTROL,
2062 mmD2VGA_CONTROL,
2063 mmD3VGA_CONTROL,
2064 mmD4VGA_CONTROL,
2065 mmD5VGA_CONTROL,
2066 mmD6VGA_CONTROL,
2067};
2068
2069static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2070{
2071 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2072 struct drm_device *dev = crtc->dev;
2073 struct amdgpu_device *adev = dev->dev_private;
2074 u32 vga_control;
2075
2076 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2077 if (enable)
2078 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2079 else
2080 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2081}
2082
2083static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2084{
2085 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2086 struct drm_device *dev = crtc->dev;
2087 struct amdgpu_device *adev = dev->dev_private;
2088
2089 if (enable)
2090 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2091 else
2092 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2093}
2094
aaa36a97
AD		 2095static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2096 struct drm_framebuffer *fb,
2097 int x, int y, int atomic)
2098{
2099 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2100 struct drm_device *dev = crtc->dev;
2101 struct amdgpu_device *adev = dev->dev_private;
2102 struct amdgpu_framebuffer *amdgpu_fb;
2103 struct drm_framebuffer *target_fb;
2104 struct drm_gem_object *obj;
2105 struct amdgpu_bo *rbo;
2106 uint64_t fb_location, tiling_flags;
2107 uint32_t fb_format, fb_pitch_pixels;
aaa36a97 2108 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
fbd76d59 2109 u32 pipe_config;
aaa36a97
AD		 2110 u32 tmp, viewport_w, viewport_h;
2111 int r;
2112 bool bypass_lut = false;
d3828147 2113 char *format_name;
aaa36a97
AD		 2114
2115 /* no fb bound */
2116 if (!atomic && !crtc->primary->fb) {
2117 DRM_DEBUG_KMS("No FB bound\n");
2118 return 0;
2119 }
2120
2121 if (atomic) {
2122 amdgpu_fb = to_amdgpu_framebuffer(fb);
2123 target_fb = fb;
849dc32b 2124 } else {
aaa36a97
AD		 2125 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2126 target_fb = crtc->primary->fb;
2127 }
2128
2129 /* If atomic, assume fb object is pinned & idle & fenced and
2130 * just update base pointers
2131 */
2132 obj = amdgpu_fb->obj;
2133 rbo = gem_to_amdgpu_bo(obj);
2134 r = amdgpu_bo_reserve(rbo, false);
2135 if (unlikely(r != 0))
2136 return r;
2137
849dc32b 2138 if (atomic) {
aaa36a97 2139 fb_location = amdgpu_bo_gpu_offset(rbo);
849dc32b 2140 } else {
aaa36a97
AD		 2141 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2142 if (unlikely(r != 0)) {
2143 amdgpu_bo_unreserve(rbo);
2144 return -EINVAL;
2145 }
2146 }
2147
2148 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2149 amdgpu_bo_unreserve(rbo);
2150
fbd76d59
MO		 2151 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2152
aaa36a97
AD		 2153 switch (target_fb->pixel_format) {
2154 case DRM_FORMAT_C8:
2155 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2156 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2157 break;
2158 case DRM_FORMAT_XRGB4444:
2159 case DRM_FORMAT_ARGB4444:
2160 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2162#ifdef __BIG_ENDIAN
2163 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2164 ENDIAN_8IN16);
2165#endif
2166 break;
2167 case DRM_FORMAT_XRGB1555:
2168 case DRM_FORMAT_ARGB1555:
2169 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2170 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2171#ifdef __BIG_ENDIAN
2172 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2173 ENDIAN_8IN16);
2174#endif
2175 break;
2176 case DRM_FORMAT_BGRX5551:
2177 case DRM_FORMAT_BGRA5551:
2178 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2179 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2180#ifdef __BIG_ENDIAN
2181 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2182 ENDIAN_8IN16);
2183#endif
2184 break;
2185 case DRM_FORMAT_RGB565:
2186 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2188#ifdef __BIG_ENDIAN
2189 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2190 ENDIAN_8IN16);
2191#endif
2192 break;
2193 case DRM_FORMAT_XRGB8888:
2194 case DRM_FORMAT_ARGB8888:
2195 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2196 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2197#ifdef __BIG_ENDIAN
2198 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2199 ENDIAN_8IN32);
2200#endif
2201 break;
2202 case DRM_FORMAT_XRGB2101010:
2203 case DRM_FORMAT_ARGB2101010:
2204 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2205 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2206#ifdef __BIG_ENDIAN
2207 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2208 ENDIAN_8IN32);
2209#endif
2210 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2211 bypass_lut = true;
2212 break;
2213 case DRM_FORMAT_BGRX1010102:
2214 case DRM_FORMAT_BGRA1010102:
2215 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2216 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2217#ifdef __BIG_ENDIAN
2218 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2219 ENDIAN_8IN32);
2220#endif
2221 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2222 bypass_lut = true;
2223 break;
2224 default:
90844f00
EE		 2225 format_name = drm_get_format_name(target_fb->pixel_format);
2226 DRM_ERROR("Unsupported screen format %s\n", format_name);
2227 kfree(format_name);
aaa36a97
AD		 2228 return -EINVAL;
2229 }
2230
fbd76d59
MO		 2231 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2232 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
aaa36a97 2233
fbd76d59
MO		 2234 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2235 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2236 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2237 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2238 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
aaa36a97 2239
aaa36a97
AD		 2240 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2241 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2242 ARRAY_2D_TILED_THIN1);
2243 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2244 tile_split);
2245 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2246 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2247 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2248 mtaspect);
2249 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2250 ADDR_SURF_MICRO_TILING_DISPLAY);
fbd76d59 2251 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
aaa36a97
AD		 2252 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2253 ARRAY_1D_TILED_THIN1);
2254 }
2255
aaa36a97
AD		 2256 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2257 pipe_config);
2258
2259 dce_v10_0_vga_enable(crtc, false);
2260
cb9e59d7
AD		 2261 /* Make sure surface address is updated at vertical blank rather than
2262 * horizontal blank
2263 */
2264 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2265 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2266 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2267 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2268
aaa36a97
AD		 2269 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2270 upper_32_bits(fb_location));
2271 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2272 upper_32_bits(fb_location));
2273 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2274 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2275 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2276 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2277 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2278 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2279
2280 /*
2281 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2282 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2283 * retain the full precision throughout the pipeline.
2284 */
2285 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2286 if (bypass_lut)
2287 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2288 else
2289 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2290 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2291
2292 if (bypass_lut)
2293 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2294
2295 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2296 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2297 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2298 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2299 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2300 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2301
2302 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2303 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2304
2305 dce_v10_0_grph_enable(crtc, true);
2306
2307 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2308 target_fb->height);
2309
2310 x &= ~3;
2311 y &= ~1;
2312 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2313 (x << 16) | y);
2314 viewport_w = crtc->mode.hdisplay;
2315 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2316 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2317 (viewport_w << 16) | viewport_h);
2318
3fd4b751
MD		 2319 /* set pageflip to happen anywhere in vblank interval */
2320 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
aaa36a97
AD		 2321
2322 if (!atomic && fb && fb != crtc->primary->fb) {
2323 amdgpu_fb = to_amdgpu_framebuffer(fb);
2324 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2325 r = amdgpu_bo_reserve(rbo, false);
2326 if (unlikely(r != 0))
2327 return r;
2328 amdgpu_bo_unpin(rbo);
2329 amdgpu_bo_unreserve(rbo);
2330 }
2331
2332 /* Bytes per pixel may have changed */
2333 dce_v10_0_bandwidth_update(adev);
2334
2335 return 0;
2336}
2337
2338static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2339 struct drm_display_mode *mode)
2340{
2341 struct drm_device *dev = crtc->dev;
2342 struct amdgpu_device *adev = dev->dev_private;
2343 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344 u32 tmp;
2345
2346 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2348 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2349 else
2350 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2351 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2352}
2353
2354static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2355{
2356 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2357 struct drm_device *dev = crtc->dev;
2358 struct amdgpu_device *adev = dev->dev_private;
2359 int i;
2360 u32 tmp;
2361
2362 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2363
2364 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2365 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2366 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2367 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2368
2369 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2370 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2371 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2372
2373 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2374 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2375 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2376
2377 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2378 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2379 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2380 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2381
2382 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2383
2384 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2385 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2386 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2387
2388 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2389 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2390 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2391
2392 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2393 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2394
2395 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2396 for (i = 0; i < 256; i++) {
2397 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2398 (amdgpu_crtc->lut_r[i] << 20) |
2399 (amdgpu_crtc->lut_g[i] << 10) |
2400 (amdgpu_crtc->lut_b[i] << 0));
2401 }
2402
2403 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2404 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2405 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2406 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2407 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2408
2409 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2410 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2411 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2412 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2413
2414 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2415 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2416 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2417 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2418
2419 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2420 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2421 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2422 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2423
2424 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2425 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2426 /* XXX this only needs to be programmed once per crtc at startup,
2427 * not sure where the best place for it is
2428 */
2429 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2430 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2431 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2432}
2433
2434static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2435{
2436 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2437 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2438
2439 switch (amdgpu_encoder->encoder_id) {
2440 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2441 if (dig->linkb)
2442 return 1;
2443 else
2444 return 0;
2445 break;
2446 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2447 if (dig->linkb)
2448 return 3;
2449 else
2450 return 2;
2451 break;
2452 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2453 if (dig->linkb)
2454 return 5;
2455 else
2456 return 4;
2457 break;
2458 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2459 return 6;
2460 break;
2461 default:
2462 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2463 return 0;
2464 }
2465}
2466
2467/**
2468 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2469 *
2470 * @crtc: drm crtc
2471 *
2472 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2473 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2474 * monitors a dedicated PPLL must be used. If a particular board has
2475 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2476 * as there is no need to program the PLL itself. If we are not able to
2477 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2478 * avoid messing up an existing monitor.
2479 *
2480 * Asic specific PLL information
2481 *
2482 * DCE 10.x
2483 * Tonga
2484 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2485 * CI
2486 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2487 *
2488 */
2489static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2490{
2491 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2492 struct drm_device *dev = crtc->dev;
2493 struct amdgpu_device *adev = dev->dev_private;
2494 u32 pll_in_use;
2495 int pll;
2496
2497 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2498 if (adev->clock.dp_extclk)
2499 /* skip PPLL programming if using ext clock */
2500 return ATOM_PPLL_INVALID;
2501 else {
2502 /* use the same PPLL for all DP monitors */
2503 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2504 if (pll != ATOM_PPLL_INVALID)
2505 return pll;
2506 }
2507 } else {
2508 /* use the same PPLL for all monitors with the same clock */
2509 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2510 if (pll != ATOM_PPLL_INVALID)
2511 return pll;
2512 }
2513
2514 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2515 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2516 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2517 return ATOM_PPLL2;
2518 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2519 return ATOM_PPLL1;
2520 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2521 return ATOM_PPLL0;
2522 DRM_ERROR("unable to allocate a PPLL\n");
2523 return ATOM_PPLL_INVALID;
2524}
2525
2526static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2527{
2528 struct amdgpu_device *adev = crtc->dev->dev_private;
2529 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2530 uint32_t cur_lock;
2531
2532 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2533 if (lock)
2534 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2535 else
2536 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2537 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2538}
2539
2540static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2541{
2542 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2543 struct amdgpu_device *adev = crtc->dev->dev_private;
2544 u32 tmp;
2545
2546 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2547 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2548 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2549}
2550
2551static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2552{
2553 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2554 struct amdgpu_device *adev = crtc->dev->dev_private;
2555 u32 tmp;
2556
3c681718
AD		 2557 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2558 upper_32_bits(amdgpu_crtc->cursor_addr));
2559 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2560 lower_32_bits(amdgpu_crtc->cursor_addr));
2561
aaa36a97
AD		 2562 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2563 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2564 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2565 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2566}
2567
29275a9b
AD		 2568static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2569 int x, int y)
aaa36a97
AD		 2570{
2571 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2572 struct amdgpu_device *adev = crtc->dev->dev_private;
2573 int xorigin = 0, yorigin = 0;
2574
2575 /* avivo cursor are offset into the total surface */
2576 x += crtc->x;
2577 y += crtc->y;
2578 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2579
2580 if (x < 0) {
2581 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2582 x = 0;
2583 }
2584 if (y < 0) {
2585 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2586 y = 0;
2587 }
2588
aaa36a97
AD		 2589 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2590 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2591 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2592 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
29275a9b
AD		 2593
2594 amdgpu_crtc->cursor_x = x;
2595 amdgpu_crtc->cursor_y = y;
aaa36a97
AD		 2596
2597 return 0;
2598}
2599
29275a9b
AD		 2600static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2601 int x, int y)
2602{
2603 int ret;
2604
2605 dce_v10_0_lock_cursor(crtc, true);
2606 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2607 dce_v10_0_lock_cursor(crtc, false);
2608
2609 return ret;
2610}
2611
2612static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2613 struct drm_file *file_priv,
2614 uint32_t handle,
2615 uint32_t width,
2616 uint32_t height,
2617 int32_t hot_x,
2618 int32_t hot_y)
aaa36a97
AD		 2619{
2620 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2621 struct drm_gem_object *obj;
f9242d1b 2622 struct amdgpu_bo *aobj;
aaa36a97
AD		 2623 int ret;
2624
2625 if (!handle) {
2626 /* turn off cursor */
2627 dce_v10_0_hide_cursor(crtc);
2628 obj = NULL;
2629 goto unpin;
2630 }
2631
2632 if ((width > amdgpu_crtc->max_cursor_width) ||
2633 (height > amdgpu_crtc->max_cursor_height)) {
2634 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2635 return -EINVAL;
2636 }
2637
a8ad0bd8 2638 obj = drm_gem_object_lookup(file_priv, handle);
aaa36a97
AD		 2639 if (!obj) {
2640 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2641 return -ENOENT;
2642 }
2643
f9242d1b
AD		 2644 aobj = gem_to_amdgpu_bo(obj);
2645 ret = amdgpu_bo_reserve(aobj, false);
2646 if (ret != 0) {
2647 drm_gem_object_unreference_unlocked(obj);
2648 return ret;
2649 }
2650
2651 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2652 amdgpu_bo_unreserve(aobj);
2653 if (ret) {
2654 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2655 drm_gem_object_unreference_unlocked(obj);
2656 return ret;
2657 }
aaa36a97
AD		 2658
2659 amdgpu_crtc->cursor_width = width;
2660 amdgpu_crtc->cursor_height = height;
2661
2662 dce_v10_0_lock_cursor(crtc, true);
ef67e38c
AD		 2663
2664 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2665 hot_y != amdgpu_crtc->cursor_hot_y) {
2666 int x, y;
2667
2668 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2669 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2670
2671 dce_v10_0_cursor_move_locked(crtc, x, y);
2672
2673 amdgpu_crtc->cursor_hot_x = hot_x;
2674 amdgpu_crtc->cursor_hot_y = hot_y;
2675 }
2676
aaa36a97
AD		 2677 dce_v10_0_show_cursor(crtc);
2678 dce_v10_0_lock_cursor(crtc, false);
2679
2680unpin:
2681 if (amdgpu_crtc->cursor_bo) {
dd0b5d2f
AD		 2682 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2683 ret = amdgpu_bo_reserve(aobj, false);
aaa36a97 2684 if (likely(ret == 0)) {
dd0b5d2f
AD		 2685 amdgpu_bo_unpin(aobj);
2686 amdgpu_bo_unreserve(aobj);
aaa36a97
AD		 2687 }
2688 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2689 }
2690
2691 amdgpu_crtc->cursor_bo = obj;
2692 return 0;
dd0b5d2f 2693}
aaa36a97 2694
dd0b5d2f
AD		 2695static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2696{
2697 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
dd0b5d2f
AD		 2698
2699 if (amdgpu_crtc->cursor_bo) {
2700 dce_v10_0_lock_cursor(crtc, true);
2701
2702 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2703 amdgpu_crtc->cursor_y);
2704
f9242d1b 2705 dce_v10_0_show_cursor(crtc);
dd0b5d2f
AD		 2706
2707 dce_v10_0_lock_cursor(crtc, false);
2708 }
aaa36a97
AD		 2709}
2710
7ea77283
ML		 2711static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2712 u16 *blue, uint32_t size)
aaa36a97
AD		 2713{
2714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7ea77283 2715 int i;
aaa36a97
AD		 2716
2717 /* userspace palettes are always correct as is */
7ea77283 2718 for (i = 0; i < size; i++) {
aaa36a97
AD		 2719 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2720 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2721 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2722 }
2723 dce_v10_0_crtc_load_lut(crtc);
7ea77283
ML		 2724
2725 return 0;
aaa36a97
AD		 2726}
2727
2728static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2729{
2730 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2731
2732 drm_crtc_cleanup(crtc);
aaa36a97
AD		 2733 kfree(amdgpu_crtc);
2734}
2735
2736static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
29275a9b 2737 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
aaa36a97
AD		 2738 .cursor_move = dce_v10_0_crtc_cursor_move,
2739 .gamma_set = dce_v10_0_crtc_gamma_set,
2740 .set_config = amdgpu_crtc_set_config,
2741 .destroy = dce_v10_0_crtc_destroy,
325cbba1 2742 .page_flip_target = amdgpu_crtc_page_flip_target,
aaa36a97
AD		 2743};
2744
2745static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2746{
2747 struct drm_device *dev = crtc->dev;
2748 struct amdgpu_device *adev = dev->dev_private;
2749 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5e6775ab 2750 unsigned type;
aaa36a97
AD		 2751
2752 switch (mode) {
2753 case DRM_MODE_DPMS_ON:
2754 amdgpu_crtc->enabled = true;
2755 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2756 dce_v10_0_vga_enable(crtc, true);
2757 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2758 dce_v10_0_vga_enable(crtc, false);
f6c7aba4 2759 /* Make sure VBLANK and PFLIP interrupts are still enabled */
5e6775ab
MD		 2760 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2761 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2762 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
9a7841e9 2763 drm_crtc_vblank_on(crtc);
aaa36a97
AD		 2764 dce_v10_0_crtc_load_lut(crtc);
2765 break;
2766 case DRM_MODE_DPMS_STANDBY:
2767 case DRM_MODE_DPMS_SUSPEND:
2768 case DRM_MODE_DPMS_OFF:
9a7841e9 2769 drm_crtc_vblank_off(crtc);
aaa36a97
AD		 2770 if (amdgpu_crtc->enabled) {
2771 dce_v10_0_vga_enable(crtc, true);
2772 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2773 dce_v10_0_vga_enable(crtc, false);
2774 }
2775 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2776 amdgpu_crtc->enabled = false;
2777 break;
2778 }
2779 /* adjust pm to dpms */
2780 amdgpu_pm_compute_clocks(adev);
2781}
2782
2783static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2784{
2785 /* disable crtc pair power gating before programming */
2786 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2787 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2788 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2789}
2790
2791static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2792{
2793 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2794 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2795}
2796
2797static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2798{
2799 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2800 struct drm_device *dev = crtc->dev;
2801 struct amdgpu_device *adev = dev->dev_private;
2802 struct amdgpu_atom_ss ss;
2803 int i;
2804
2805 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2806 if (crtc->primary->fb) {
2807 int r;
2808 struct amdgpu_framebuffer *amdgpu_fb;
2809 struct amdgpu_bo *rbo;
2810
2811 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2812 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2813 r = amdgpu_bo_reserve(rbo, false);
2814 if (unlikely(r))
2815 DRM_ERROR("failed to reserve rbo before unpin\n");
2816 else {
2817 amdgpu_bo_unpin(rbo);
2818 amdgpu_bo_unreserve(rbo);
2819 }
2820 }
2821 /* disable the GRPH */
2822 dce_v10_0_grph_enable(crtc, false);
2823
2824 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2825
2826 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2827 if (adev->mode_info.crtcs[i] &&
2828 adev->mode_info.crtcs[i]->enabled &&
2829 i != amdgpu_crtc->crtc_id &&
2830 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2831 /* one other crtc is using this pll don't turn
2832 * off the pll
2833 */
2834 goto done;
2835 }
2836 }
2837
2838 switch (amdgpu_crtc->pll_id) {
2839 case ATOM_PPLL0:
2840 case ATOM_PPLL1:
2841 case ATOM_PPLL2:
2842 /* disable the ppll */
2843 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2844 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2845 break;
2846 default:
2847 break;
2848 }
2849done:
2850 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2851 amdgpu_crtc->adjusted_clock = 0;
2852 amdgpu_crtc->encoder = NULL;
2853 amdgpu_crtc->connector = NULL;
2854}
2855
2856static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2857 struct drm_display_mode *mode,
2858 struct drm_display_mode *adjusted_mode,
2859 int x, int y, struct drm_framebuffer *old_fb)
2860{
2861 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2862
2863 if (!amdgpu_crtc->adjusted_clock)
2864 return -EINVAL;
2865
2866 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2867 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2868 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2869 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2870 amdgpu_atombios_crtc_scaler_setup(crtc);
dd0b5d2f 2871 dce_v10_0_cursor_reset(crtc);
aaa36a97
AD		 2872 /* update the hw version fpr dpm */
2873 amdgpu_crtc->hw_mode = *adjusted_mode;
2874
2875 return 0;
2876}
2877
2878static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2879 const struct drm_display_mode *mode,
2880 struct drm_display_mode *adjusted_mode)
2881{
2882 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2883 struct drm_device *dev = crtc->dev;
2884 struct drm_encoder *encoder;
2885
2886 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2887 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2888 if (encoder->crtc == crtc) {
2889 amdgpu_crtc->encoder = encoder;
2890 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2891 break;
2892 }
2893 }
2894 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2895 amdgpu_crtc->encoder = NULL;
2896 amdgpu_crtc->connector = NULL;
2897 return false;
2898 }
2899 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2900 return false;
2901 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2902 return false;
2903 /* pick pll */
2904 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2905 /* if we can't get a PPLL for a non-DP encoder, fail */
2906 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2907 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2908 return false;
2909
2910 return true;
2911}
2912
2913static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2914 struct drm_framebuffer *old_fb)
2915{
2916 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2917}
2918
2919static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2920 struct drm_framebuffer *fb,
2921 int x, int y, enum mode_set_atomic state)
2922{
2923 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2924}
2925
2926static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2927 .dpms = dce_v10_0_crtc_dpms,
2928 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2929 .mode_set = dce_v10_0_crtc_mode_set,
2930 .mode_set_base = dce_v10_0_crtc_set_base,
2931 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2932 .prepare = dce_v10_0_crtc_prepare,
2933 .commit = dce_v10_0_crtc_commit,
2934 .load_lut = dce_v10_0_crtc_load_lut,
2935 .disable = dce_v10_0_crtc_disable,
2936};
2937
2938static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2939{
2940 struct amdgpu_crtc *amdgpu_crtc;
2941 int i;
2942
2943 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2944 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2945 if (amdgpu_crtc == NULL)
2946 return -ENOMEM;
2947
2948 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2949
2950 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2951 amdgpu_crtc->crtc_id = index;
aaa36a97
AD		 2952 adev->mode_info.crtcs[index] = amdgpu_crtc;
2953
2954 amdgpu_crtc->max_cursor_width = 128;
2955 amdgpu_crtc->max_cursor_height = 128;
2956 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2957 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2958
2959 for (i = 0; i < 256; i++) {
2960 amdgpu_crtc->lut_r[i] = i << 2;
2961 amdgpu_crtc->lut_g[i] = i << 2;
2962 amdgpu_crtc->lut_b[i] = i << 2;
2963 }
2964
2965 switch (amdgpu_crtc->crtc_id) {
2966 case 0:
2967 default:
2968 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2969 break;
2970 case 1:
2971 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2972 break;
2973 case 2:
2974 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2975 break;
2976 case 3:
2977 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2978 break;
2979 case 4:
2980 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2981 break;
2982 case 5:
2983 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2984 break;
2985 }
2986
2987 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2988 amdgpu_crtc->adjusted_clock = 0;
2989 amdgpu_crtc->encoder = NULL;
2990 amdgpu_crtc->connector = NULL;
2991 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2992
2993 return 0;
2994}
2995
5fc3aeeb 2996static int dce_v10_0_early_init(void *handle)
aaa36a97 2997{
5fc3aeeb 2998 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2999
aaa36a97
AD		 3000 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
3001 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
3002
3003 dce_v10_0_set_display_funcs(adev);
3004 dce_v10_0_set_irq_funcs(adev);
3005
83c9b025
ED		 3006 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
3007
aaa36a97 3008 switch (adev->asic_type) {
84390860 3009 case CHIP_FIJI:
aaa36a97 3010 case CHIP_TONGA:
aaa36a97
AD		 3011 adev->mode_info.num_hpd = 6;
3012 adev->mode_info.num_dig = 7;
3013 break;
3014 default:
3015 /* FIXME: not supported yet */
3016 return -EINVAL;
3017 }
3018
3019 return 0;
3020}
3021
5fc3aeeb 3022static int dce_v10_0_sw_init(void *handle)
aaa36a97
AD		 3023{
3024 int r, i;
5fc3aeeb 3025 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3026
3027 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3028 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3029 if (r)
3030 return r;
3031 }
3032
3033 for (i = 8; i < 20; i += 2) {
3034 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3035 if (r)
3036 return r;
3037 }
3038
3039 /* HPD hotplug */
3040 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3041 if (r)
3042 return r;
3043
aaa36a97
AD		 3044 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3045
cb9e59d7
AD		 3046 adev->ddev->mode_config.async_page_flip = true;
3047
aaa36a97
AD		 3048 adev->ddev->mode_config.max_width = 16384;
3049 adev->ddev->mode_config.max_height = 16384;
3050
3051 adev->ddev->mode_config.preferred_depth = 24;
3052 adev->ddev->mode_config.prefer_shadow = 1;
3053
3054 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3055
3056 r = amdgpu_modeset_create_props(adev);
3057 if (r)
3058 return r;
3059
3060 adev->ddev->mode_config.max_width = 16384;
3061 adev->ddev->mode_config.max_height = 16384;
3062
3063 /* allocate crtcs */
3064 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3065 r = dce_v10_0_crtc_init(adev, i);
3066 if (r)
3067 return r;
3068 }
3069
3070 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3071 amdgpu_print_display_setup(adev->ddev);
3072 else
3073 return -EINVAL;
3074
3075 /* setup afmt */
720a6ce3
TSD		 3076 r = dce_v10_0_afmt_init(adev);
3077 if (r)
3078 return r;
aaa36a97
AD		 3079
3080 r = dce_v10_0_audio_init(adev);
3081 if (r)
3082 return r;
3083
3084 drm_kms_helper_poll_init(adev->ddev);
3085
98822a2f
TSD		 3086 adev->mode_info.mode_config_initialized = true;
3087 return 0;
aaa36a97
AD		 3088}
3089
5fc3aeeb 3090static int dce_v10_0_sw_fini(void *handle)
aaa36a97 3091{
5fc3aeeb 3092 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3093
aaa36a97
AD		 3094 kfree(adev->mode_info.bios_hardcoded_edid);
3095
3096 drm_kms_helper_poll_fini(adev->ddev);
3097
3098 dce_v10_0_audio_fini(adev);
3099
3100 dce_v10_0_afmt_fini(adev);
3101
3102 drm_mode_config_cleanup(adev->ddev);
3103 adev->mode_info.mode_config_initialized = false;
3104
3105 return 0;
3106}
3107
5fc3aeeb 3108static int dce_v10_0_hw_init(void *handle)
aaa36a97
AD		 3109{
3110 int i;
5fc3aeeb 3111 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3112
3113 dce_v10_0_init_golden_registers(adev);
3114
3115 /* init dig PHYs, disp eng pll */
3116 amdgpu_atombios_encoder_init_dig(adev);
3117 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3118
3119 /* initialize hpd */
3120 dce_v10_0_hpd_init(adev);
3121
3122 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3123 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3124 }
3125
f6c7aba4
MD		 3126 dce_v10_0_pageflip_interrupt_init(adev);
3127
aaa36a97
AD		 3128 return 0;
3129}
3130
5fc3aeeb 3131static int dce_v10_0_hw_fini(void *handle)
aaa36a97
AD		 3132{
3133 int i;
5fc3aeeb 3134 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3135
3136 dce_v10_0_hpd_fini(adev);
3137
3138 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3139 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3140 }
3141
f6c7aba4
MD		 3142 dce_v10_0_pageflip_interrupt_fini(adev);
3143
aaa36a97
AD		 3144 return 0;
3145}
3146
5fc3aeeb 3147static int dce_v10_0_suspend(void *handle)
aaa36a97 3148{
5fc3aeeb 3149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 3150
aaa36a97
AD		 3151 amdgpu_atombios_scratch_regs_save(adev);
3152
f9fff064 3153 return dce_v10_0_hw_fini(handle);
aaa36a97
AD		 3154}
3155
5fc3aeeb 3156static int dce_v10_0_resume(void *handle)
aaa36a97 3157{
5fc3aeeb 3158 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064 3159 int ret;
aaa36a97 3160
f9fff064 3161 ret = dce_v10_0_hw_init(handle);
aaa36a97
AD		 3162
3163 amdgpu_atombios_scratch_regs_restore(adev);
3164
aaa36a97
AD		 3165 /* turn on the BL */
3166 if (adev->mode_info.bl_encoder) {
3167 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3168 adev->mode_info.bl_encoder);
3169 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3170 bl_level);
3171 }
3172
f9fff064 3173 return ret;
aaa36a97
AD		 3174}
3175
5fc3aeeb 3176static bool dce_v10_0_is_idle(void *handle)
aaa36a97 3177{
aaa36a97
AD		 3178 return true;
3179}
3180
5fc3aeeb 3181static int dce_v10_0_wait_for_idle(void *handle)
aaa36a97 3182{
aaa36a97
AD		 3183 return 0;
3184}
3185
81e04e18
CZ		 3186static int dce_v10_0_check_soft_reset(void *handle)
3187{
3188 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3189
3190 if (dce_v10_0_is_display_hung(adev))
3191 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = true;
3192 else
3193 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = false;
3194
3195 return 0;
3196}
3197
5fc3aeeb 3198static int dce_v10_0_soft_reset(void *handle)
aaa36a97
AD		 3199{
3200 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 3202
81e04e18
CZ		 3203 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang)
3204 return 0;
3205
aaa36a97
AD		 3206 if (dce_v10_0_is_display_hung(adev))
3207 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3208
3209 if (srbm_soft_reset) {
aaa36a97
AD		 3210 tmp = RREG32(mmSRBM_SOFT_RESET);
3211 tmp |= srbm_soft_reset;
3212 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3213 WREG32(mmSRBM_SOFT_RESET, tmp);
3214 tmp = RREG32(mmSRBM_SOFT_RESET);
3215
3216 udelay(50);
3217
3218 tmp &= ~srbm_soft_reset;
3219 WREG32(mmSRBM_SOFT_RESET, tmp);
3220 tmp = RREG32(mmSRBM_SOFT_RESET);
3221
3222 /* Wait a little for things to settle down */
3223 udelay(50);
aaa36a97
AD		 3224 }
3225 return 0;
3226}
3227
3228static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3229 int crtc,
3230 enum amdgpu_interrupt_state state)
3231{
3232 u32 lb_interrupt_mask;
3233
3234 if (crtc >= adev->mode_info.num_crtc) {
3235 DRM_DEBUG("invalid crtc %d\n", crtc);
3236 return;
3237 }
3238
3239 switch (state) {
3240 case AMDGPU_IRQ_STATE_DISABLE:
3241 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3242 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3243 VBLANK_INTERRUPT_MASK, 0);
3244 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3245 break;
3246 case AMDGPU_IRQ_STATE_ENABLE:
3247 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3248 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3249 VBLANK_INTERRUPT_MASK, 1);
3250 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3251 break;
3252 default:
3253 break;
3254 }
3255}
3256
3257static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3258 int crtc,
3259 enum amdgpu_interrupt_state state)
3260{
3261 u32 lb_interrupt_mask;
3262
3263 if (crtc >= adev->mode_info.num_crtc) {
3264 DRM_DEBUG("invalid crtc %d\n", crtc);
3265 return;
3266 }
3267
3268 switch (state) {
3269 case AMDGPU_IRQ_STATE_DISABLE:
3270 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3271 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3272 VLINE_INTERRUPT_MASK, 0);
3273 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3274 break;
3275 case AMDGPU_IRQ_STATE_ENABLE:
3276 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3277 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3278 VLINE_INTERRUPT_MASK, 1);
3279 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3280 break;
3281 default:
3282 break;
3283 }
3284}
3285
3286static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3287 struct amdgpu_irq_src *source,
3288 unsigned hpd,
3289 enum amdgpu_interrupt_state state)
3290{
3291 u32 tmp;
3292
3293 if (hpd >= adev->mode_info.num_hpd) {
3294 DRM_DEBUG("invalid hdp %d\n", hpd);
3295 return 0;
3296 }
3297
3298 switch (state) {
3299 case AMDGPU_IRQ_STATE_DISABLE:
3300 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3301 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3302 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3303 break;
3304 case AMDGPU_IRQ_STATE_ENABLE:
3305 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3306 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3307 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3308 break;
3309 default:
3310 break;
3311 }
3312
3313 return 0;
3314}
3315
3316static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3317 struct amdgpu_irq_src *source,
3318 unsigned type,
3319 enum amdgpu_interrupt_state state)
3320{
3321 switch (type) {
3322 case AMDGPU_CRTC_IRQ_VBLANK1:
3323 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3324 break;
3325 case AMDGPU_CRTC_IRQ_VBLANK2:
3326 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3327 break;
3328 case AMDGPU_CRTC_IRQ_VBLANK3:
3329 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3330 break;
3331 case AMDGPU_CRTC_IRQ_VBLANK4:
3332 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3333 break;
3334 case AMDGPU_CRTC_IRQ_VBLANK5:
3335 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3336 break;
3337 case AMDGPU_CRTC_IRQ_VBLANK6:
3338 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3339 break;
3340 case AMDGPU_CRTC_IRQ_VLINE1:
3341 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3342 break;
3343 case AMDGPU_CRTC_IRQ_VLINE2:
3344 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3345 break;
3346 case AMDGPU_CRTC_IRQ_VLINE3:
3347 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3348 break;
3349 case AMDGPU_CRTC_IRQ_VLINE4:
3350 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3351 break;
3352 case AMDGPU_CRTC_IRQ_VLINE5:
3353 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3354 break;
3355 case AMDGPU_CRTC_IRQ_VLINE6:
3356 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3357 break;
3358 default:
3359 break;
3360 }
3361 return 0;
3362}
3363
3364static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3365 struct amdgpu_irq_src *src,
3366 unsigned type,
3367 enum amdgpu_interrupt_state state)
3368{
7dfac896
AD		 3369 u32 reg;
3370
3371 if (type >= adev->mode_info.num_crtc) {
3372 DRM_ERROR("invalid pageflip crtc %d\n", type);
3373 return -EINVAL;
aaa36a97
AD		 3374 }
3375
7dfac896 3376 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
aaa36a97 3377 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3378 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3379 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97 3380 else
7dfac896
AD		 3381 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3382 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97
AD		 3383
3384 return 0;
3385}
3386
3387static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3388 struct amdgpu_irq_src *source,
3389 struct amdgpu_iv_entry *entry)
3390{
aaa36a97
AD		 3391 unsigned long flags;
3392 unsigned crtc_id;
3393 struct amdgpu_crtc *amdgpu_crtc;
3394 struct amdgpu_flip_work *works;
3395
3396 crtc_id = (entry->src_id - 8) >> 1;
3397 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3398
7dfac896
AD		 3399 if (crtc_id >= adev->mode_info.num_crtc) {
3400 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3401 return -EINVAL;
aaa36a97
AD		 3402 }
3403
7dfac896
AD		 3404 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3405 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3406 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3407 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
aaa36a97
AD		 3408
3409 /* IRQ could occur when in initial stage */
3410 if (amdgpu_crtc == NULL)
3411 return 0;
3412
3413 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3414 works = amdgpu_crtc->pflip_works;
3415 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3416 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3417 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3418 amdgpu_crtc->pflip_status,
3419 AMDGPU_FLIP_SUBMITTED);
3420 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3421 return 0;
3422 }
3423
3424 /* page flip completed. clean up */
3425 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3426 amdgpu_crtc->pflip_works = NULL;
3427
3428 /* wakeup usersapce */
3429 if (works->event)
56286769 3430 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
aaa36a97
AD		 3431
3432 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3433
60629c4d 3434 drm_crtc_vblank_put(&amdgpu_crtc->base);
87d58c11 3435 schedule_work(&works->unpin_work);
aaa36a97
AD		 3436
3437 return 0;
3438}
3439
3440static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3441 int hpd)
3442{
3443 u32 tmp;
3444
3445 if (hpd >= adev->mode_info.num_hpd) {
3446 DRM_DEBUG("invalid hdp %d\n", hpd);
3447 return;
3448 }
3449
3450 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3451 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3452 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3453}
3454
3455static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3456 int crtc)
3457{
3458 u32 tmp;
3459
3460 if (crtc >= adev->mode_info.num_crtc) {
3461 DRM_DEBUG("invalid crtc %d\n", crtc);
3462 return;
3463 }
3464
3465 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3466 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3467 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3468}
3469
3470static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3471 int crtc)
3472{
3473 u32 tmp;
3474
3475 if (crtc >= adev->mode_info.num_crtc) {
3476 DRM_DEBUG("invalid crtc %d\n", crtc);
3477 return;
3478 }
3479
3480 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3481 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3482 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3483}
3484
3485static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3486 struct amdgpu_irq_src *source,
3487 struct amdgpu_iv_entry *entry)
3488{
3489 unsigned crtc = entry->src_id - 1;
3490 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3491 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3492
3493 switch (entry->src_data) {
3494 case 0: /* vblank */
bd833144 3495 if (disp_int & interrupt_status_offsets[crtc].vblank)
aaa36a97 3496 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
bd833144
MK		 3497 else
3498 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3499
3500 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3501 drm_handle_vblank(adev->ddev, crtc);
aaa36a97 3502 }
bd833144
MK		 3503 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3504
aaa36a97
AD		 3505 break;
3506 case 1: /* vline */
bd833144 3507 if (disp_int & interrupt_status_offsets[crtc].vline)
aaa36a97 3508 dce_v10_0_crtc_vline_int_ack(adev, crtc);
bd833144
MK		 3509 else
3510 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3511
3512 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3513
aaa36a97
AD		 3514 break;
3515 default:
3516 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3517 break;
3518 }
3519
3520 return 0;
3521}
3522
3523static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3524 struct amdgpu_irq_src *source,
3525 struct amdgpu_iv_entry *entry)
3526{
3527 uint32_t disp_int, mask;
3528 unsigned hpd;
3529
3530 if (entry->src_data >= adev->mode_info.num_hpd) {
3531 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3532 return 0;
3533 }
3534
3535 hpd = entry->src_data;
3536 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3537 mask = interrupt_status_offsets[hpd].hpd;
3538
3539 if (disp_int & mask) {
3540 dce_v10_0_hpd_int_ack(adev, hpd);
3541 schedule_work(&adev->hotplug_work);
3542 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3543 }
3544
3545 return 0;
3546}
3547
5fc3aeeb 3548static int dce_v10_0_set_clockgating_state(void *handle,
3549 enum amd_clockgating_state state)
aaa36a97
AD		 3550{
3551 return 0;
3552}
3553
5fc3aeeb 3554static int dce_v10_0_set_powergating_state(void *handle,
3555 enum amd_powergating_state state)
aaa36a97
AD		 3556{
3557 return 0;
3558}
3559
5fc3aeeb 3560const struct amd_ip_funcs dce_v10_0_ip_funcs = {
88a907d6 3561 .name = "dce_v10_0",
aaa36a97
AD		 3562 .early_init = dce_v10_0_early_init,
3563 .late_init = NULL,
3564 .sw_init = dce_v10_0_sw_init,
3565 .sw_fini = dce_v10_0_sw_fini,
3566 .hw_init = dce_v10_0_hw_init,
3567 .hw_fini = dce_v10_0_hw_fini,
3568 .suspend = dce_v10_0_suspend,
3569 .resume = dce_v10_0_resume,
3570 .is_idle = dce_v10_0_is_idle,
3571 .wait_for_idle = dce_v10_0_wait_for_idle,
81e04e18 3572 .check_soft_reset = dce_v10_0_check_soft_reset,
aaa36a97 3573 .soft_reset = dce_v10_0_soft_reset,
aaa36a97
AD		 3574 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3575 .set_powergating_state = dce_v10_0_set_powergating_state,
3576};
3577
3578static void
3579dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3580 struct drm_display_mode *mode,
3581 struct drm_display_mode *adjusted_mode)
3582{
3583 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3584
3585 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3586
3587 /* need to call this here rather than in prepare() since we need some crtc info */
3588 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3589
3590 /* set scaler clears this on some chips */
3591 dce_v10_0_set_interleave(encoder->crtc, mode);
3592
3593 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3594 dce_v10_0_afmt_enable(encoder, true);
3595 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3596 }
3597}
3598
3599static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3600{
3601 struct amdgpu_device *adev = encoder->dev->dev_private;
3602 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3603 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3604
3605 if ((amdgpu_encoder->active_device &
3606 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3607 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3608 ENCODER_OBJECT_ID_NONE)) {
3609 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3610 if (dig) {
3611 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3612 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3613 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3614 }
3615 }
3616
3617 amdgpu_atombios_scratch_regs_lock(adev, true);
3618
3619 if (connector) {
3620 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3621
3622 /* select the clock/data port if it uses a router */
3623 if (amdgpu_connector->router.cd_valid)
3624 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3625
3626 /* turn eDP panel on for mode set */
3627 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3628 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3629 ATOM_TRANSMITTER_ACTION_POWER_ON);
3630 }
3631
3632 /* this is needed for the pll/ss setup to work correctly in some cases */
3633 amdgpu_atombios_encoder_set_crtc_source(encoder);
3634 /* set up the FMT blocks */
3635 dce_v10_0_program_fmt(encoder);
3636}
3637
3638static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3639{
3640 struct drm_device *dev = encoder->dev;
3641 struct amdgpu_device *adev = dev->dev_private;
3642
3643 /* need to call this here as we need the crtc set up */
3644 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3645 amdgpu_atombios_scratch_regs_lock(adev, false);
3646}
3647
3648static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3649{
3650 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3651 struct amdgpu_encoder_atom_dig *dig;
3652
3653 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3654
3655 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3656 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3657 dce_v10_0_afmt_enable(encoder, false);
3658 dig = amdgpu_encoder->enc_priv;
3659 dig->dig_encoder = -1;
3660 }
3661 amdgpu_encoder->active_device = 0;
3662}
3663
3664/* these are handled by the primary encoders */
3665static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3666{
3667
3668}
3669
3670static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3671{
3672
3673}
3674
3675static void
3676dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3677 struct drm_display_mode *mode,
3678 struct drm_display_mode *adjusted_mode)
3679{
3680
3681}
3682
3683static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3684{
3685
3686}
3687
3688static void
3689dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3690{
3691
3692}
3693
aaa36a97
AD		 3694static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3695 .dpms = dce_v10_0_ext_dpms,
aaa36a97
AD		 3696 .prepare = dce_v10_0_ext_prepare,
3697 .mode_set = dce_v10_0_ext_mode_set,
3698 .commit = dce_v10_0_ext_commit,
3699 .disable = dce_v10_0_ext_disable,
3700 /* no detect for TMDS/LVDS yet */
3701};
3702
3703static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3704 .dpms = amdgpu_atombios_encoder_dpms,
3705 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3706 .prepare = dce_v10_0_encoder_prepare,
3707 .mode_set = dce_v10_0_encoder_mode_set,
3708 .commit = dce_v10_0_encoder_commit,
3709 .disable = dce_v10_0_encoder_disable,
3710 .detect = amdgpu_atombios_encoder_dig_detect,
3711};
3712
3713static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3714 .dpms = amdgpu_atombios_encoder_dpms,
3715 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3716 .prepare = dce_v10_0_encoder_prepare,
3717 .mode_set = dce_v10_0_encoder_mode_set,
3718 .commit = dce_v10_0_encoder_commit,
3719 .detect = amdgpu_atombios_encoder_dac_detect,
3720};
3721
3722static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3723{
3724 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3725 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3726 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3727 kfree(amdgpu_encoder->enc_priv);
3728 drm_encoder_cleanup(encoder);
3729 kfree(amdgpu_encoder);
3730}
3731
3732static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3733 .destroy = dce_v10_0_encoder_destroy,
3734};
3735
3736static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3737 uint32_t encoder_enum,
3738 uint32_t supported_device,
3739 u16 caps)
3740{
3741 struct drm_device *dev = adev->ddev;
3742 struct drm_encoder *encoder;
3743 struct amdgpu_encoder *amdgpu_encoder;
3744
3745 /* see if we already added it */
3746 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3747 amdgpu_encoder = to_amdgpu_encoder(encoder);
3748 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3749 amdgpu_encoder->devices |= supported_device;
3750 return;
3751 }
3752
3753 }
3754
3755 /* add a new one */
3756 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3757 if (!amdgpu_encoder)
3758 return;
3759
3760 encoder = &amdgpu_encoder->base;
3761 switch (adev->mode_info.num_crtc) {
3762 case 1:
3763 encoder->possible_crtcs = 0x1;
3764 break;
3765 case 2:
3766 default:
3767 encoder->possible_crtcs = 0x3;
3768 break;
3769 case 4:
3770 encoder->possible_crtcs = 0xf;
3771 break;
3772 case 6:
3773 encoder->possible_crtcs = 0x3f;
3774 break;
3775 }
3776
3777 amdgpu_encoder->enc_priv = NULL;
3778
3779 amdgpu_encoder->encoder_enum = encoder_enum;
3780 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3781 amdgpu_encoder->devices = supported_device;
3782 amdgpu_encoder->rmx_type = RMX_OFF;
3783 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3784 amdgpu_encoder->is_ext_encoder = false;
3785 amdgpu_encoder->caps = caps;
3786
3787 switch (amdgpu_encoder->encoder_id) {
3788 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3789 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3790 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3791 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3792 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3793 break;
3794 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3799 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3800 amdgpu_encoder->rmx_type = RMX_FULL;
3801 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3802 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3803 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3804 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3805 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3806 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3807 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3808 } else {
3809 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3810 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3811 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3812 }
3813 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3814 break;
3815 case ENCODER_OBJECT_ID_SI170B:
3816 case ENCODER_OBJECT_ID_CH7303:
3817 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3818 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3819 case ENCODER_OBJECT_ID_TITFP513:
3820 case ENCODER_OBJECT_ID_VT1623:
3821 case ENCODER_OBJECT_ID_HDMI_SI1930:
3822 case ENCODER_OBJECT_ID_TRAVIS:
3823 case ENCODER_OBJECT_ID_NUTMEG:
3824 /* these are handled by the primary encoders */
3825 amdgpu_encoder->is_ext_encoder = true;
3826 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3827 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3828 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3829 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3830 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3831 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3832 else
3833 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3834 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3835 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3836 break;
3837 }
3838}
3839
3840static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3841 .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3842 .bandwidth_update = &dce_v10_0_bandwidth_update,
3843 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3844 .vblank_wait = &dce_v10_0_vblank_wait,
3845 .is_display_hung = &dce_v10_0_is_display_hung,
3846 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3847 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3848 .hpd_sense = &dce_v10_0_hpd_sense,
3849 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3850 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3851 .page_flip = &dce_v10_0_page_flip,
3852 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3853 .add_encoder = &dce_v10_0_encoder_add,
3854 .add_connector = &amdgpu_connector_add,
3855 .stop_mc_access = &dce_v10_0_stop_mc_access,
3856 .resume_mc_access = &dce_v10_0_resume_mc_access,
3857};
3858
3859static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3860{
3861 if (adev->mode_info.funcs == NULL)
3862 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3863}
3864
3865static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3866 .set = dce_v10_0_set_crtc_irq_state,
3867 .process = dce_v10_0_crtc_irq,
3868};
3869
3870static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3871 .set = dce_v10_0_set_pageflip_irq_state,
3872 .process = dce_v10_0_pageflip_irq,
3873};
3874
3875static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3876 .set = dce_v10_0_set_hpd_irq_state,
3877 .process = dce_v10_0_hpd_irq,
3878};
3879
3880static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3881{
3882 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3883 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3884
3885 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3886 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3887
3888 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3889 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3890}
Linux kernel - Deliverables
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