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drm: make drm_get_format_name thread-safe
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v8_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "cikd.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_8_0_d.h"
36#include "dce/dce_8_0_sh_mask.h"
37
38#include "gca/gfx_7_2_enum.h"
39
40#include "gmc/gmc_7_1_d.h"
41#include "gmc/gmc_7_1_sh_mask.h"
42
43#include "oss/oss_2_0_d.h"
44#include "oss/oss_2_0_sh_mask.h"
45
46static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
47static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
48
49static const u32 crtc_offsets[6] =
50{
51 CRTC0_REGISTER_OFFSET,
52 CRTC1_REGISTER_OFFSET,
53 CRTC2_REGISTER_OFFSET,
54 CRTC3_REGISTER_OFFSET,
55 CRTC4_REGISTER_OFFSET,
56 CRTC5_REGISTER_OFFSET
57};
58
59static const uint32_t dig_offsets[] = {
60 CRTC0_REGISTER_OFFSET,
61 CRTC1_REGISTER_OFFSET,
62 CRTC2_REGISTER_OFFSET,
63 CRTC3_REGISTER_OFFSET,
64 CRTC4_REGISTER_OFFSET,
65 CRTC5_REGISTER_OFFSET,
66 (0x13830 - 0x7030) >> 2,
67};
68
69static const struct {
70 uint32_t reg;
71 uint32_t vblank;
72 uint32_t vline;
73 uint32_t hpd;
74
75} interrupt_status_offsets[6] = { {
76 .reg = mmDISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
80}, {
81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
85}, {
86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
90}, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
105} };
106
107static const uint32_t hpd_int_control_offsets[6] = {
108 mmDC_HPD1_INT_CONTROL,
109 mmDC_HPD2_INT_CONTROL,
110 mmDC_HPD3_INT_CONTROL,
111 mmDC_HPD4_INT_CONTROL,
112 mmDC_HPD5_INT_CONTROL,
113 mmDC_HPD6_INT_CONTROL,
114};
115
116static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
117 u32 block_offset, u32 reg)
118{
119 unsigned long flags;
120 u32 r;
121
122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
126
127 return r;
128}
129
130static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
131 u32 block_offset, u32 reg, u32 v)
132{
133 unsigned long flags;
134
135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
139}
140
141static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
142{
143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
145 return true;
146 else
147 return false;
148}
149
150static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
151{
152 u32 pos1, pos2;
153
154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
156
157 if (pos1 != pos2)
158 return true;
159 else
160 return false;
161}
162
163/**
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
165 *
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
168 *
169 * Wait for vblank on the requested crtc (evergreen+).
170 */
171static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
172{
173 unsigned i = 0;
174
175 if (crtc >= adev->mode_info.num_crtc)
176 return;
177
178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
179 return;
180
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
183 */
184 while (dce_v8_0_is_in_vblank(adev, crtc)) {
185 if (i++ % 100 == 0) {
186 if (!dce_v8_0_is_counter_moving(adev, crtc))
187 break;
188 }
189 }
190
191 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
192 if (i++ % 100 == 0) {
193 if (!dce_v8_0_is_counter_moving(adev, crtc))
194 break;
195 }
196 }
197}
198
199static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
200{
201 if (crtc >= adev->mode_info.num_crtc)
202 return 0;
203 else
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
205}
206
f6c7aba4
MD		 207static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
208{
209 unsigned i;
210
211 /* Enable pflip interrupts */
212 for (i = 0; i < adev->mode_info.num_crtc; i++)
213 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
214}
215
216static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
217{
218 unsigned i;
219
220 /* Disable pflip interrupts */
221 for (i = 0; i < adev->mode_info.num_crtc; i++)
222 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
223}
224
a2e73f56
AD		 225/**
226 * dce_v8_0_page_flip - pageflip callback.
227 *
228 * @adev: amdgpu_device pointer
229 * @crtc_id: crtc to cleanup pageflip on
230 * @crtc_base: new address of the crtc (GPU MC address)
231 *
82326860
AD		 232 * Triggers the actual pageflip by updating the primary
233 * surface base address.
a2e73f56
AD		 234 */
235static void dce_v8_0_page_flip(struct amdgpu_device *adev,
cb9e59d7 236 int crtc_id, u64 crtc_base, bool async)
a2e73f56
AD		 237{
238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
a2e73f56 239
cb9e59d7
AD		 240 /* flip at hsync for async, default is vsync */
241 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
242 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
82326860 243 /* update the primary scanout addresses */
a2e73f56
AD		 244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
245 upper_32_bits(crtc_base));
82326860 246 /* writing to the low address triggers the update */
a2e73f56 247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
82326860
AD		 248 lower_32_bits(crtc_base));
249 /* post the write */
250 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
a2e73f56
AD		 251}
252
253static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
254 u32 *vbl, u32 *position)
255{
256 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
257 return -EINVAL;
258
259 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
260 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
261
262 return 0;
263}
264
265/**
266 * dce_v8_0_hpd_sense - hpd sense callback.
267 *
268 * @adev: amdgpu_device pointer
269 * @hpd: hpd (hotplug detect) pin
270 *
271 * Checks if a digital monitor is connected (evergreen+).
272 * Returns true if connected, false if not connected.
273 */
274static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
275 enum amdgpu_hpd_id hpd)
276{
277 bool connected = false;
278
279 switch (hpd) {
280 case AMDGPU_HPD_1:
281 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
282 connected = true;
283 break;
284 case AMDGPU_HPD_2:
285 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
286 connected = true;
287 break;
288 case AMDGPU_HPD_3:
289 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
290 connected = true;
291 break;
292 case AMDGPU_HPD_4:
293 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
294 connected = true;
295 break;
296 case AMDGPU_HPD_5:
297 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
298 connected = true;
299 break;
300 case AMDGPU_HPD_6:
301 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
302 connected = true;
303 break;
304 default:
305 break;
306 }
307
308 return connected;
309}
310
311/**
312 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
313 *
314 * @adev: amdgpu_device pointer
315 * @hpd: hpd (hotplug detect) pin
316 *
317 * Set the polarity of the hpd pin (evergreen+).
318 */
319static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
320 enum amdgpu_hpd_id hpd)
321{
322 u32 tmp;
323 bool connected = dce_v8_0_hpd_sense(adev, hpd);
324
325 switch (hpd) {
326 case AMDGPU_HPD_1:
327 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
328 if (connected)
329 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
330 else
331 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
332 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
333 break;
334 case AMDGPU_HPD_2:
335 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
336 if (connected)
337 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
338 else
339 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
340 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
341 break;
342 case AMDGPU_HPD_3:
343 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
344 if (connected)
345 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
346 else
347 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
348 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
349 break;
350 case AMDGPU_HPD_4:
351 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
352 if (connected)
353 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
354 else
355 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
356 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
357 break;
358 case AMDGPU_HPD_5:
359 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
360 if (connected)
361 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
362 else
363 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
364 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
365 break;
366 case AMDGPU_HPD_6:
367 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
368 if (connected)
369 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
370 else
371 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
372 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
373 break;
374 default:
375 break;
376 }
377}
378
379/**
380 * dce_v8_0_hpd_init - hpd setup callback.
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Setup the hpd pins used by the card (evergreen+).
385 * Enable the pin, set the polarity, and enable the hpd interrupts.
386 */
387static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
388{
389 struct drm_device *dev = adev->ddev;
390 struct drm_connector *connector;
391 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
392 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
393 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
394
395 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
396 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
397
398 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
399 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
400 /* don't try to enable hpd on eDP or LVDS avoid breaking the
401 * aux dp channel on imac and help (but not completely fix)
402 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
403 * also avoid interrupt storms during dpms.
404 */
405 continue;
406 }
407 switch (amdgpu_connector->hpd.hpd) {
408 case AMDGPU_HPD_1:
409 WREG32(mmDC_HPD1_CONTROL, tmp);
410 break;
411 case AMDGPU_HPD_2:
412 WREG32(mmDC_HPD2_CONTROL, tmp);
413 break;
414 case AMDGPU_HPD_3:
415 WREG32(mmDC_HPD3_CONTROL, tmp);
416 break;
417 case AMDGPU_HPD_4:
418 WREG32(mmDC_HPD4_CONTROL, tmp);
419 break;
420 case AMDGPU_HPD_5:
421 WREG32(mmDC_HPD5_CONTROL, tmp);
422 break;
423 case AMDGPU_HPD_6:
424 WREG32(mmDC_HPD6_CONTROL, tmp);
425 break;
426 default:
427 break;
428 }
429 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
430 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
431 }
432}
433
434/**
435 * dce_v8_0_hpd_fini - hpd tear down callback.
436 *
437 * @adev: amdgpu_device pointer
438 *
439 * Tear down the hpd pins used by the card (evergreen+).
440 * Disable the hpd interrupts.
441 */
442static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
443{
444 struct drm_device *dev = adev->ddev;
445 struct drm_connector *connector;
446
447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
448 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
449
450 switch (amdgpu_connector->hpd.hpd) {
451 case AMDGPU_HPD_1:
452 WREG32(mmDC_HPD1_CONTROL, 0);
453 break;
454 case AMDGPU_HPD_2:
455 WREG32(mmDC_HPD2_CONTROL, 0);
456 break;
457 case AMDGPU_HPD_3:
458 WREG32(mmDC_HPD3_CONTROL, 0);
459 break;
460 case AMDGPU_HPD_4:
461 WREG32(mmDC_HPD4_CONTROL, 0);
462 break;
463 case AMDGPU_HPD_5:
464 WREG32(mmDC_HPD5_CONTROL, 0);
465 break;
466 case AMDGPU_HPD_6:
467 WREG32(mmDC_HPD6_CONTROL, 0);
468 break;
469 default:
470 break;
471 }
472 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
473 }
474}
475
476static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
477{
478 return mmDC_GPIO_HPD_A;
479}
480
481static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
482{
483 u32 crtc_hung = 0;
484 u32 crtc_status[6];
485 u32 i, j, tmp;
486
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
489 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 crtc_hung |= (1 << i);
491 }
492 }
493
494 for (j = 0; j < 10; j++) {
495 for (i = 0; i < adev->mode_info.num_crtc; i++) {
496 if (crtc_hung & (1 << i)) {
497 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
498 if (tmp != crtc_status[i])
499 crtc_hung &= ~(1 << i);
500 }
501 }
502 if (crtc_hung == 0)
503 return false;
504 udelay(100);
505 }
506
507 return true;
508}
509
510static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
511 struct amdgpu_mode_mc_save *save)
512{
513 u32 crtc_enabled, tmp;
514 int i;
515
516 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
517 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
518
519 /* disable VGA render */
520 tmp = RREG32(mmVGA_RENDER_CONTROL);
521 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
522 WREG32(mmVGA_RENDER_CONTROL, tmp);
523
524 /* blank the display controllers */
525 for (i = 0; i < adev->mode_info.num_crtc; i++) {
526 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
527 CRTC_CONTROL, CRTC_MASTER_EN);
528 if (crtc_enabled) {
5a3f25db 529#if 1
a2e73f56
AD		 530 save->crtc_enabled[i] = true;
531 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
532 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
5a3f25db
JZ		 533 /*it is correct only for RGB ; black is 0*/
534 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
a2e73f56
AD		 535 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
a2e73f56 537 }
5a3f25db 538 mdelay(20);
a2e73f56
AD		 539#else
540 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
541 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
542 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
543 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
544 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
545 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
546 save->crtc_enabled[i] = false;
547 /* ***** */
548#endif
549 } else {
550 save->crtc_enabled[i] = false;
551 }
552 }
553}
554
555static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
556 struct amdgpu_mode_mc_save *save)
557{
5a3f25db
JZ		 558 u32 tmp;
559 int i;
a2e73f56
AD		 560
561 /* update crtc base addresses */
562 for (i = 0; i < adev->mode_info.num_crtc; i++) {
563 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
564 upper_32_bits(adev->mc.vram_start));
a2e73f56
AD		 565 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
566 (u32)adev->mc.vram_start);
a2e73f56
AD		 567
568 if (save->crtc_enabled[i]) {
a2e73f56
AD		 569 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
570 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
a2e73f56 571 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
a2e73f56 572 }
5a3f25db 573 mdelay(20);
a2e73f56
AD		 574 }
575
576 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
577 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
578
579 /* Unlock vga access */
580 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
581 mdelay(1);
582 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
583}
584
585static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
586 bool render)
587{
588 u32 tmp;
589
590 /* Lockout access through VGA aperture*/
591 tmp = RREG32(mmVGA_HDP_CONTROL);
592 if (render)
593 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
594 else
595 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
596 WREG32(mmVGA_HDP_CONTROL, tmp);
597
598 /* disable VGA render */
599 tmp = RREG32(mmVGA_RENDER_CONTROL);
600 if (render)
601 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
602 else
603 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
604 WREG32(mmVGA_RENDER_CONTROL, tmp);
605}
606
607static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
608{
609 struct drm_device *dev = encoder->dev;
610 struct amdgpu_device *adev = dev->dev_private;
611 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
612 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
613 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
614 int bpc = 0;
615 u32 tmp = 0;
616 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
617
618 if (connector) {
619 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
620 bpc = amdgpu_connector_get_monitor_bpc(connector);
621 dither = amdgpu_connector->dither;
622 }
623
624 /* LVDS/eDP FMT is set up by atom */
625 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
626 return;
627
628 /* not needed for analog */
629 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
630 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
631 return;
632
633 if (bpc == 0)
634 return;
635
636 switch (bpc) {
637 case 6:
638 if (dither == AMDGPU_FMT_DITHER_ENABLE)
639 /* XXX sort out optimal dither settings */
640 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
641 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
642 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
643 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
644 else
645 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
646 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
647 break;
648 case 8:
649 if (dither == AMDGPU_FMT_DITHER_ENABLE)
650 /* XXX sort out optimal dither settings */
651 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
652 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
653 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
654 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
655 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
656 else
657 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
658 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
659 break;
660 case 10:
661 if (dither == AMDGPU_FMT_DITHER_ENABLE)
662 /* XXX sort out optimal dither settings */
663 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
664 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
665 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
666 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
667 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
668 else
669 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
670 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
671 break;
672 default:
673 /* not needed */
674 break;
675 }
676
677 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
678}
679
680
681/* display watermark setup */
682/**
683 * dce_v8_0_line_buffer_adjust - Set up the line buffer
684 *
685 * @adev: amdgpu_device pointer
686 * @amdgpu_crtc: the selected display controller
687 * @mode: the current display mode on the selected display
688 * controller
689 *
690 * Setup up the line buffer allocation for
691 * the selected display controller (CIK).
692 * Returns the line buffer size in pixels.
693 */
694static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
695 struct amdgpu_crtc *amdgpu_crtc,
696 struct drm_display_mode *mode)
697{
698 u32 tmp, buffer_alloc, i;
699 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
700 /*
701 * Line Buffer Setup
702 * There are 6 line buffers, one for each display controllers.
703 * There are 3 partitions per LB. Select the number of partitions
704 * to enable based on the display width. For display widths larger
705 * than 4096, you need use to use 2 display controllers and combine
706 * them using the stereo blender.
707 */
708 if (amdgpu_crtc->base.enabled && mode) {
709 if (mode->crtc_hdisplay < 1920) {
710 tmp = 1;
711 buffer_alloc = 2;
712 } else if (mode->crtc_hdisplay < 2560) {
713 tmp = 2;
714 buffer_alloc = 2;
715 } else if (mode->crtc_hdisplay < 4096) {
716 tmp = 0;
2f7d10b3 717 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 718 } else {
719 DRM_DEBUG_KMS("Mode too big for LB!\n");
720 tmp = 0;
2f7d10b3 721 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 722 }
723 } else {
724 tmp = 1;
725 buffer_alloc = 0;
726 }
727
728 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
729 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
730 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
731
732 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
733 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
734 for (i = 0; i < adev->usec_timeout; i++) {
735 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
736 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
737 break;
738 udelay(1);
739 }
740
741 if (amdgpu_crtc->base.enabled && mode) {
742 switch (tmp) {
743 case 0:
744 default:
745 return 4096 * 2;
746 case 1:
747 return 1920 * 2;
748 case 2:
749 return 2560 * 2;
750 }
751 }
752
753 /* controller not enabled, so no lb used */
754 return 0;
755}
756
757/**
758 * cik_get_number_of_dram_channels - get the number of dram channels
759 *
760 * @adev: amdgpu_device pointer
761 *
762 * Look up the number of video ram channels (CIK).
763 * Used for display watermark bandwidth calculations
764 * Returns the number of dram channels
765 */
766static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
767{
768 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
769
770 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
771 case 0:
772 default:
773 return 1;
774 case 1:
775 return 2;
776 case 2:
777 return 4;
778 case 3:
779 return 8;
780 case 4:
781 return 3;
782 case 5:
783 return 6;
784 case 6:
785 return 10;
786 case 7:
787 return 12;
788 case 8:
789 return 16;
790 }
791}
792
793struct dce8_wm_params {
794 u32 dram_channels; /* number of dram channels */
795 u32 yclk; /* bandwidth per dram data pin in kHz */
796 u32 sclk; /* engine clock in kHz */
797 u32 disp_clk; /* display clock in kHz */
798 u32 src_width; /* viewport width */
799 u32 active_time; /* active display time in ns */
800 u32 blank_time; /* blank time in ns */
801 bool interlaced; /* mode is interlaced */
802 fixed20_12 vsc; /* vertical scale ratio */
803 u32 num_heads; /* number of active crtcs */
804 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
805 u32 lb_size; /* line buffer allocated to pipe */
806 u32 vtaps; /* vertical scaler taps */
807};
808
809/**
810 * dce_v8_0_dram_bandwidth - get the dram bandwidth
811 *
812 * @wm: watermark calculation data
813 *
814 * Calculate the raw dram bandwidth (CIK).
815 * Used for display watermark bandwidth calculations
816 * Returns the dram bandwidth in MBytes/s
817 */
818static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
819{
820 /* Calculate raw DRAM Bandwidth */
821 fixed20_12 dram_efficiency; /* 0.7 */
822 fixed20_12 yclk, dram_channels, bandwidth;
823 fixed20_12 a;
824
825 a.full = dfixed_const(1000);
826 yclk.full = dfixed_const(wm->yclk);
827 yclk.full = dfixed_div(yclk, a);
828 dram_channels.full = dfixed_const(wm->dram_channels * 4);
829 a.full = dfixed_const(10);
830 dram_efficiency.full = dfixed_const(7);
831 dram_efficiency.full = dfixed_div(dram_efficiency, a);
832 bandwidth.full = dfixed_mul(dram_channels, yclk);
833 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
834
835 return dfixed_trunc(bandwidth);
836}
837
838/**
839 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
840 *
841 * @wm: watermark calculation data
842 *
843 * Calculate the dram bandwidth used for display (CIK).
844 * Used for display watermark bandwidth calculations
845 * Returns the dram bandwidth for display in MBytes/s
846 */
847static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
848{
849 /* Calculate DRAM Bandwidth and the part allocated to display. */
850 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
851 fixed20_12 yclk, dram_channels, bandwidth;
852 fixed20_12 a;
853
854 a.full = dfixed_const(1000);
855 yclk.full = dfixed_const(wm->yclk);
856 yclk.full = dfixed_div(yclk, a);
857 dram_channels.full = dfixed_const(wm->dram_channels * 4);
858 a.full = dfixed_const(10);
859 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
860 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
861 bandwidth.full = dfixed_mul(dram_channels, yclk);
862 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
863
864 return dfixed_trunc(bandwidth);
865}
866
867/**
868 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
869 *
870 * @wm: watermark calculation data
871 *
872 * Calculate the data return bandwidth used for display (CIK).
873 * Used for display watermark bandwidth calculations
874 * Returns the data return bandwidth in MBytes/s
875 */
876static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
877{
878 /* Calculate the display Data return Bandwidth */
879 fixed20_12 return_efficiency; /* 0.8 */
880 fixed20_12 sclk, bandwidth;
881 fixed20_12 a;
882
883 a.full = dfixed_const(1000);
884 sclk.full = dfixed_const(wm->sclk);
885 sclk.full = dfixed_div(sclk, a);
886 a.full = dfixed_const(10);
887 return_efficiency.full = dfixed_const(8);
888 return_efficiency.full = dfixed_div(return_efficiency, a);
889 a.full = dfixed_const(32);
890 bandwidth.full = dfixed_mul(a, sclk);
891 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
892
893 return dfixed_trunc(bandwidth);
894}
895
896/**
897 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
898 *
899 * @wm: watermark calculation data
900 *
901 * Calculate the dmif bandwidth used for display (CIK).
902 * Used for display watermark bandwidth calculations
903 * Returns the dmif bandwidth in MBytes/s
904 */
905static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
906{
907 /* Calculate the DMIF Request Bandwidth */
908 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
909 fixed20_12 disp_clk, bandwidth;
910 fixed20_12 a, b;
911
912 a.full = dfixed_const(1000);
913 disp_clk.full = dfixed_const(wm->disp_clk);
914 disp_clk.full = dfixed_div(disp_clk, a);
915 a.full = dfixed_const(32);
916 b.full = dfixed_mul(a, disp_clk);
917
918 a.full = dfixed_const(10);
919 disp_clk_request_efficiency.full = dfixed_const(8);
920 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
921
922 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
923
924 return dfixed_trunc(bandwidth);
925}
926
927/**
928 * dce_v8_0_available_bandwidth - get the min available bandwidth
929 *
930 * @wm: watermark calculation data
931 *
932 * Calculate the min available bandwidth used for display (CIK).
933 * Used for display watermark bandwidth calculations
934 * Returns the min available bandwidth in MBytes/s
935 */
936static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
937{
938 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
939 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
940 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
941 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
942
943 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
944}
945
946/**
947 * dce_v8_0_average_bandwidth - get the average available bandwidth
948 *
949 * @wm: watermark calculation data
950 *
951 * Calculate the average available bandwidth used for display (CIK).
952 * Used for display watermark bandwidth calculations
953 * Returns the average available bandwidth in MBytes/s
954 */
955static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
956{
957 /* Calculate the display mode Average Bandwidth
958 * DisplayMode should contain the source and destination dimensions,
959 * timing, etc.
960 */
961 fixed20_12 bpp;
962 fixed20_12 line_time;
963 fixed20_12 src_width;
964 fixed20_12 bandwidth;
965 fixed20_12 a;
966
967 a.full = dfixed_const(1000);
968 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
969 line_time.full = dfixed_div(line_time, a);
970 bpp.full = dfixed_const(wm->bytes_per_pixel);
971 src_width.full = dfixed_const(wm->src_width);
972 bandwidth.full = dfixed_mul(src_width, bpp);
973 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
974 bandwidth.full = dfixed_div(bandwidth, line_time);
975
976 return dfixed_trunc(bandwidth);
977}
978
979/**
980 * dce_v8_0_latency_watermark - get the latency watermark
981 *
982 * @wm: watermark calculation data
983 *
984 * Calculate the latency watermark (CIK).
985 * Used for display watermark bandwidth calculations
986 * Returns the latency watermark in ns
987 */
988static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
989{
990 /* First calculate the latency in ns */
991 u32 mc_latency = 2000; /* 2000 ns. */
992 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
993 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
994 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
995 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
996 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
997 (wm->num_heads * cursor_line_pair_return_time);
998 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
999 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1000 u32 tmp, dmif_size = 12288;
1001 fixed20_12 a, b, c;
1002
1003 if (wm->num_heads == 0)
1004 return 0;
1005
1006 a.full = dfixed_const(2);
1007 b.full = dfixed_const(1);
1008 if ((wm->vsc.full > a.full) ||
1009 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1010 (wm->vtaps >= 5) ||
1011 ((wm->vsc.full >= a.full) && wm->interlaced))
1012 max_src_lines_per_dst_line = 4;
1013 else
1014 max_src_lines_per_dst_line = 2;
1015
1016 a.full = dfixed_const(available_bandwidth);
1017 b.full = dfixed_const(wm->num_heads);
1018 a.full = dfixed_div(a, b);
1019
1020 b.full = dfixed_const(mc_latency + 512);
1021 c.full = dfixed_const(wm->disp_clk);
1022 b.full = dfixed_div(b, c);
1023
1024 c.full = dfixed_const(dmif_size);
1025 b.full = dfixed_div(c, b);
1026
1027 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1028
1029 b.full = dfixed_const(1000);
1030 c.full = dfixed_const(wm->disp_clk);
1031 b.full = dfixed_div(c, b);
1032 c.full = dfixed_const(wm->bytes_per_pixel);
1033 b.full = dfixed_mul(b, c);
1034
1035 lb_fill_bw = min(tmp, dfixed_trunc(b));
1036
1037 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1038 b.full = dfixed_const(1000);
1039 c.full = dfixed_const(lb_fill_bw);
1040 b.full = dfixed_div(c, b);
1041 a.full = dfixed_div(a, b);
1042 line_fill_time = dfixed_trunc(a);
1043
1044 if (line_fill_time < wm->active_time)
1045 return latency;
1046 else
1047 return latency + (line_fill_time - wm->active_time);
1048
1049}
1050
1051/**
1052 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1053 * average and available dram bandwidth
1054 *
1055 * @wm: watermark calculation data
1056 *
1057 * Check if the display average bandwidth fits in the display
1058 * dram bandwidth (CIK).
1059 * Used for display watermark bandwidth calculations
1060 * Returns true if the display fits, false if not.
1061 */
1062static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1063{
1064 if (dce_v8_0_average_bandwidth(wm) <=
1065 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1066 return true;
1067 else
1068 return false;
1069}
1070
1071/**
1072 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1073 * average and available bandwidth
1074 *
1075 * @wm: watermark calculation data
1076 *
1077 * Check if the display average bandwidth fits in the display
1078 * available bandwidth (CIK).
1079 * Used for display watermark bandwidth calculations
1080 * Returns true if the display fits, false if not.
1081 */
1082static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1083{
1084 if (dce_v8_0_average_bandwidth(wm) <=
1085 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1086 return true;
1087 else
1088 return false;
1089}
1090
1091/**
1092 * dce_v8_0_check_latency_hiding - check latency hiding
1093 *
1094 * @wm: watermark calculation data
1095 *
1096 * Check latency hiding (CIK).
1097 * Used for display watermark bandwidth calculations
1098 * Returns true if the display fits, false if not.
1099 */
1100static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1101{
1102 u32 lb_partitions = wm->lb_size / wm->src_width;
1103 u32 line_time = wm->active_time + wm->blank_time;
1104 u32 latency_tolerant_lines;
1105 u32 latency_hiding;
1106 fixed20_12 a;
1107
1108 a.full = dfixed_const(1);
1109 if (wm->vsc.full > a.full)
1110 latency_tolerant_lines = 1;
1111 else {
1112 if (lb_partitions <= (wm->vtaps + 1))
1113 latency_tolerant_lines = 1;
1114 else
1115 latency_tolerant_lines = 2;
1116 }
1117
1118 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1119
1120 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1121 return true;
1122 else
1123 return false;
1124}
1125
1126/**
1127 * dce_v8_0_program_watermarks - program display watermarks
1128 *
1129 * @adev: amdgpu_device pointer
1130 * @amdgpu_crtc: the selected display controller
1131 * @lb_size: line buffer size
1132 * @num_heads: number of display controllers in use
1133 *
1134 * Calculate and program the display watermarks for the
1135 * selected display controller (CIK).
1136 */
1137static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1138 struct amdgpu_crtc *amdgpu_crtc,
1139 u32 lb_size, u32 num_heads)
1140{
1141 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1142 struct dce8_wm_params wm_low, wm_high;
1143 u32 pixel_period;
1144 u32 line_time = 0;
1145 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1146 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
a2e73f56
AD		 1147
1148 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1149 pixel_period = 1000000 / (u32)mode->clock;
1150 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1151
1152 /* watermark for high clocks */
1153 if (adev->pm.dpm_enabled) {
1154 wm_high.yclk =
1155 amdgpu_dpm_get_mclk(adev, false) * 10;
1156 wm_high.sclk =
1157 amdgpu_dpm_get_sclk(adev, false) * 10;
1158 } else {
1159 wm_high.yclk = adev->pm.current_mclk * 10;
1160 wm_high.sclk = adev->pm.current_sclk * 10;
1161 }
1162
1163 wm_high.disp_clk = mode->clock;
1164 wm_high.src_width = mode->crtc_hdisplay;
1165 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1166 wm_high.blank_time = line_time - wm_high.active_time;
1167 wm_high.interlaced = false;
1168 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1169 wm_high.interlaced = true;
1170 wm_high.vsc = amdgpu_crtc->vsc;
1171 wm_high.vtaps = 1;
1172 if (amdgpu_crtc->rmx_type != RMX_OFF)
1173 wm_high.vtaps = 2;
1174 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1175 wm_high.lb_size = lb_size;
1176 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1177 wm_high.num_heads = num_heads;
1178
1179 /* set for high clocks */
1180 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1181
1182 /* possibly force display priority to high */
1183 /* should really do this at mode validation time... */
1184 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1185 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1186 !dce_v8_0_check_latency_hiding(&wm_high) ||
1187 (adev->mode_info.disp_priority == 2)) {
1188 DRM_DEBUG_KMS("force priority to high\n");
1189 }
1190
1191 /* watermark for low clocks */
1192 if (adev->pm.dpm_enabled) {
1193 wm_low.yclk =
1194 amdgpu_dpm_get_mclk(adev, true) * 10;
1195 wm_low.sclk =
1196 amdgpu_dpm_get_sclk(adev, true) * 10;
1197 } else {
1198 wm_low.yclk = adev->pm.current_mclk * 10;
1199 wm_low.sclk = adev->pm.current_sclk * 10;
1200 }
1201
1202 wm_low.disp_clk = mode->clock;
1203 wm_low.src_width = mode->crtc_hdisplay;
1204 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1205 wm_low.blank_time = line_time - wm_low.active_time;
1206 wm_low.interlaced = false;
1207 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1208 wm_low.interlaced = true;
1209 wm_low.vsc = amdgpu_crtc->vsc;
1210 wm_low.vtaps = 1;
1211 if (amdgpu_crtc->rmx_type != RMX_OFF)
1212 wm_low.vtaps = 2;
1213 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1214 wm_low.lb_size = lb_size;
1215 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1216 wm_low.num_heads = num_heads;
1217
1218 /* set for low clocks */
1219 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1220
1221 /* possibly force display priority to high */
1222 /* should really do this at mode validation time... */
1223 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1224 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1225 !dce_v8_0_check_latency_hiding(&wm_low) ||
1226 (adev->mode_info.disp_priority == 2)) {
1227 DRM_DEBUG_KMS("force priority to high\n");
1228 }
8e36f9d3 1229 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
a2e73f56
AD		 1230 }
1231
1232 /* select wm A */
1233 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1234 tmp = wm_mask;
1235 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1236 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1237 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1238 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1239 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1240 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1241 /* select wm B */
1242 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1243 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1244 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1245 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1246 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1247 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1248 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1249 /* restore original selection */
1250 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1251
1252 /* save values for DPM */
1253 amdgpu_crtc->line_time = line_time;
1254 amdgpu_crtc->wm_high = latency_watermark_a;
1255 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1256 /* Save number of lines the linebuffer leads before the scanout */
1257 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
a2e73f56
AD		 1258}
1259
1260/**
1261 * dce_v8_0_bandwidth_update - program display watermarks
1262 *
1263 * @adev: amdgpu_device pointer
1264 *
1265 * Calculate and program the display watermarks and line
1266 * buffer allocation (CIK).
1267 */
1268static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1269{
1270 struct drm_display_mode *mode = NULL;
1271 u32 num_heads = 0, lb_size;
1272 int i;
1273
1274 amdgpu_update_display_priority(adev);
1275
1276 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1277 if (adev->mode_info.crtcs[i]->base.enabled)
1278 num_heads++;
1279 }
1280 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1281 mode = &adev->mode_info.crtcs[i]->base.mode;
1282 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1283 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1284 lb_size, num_heads);
1285 }
1286}
1287
1288static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1289{
1290 int i;
1291 u32 offset, tmp;
1292
1293 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1294 offset = adev->mode_info.audio.pin[i].offset;
1295 tmp = RREG32_AUDIO_ENDPT(offset,
1296 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1297 if (((tmp &
1298 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1299 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1300 adev->mode_info.audio.pin[i].connected = false;
1301 else
1302 adev->mode_info.audio.pin[i].connected = true;
1303 }
1304}
1305
1306static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1307{
1308 int i;
1309
1310 dce_v8_0_audio_get_connected_pins(adev);
1311
1312 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1313 if (adev->mode_info.audio.pin[i].connected)
1314 return &adev->mode_info.audio.pin[i];
1315 }
1316 DRM_ERROR("No connected audio pins found!\n");
1317 return NULL;
1318}
1319
1320static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1321{
1322 struct amdgpu_device *adev = encoder->dev->dev_private;
1323 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1324 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1325 u32 offset;
1326
1327 if (!dig || !dig->afmt || !dig->afmt->pin)
1328 return;
1329
1330 offset = dig->afmt->offset;
1331
1332 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1333 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1334}
1335
1336static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1337 struct drm_display_mode *mode)
1338{
1339 struct amdgpu_device *adev = encoder->dev->dev_private;
1340 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1341 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1342 struct drm_connector *connector;
1343 struct amdgpu_connector *amdgpu_connector = NULL;
1344 u32 tmp = 0, offset;
1345
1346 if (!dig || !dig->afmt || !dig->afmt->pin)
1347 return;
1348
1349 offset = dig->afmt->pin->offset;
1350
1351 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1352 if (connector->encoder == encoder) {
1353 amdgpu_connector = to_amdgpu_connector(connector);
1354 break;
1355 }
1356 }
1357
1358 if (!amdgpu_connector) {
1359 DRM_ERROR("Couldn't find encoder's connector\n");
1360 return;
1361 }
1362
1363 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1364 if (connector->latency_present[1])
1365 tmp =
1366 (connector->video_latency[1] <<
1367 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1368 (connector->audio_latency[1] <<
1369 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1370 else
1371 tmp =
1372 (0 <<
1373 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1374 (0 <<
1375 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1376 } else {
1377 if (connector->latency_present[0])
1378 tmp =
1379 (connector->video_latency[0] <<
1380 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1381 (connector->audio_latency[0] <<
1382 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1383 else
1384 tmp =
1385 (0 <<
1386 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1387 (0 <<
1388 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1389
1390 }
1391 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1392}
1393
1394static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1395{
1396 struct amdgpu_device *adev = encoder->dev->dev_private;
1397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1398 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1399 struct drm_connector *connector;
1400 struct amdgpu_connector *amdgpu_connector = NULL;
1401 u32 offset, tmp;
1402 u8 *sadb = NULL;
1403 int sad_count;
1404
1405 if (!dig || !dig->afmt || !dig->afmt->pin)
1406 return;
1407
1408 offset = dig->afmt->pin->offset;
1409
1410 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1411 if (connector->encoder == encoder) {
1412 amdgpu_connector = to_amdgpu_connector(connector);
1413 break;
1414 }
1415 }
1416
1417 if (!amdgpu_connector) {
1418 DRM_ERROR("Couldn't find encoder's connector\n");
1419 return;
1420 }
1421
1422 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1423 if (sad_count < 0) {
1424 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1425 sad_count = 0;
1426 }
1427
1428 /* program the speaker allocation */
1429 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1430 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1431 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1432 /* set HDMI mode */
1433 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1434 if (sad_count)
1435 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1436 else
1437 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1438 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1439
1440 kfree(sadb);
1441}
1442
1443static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1444{
1445 struct amdgpu_device *adev = encoder->dev->dev_private;
1446 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1447 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1448 u32 offset;
1449 struct drm_connector *connector;
1450 struct amdgpu_connector *amdgpu_connector = NULL;
1451 struct cea_sad *sads;
1452 int i, sad_count;
1453
1454 static const u16 eld_reg_to_type[][2] = {
1455 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1456 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1457 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1458 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1459 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1460 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1461 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1462 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1463 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1464 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1465 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1466 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1467 };
1468
1469 if (!dig || !dig->afmt || !dig->afmt->pin)
1470 return;
1471
1472 offset = dig->afmt->pin->offset;
1473
1474 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1475 if (connector->encoder == encoder) {
1476 amdgpu_connector = to_amdgpu_connector(connector);
1477 break;
1478 }
1479 }
1480
1481 if (!amdgpu_connector) {
1482 DRM_ERROR("Couldn't find encoder's connector\n");
1483 return;
1484 }
1485
1486 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1487 if (sad_count <= 0) {
1488 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1489 return;
1490 }
1491 BUG_ON(!sads);
1492
1493 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1494 u32 value = 0;
1495 u8 stereo_freqs = 0;
1496 int max_channels = -1;
1497 int j;
1498
1499 for (j = 0; j < sad_count; j++) {
1500 struct cea_sad *sad = &sads[j];
1501
1502 if (sad->format == eld_reg_to_type[i][1]) {
1503 if (sad->channels > max_channels) {
1504 value = (sad->channels <<
1505 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1506 (sad->byte2 <<
1507 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1508 (sad->freq <<
1509 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1510 max_channels = sad->channels;
1511 }
1512
1513 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1514 stereo_freqs |= sad->freq;
1515 else
1516 break;
1517 }
1518 }
1519
1520 value |= (stereo_freqs <<
1521 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1522
1523 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1524 }
1525
1526 kfree(sads);
1527}
1528
1529static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1530 struct amdgpu_audio_pin *pin,
1531 bool enable)
1532{
1533 if (!pin)
1534 return;
1535
1536 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1537 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1538}
1539
1540static const u32 pin_offsets[7] =
1541{
1542 (0x1780 - 0x1780),
1543 (0x1786 - 0x1780),
1544 (0x178c - 0x1780),
1545 (0x1792 - 0x1780),
1546 (0x1798 - 0x1780),
1547 (0x179d - 0x1780),
1548 (0x17a4 - 0x1780),
1549};
1550
1551static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1552{
1553 int i;
1554
1555 if (!amdgpu_audio)
1556 return 0;
1557
1558 adev->mode_info.audio.enabled = true;
1559
1560 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1561 adev->mode_info.audio.num_pins = 7;
1562 else if ((adev->asic_type == CHIP_KABINI) ||
1563 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1564 adev->mode_info.audio.num_pins = 3;
1565 else if ((adev->asic_type == CHIP_BONAIRE) ||
1566 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1567 adev->mode_info.audio.num_pins = 7;
1568 else
1569 adev->mode_info.audio.num_pins = 3;
1570
1571 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1572 adev->mode_info.audio.pin[i].channels = -1;
1573 adev->mode_info.audio.pin[i].rate = -1;
1574 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1575 adev->mode_info.audio.pin[i].status_bits = 0;
1576 adev->mode_info.audio.pin[i].category_code = 0;
1577 adev->mode_info.audio.pin[i].connected = false;
1578 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1579 adev->mode_info.audio.pin[i].id = i;
1580 /* disable audio. it will be set up later */
1581 /* XXX remove once we switch to ip funcs */
1582 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1583 }
1584
1585 return 0;
1586}
1587
1588static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1589{
1590 int i;
1591
84cffef1
TSD		 1592 if (!amdgpu_audio)
1593 return;
1594
a2e73f56
AD		 1595 if (!adev->mode_info.audio.enabled)
1596 return;
1597
1598 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1599 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1600
1601 adev->mode_info.audio.enabled = false;
1602}
1603
1604/*
1605 * update the N and CTS parameters for a given pixel clock rate
1606 */
1607static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1608{
1609 struct drm_device *dev = encoder->dev;
1610 struct amdgpu_device *adev = dev->dev_private;
1611 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1613 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1614 uint32_t offset = dig->afmt->offset;
1615
1616 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1617 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1618
1619 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1620 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1621
1622 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1623 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1624}
1625
1626/*
1627 * build a HDMI Video Info Frame
1628 */
1629static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1630 void *buffer, size_t size)
1631{
1632 struct drm_device *dev = encoder->dev;
1633 struct amdgpu_device *adev = dev->dev_private;
1634 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1635 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1636 uint32_t offset = dig->afmt->offset;
1637 uint8_t *frame = buffer + 3;
1638 uint8_t *header = buffer;
1639
1640 WREG32(mmAFMT_AVI_INFO0 + offset,
1641 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1642 WREG32(mmAFMT_AVI_INFO1 + offset,
1643 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1644 WREG32(mmAFMT_AVI_INFO2 + offset,
1645 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1646 WREG32(mmAFMT_AVI_INFO3 + offset,
1647 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1648}
1649
1650static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1651{
1652 struct drm_device *dev = encoder->dev;
1653 struct amdgpu_device *adev = dev->dev_private;
1654 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1655 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1657 u32 dto_phase = 24 * 1000;
1658 u32 dto_modulo = clock;
1659
1660 if (!dig || !dig->afmt)
1661 return;
1662
1663 /* XXX two dtos; generally use dto0 for hdmi */
1664 /* Express [24MHz / target pixel clock] as an exact rational
1665 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1666 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1667 */
1668 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1669 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1670 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1671}
1672
1673/*
1674 * update the info frames with the data from the current display mode
1675 */
1676static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1677 struct drm_display_mode *mode)
1678{
1679 struct drm_device *dev = encoder->dev;
1680 struct amdgpu_device *adev = dev->dev_private;
1681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1682 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1683 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1684 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1685 struct hdmi_avi_infoframe frame;
1686 uint32_t offset, val;
1687 ssize_t err;
1688 int bpc = 8;
1689
1690 if (!dig || !dig->afmt)
1691 return;
1692
1693 /* Silent, r600_hdmi_enable will raise WARN for us */
1694 if (!dig->afmt->enabled)
1695 return;
1696 offset = dig->afmt->offset;
1697
1698 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1699 if (encoder->crtc) {
1700 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1701 bpc = amdgpu_crtc->bpc;
1702 }
1703
1704 /* disable audio prior to setting up hw */
1705 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1706 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1707
1708 dce_v8_0_audio_set_dto(encoder, mode->clock);
1709
1710 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1711 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1712
1713 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1714
1715 val = RREG32(mmHDMI_CONTROL + offset);
1716 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1717 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1718
1719 switch (bpc) {
1720 case 0:
1721 case 6:
1722 case 8:
1723 case 16:
1724 default:
1725 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1726 connector->name, bpc);
1727 break;
1728 case 10:
1729 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1730 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1731 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1732 connector->name);
1733 break;
1734 case 12:
1735 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1736 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1737 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1738 connector->name);
1739 break;
1740 }
1741
1742 WREG32(mmHDMI_CONTROL + offset, val);
1743
1744 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1745 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1746 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1747 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1748
1749 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1750 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1751 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1752
1753 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1754 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1755
1756 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1757 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1758
1759 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1760
1761 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1762 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1763 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1764
1765 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1766 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1767
1768 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1769
1770 if (bpc > 8)
1771 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1772 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1773 else
1774 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1775 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1776 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1777
1778 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1779
1780 WREG32(mmAFMT_60958_0 + offset,
1781 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1782
1783 WREG32(mmAFMT_60958_1 + offset,
1784 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1785
1786 WREG32(mmAFMT_60958_2 + offset,
1787 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1788 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1789 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1790 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1791 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1792 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1793
1794 dce_v8_0_audio_write_speaker_allocation(encoder);
1795
1796
1797 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1798 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1799
1800 dce_v8_0_afmt_audio_select_pin(encoder);
1801 dce_v8_0_audio_write_sad_regs(encoder);
1802 dce_v8_0_audio_write_latency_fields(encoder, mode);
1803
1804 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1805 if (err < 0) {
1806 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1807 return;
1808 }
1809
1810 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1811 if (err < 0) {
1812 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1813 return;
1814 }
1815
1816 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1817
1818 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1819 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1820 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */
1821
1822 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1823 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1824 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1825
1826 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1827 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1828
1829 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1830 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1831 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1832 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1833 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1834
1835 /* enable audio after to setting up hw */
1836 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1837}
1838
1839static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1840{
1841 struct drm_device *dev = encoder->dev;
1842 struct amdgpu_device *adev = dev->dev_private;
1843 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1844 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1845
1846 if (!dig || !dig->afmt)
1847 return;
1848
1849 /* Silent, r600_hdmi_enable will raise WARN for us */
1850 if (enable && dig->afmt->enabled)
1851 return;
1852 if (!enable && !dig->afmt->enabled)
1853 return;
1854
1855 if (!enable && dig->afmt->pin) {
1856 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1857 dig->afmt->pin = NULL;
1858 }
1859
1860 dig->afmt->enabled = enable;
1861
1862 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1863 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1864}
1865
ff923479 1866static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
a2e73f56
AD		 1867{
1868 int i;
1869
1870 for (i = 0; i < adev->mode_info.num_dig; i++)
1871 adev->mode_info.afmt[i] = NULL;
1872
1873 /* DCE8 has audio blocks tied to DIG encoders */
1874 for (i = 0; i < adev->mode_info.num_dig; i++) {
1875 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1876 if (adev->mode_info.afmt[i]) {
1877 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1878 adev->mode_info.afmt[i]->id = i;
ff923479
TSD		 1879 } else {
1880 int j;
1881 for (j = 0; j < i; j++) {
1882 kfree(adev->mode_info.afmt[j]);
1883 adev->mode_info.afmt[j] = NULL;
1884 }
1885 return -ENOMEM;
a2e73f56
AD		 1886 }
1887 }
ff923479 1888 return 0;
a2e73f56
AD		 1889}
1890
1891static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1892{
1893 int i;
1894
1895 for (i = 0; i < adev->mode_info.num_dig; i++) {
1896 kfree(adev->mode_info.afmt[i]);
1897 adev->mode_info.afmt[i] = NULL;
1898 }
1899}
1900
1901static const u32 vga_control_regs[6] =
1902{
1903 mmD1VGA_CONTROL,
1904 mmD2VGA_CONTROL,
1905 mmD3VGA_CONTROL,
1906 mmD4VGA_CONTROL,
1907 mmD5VGA_CONTROL,
1908 mmD6VGA_CONTROL,
1909};
1910
1911static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1912{
1913 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1914 struct drm_device *dev = crtc->dev;
1915 struct amdgpu_device *adev = dev->dev_private;
1916 u32 vga_control;
1917
1918 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1919 if (enable)
1920 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1921 else
1922 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1923}
1924
1925static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1926{
1927 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1928 struct drm_device *dev = crtc->dev;
1929 struct amdgpu_device *adev = dev->dev_private;
1930
1931 if (enable)
1932 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1933 else
1934 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1935}
1936
a2e73f56
AD		 1937static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1938 struct drm_framebuffer *fb,
1939 int x, int y, int atomic)
1940{
1941 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1942 struct drm_device *dev = crtc->dev;
1943 struct amdgpu_device *adev = dev->dev_private;
1944 struct amdgpu_framebuffer *amdgpu_fb;
1945 struct drm_framebuffer *target_fb;
1946 struct drm_gem_object *obj;
1947 struct amdgpu_bo *rbo;
1948 uint64_t fb_location, tiling_flags;
1949 uint32_t fb_format, fb_pitch_pixels;
a2e73f56 1950 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
fbd76d59 1951 u32 pipe_config;
cb9e59d7 1952 u32 viewport_w, viewport_h;
a2e73f56
AD		 1953 int r;
1954 bool bypass_lut = false;
90844f00 1955 const char *format_name;
a2e73f56
AD		 1956
1957 /* no fb bound */
1958 if (!atomic && !crtc->primary->fb) {
1959 DRM_DEBUG_KMS("No FB bound\n");
1960 return 0;
1961 }
1962
1963 if (atomic) {
1964 amdgpu_fb = to_amdgpu_framebuffer(fb);
1965 target_fb = fb;
92821c26 1966 } else {
a2e73f56
AD		 1967 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1968 target_fb = crtc->primary->fb;
1969 }
1970
1971 /* If atomic, assume fb object is pinned & idle & fenced and
1972 * just update base pointers
1973 */
1974 obj = amdgpu_fb->obj;
1975 rbo = gem_to_amdgpu_bo(obj);
1976 r = amdgpu_bo_reserve(rbo, false);
1977 if (unlikely(r != 0))
1978 return r;
1979
92821c26 1980 if (atomic) {
a2e73f56 1981 fb_location = amdgpu_bo_gpu_offset(rbo);
92821c26 1982 } else {
a2e73f56
AD		 1983 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1984 if (unlikely(r != 0)) {
1985 amdgpu_bo_unreserve(rbo);
1986 return -EINVAL;
1987 }
1988 }
1989
1990 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
1991 amdgpu_bo_unreserve(rbo);
1992
fbd76d59
MO		 1993 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1994
a2e73f56
AD		 1995 switch (target_fb->pixel_format) {
1996 case DRM_FORMAT_C8:
1997 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1998 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1999 break;
2000 case DRM_FORMAT_XRGB4444:
2001 case DRM_FORMAT_ARGB4444:
2002 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2003 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2004#ifdef __BIG_ENDIAN
2005 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2006#endif
2007 break;
2008 case DRM_FORMAT_XRGB1555:
2009 case DRM_FORMAT_ARGB1555:
2010 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2011 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2012#ifdef __BIG_ENDIAN
2013 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2014#endif
2015 break;
2016 case DRM_FORMAT_BGRX5551:
2017 case DRM_FORMAT_BGRA5551:
2018 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2019 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2020#ifdef __BIG_ENDIAN
2021 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2022#endif
2023 break;
2024 case DRM_FORMAT_RGB565:
2025 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2026 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2027#ifdef __BIG_ENDIAN
2028 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2029#endif
2030 break;
2031 case DRM_FORMAT_XRGB8888:
2032 case DRM_FORMAT_ARGB8888:
2033 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2034 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2035#ifdef __BIG_ENDIAN
2036 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2037#endif
2038 break;
2039 case DRM_FORMAT_XRGB2101010:
2040 case DRM_FORMAT_ARGB2101010:
2041 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2042 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2043#ifdef __BIG_ENDIAN
2044 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2045#endif
2046 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2047 bypass_lut = true;
2048 break;
2049 case DRM_FORMAT_BGRX1010102:
2050 case DRM_FORMAT_BGRA1010102:
2051 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2052 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2053#ifdef __BIG_ENDIAN
2054 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2055#endif
2056 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2057 bypass_lut = true;
2058 break;
2059 default:
90844f00
EE		 2060 format_name = drm_get_format_name(target_fb->pixel_format);
2061 DRM_ERROR("Unsupported screen format %s\n", format_name);
2062 kfree(format_name);
a2e73f56
AD		 2063 return -EINVAL;
2064 }
2065
fbd76d59
MO		 2066 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2067 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
a2e73f56 2068
fbd76d59
MO		 2069 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2070 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2071 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2072 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2073 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
a2e73f56 2074
a2e73f56
AD		 2075 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2076 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2077 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2078 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2079 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2080 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2081 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
fbd76d59 2082 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
a2e73f56
AD		 2083 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2084 }
2085
a2e73f56
AD		 2086 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2087
2088 dce_v8_0_vga_enable(crtc, false);
2089
cb9e59d7
AD		 2090 /* Make sure surface address is updated at vertical blank rather than
2091 * horizontal blank
2092 */
2093 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2094
a2e73f56
AD		 2095 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2096 upper_32_bits(fb_location));
2097 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2098 upper_32_bits(fb_location));
2099 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2100 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2101 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2102 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2103 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2104 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2105
2106 /*
2107 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2108 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2109 * retain the full precision throughout the pipeline.
2110 */
2111 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2112 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2113 ~LUT_10BIT_BYPASS_EN);
2114
2115 if (bypass_lut)
2116 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2117
2118 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2119 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2120 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2121 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2122 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2123 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2124
2125 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2126 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2127
2128 dce_v8_0_grph_enable(crtc, true);
2129
2130 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2131 target_fb->height);
2132
2133 x &= ~3;
2134 y &= ~1;
2135 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2136 (x << 16) | y);
2137 viewport_w = crtc->mode.hdisplay;
2138 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2139 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2140 (viewport_w << 16) | viewport_h);
2141
a2e73f56
AD		 2142 /* set pageflip to happen only at start of vblank interval (front porch) */
2143 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2144
2145 if (!atomic && fb && fb != crtc->primary->fb) {
2146 amdgpu_fb = to_amdgpu_framebuffer(fb);
2147 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2148 r = amdgpu_bo_reserve(rbo, false);
2149 if (unlikely(r != 0))
2150 return r;
2151 amdgpu_bo_unpin(rbo);
2152 amdgpu_bo_unreserve(rbo);
2153 }
2154
2155 /* Bytes per pixel may have changed */
2156 dce_v8_0_bandwidth_update(adev);
2157
2158 return 0;
2159}
2160
2161static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2162 struct drm_display_mode *mode)
2163{
2164 struct drm_device *dev = crtc->dev;
2165 struct amdgpu_device *adev = dev->dev_private;
2166 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2167
2168 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2169 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2170 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2171 else
2172 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2173}
2174
2175static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2176{
2177 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2178 struct drm_device *dev = crtc->dev;
2179 struct amdgpu_device *adev = dev->dev_private;
2180 int i;
2181
2182 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2183
2184 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2185 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2186 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2187 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2188 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2189 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2190 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2191 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2192 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2193 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2194
2195 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2196
2197 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2198 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2199 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2200
2201 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2202 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2203 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2204
2205 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2206 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2207
2208 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2209 for (i = 0; i < 256; i++) {
2210 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2211 (amdgpu_crtc->lut_r[i] << 20) |
2212 (amdgpu_crtc->lut_g[i] << 10) |
2213 (amdgpu_crtc->lut_b[i] << 0));
2214 }
2215
2216 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2217 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2218 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2219 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2220 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2221 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2222 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2223 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2224 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2225 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2226 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2227 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2228 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2229 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2230 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2231 /* XXX this only needs to be programmed once per crtc at startup,
2232 * not sure where the best place for it is
2233 */
2234 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2235 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2236}
2237
2238static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2239{
2240 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2241 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2242
2243 switch (amdgpu_encoder->encoder_id) {
2244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2245 if (dig->linkb)
2246 return 1;
2247 else
2248 return 0;
2249 break;
2250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2251 if (dig->linkb)
2252 return 3;
2253 else
2254 return 2;
2255 break;
2256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2257 if (dig->linkb)
2258 return 5;
2259 else
2260 return 4;
2261 break;
2262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2263 return 6;
2264 break;
2265 default:
2266 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2267 return 0;
2268 }
2269}
2270
2271/**
2272 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2273 *
2274 * @crtc: drm crtc
2275 *
2276 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2277 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2278 * monitors a dedicated PPLL must be used. If a particular board has
2279 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2280 * as there is no need to program the PLL itself. If we are not able to
2281 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2282 * avoid messing up an existing monitor.
2283 *
2284 * Asic specific PLL information
2285 *
2286 * DCE 8.x
2287 * KB/KV
2288 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2289 * CI
2290 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2291 *
2292 */
2293static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2294{
2295 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2296 struct drm_device *dev = crtc->dev;
2297 struct amdgpu_device *adev = dev->dev_private;
2298 u32 pll_in_use;
2299 int pll;
2300
2301 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2302 if (adev->clock.dp_extclk)
2303 /* skip PPLL programming if using ext clock */
2304 return ATOM_PPLL_INVALID;
2305 else {
2306 /* use the same PPLL for all DP monitors */
2307 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2308 if (pll != ATOM_PPLL_INVALID)
2309 return pll;
2310 }
2311 } else {
2312 /* use the same PPLL for all monitors with the same clock */
2313 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2314 if (pll != ATOM_PPLL_INVALID)
2315 return pll;
2316 }
2317 /* otherwise, pick one of the plls */
2318 if ((adev->asic_type == CHIP_KABINI) ||
2319 (adev->asic_type == CHIP_MULLINS)) {
2320 /* KB/ML has PPLL1 and PPLL2 */
2321 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2322 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2323 return ATOM_PPLL2;
2324 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2325 return ATOM_PPLL1;
2326 DRM_ERROR("unable to allocate a PPLL\n");
2327 return ATOM_PPLL_INVALID;
2328 } else {
2329 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2330 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2331 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2332 return ATOM_PPLL2;
2333 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2334 return ATOM_PPLL1;
2335 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2336 return ATOM_PPLL0;
2337 DRM_ERROR("unable to allocate a PPLL\n");
2338 return ATOM_PPLL_INVALID;
2339 }
2340 return ATOM_PPLL_INVALID;
2341}
2342
2343static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2344{
2345 struct amdgpu_device *adev = crtc->dev->dev_private;
2346 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2347 uint32_t cur_lock;
2348
2349 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2350 if (lock)
2351 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2352 else
2353 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2354 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2355}
2356
2357static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2358{
2359 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2360 struct amdgpu_device *adev = crtc->dev->dev_private;
2361
2362 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2363 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2364 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2365}
2366
2367static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2368{
2369 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2370 struct amdgpu_device *adev = crtc->dev->dev_private;
2371
a2df42da
AD		 2372 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2373 upper_32_bits(amdgpu_crtc->cursor_addr));
2374 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2375 lower_32_bits(amdgpu_crtc->cursor_addr));
2376
a2e73f56
AD		 2377 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2378 CUR_CONTROL__CURSOR_EN_MASK |
2379 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2380 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2381}
2382
77ed35b8
AD		 2383static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2384 int x, int y)
a2e73f56
AD		 2385{
2386 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2387 struct amdgpu_device *adev = crtc->dev->dev_private;
2388 int xorigin = 0, yorigin = 0;
2389
2390 /* avivo cursor are offset into the total surface */
2391 x += crtc->x;
2392 y += crtc->y;
2393 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2394
2395 if (x < 0) {
2396 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2397 x = 0;
2398 }
2399 if (y < 0) {
2400 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2401 y = 0;
2402 }
2403
a2e73f56
AD		 2404 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2405 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2406 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2407 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
77ed35b8
AD		 2408
2409 amdgpu_crtc->cursor_x = x;
2410 amdgpu_crtc->cursor_y = y;
a2e73f56
AD		 2411
2412 return 0;
2413}
2414
77ed35b8
AD		 2415static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2416 int x, int y)
2417{
2418 int ret;
2419
2420 dce_v8_0_lock_cursor(crtc, true);
2421 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2422 dce_v8_0_lock_cursor(crtc, false);
2423
2424 return ret;
2425}
2426
2427static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2428 struct drm_file *file_priv,
2429 uint32_t handle,
2430 uint32_t width,
2431 uint32_t height,
2432 int32_t hot_x,
2433 int32_t hot_y)
a2e73f56
AD		 2434{
2435 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2436 struct drm_gem_object *obj;
72b40067 2437 struct amdgpu_bo *aobj;
a2e73f56
AD		 2438 int ret;
2439
2440 if (!handle) {
2441 /* turn off cursor */
2442 dce_v8_0_hide_cursor(crtc);
2443 obj = NULL;
2444 goto unpin;
2445 }
2446
2447 if ((width > amdgpu_crtc->max_cursor_width) ||
2448 (height > amdgpu_crtc->max_cursor_height)) {
2449 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2450 return -EINVAL;
2451 }
2452
a8ad0bd8 2453 obj = drm_gem_object_lookup(file_priv, handle);
a2e73f56
AD		 2454 if (!obj) {
2455 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2456 return -ENOENT;
2457 }
2458
72b40067
AD		 2459 aobj = gem_to_amdgpu_bo(obj);
2460 ret = amdgpu_bo_reserve(aobj, false);
2461 if (ret != 0) {
2462 drm_gem_object_unreference_unlocked(obj);
2463 return ret;
2464 }
2465
2466 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2467 amdgpu_bo_unreserve(aobj);
2468 if (ret) {
2469 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2470 drm_gem_object_unreference_unlocked(obj);
2471 return ret;
2472 }
a2e73f56
AD		 2473
2474 amdgpu_crtc->cursor_width = width;
2475 amdgpu_crtc->cursor_height = height;
2476
2477 dce_v8_0_lock_cursor(crtc, true);
c4e0dfad
AD		 2478
2479 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2480 hot_y != amdgpu_crtc->cursor_hot_y) {
2481 int x, y;
2482
2483 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2484 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2485
2486 dce_v8_0_cursor_move_locked(crtc, x, y);
2487
2488 amdgpu_crtc->cursor_hot_x = hot_x;
2489 amdgpu_crtc->cursor_hot_y = hot_y;
2490 }
2491
a2e73f56
AD		 2492 dce_v8_0_show_cursor(crtc);
2493 dce_v8_0_lock_cursor(crtc, false);
2494
2495unpin:
2496 if (amdgpu_crtc->cursor_bo) {
fd70cf63
AD		 2497 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2498 ret = amdgpu_bo_reserve(aobj, false);
a2e73f56 2499 if (likely(ret == 0)) {
fd70cf63
AD		 2500 amdgpu_bo_unpin(aobj);
2501 amdgpu_bo_unreserve(aobj);
a2e73f56
AD		 2502 }
2503 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2504 }
2505
2506 amdgpu_crtc->cursor_bo = obj;
2507 return 0;
fd70cf63 2508}
a2e73f56 2509
fd70cf63
AD		 2510static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2511{
2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
fd70cf63
AD		 2513
2514 if (amdgpu_crtc->cursor_bo) {
2515 dce_v8_0_lock_cursor(crtc, true);
2516
2517 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2518 amdgpu_crtc->cursor_y);
2519
72b40067 2520 dce_v8_0_show_cursor(crtc);
fd70cf63
AD		 2521
2522 dce_v8_0_lock_cursor(crtc, false);
2523 }
a2e73f56
AD		 2524}
2525
7ea77283
ML		 2526static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2527 u16 *blue, uint32_t size)
a2e73f56
AD		 2528{
2529 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7ea77283 2530 int i;
a2e73f56
AD		 2531
2532 /* userspace palettes are always correct as is */
7ea77283 2533 for (i = 0; i < size; i++) {
a2e73f56
AD		 2534 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2535 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2536 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2537 }
2538 dce_v8_0_crtc_load_lut(crtc);
7ea77283
ML		 2539
2540 return 0;
a2e73f56
AD		 2541}
2542
2543static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2544{
2545 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2546
2547 drm_crtc_cleanup(crtc);
a2e73f56
AD		 2548 kfree(amdgpu_crtc);
2549}
2550
2551static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
77ed35b8 2552 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
a2e73f56
AD		 2553 .cursor_move = dce_v8_0_crtc_cursor_move,
2554 .gamma_set = dce_v8_0_crtc_gamma_set,
2555 .set_config = amdgpu_crtc_set_config,
2556 .destroy = dce_v8_0_crtc_destroy,
2557 .page_flip = amdgpu_crtc_page_flip,
2558};
2559
2560static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2561{
2562 struct drm_device *dev = crtc->dev;
2563 struct amdgpu_device *adev = dev->dev_private;
2564 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1002d718 2565 unsigned type;
a2e73f56
AD		 2566
2567 switch (mode) {
2568 case DRM_MODE_DPMS_ON:
2569 amdgpu_crtc->enabled = true;
2570 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2571 dce_v8_0_vga_enable(crtc, true);
2572 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2573 dce_v8_0_vga_enable(crtc, false);
f6c7aba4 2574 /* Make sure VBLANK and PFLIP interrupts are still enabled */
1002d718
MD		 2575 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2576 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2577 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
9a7841e9 2578 drm_crtc_vblank_on(crtc);
a2e73f56
AD		 2579 dce_v8_0_crtc_load_lut(crtc);
2580 break;
2581 case DRM_MODE_DPMS_STANDBY:
2582 case DRM_MODE_DPMS_SUSPEND:
2583 case DRM_MODE_DPMS_OFF:
9a7841e9 2584 drm_crtc_vblank_off(crtc);
a2e73f56
AD		 2585 if (amdgpu_crtc->enabled) {
2586 dce_v8_0_vga_enable(crtc, true);
2587 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2588 dce_v8_0_vga_enable(crtc, false);
2589 }
2590 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2591 amdgpu_crtc->enabled = false;
2592 break;
2593 }
2594 /* adjust pm to dpms */
2595 amdgpu_pm_compute_clocks(adev);
2596}
2597
2598static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2599{
2600 /* disable crtc pair power gating before programming */
2601 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2602 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2603 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2604}
2605
2606static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2607{
2608 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2609 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2610}
2611
2612static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2613{
2614 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2615 struct drm_device *dev = crtc->dev;
2616 struct amdgpu_device *adev = dev->dev_private;
2617 struct amdgpu_atom_ss ss;
2618 int i;
2619
2620 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2621 if (crtc->primary->fb) {
2622 int r;
2623 struct amdgpu_framebuffer *amdgpu_fb;
2624 struct amdgpu_bo *rbo;
2625
2626 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2627 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2628 r = amdgpu_bo_reserve(rbo, false);
2629 if (unlikely(r))
2630 DRM_ERROR("failed to reserve rbo before unpin\n");
2631 else {
2632 amdgpu_bo_unpin(rbo);
2633 amdgpu_bo_unreserve(rbo);
2634 }
2635 }
2636 /* disable the GRPH */
2637 dce_v8_0_grph_enable(crtc, false);
2638
2639 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2640
2641 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2642 if (adev->mode_info.crtcs[i] &&
2643 adev->mode_info.crtcs[i]->enabled &&
2644 i != amdgpu_crtc->crtc_id &&
2645 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2646 /* one other crtc is using this pll don't turn
2647 * off the pll
2648 */
2649 goto done;
2650 }
2651 }
2652
2653 switch (amdgpu_crtc->pll_id) {
2654 case ATOM_PPLL1:
2655 case ATOM_PPLL2:
2656 /* disable the ppll */
2657 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2658 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2659 break;
2660 case ATOM_PPLL0:
2661 /* disable the ppll */
2662 if ((adev->asic_type == CHIP_KAVERI) ||
2663 (adev->asic_type == CHIP_BONAIRE) ||
2664 (adev->asic_type == CHIP_HAWAII))
2665 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2666 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2667 break;
2668 default:
2669 break;
2670 }
2671done:
2672 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2673 amdgpu_crtc->adjusted_clock = 0;
2674 amdgpu_crtc->encoder = NULL;
2675 amdgpu_crtc->connector = NULL;
2676}
2677
2678static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2679 struct drm_display_mode *mode,
2680 struct drm_display_mode *adjusted_mode,
2681 int x, int y, struct drm_framebuffer *old_fb)
2682{
2683 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2684
2685 if (!amdgpu_crtc->adjusted_clock)
2686 return -EINVAL;
2687
2688 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2689 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2690 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2691 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2692 amdgpu_atombios_crtc_scaler_setup(crtc);
fd70cf63 2693 dce_v8_0_cursor_reset(crtc);
a2e73f56
AD		 2694 /* update the hw version fpr dpm */
2695 amdgpu_crtc->hw_mode = *adjusted_mode;
2696
2697 return 0;
2698}
2699
2700static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2701 const struct drm_display_mode *mode,
2702 struct drm_display_mode *adjusted_mode)
2703{
2704 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2705 struct drm_device *dev = crtc->dev;
2706 struct drm_encoder *encoder;
2707
2708 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2709 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2710 if (encoder->crtc == crtc) {
2711 amdgpu_crtc->encoder = encoder;
2712 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2713 break;
2714 }
2715 }
2716 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2717 amdgpu_crtc->encoder = NULL;
2718 amdgpu_crtc->connector = NULL;
2719 return false;
2720 }
2721 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2722 return false;
2723 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2724 return false;
2725 /* pick pll */
2726 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2727 /* if we can't get a PPLL for a non-DP encoder, fail */
2728 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2729 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2730 return false;
2731
2732 return true;
2733}
2734
2735static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2736 struct drm_framebuffer *old_fb)
2737{
2738 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2739}
2740
2741static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2742 struct drm_framebuffer *fb,
2743 int x, int y, enum mode_set_atomic state)
2744{
2745 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2746}
2747
2748static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2749 .dpms = dce_v8_0_crtc_dpms,
2750 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2751 .mode_set = dce_v8_0_crtc_mode_set,
2752 .mode_set_base = dce_v8_0_crtc_set_base,
2753 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2754 .prepare = dce_v8_0_crtc_prepare,
2755 .commit = dce_v8_0_crtc_commit,
2756 .load_lut = dce_v8_0_crtc_load_lut,
2757 .disable = dce_v8_0_crtc_disable,
2758};
2759
2760static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2761{
2762 struct amdgpu_crtc *amdgpu_crtc;
2763 int i;
2764
2765 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2766 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2767 if (amdgpu_crtc == NULL)
2768 return -ENOMEM;
2769
2770 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2771
2772 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2773 amdgpu_crtc->crtc_id = index;
a2e73f56
AD		 2774 adev->mode_info.crtcs[index] = amdgpu_crtc;
2775
2776 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2777 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2778 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2779 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2780
2781 for (i = 0; i < 256; i++) {
2782 amdgpu_crtc->lut_r[i] = i << 2;
2783 amdgpu_crtc->lut_g[i] = i << 2;
2784 amdgpu_crtc->lut_b[i] = i << 2;
2785 }
2786
2787 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2788
2789 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2790 amdgpu_crtc->adjusted_clock = 0;
2791 amdgpu_crtc->encoder = NULL;
2792 amdgpu_crtc->connector = NULL;
2793 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2794
2795 return 0;
2796}
2797
5fc3aeeb 2798static int dce_v8_0_early_init(void *handle)
a2e73f56 2799{
5fc3aeeb 2800 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2801
a2e73f56
AD		 2802 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2803 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2804
2805 dce_v8_0_set_display_funcs(adev);
2806 dce_v8_0_set_irq_funcs(adev);
2807
2808 switch (adev->asic_type) {
2809 case CHIP_BONAIRE:
2810 case CHIP_HAWAII:
2811 adev->mode_info.num_crtc = 6;
2812 adev->mode_info.num_hpd = 6;
2813 adev->mode_info.num_dig = 6;
2814 break;
2815 case CHIP_KAVERI:
2816 adev->mode_info.num_crtc = 4;
2817 adev->mode_info.num_hpd = 6;
2818 adev->mode_info.num_dig = 7;
2819 break;
2820 case CHIP_KABINI:
2821 case CHIP_MULLINS:
2822 adev->mode_info.num_crtc = 2;
2823 adev->mode_info.num_hpd = 6;
2824 adev->mode_info.num_dig = 6; /* ? */
2825 break;
2826 default:
2827 /* FIXME: not supported yet */
2828 return -EINVAL;
2829 }
2830
2831 return 0;
2832}
2833
5fc3aeeb 2834static int dce_v8_0_sw_init(void *handle)
a2e73f56
AD		 2835{
2836 int r, i;
5fc3aeeb 2837 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2838
2839 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2840 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2841 if (r)
2842 return r;
2843 }
2844
2845 for (i = 8; i < 20; i += 2) {
2846 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2847 if (r)
2848 return r;
2849 }
2850
2851 /* HPD hotplug */
2852 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2853 if (r)
2854 return r;
2855
a2e73f56
AD		 2856 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2857
cb9e59d7
AD		 2858 adev->ddev->mode_config.async_page_flip = true;
2859
a2e73f56
AD		 2860 adev->ddev->mode_config.max_width = 16384;
2861 adev->ddev->mode_config.max_height = 16384;
2862
2863 adev->ddev->mode_config.preferred_depth = 24;
2864 adev->ddev->mode_config.prefer_shadow = 1;
2865
2866 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2867
2868 r = amdgpu_modeset_create_props(adev);
2869 if (r)
2870 return r;
2871
2872 adev->ddev->mode_config.max_width = 16384;
2873 adev->ddev->mode_config.max_height = 16384;
2874
2875 /* allocate crtcs */
2876 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2877 r = dce_v8_0_crtc_init(adev, i);
2878 if (r)
2879 return r;
2880 }
2881
2882 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2883 amdgpu_print_display_setup(adev->ddev);
2884 else
2885 return -EINVAL;
2886
2887 /* setup afmt */
ff923479
TSD		 2888 r = dce_v8_0_afmt_init(adev);
2889 if (r)
2890 return r;
a2e73f56
AD		 2891
2892 r = dce_v8_0_audio_init(adev);
2893 if (r)
2894 return r;
2895
2896 drm_kms_helper_poll_init(adev->ddev);
2897
74c1e842
TSD		 2898 adev->mode_info.mode_config_initialized = true;
2899 return 0;
a2e73f56
AD		 2900}
2901
5fc3aeeb 2902static int dce_v8_0_sw_fini(void *handle)
a2e73f56 2903{
5fc3aeeb 2904 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2905
a2e73f56
AD		 2906 kfree(adev->mode_info.bios_hardcoded_edid);
2907
2908 drm_kms_helper_poll_fini(adev->ddev);
2909
2910 dce_v8_0_audio_fini(adev);
2911
2912 dce_v8_0_afmt_fini(adev);
2913
2914 drm_mode_config_cleanup(adev->ddev);
2915 adev->mode_info.mode_config_initialized = false;
2916
2917 return 0;
2918}
2919
5fc3aeeb 2920static int dce_v8_0_hw_init(void *handle)
a2e73f56
AD		 2921{
2922 int i;
5fc3aeeb 2923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2924
2925 /* init dig PHYs, disp eng pll */
2926 amdgpu_atombios_encoder_init_dig(adev);
2927 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2928
2929 /* initialize hpd */
2930 dce_v8_0_hpd_init(adev);
2931
2932 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2933 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2934 }
2935
f6c7aba4
MD		 2936 dce_v8_0_pageflip_interrupt_init(adev);
2937
a2e73f56
AD		 2938 return 0;
2939}
2940
5fc3aeeb 2941static int dce_v8_0_hw_fini(void *handle)
a2e73f56
AD		 2942{
2943 int i;
5fc3aeeb 2944 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2945
2946 dce_v8_0_hpd_fini(adev);
2947
2948 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2949 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2950 }
2951
f6c7aba4
MD		 2952 dce_v8_0_pageflip_interrupt_fini(adev);
2953
a2e73f56
AD		 2954 return 0;
2955}
2956
5fc3aeeb 2957static int dce_v8_0_suspend(void *handle)
a2e73f56 2958{
5fc3aeeb 2959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 2960
a2e73f56
AD		 2961 amdgpu_atombios_scratch_regs_save(adev);
2962
f9fff064 2963 return dce_v8_0_hw_fini(handle);
a2e73f56
AD		 2964}
2965
5fc3aeeb 2966static int dce_v8_0_resume(void *handle)
a2e73f56 2967{
5fc3aeeb 2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064
AD		 2969 int ret;
2970
2971 ret = dce_v8_0_hw_init(handle);
a2e73f56
AD		 2972
2973 amdgpu_atombios_scratch_regs_restore(adev);
2974
a2e73f56
AD		 2975 /* turn on the BL */
2976 if (adev->mode_info.bl_encoder) {
2977 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2978 adev->mode_info.bl_encoder);
2979 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2980 bl_level);
2981 }
2982
f9fff064 2983 return ret;
a2e73f56
AD		 2984}
2985
5fc3aeeb 2986static bool dce_v8_0_is_idle(void *handle)
a2e73f56 2987{
a2e73f56
AD		 2988 return true;
2989}
2990
5fc3aeeb 2991static int dce_v8_0_wait_for_idle(void *handle)
a2e73f56 2992{
a2e73f56
AD		 2993 return 0;
2994}
2995
5fc3aeeb 2996static int dce_v8_0_soft_reset(void *handle)
a2e73f56
AD		 2997{
2998 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 2999 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 3000
3001 if (dce_v8_0_is_display_hung(adev))
3002 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3003
3004 if (srbm_soft_reset) {
a2e73f56
AD		 3005 tmp = RREG32(mmSRBM_SOFT_RESET);
3006 tmp |= srbm_soft_reset;
3007 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3008 WREG32(mmSRBM_SOFT_RESET, tmp);
3009 tmp = RREG32(mmSRBM_SOFT_RESET);
3010
3011 udelay(50);
3012
3013 tmp &= ~srbm_soft_reset;
3014 WREG32(mmSRBM_SOFT_RESET, tmp);
3015 tmp = RREG32(mmSRBM_SOFT_RESET);
3016
3017 /* Wait a little for things to settle down */
3018 udelay(50);
a2e73f56
AD		 3019 }
3020 return 0;
3021}
3022
3023static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3024 int crtc,
3025 enum amdgpu_interrupt_state state)
3026{
3027 u32 reg_block, lb_interrupt_mask;
3028
3029 if (crtc >= adev->mode_info.num_crtc) {
3030 DRM_DEBUG("invalid crtc %d\n", crtc);
3031 return;
3032 }
3033
3034 switch (crtc) {
3035 case 0:
3036 reg_block = CRTC0_REGISTER_OFFSET;
3037 break;
3038 case 1:
3039 reg_block = CRTC1_REGISTER_OFFSET;
3040 break;
3041 case 2:
3042 reg_block = CRTC2_REGISTER_OFFSET;
3043 break;
3044 case 3:
3045 reg_block = CRTC3_REGISTER_OFFSET;
3046 break;
3047 case 4:
3048 reg_block = CRTC4_REGISTER_OFFSET;
3049 break;
3050 case 5:
3051 reg_block = CRTC5_REGISTER_OFFSET;
3052 break;
3053 default:
3054 DRM_DEBUG("invalid crtc %d\n", crtc);
3055 return;
3056 }
3057
3058 switch (state) {
3059 case AMDGPU_IRQ_STATE_DISABLE:
3060 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3061 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3062 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3063 break;
3064 case AMDGPU_IRQ_STATE_ENABLE:
3065 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3066 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3067 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3068 break;
3069 default:
3070 break;
3071 }
3072}
3073
3074static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3075 int crtc,
3076 enum amdgpu_interrupt_state state)
3077{
3078 u32 reg_block, lb_interrupt_mask;
3079
3080 if (crtc >= adev->mode_info.num_crtc) {
3081 DRM_DEBUG("invalid crtc %d\n", crtc);
3082 return;
3083 }
3084
3085 switch (crtc) {
3086 case 0:
3087 reg_block = CRTC0_REGISTER_OFFSET;
3088 break;
3089 case 1:
3090 reg_block = CRTC1_REGISTER_OFFSET;
3091 break;
3092 case 2:
3093 reg_block = CRTC2_REGISTER_OFFSET;
3094 break;
3095 case 3:
3096 reg_block = CRTC3_REGISTER_OFFSET;
3097 break;
3098 case 4:
3099 reg_block = CRTC4_REGISTER_OFFSET;
3100 break;
3101 case 5:
3102 reg_block = CRTC5_REGISTER_OFFSET;
3103 break;
3104 default:
3105 DRM_DEBUG("invalid crtc %d\n", crtc);
3106 return;
3107 }
3108
3109 switch (state) {
3110 case AMDGPU_IRQ_STATE_DISABLE:
3111 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3112 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3113 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3114 break;
3115 case AMDGPU_IRQ_STATE_ENABLE:
3116 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3117 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3118 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3119 break;
3120 default:
3121 break;
3122 }
3123}
3124
3125static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3126 struct amdgpu_irq_src *src,
3127 unsigned type,
3128 enum amdgpu_interrupt_state state)
3129{
3130 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3131
3132 switch (type) {
3133 case AMDGPU_HPD_1:
3134 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3135 break;
3136 case AMDGPU_HPD_2:
3137 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3138 break;
3139 case AMDGPU_HPD_3:
3140 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3141 break;
3142 case AMDGPU_HPD_4:
3143 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3144 break;
3145 case AMDGPU_HPD_5:
3146 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3147 break;
3148 case AMDGPU_HPD_6:
3149 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3150 break;
3151 default:
3152 DRM_DEBUG("invalid hdp %d\n", type);
3153 return 0;
3154 }
3155
3156 switch (state) {
3157 case AMDGPU_IRQ_STATE_DISABLE:
3158 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3159 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3160 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3161 break;
3162 case AMDGPU_IRQ_STATE_ENABLE:
3163 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3164 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3165 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3166 break;
3167 default:
3168 break;
3169 }
3170
3171 return 0;
3172}
3173
3174static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3175 struct amdgpu_irq_src *src,
3176 unsigned type,
3177 enum amdgpu_interrupt_state state)
3178{
3179 switch (type) {
3180 case AMDGPU_CRTC_IRQ_VBLANK1:
3181 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3182 break;
3183 case AMDGPU_CRTC_IRQ_VBLANK2:
3184 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3185 break;
3186 case AMDGPU_CRTC_IRQ_VBLANK3:
3187 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3188 break;
3189 case AMDGPU_CRTC_IRQ_VBLANK4:
3190 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3191 break;
3192 case AMDGPU_CRTC_IRQ_VBLANK5:
3193 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3194 break;
3195 case AMDGPU_CRTC_IRQ_VBLANK6:
3196 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3197 break;
3198 case AMDGPU_CRTC_IRQ_VLINE1:
3199 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3200 break;
3201 case AMDGPU_CRTC_IRQ_VLINE2:
3202 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3203 break;
3204 case AMDGPU_CRTC_IRQ_VLINE3:
3205 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3206 break;
3207 case AMDGPU_CRTC_IRQ_VLINE4:
3208 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3209 break;
3210 case AMDGPU_CRTC_IRQ_VLINE5:
3211 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3212 break;
3213 case AMDGPU_CRTC_IRQ_VLINE6:
3214 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3215 break;
3216 default:
3217 break;
3218 }
3219 return 0;
3220}
3221
3222static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3223 struct amdgpu_irq_src *source,
3224 struct amdgpu_iv_entry *entry)
3225{
3226 unsigned crtc = entry->src_id - 1;
3227 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3228 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3229
3230 switch (entry->src_data) {
3231 case 0: /* vblank */
bd833144 3232 if (disp_int & interrupt_status_offsets[crtc].vblank)
a2e73f56 3233 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
bd833144
MK		 3234 else
3235 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3236
3237 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3238 drm_handle_vblank(adev->ddev, crtc);
a2e73f56 3239 }
bd833144
MK		 3240 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3241
a2e73f56
AD		 3242 break;
3243 case 1: /* vline */
bd833144 3244 if (disp_int & interrupt_status_offsets[crtc].vline)
a2e73f56 3245 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
bd833144
MK		 3246 else
3247 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3248
3249 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3250
a2e73f56
AD		 3251 break;
3252 default:
3253 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3254 break;
3255 }
3256
3257 return 0;
3258}
3259
3260static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *src,
3262 unsigned type,
3263 enum amdgpu_interrupt_state state)
3264{
7dfac896
AD		 3265 u32 reg;
3266
3267 if (type >= adev->mode_info.num_crtc) {
3268 DRM_ERROR("invalid pageflip crtc %d\n", type);
3269 return -EINVAL;
a2e73f56
AD		 3270 }
3271
7dfac896 3272 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
a2e73f56 3273 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3274 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3275 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56 3276 else
7dfac896
AD		 3277 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3278 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56
AD		 3279
3280 return 0;
3281}
3282
3283static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3284 struct amdgpu_irq_src *source,
3285 struct amdgpu_iv_entry *entry)
3286{
a2e73f56
AD		 3287 unsigned long flags;
3288 unsigned crtc_id;
3289 struct amdgpu_crtc *amdgpu_crtc;
3290 struct amdgpu_flip_work *works;
3291
3292 crtc_id = (entry->src_id - 8) >> 1;
3293 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3294
7dfac896
AD		 3295 if (crtc_id >= adev->mode_info.num_crtc) {
3296 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3297 return -EINVAL;
a2e73f56
AD		 3298 }
3299
7dfac896
AD		 3300 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3301 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3302 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3303 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
a2e73f56
AD		 3304
3305 /* IRQ could occur when in initial stage */
3306 if (amdgpu_crtc == NULL)
3307 return 0;
3308
3309 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3310 works = amdgpu_crtc->pflip_works;
3311 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3312 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3313 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3314 amdgpu_crtc->pflip_status,
3315 AMDGPU_FLIP_SUBMITTED);
3316 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3317 return 0;
3318 }
3319
3320 /* page flip completed. clean up */
3321 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3322 amdgpu_crtc->pflip_works = NULL;
3323
3324 /* wakeup usersapce */
3325 if (works->event)
56286769 3326 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
a2e73f56
AD		 3327
3328 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3329
60629c4d 3330 drm_crtc_vblank_put(&amdgpu_crtc->base);
87d58c11 3331 schedule_work(&works->unpin_work);
a2e73f56
AD		 3332
3333 return 0;
3334}
3335
3336static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3337 struct amdgpu_irq_src *source,
3338 struct amdgpu_iv_entry *entry)
3339{
3340 uint32_t disp_int, mask, int_control, tmp;
3341 unsigned hpd;
3342
e922cfb1 3343 if (entry->src_data >= adev->mode_info.num_hpd) {
a2e73f56
AD		 3344 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3345 return 0;
3346 }
3347
3348 hpd = entry->src_data;
3349 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3350 mask = interrupt_status_offsets[hpd].hpd;
3351 int_control = hpd_int_control_offsets[hpd];
3352
3353 if (disp_int & mask) {
3354 tmp = RREG32(int_control);
3355 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3356 WREG32(int_control, tmp);
3357 schedule_work(&adev->hotplug_work);
3358 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3359 }
3360
3361 return 0;
3362
3363}
3364
5fc3aeeb 3365static int dce_v8_0_set_clockgating_state(void *handle,
3366 enum amd_clockgating_state state)
a2e73f56
AD		 3367{
3368 return 0;
3369}
3370
5fc3aeeb 3371static int dce_v8_0_set_powergating_state(void *handle,
3372 enum amd_powergating_state state)
a2e73f56
AD		 3373{
3374 return 0;
3375}
3376
5fc3aeeb 3377const struct amd_ip_funcs dce_v8_0_ip_funcs = {
88a907d6 3378 .name = "dce_v8_0",
a2e73f56
AD		 3379 .early_init = dce_v8_0_early_init,
3380 .late_init = NULL,
3381 .sw_init = dce_v8_0_sw_init,
3382 .sw_fini = dce_v8_0_sw_fini,
3383 .hw_init = dce_v8_0_hw_init,
3384 .hw_fini = dce_v8_0_hw_fini,
3385 .suspend = dce_v8_0_suspend,
3386 .resume = dce_v8_0_resume,
3387 .is_idle = dce_v8_0_is_idle,
3388 .wait_for_idle = dce_v8_0_wait_for_idle,
3389 .soft_reset = dce_v8_0_soft_reset,
a2e73f56
AD		 3390 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3391 .set_powergating_state = dce_v8_0_set_powergating_state,
3392};
3393
3394static void
3395dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3396 struct drm_display_mode *mode,
3397 struct drm_display_mode *adjusted_mode)
3398{
3399 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3400
3401 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3402
3403 /* need to call this here rather than in prepare() since we need some crtc info */
3404 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3405
3406 /* set scaler clears this on some chips */
3407 dce_v8_0_set_interleave(encoder->crtc, mode);
3408
3409 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3410 dce_v8_0_afmt_enable(encoder, true);
3411 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3412 }
3413}
3414
3415static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3416{
3417 struct amdgpu_device *adev = encoder->dev->dev_private;
3418 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3419 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3420
3421 if ((amdgpu_encoder->active_device &
3422 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3423 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3424 ENCODER_OBJECT_ID_NONE)) {
3425 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3426 if (dig) {
3427 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3428 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3429 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3430 }
3431 }
3432
3433 amdgpu_atombios_scratch_regs_lock(adev, true);
3434
3435 if (connector) {
3436 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3437
3438 /* select the clock/data port if it uses a router */
3439 if (amdgpu_connector->router.cd_valid)
3440 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3441
3442 /* turn eDP panel on for mode set */
3443 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3444 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3445 ATOM_TRANSMITTER_ACTION_POWER_ON);
3446 }
3447
3448 /* this is needed for the pll/ss setup to work correctly in some cases */
3449 amdgpu_atombios_encoder_set_crtc_source(encoder);
3450 /* set up the FMT blocks */
3451 dce_v8_0_program_fmt(encoder);
3452}
3453
3454static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3455{
3456 struct drm_device *dev = encoder->dev;
3457 struct amdgpu_device *adev = dev->dev_private;
3458
3459 /* need to call this here as we need the crtc set up */
3460 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3461 amdgpu_atombios_scratch_regs_lock(adev, false);
3462}
3463
3464static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3465{
3466 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3467 struct amdgpu_encoder_atom_dig *dig;
3468
3469 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3470
3471 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3472 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3473 dce_v8_0_afmt_enable(encoder, false);
3474 dig = amdgpu_encoder->enc_priv;
3475 dig->dig_encoder = -1;
3476 }
3477 amdgpu_encoder->active_device = 0;
3478}
3479
3480/* these are handled by the primary encoders */
3481static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3482{
3483
3484}
3485
3486static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3487{
3488
3489}
3490
3491static void
3492dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3493 struct drm_display_mode *mode,
3494 struct drm_display_mode *adjusted_mode)
3495{
3496
3497}
3498
3499static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3500{
3501
3502}
3503
3504static void
3505dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3506{
3507
3508}
3509
a2e73f56
AD		 3510static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3511 .dpms = dce_v8_0_ext_dpms,
a2e73f56
AD		 3512 .prepare = dce_v8_0_ext_prepare,
3513 .mode_set = dce_v8_0_ext_mode_set,
3514 .commit = dce_v8_0_ext_commit,
3515 .disable = dce_v8_0_ext_disable,
3516 /* no detect for TMDS/LVDS yet */
3517};
3518
3519static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3520 .dpms = amdgpu_atombios_encoder_dpms,
3521 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3522 .prepare = dce_v8_0_encoder_prepare,
3523 .mode_set = dce_v8_0_encoder_mode_set,
3524 .commit = dce_v8_0_encoder_commit,
3525 .disable = dce_v8_0_encoder_disable,
3526 .detect = amdgpu_atombios_encoder_dig_detect,
3527};
3528
3529static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3530 .dpms = amdgpu_atombios_encoder_dpms,
3531 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3532 .prepare = dce_v8_0_encoder_prepare,
3533 .mode_set = dce_v8_0_encoder_mode_set,
3534 .commit = dce_v8_0_encoder_commit,
3535 .detect = amdgpu_atombios_encoder_dac_detect,
3536};
3537
3538static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3539{
3540 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3541 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3542 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3543 kfree(amdgpu_encoder->enc_priv);
3544 drm_encoder_cleanup(encoder);
3545 kfree(amdgpu_encoder);
3546}
3547
3548static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3549 .destroy = dce_v8_0_encoder_destroy,
3550};
3551
3552static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3553 uint32_t encoder_enum,
3554 uint32_t supported_device,
3555 u16 caps)
3556{
3557 struct drm_device *dev = adev->ddev;
3558 struct drm_encoder *encoder;
3559 struct amdgpu_encoder *amdgpu_encoder;
3560
3561 /* see if we already added it */
3562 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3563 amdgpu_encoder = to_amdgpu_encoder(encoder);
3564 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3565 amdgpu_encoder->devices |= supported_device;
3566 return;
3567 }
3568
3569 }
3570
3571 /* add a new one */
3572 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3573 if (!amdgpu_encoder)
3574 return;
3575
3576 encoder = &amdgpu_encoder->base;
3577 switch (adev->mode_info.num_crtc) {
3578 case 1:
3579 encoder->possible_crtcs = 0x1;
3580 break;
3581 case 2:
3582 default:
3583 encoder->possible_crtcs = 0x3;
3584 break;
3585 case 4:
3586 encoder->possible_crtcs = 0xf;
3587 break;
3588 case 6:
3589 encoder->possible_crtcs = 0x3f;
3590 break;
3591 }
3592
3593 amdgpu_encoder->enc_priv = NULL;
3594
3595 amdgpu_encoder->encoder_enum = encoder_enum;
3596 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3597 amdgpu_encoder->devices = supported_device;
3598 amdgpu_encoder->rmx_type = RMX_OFF;
3599 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3600 amdgpu_encoder->is_ext_encoder = false;
3601 amdgpu_encoder->caps = caps;
3602
3603 switch (amdgpu_encoder->encoder_id) {
3604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3606 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3607 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3608 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3609 break;
3610 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3611 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3613 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3614 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3615 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3616 amdgpu_encoder->rmx_type = RMX_FULL;
3617 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3618 DRM_MODE_ENCODER_LVDS, NULL);
a2e73f56
AD		 3619 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3620 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3621 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3622 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3623 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3624 } else {
3625 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3626 DRM_MODE_ENCODER_TMDS, NULL);
a2e73f56
AD		 3627 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3628 }
3629 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3630 break;
3631 case ENCODER_OBJECT_ID_SI170B:
3632 case ENCODER_OBJECT_ID_CH7303:
3633 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3634 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3635 case ENCODER_OBJECT_ID_TITFP513:
3636 case ENCODER_OBJECT_ID_VT1623:
3637 case ENCODER_OBJECT_ID_HDMI_SI1930:
3638 case ENCODER_OBJECT_ID_TRAVIS:
3639 case ENCODER_OBJECT_ID_NUTMEG:
3640 /* these are handled by the primary encoders */
3641 amdgpu_encoder->is_ext_encoder = true;
3642 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3643 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3644 DRM_MODE_ENCODER_LVDS, NULL);
a2e73f56
AD		 3645 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3646 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3647 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3648 else
3649 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3650 DRM_MODE_ENCODER_TMDS, NULL);
a2e73f56
AD		 3651 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3652 break;
3653 }
3654}
3655
3656static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3657 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3658 .bandwidth_update = &dce_v8_0_bandwidth_update,
3659 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3660 .vblank_wait = &dce_v8_0_vblank_wait,
3661 .is_display_hung = &dce_v8_0_is_display_hung,
3662 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3663 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3664 .hpd_sense = &dce_v8_0_hpd_sense,
3665 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3666 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3667 .page_flip = &dce_v8_0_page_flip,
3668 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3669 .add_encoder = &dce_v8_0_encoder_add,
3670 .add_connector = &amdgpu_connector_add,
3671 .stop_mc_access = &dce_v8_0_stop_mc_access,
3672 .resume_mc_access = &dce_v8_0_resume_mc_access,
3673};
3674
3675static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3676{
3677 if (adev->mode_info.funcs == NULL)
3678 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3679}
3680
3681static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3682 .set = dce_v8_0_set_crtc_interrupt_state,
3683 .process = dce_v8_0_crtc_irq,
3684};
3685
3686static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3687 .set = dce_v8_0_set_pageflip_interrupt_state,
3688 .process = dce_v8_0_pageflip_irq,
3689};
3690
3691static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3692 .set = dce_v8_0_set_hpd_interrupt_state,
3693 .process = dce_v8_0_hpd_irq,
3694};
3695
3696static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3697{
3698 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3699 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3700
3701 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3702 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3703
3704 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3705 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3706}
Linux kernel - Deliverables
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