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drm/amdgpu: set proper index/data pair for smc regs on CZ (v2)
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_vi.h"
31
32#include "gmc/gmc_8_2_d.h"
33#include "gmc/gmc_8_2_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44#include "gca/gfx_8_0_enum.h"
45
46#include "uvd/uvd_5_0_d.h"
47#include "uvd/uvd_5_0_sh_mask.h"
48
49#include "dce/dce_10_0_d.h"
50#include "dce/dce_10_0_sh_mask.h"
51
52#define GFX8_NUM_GFX_RINGS 1
53#define GFX8_NUM_COMPUTE_RINGS 8
54
55#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
56#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
57#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
58
59#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
60#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
61#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
62#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
63#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
64#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
65#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
66#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
67#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
68
c65444fe
JZ		 69MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
70MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
71MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
72MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
75
76MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
77MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
78MODULE_FIRMWARE("amdgpu/tonga_me.bin");
79MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
80MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
81MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
82
83MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
84MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
85MODULE_FIRMWARE("amdgpu/topaz_me.bin");
86MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
87MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
88MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97
AD		 89
90static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
91{
92 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
93 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
94 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
95 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
96 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
97 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
98 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
99 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
100 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
101 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
102 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
103 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
104 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
105 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
106 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
107 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
108};
109
110static const u32 golden_settings_tonga_a11[] =
111{
112 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
113 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
114 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
115 mmGB_GPU_ID, 0x0000000f, 0x00000000,
116 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
117 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
118 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 119 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 120 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
121 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 122 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 123 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
124 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
125 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 126 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 127};
128
129static const u32 tonga_golden_common_all[] =
130{
131 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
132 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
133 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
134 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
135 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
136 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
137 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
138 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
139};
140
141static const u32 tonga_mgcg_cgcg_init[] =
142{
143 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
144 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
145 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
146 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
147 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
148 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
149 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
150 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
151 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
152 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
153 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
154 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
155 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
156 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
157 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
158 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
159 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
160 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
161 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
162 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
163 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
164 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
165 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
166 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
167 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
168 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
169 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
170 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
171 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
172 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
173 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
174 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
175 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
176 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
177 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
178 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
179 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
180 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
181 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
182 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
183 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
184 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
185 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
186 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
187 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
188 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
189 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
190 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
191 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
192 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
193 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
194 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
195 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
196 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
197 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
198 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
199 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
200 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
201 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
202 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
203 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
204 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
205 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
206 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
207 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
208 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
209 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
210 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
211 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
212 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
213 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
214 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
215 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
216 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
217 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
218};
219
220static const u32 golden_settings_iceland_a11[] =
221{
222 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
223 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
224 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
225 mmGB_GPU_ID, 0x0000000f, 0x00000000,
226 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
227 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
228 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
229 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
6a00a09e 230 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 231 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
232 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 233 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 234 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
235 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
236 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
237};
238
239static const u32 iceland_golden_common_all[] =
240{
241 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
242 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
243 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
244 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
245 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
246 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
247 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
248 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
249};
250
251static const u32 iceland_mgcg_cgcg_init[] =
252{
253 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
254 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
255 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
256 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
257 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
258 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
259 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
260 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
261 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
262 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
263 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
264 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
265 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
266 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
267 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
268 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
269 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
270 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
271 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
272 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
273 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
274 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
275 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
276 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
277 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
278 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
279 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
280 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
281 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
282 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
283 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
284 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
285 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
286 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
287 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
288 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
289 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
290 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
291 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
292 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
293 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
294 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
295 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
296 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
297 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
298 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
299 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
300 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
301 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
302 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
303 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
304 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
305 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
306 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
307 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
308 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
309 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
310 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
311 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
312 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
313 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
314 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
315 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
316 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
317};
318
319static const u32 cz_golden_settings_a11[] =
320{
321 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
322 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
323 mmGB_GPU_ID, 0x0000000f, 0x00000000,
324 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 326 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 327 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
6a00a09e 328 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 329 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
330 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
331};
332
333static const u32 cz_golden_common_all[] =
334{
335 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
336 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
337 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
338 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
339 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
340 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
341 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
342 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
343};
344
345static const u32 cz_mgcg_cgcg_init[] =
346{
347 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
348 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
349 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
350 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
351 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
352 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
353 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
354 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
355 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
356 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
357 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
358 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
359 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
360 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
362 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
364 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
365 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
366 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
367 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
368 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
369 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
371 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
372 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
373 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
374 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
375 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
376 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
377 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
378 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
379 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
380 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
381 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
382 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
383 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
384 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
385 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
386 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
387 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
388 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
389 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
390 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
391 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
392 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
393 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
394 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
395 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
396 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
397 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
398 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
399 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
400 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
401 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
402 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
403 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
404 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
405 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
406 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
407 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
408 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
409 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
410 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
411 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
412 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
413 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
414 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
415 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
416 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
417 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
418 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
419 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
420 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
421 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
422};
423
424static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
425static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
426static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
427
428static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
429{
430 switch (adev->asic_type) {
431 case CHIP_TOPAZ:
432 amdgpu_program_register_sequence(adev,
433 iceland_mgcg_cgcg_init,
434 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
435 amdgpu_program_register_sequence(adev,
436 golden_settings_iceland_a11,
437 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
438 amdgpu_program_register_sequence(adev,
439 iceland_golden_common_all,
440 (const u32)ARRAY_SIZE(iceland_golden_common_all));
441 break;
442 case CHIP_TONGA:
443 amdgpu_program_register_sequence(adev,
444 tonga_mgcg_cgcg_init,
445 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
446 amdgpu_program_register_sequence(adev,
447 golden_settings_tonga_a11,
448 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
449 amdgpu_program_register_sequence(adev,
450 tonga_golden_common_all,
451 (const u32)ARRAY_SIZE(tonga_golden_common_all));
452 break;
453 case CHIP_CARRIZO:
454 amdgpu_program_register_sequence(adev,
455 cz_mgcg_cgcg_init,
456 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
457 amdgpu_program_register_sequence(adev,
458 cz_golden_settings_a11,
459 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
460 amdgpu_program_register_sequence(adev,
461 cz_golden_common_all,
462 (const u32)ARRAY_SIZE(cz_golden_common_all));
463 break;
464 default:
465 break;
466 }
467}
468
469static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
470{
471 int i;
472
473 adev->gfx.scratch.num_reg = 7;
474 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
475 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
476 adev->gfx.scratch.free[i] = true;
477 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
478 }
479}
480
481static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
482{
483 struct amdgpu_device *adev = ring->adev;
484 uint32_t scratch;
485 uint32_t tmp = 0;
486 unsigned i;
487 int r;
488
489 r = amdgpu_gfx_scratch_get(adev, &scratch);
490 if (r) {
491 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
492 return r;
493 }
494 WREG32(scratch, 0xCAFEDEAD);
495 r = amdgpu_ring_lock(ring, 3);
496 if (r) {
497 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
498 ring->idx, r);
499 amdgpu_gfx_scratch_free(adev, scratch);
500 return r;
501 }
502 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
503 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
504 amdgpu_ring_write(ring, 0xDEADBEEF);
505 amdgpu_ring_unlock_commit(ring);
506
507 for (i = 0; i < adev->usec_timeout; i++) {
508 tmp = RREG32(scratch);
509 if (tmp == 0xDEADBEEF)
510 break;
511 DRM_UDELAY(1);
512 }
513 if (i < adev->usec_timeout) {
514 DRM_INFO("ring test on %d succeeded in %d usecs\n",
515 ring->idx, i);
516 } else {
517 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
518 ring->idx, scratch, tmp);
519 r = -EINVAL;
520 }
521 amdgpu_gfx_scratch_free(adev, scratch);
522 return r;
523}
524
525static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
526{
527 struct amdgpu_device *adev = ring->adev;
528 struct amdgpu_ib ib;
529 uint32_t scratch;
530 uint32_t tmp = 0;
531 unsigned i;
532 int r;
533
534 r = amdgpu_gfx_scratch_get(adev, &scratch);
535 if (r) {
536 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
537 return r;
538 }
539 WREG32(scratch, 0xCAFEDEAD);
540 r = amdgpu_ib_get(ring, NULL, 256, &ib);
541 if (r) {
542 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
543 amdgpu_gfx_scratch_free(adev, scratch);
544 return r;
545 }
546 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
547 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
548 ib.ptr[2] = 0xDEADBEEF;
549 ib.length_dw = 3;
550 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
551 if (r) {
552 amdgpu_gfx_scratch_free(adev, scratch);
553 amdgpu_ib_free(adev, &ib);
554 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
555 return r;
556 }
557 r = amdgpu_fence_wait(ib.fence, false);
558 if (r) {
559 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
560 amdgpu_gfx_scratch_free(adev, scratch);
561 amdgpu_ib_free(adev, &ib);
562 return r;
563 }
564 for (i = 0; i < adev->usec_timeout; i++) {
565 tmp = RREG32(scratch);
566 if (tmp == 0xDEADBEEF)
567 break;
568 DRM_UDELAY(1);
569 }
570 if (i < adev->usec_timeout) {
571 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
572 ib.fence->ring->idx, i);
573 } else {
574 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
575 scratch, tmp);
576 r = -EINVAL;
577 }
578 amdgpu_gfx_scratch_free(adev, scratch);
579 amdgpu_ib_free(adev, &ib);
580 return r;
581}
582
583static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
584{
585 const char *chip_name;
586 char fw_name[30];
587 int err;
588 struct amdgpu_firmware_info *info = NULL;
589 const struct common_firmware_header *header = NULL;
590
591 DRM_DEBUG("\n");
592
593 switch (adev->asic_type) {
594 case CHIP_TOPAZ:
595 chip_name = "topaz";
596 break;
597 case CHIP_TONGA:
598 chip_name = "tonga";
599 break;
600 case CHIP_CARRIZO:
601 chip_name = "carrizo";
602 break;
603 default:
604 BUG();
605 }
606
c65444fe 607 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 608 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
609 if (err)
610 goto out;
611 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
612 if (err)
613 goto out;
614
c65444fe 615 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 616 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
617 if (err)
618 goto out;
619 err = amdgpu_ucode_validate(adev->gfx.me_fw);
620 if (err)
621 goto out;
622
c65444fe 623 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 624 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
625 if (err)
626 goto out;
627 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
628 if (err)
629 goto out;
630
c65444fe 631 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 632 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
633 if (err)
634 goto out;
635 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
636
c65444fe 637 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 638 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
639 if (err)
640 goto out;
641 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
642 if (err)
643 goto out;
644
c65444fe 645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
aaa36a97
AD		 646 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
647 if (!err) {
648 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
649 if (err)
650 goto out;
651 } else {
652 err = 0;
653 adev->gfx.mec2_fw = NULL;
654 }
655
656 if (adev->firmware.smu_load) {
657 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
658 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
659 info->fw = adev->gfx.pfp_fw;
660 header = (const struct common_firmware_header *)info->fw->data;
661 adev->firmware.fw_size +=
662 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
663
664 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
665 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
666 info->fw = adev->gfx.me_fw;
667 header = (const struct common_firmware_header *)info->fw->data;
668 adev->firmware.fw_size +=
669 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
670
671 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
672 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
673 info->fw = adev->gfx.ce_fw;
674 header = (const struct common_firmware_header *)info->fw->data;
675 adev->firmware.fw_size +=
676 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
677
678 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
679 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
680 info->fw = adev->gfx.rlc_fw;
681 header = (const struct common_firmware_header *)info->fw->data;
682 adev->firmware.fw_size +=
683 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
684
685 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
686 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
687 info->fw = adev->gfx.mec_fw;
688 header = (const struct common_firmware_header *)info->fw->data;
689 adev->firmware.fw_size +=
690 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
691
692 if (adev->gfx.mec2_fw) {
693 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
694 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
695 info->fw = adev->gfx.mec2_fw;
696 header = (const struct common_firmware_header *)info->fw->data;
697 adev->firmware.fw_size +=
698 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
699 }
700
701 }
702
703out:
704 if (err) {
705 dev_err(adev->dev,
706 "gfx8: Failed to load firmware \"%s\"\n",
707 fw_name);
708 release_firmware(adev->gfx.pfp_fw);
709 adev->gfx.pfp_fw = NULL;
710 release_firmware(adev->gfx.me_fw);
711 adev->gfx.me_fw = NULL;
712 release_firmware(adev->gfx.ce_fw);
713 adev->gfx.ce_fw = NULL;
714 release_firmware(adev->gfx.rlc_fw);
715 adev->gfx.rlc_fw = NULL;
716 release_firmware(adev->gfx.mec_fw);
717 adev->gfx.mec_fw = NULL;
718 release_firmware(adev->gfx.mec2_fw);
719 adev->gfx.mec2_fw = NULL;
720 }
721 return err;
722}
723
724static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
725{
726 int r;
727
728 if (adev->gfx.mec.hpd_eop_obj) {
729 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
730 if (unlikely(r != 0))
731 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
732 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
733 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
734
735 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
736 adev->gfx.mec.hpd_eop_obj = NULL;
737 }
738}
739
740#define MEC_HPD_SIZE 2048
741
742static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
743{
744 int r;
745 u32 *hpd;
746
747 /*
748 * we assign only 1 pipe because all other pipes will
749 * be handled by KFD
750 */
751 adev->gfx.mec.num_mec = 1;
752 adev->gfx.mec.num_pipe = 1;
753 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
754
755 if (adev->gfx.mec.hpd_eop_obj == NULL) {
756 r = amdgpu_bo_create(adev,
757 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
758 PAGE_SIZE, true,
759 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
760 &adev->gfx.mec.hpd_eop_obj);
761 if (r) {
762 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
763 return r;
764 }
765 }
766
767 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
768 if (unlikely(r != 0)) {
769 gfx_v8_0_mec_fini(adev);
770 return r;
771 }
772 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
773 &adev->gfx.mec.hpd_eop_gpu_addr);
774 if (r) {
775 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
776 gfx_v8_0_mec_fini(adev);
777 return r;
778 }
779 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
780 if (r) {
781 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
782 gfx_v8_0_mec_fini(adev);
783 return r;
784 }
785
786 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
787
788 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
789 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
790
791 return 0;
792}
793
5fc3aeeb 794static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 795{
796 int i, r;
797 struct amdgpu_ring *ring;
5fc3aeeb 798 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 799
800 /* EOP Event */
801 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
802 if (r)
803 return r;
804
805 /* Privileged reg */
806 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
807 if (r)
808 return r;
809
810 /* Privileged inst */
811 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
812 if (r)
813 return r;
814
815 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
816
817 gfx_v8_0_scratch_init(adev);
818
819 r = gfx_v8_0_init_microcode(adev);
820 if (r) {
821 DRM_ERROR("Failed to load gfx firmware!\n");
822 return r;
823 }
824
825 r = gfx_v8_0_mec_init(adev);
826 if (r) {
827 DRM_ERROR("Failed to init MEC BOs!\n");
828 return r;
829 }
830
831 r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
832 if (r) {
833 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
834 return r;
835 }
836
837 /* set up the gfx ring */
838 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
839 ring = &adev->gfx.gfx_ring[i];
840 ring->ring_obj = NULL;
841 sprintf(ring->name, "gfx");
842 /* no gfx doorbells on iceland */
843 if (adev->asic_type != CHIP_TOPAZ) {
844 ring->use_doorbell = true;
845 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
846 }
847
848 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
849 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
850 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
851 AMDGPU_RING_TYPE_GFX);
852 if (r)
853 return r;
854 }
855
856 /* set up the compute queues */
857 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
858 unsigned irq_type;
859
860 /* max 32 queues per MEC */
861 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
862 DRM_ERROR("Too many (%d) compute rings!\n", i);
863 break;
864 }
865 ring = &adev->gfx.compute_ring[i];
866 ring->ring_obj = NULL;
867 ring->use_doorbell = true;
868 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
869 ring->me = 1; /* first MEC */
870 ring->pipe = i / 8;
871 ring->queue = i % 8;
872 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
873 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
874 /* type-2 packets are deprecated on MEC, use type-3 instead */
875 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
876 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
877 &adev->gfx.eop_irq, irq_type,
878 AMDGPU_RING_TYPE_COMPUTE);
879 if (r)
880 return r;
881 }
882
883 /* reserve GDS, GWS and OA resource for gfx */
884 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
885 PAGE_SIZE, true,
886 AMDGPU_GEM_DOMAIN_GDS, 0,
887 NULL, &adev->gds.gds_gfx_bo);
888 if (r)
889 return r;
890
891 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
892 PAGE_SIZE, true,
893 AMDGPU_GEM_DOMAIN_GWS, 0,
894 NULL, &adev->gds.gws_gfx_bo);
895 if (r)
896 return r;
897
898 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
899 PAGE_SIZE, true,
900 AMDGPU_GEM_DOMAIN_OA, 0,
901 NULL, &adev->gds.oa_gfx_bo);
902 if (r)
903 return r;
904
a101a899
KW		 905 adev->gfx.ce_ram_size = 0x8000;
906
aaa36a97
AD		 907 return 0;
908}
909
5fc3aeeb 910static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 911{
912 int i;
5fc3aeeb 913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 914
915 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
916 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
917 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
918
919 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
920 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
921 for (i = 0; i < adev->gfx.num_compute_rings; i++)
922 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
923
924 amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
925
926 gfx_v8_0_mec_fini(adev);
927
928 return 0;
929}
930
931static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
932{
933 const u32 num_tile_mode_states = 32;
934 const u32 num_secondary_tile_mode_states = 16;
935 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
936
937 switch (adev->gfx.config.mem_row_size_in_kb) {
938 case 1:
939 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
940 break;
941 case 2:
942 default:
943 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
944 break;
945 case 4:
946 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
947 break;
948 }
949
950 switch (adev->asic_type) {
951 case CHIP_TOPAZ:
952 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
953 switch (reg_offset) {
954 case 0:
955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P2) |
957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
958 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
959 break;
960 case 1:
961 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
962 PIPE_CONFIG(ADDR_SURF_P2) |
963 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
964 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
965 break;
966 case 2:
967 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
968 PIPE_CONFIG(ADDR_SURF_P2) |
969 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
970 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
971 break;
972 case 3:
973 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
974 PIPE_CONFIG(ADDR_SURF_P2) |
975 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
976 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
977 break;
978 case 4:
979 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
980 PIPE_CONFIG(ADDR_SURF_P2) |
981 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
982 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
983 break;
984 case 5:
985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
988 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
989 break;
990 case 6:
991 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
992 PIPE_CONFIG(ADDR_SURF_P2) |
993 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
994 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
995 break;
996 case 8:
997 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
998 PIPE_CONFIG(ADDR_SURF_P2));
999 break;
1000 case 9:
1001 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1005 break;
1006 case 10:
1007 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1008 PIPE_CONFIG(ADDR_SURF_P2) |
1009 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1010 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1011 break;
1012 case 11:
1013 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1014 PIPE_CONFIG(ADDR_SURF_P2) |
1015 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1016 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1017 break;
1018 case 13:
1019 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1020 PIPE_CONFIG(ADDR_SURF_P2) |
1021 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1022 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1023 break;
1024 case 14:
1025 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P2) |
1027 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1028 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1029 break;
1030 case 15:
1031 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1032 PIPE_CONFIG(ADDR_SURF_P2) |
1033 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1034 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1035 break;
1036 case 16:
1037 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P2) |
1039 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1040 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1041 break;
1042 case 18:
1043 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1044 PIPE_CONFIG(ADDR_SURF_P2) |
1045 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1046 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1047 break;
1048 case 19:
1049 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1050 PIPE_CONFIG(ADDR_SURF_P2) |
1051 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1052 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1053 break;
1054 case 20:
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1056 PIPE_CONFIG(ADDR_SURF_P2) |
1057 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1058 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1059 break;
1060 case 21:
1061 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1062 PIPE_CONFIG(ADDR_SURF_P2) |
1063 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1064 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1065 break;
1066 case 22:
1067 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1068 PIPE_CONFIG(ADDR_SURF_P2) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1070 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1071 break;
1072 case 24:
1073 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1074 PIPE_CONFIG(ADDR_SURF_P2) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1076 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1077 break;
1078 case 25:
1079 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1080 PIPE_CONFIG(ADDR_SURF_P2) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1082 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1083 break;
1084 case 26:
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1086 PIPE_CONFIG(ADDR_SURF_P2) |
1087 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1089 break;
1090 case 27:
1091 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1092 PIPE_CONFIG(ADDR_SURF_P2) |
1093 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1094 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1095 break;
1096 case 28:
1097 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1098 PIPE_CONFIG(ADDR_SURF_P2) |
1099 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1101 break;
1102 case 29:
1103 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P2) |
1105 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1107 break;
1108 case 7:
1109 case 12:
1110 case 17:
1111 case 23:
1112 /* unused idx */
1113 continue;
1114 default:
1115 gb_tile_moden = 0;
1116 break;
1117 };
1118 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1119 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1120 }
1121 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1122 switch (reg_offset) {
1123 case 0:
1124 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1127 NUM_BANKS(ADDR_SURF_8_BANK));
1128 break;
1129 case 1:
1130 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1133 NUM_BANKS(ADDR_SURF_8_BANK));
1134 break;
1135 case 2:
1136 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1139 NUM_BANKS(ADDR_SURF_8_BANK));
1140 break;
1141 case 3:
1142 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1145 NUM_BANKS(ADDR_SURF_8_BANK));
1146 break;
1147 case 4:
1148 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_8_BANK));
1152 break;
1153 case 5:
1154 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1157 NUM_BANKS(ADDR_SURF_8_BANK));
1158 break;
1159 case 6:
1160 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163 NUM_BANKS(ADDR_SURF_8_BANK));
1164 break;
1165 case 8:
1166 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1169 NUM_BANKS(ADDR_SURF_16_BANK));
1170 break;
1171 case 9:
1172 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 break;
1177 case 10:
1178 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1181 NUM_BANKS(ADDR_SURF_16_BANK));
1182 break;
1183 case 11:
1184 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 break;
1189 case 12:
1190 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1193 NUM_BANKS(ADDR_SURF_16_BANK));
1194 break;
1195 case 13:
1196 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 break;
1201 case 14:
1202 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1205 NUM_BANKS(ADDR_SURF_8_BANK));
1206 break;
1207 case 7:
1208 /* unused idx */
1209 continue;
1210 default:
1211 gb_tile_moden = 0;
1212 break;
1213 };
1214 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1215 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1216 }
1217 case CHIP_TONGA:
1218 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1219 switch (reg_offset) {
1220 case 0:
1221 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1222 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1223 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1224 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1225 break;
1226 case 1:
1227 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1231 break;
1232 case 2:
1233 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1236 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1237 break;
1238 case 3:
1239 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1240 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1243 break;
1244 case 4:
1245 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1248 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1249 break;
1250 case 5:
1251 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1252 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1253 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1254 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1255 break;
1256 case 6:
1257 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1260 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1261 break;
1262 case 7:
1263 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1264 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1267 break;
1268 case 8:
1269 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1270 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1271 break;
1272 case 9:
1273 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1274 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1275 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1276 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1277 break;
1278 case 10:
1279 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1280 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1283 break;
1284 case 11:
1285 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1286 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1287 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1288 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1289 break;
1290 case 12:
1291 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1295 break;
1296 case 13:
1297 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1298 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1299 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1301 break;
1302 case 14:
1303 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1304 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1307 break;
1308 case 15:
1309 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1310 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1311 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1313 break;
1314 case 16:
1315 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1316 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1319 break;
1320 case 17:
1321 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1322 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1323 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1325 break;
1326 case 18:
1327 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1328 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1329 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1330 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1331 break;
1332 case 19:
1333 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1335 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1337 break;
1338 case 20:
1339 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1340 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1341 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1342 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1343 break;
1344 case 21:
1345 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1347 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1348 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1349 break;
1350 case 22:
1351 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1352 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1353 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1354 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1355 break;
1356 case 23:
1357 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1358 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1359 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1360 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1361 break;
1362 case 24:
1363 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1364 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1365 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1366 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1367 break;
1368 case 25:
1369 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1370 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1371 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1372 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1373 break;
1374 case 26:
1375 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1376 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1377 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1378 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1379 break;
1380 case 27:
1381 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1382 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1383 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1384 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1385 break;
1386 case 28:
1387 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1388 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1389 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1390 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1391 break;
1392 case 29:
1393 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1394 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1395 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1397 break;
1398 case 30:
1399 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1402 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1403 break;
1404 default:
1405 gb_tile_moden = 0;
1406 break;
1407 };
1408 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1409 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1410 }
1411 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1412 switch (reg_offset) {
1413 case 0:
1414 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1415 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1416 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1417 NUM_BANKS(ADDR_SURF_16_BANK));
1418 break;
1419 case 1:
1420 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1423 NUM_BANKS(ADDR_SURF_16_BANK));
1424 break;
1425 case 2:
1426 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1429 NUM_BANKS(ADDR_SURF_16_BANK));
1430 break;
1431 case 3:
1432 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1435 NUM_BANKS(ADDR_SURF_16_BANK));
1436 break;
1437 case 4:
1438 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1439 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1440 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1441 NUM_BANKS(ADDR_SURF_16_BANK));
1442 break;
1443 case 5:
1444 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1447 NUM_BANKS(ADDR_SURF_16_BANK));
1448 break;
1449 case 6:
1450 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1453 NUM_BANKS(ADDR_SURF_16_BANK));
1454 break;
1455 case 8:
1456 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1459 NUM_BANKS(ADDR_SURF_16_BANK));
1460 break;
1461 case 9:
1462 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1464 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1465 NUM_BANKS(ADDR_SURF_16_BANK));
1466 break;
1467 case 10:
1468 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1470 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1471 NUM_BANKS(ADDR_SURF_16_BANK));
1472 break;
1473 case 11:
1474 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1475 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1476 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1477 NUM_BANKS(ADDR_SURF_16_BANK));
1478 break;
1479 case 12:
1480 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1483 NUM_BANKS(ADDR_SURF_8_BANK));
1484 break;
1485 case 13:
1486 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1489 NUM_BANKS(ADDR_SURF_4_BANK));
1490 break;
1491 case 14:
1492 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1495 NUM_BANKS(ADDR_SURF_4_BANK));
1496 break;
1497 case 7:
1498 /* unused idx */
1499 continue;
1500 default:
1501 gb_tile_moden = 0;
1502 break;
1503 };
1504 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1505 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1506 }
1507 break;
1508 case CHIP_CARRIZO:
1509 default:
1510 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1511 switch (reg_offset) {
1512 case 0:
1513 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1514 PIPE_CONFIG(ADDR_SURF_P2) |
1515 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1516 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1517 break;
1518 case 1:
1519 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1520 PIPE_CONFIG(ADDR_SURF_P2) |
1521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1523 break;
1524 case 2:
1525 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1526 PIPE_CONFIG(ADDR_SURF_P2) |
1527 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1528 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1529 break;
1530 case 3:
1531 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1532 PIPE_CONFIG(ADDR_SURF_P2) |
1533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1534 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1535 break;
1536 case 4:
1537 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1538 PIPE_CONFIG(ADDR_SURF_P2) |
1539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1540 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1541 break;
1542 case 5:
1543 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1544 PIPE_CONFIG(ADDR_SURF_P2) |
1545 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1546 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1547 break;
1548 case 6:
1549 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1550 PIPE_CONFIG(ADDR_SURF_P2) |
1551 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1552 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1553 break;
1554 case 8:
1555 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1556 PIPE_CONFIG(ADDR_SURF_P2));
1557 break;
1558 case 9:
1559 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1560 PIPE_CONFIG(ADDR_SURF_P2) |
1561 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1562 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1563 break;
1564 case 10:
1565 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1566 PIPE_CONFIG(ADDR_SURF_P2) |
1567 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1569 break;
1570 case 11:
1571 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1572 PIPE_CONFIG(ADDR_SURF_P2) |
1573 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1574 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1575 break;
1576 case 13:
1577 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1578 PIPE_CONFIG(ADDR_SURF_P2) |
1579 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1581 break;
1582 case 14:
1583 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1584 PIPE_CONFIG(ADDR_SURF_P2) |
1585 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1586 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1587 break;
1588 case 15:
1589 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1590 PIPE_CONFIG(ADDR_SURF_P2) |
1591 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1593 break;
1594 case 16:
1595 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1596 PIPE_CONFIG(ADDR_SURF_P2) |
1597 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1598 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1599 break;
1600 case 18:
1601 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1602 PIPE_CONFIG(ADDR_SURF_P2) |
1603 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1605 break;
1606 case 19:
1607 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1608 PIPE_CONFIG(ADDR_SURF_P2) |
1609 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1610 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1611 break;
1612 case 20:
1613 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1614 PIPE_CONFIG(ADDR_SURF_P2) |
1615 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1617 break;
1618 case 21:
1619 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1620 PIPE_CONFIG(ADDR_SURF_P2) |
1621 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1622 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1623 break;
1624 case 22:
1625 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1626 PIPE_CONFIG(ADDR_SURF_P2) |
1627 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1628 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1629 break;
1630 case 24:
1631 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1632 PIPE_CONFIG(ADDR_SURF_P2) |
1633 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1634 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1635 break;
1636 case 25:
1637 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1638 PIPE_CONFIG(ADDR_SURF_P2) |
1639 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1640 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1641 break;
1642 case 26:
1643 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1644 PIPE_CONFIG(ADDR_SURF_P2) |
1645 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1646 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1647 break;
1648 case 27:
1649 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1650 PIPE_CONFIG(ADDR_SURF_P2) |
1651 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1652 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1653 break;
1654 case 28:
1655 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1656 PIPE_CONFIG(ADDR_SURF_P2) |
1657 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1658 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1659 break;
1660 case 29:
1661 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1662 PIPE_CONFIG(ADDR_SURF_P2) |
1663 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1664 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1665 break;
1666 case 7:
1667 case 12:
1668 case 17:
1669 case 23:
1670 /* unused idx */
1671 continue;
1672 default:
1673 gb_tile_moden = 0;
1674 break;
1675 };
1676 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1677 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1678 }
1679 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1680 switch (reg_offset) {
1681 case 0:
1682 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1685 NUM_BANKS(ADDR_SURF_8_BANK));
1686 break;
1687 case 1:
1688 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1691 NUM_BANKS(ADDR_SURF_8_BANK));
1692 break;
1693 case 2:
1694 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1697 NUM_BANKS(ADDR_SURF_8_BANK));
1698 break;
1699 case 3:
1700 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1703 NUM_BANKS(ADDR_SURF_8_BANK));
1704 break;
1705 case 4:
1706 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1707 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1708 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1709 NUM_BANKS(ADDR_SURF_8_BANK));
1710 break;
1711 case 5:
1712 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1713 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1714 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1715 NUM_BANKS(ADDR_SURF_8_BANK));
1716 break;
1717 case 6:
1718 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1721 NUM_BANKS(ADDR_SURF_8_BANK));
1722 break;
1723 case 8:
1724 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1727 NUM_BANKS(ADDR_SURF_16_BANK));
1728 break;
1729 case 9:
1730 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1733 NUM_BANKS(ADDR_SURF_16_BANK));
1734 break;
1735 case 10:
1736 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1737 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1738 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1739 NUM_BANKS(ADDR_SURF_16_BANK));
1740 break;
1741 case 11:
1742 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1745 NUM_BANKS(ADDR_SURF_16_BANK));
1746 break;
1747 case 12:
1748 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1751 NUM_BANKS(ADDR_SURF_16_BANK));
1752 break;
1753 case 13:
1754 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1755 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1756 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1757 NUM_BANKS(ADDR_SURF_16_BANK));
1758 break;
1759 case 14:
1760 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1763 NUM_BANKS(ADDR_SURF_8_BANK));
1764 break;
1765 case 7:
1766 /* unused idx */
1767 continue;
1768 default:
1769 gb_tile_moden = 0;
1770 break;
1771 };
1772 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1773 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1774 }
1775 }
1776}
1777
1778static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1779{
1780 u32 i, mask = 0;
1781
1782 for (i = 0; i < bit_width; i++) {
1783 mask <<= 1;
1784 mask |= 1;
1785 }
1786 return mask;
1787}
1788
1789void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1790{
1791 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1792
1793 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1794 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1795 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1796 } else if (se_num == 0xffffffff) {
1797 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1798 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1799 } else if (sh_num == 0xffffffff) {
1800 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1801 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1802 } else {
1803 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1804 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1805 }
1806 WREG32(mmGRBM_GFX_INDEX, data);
1807}
1808
1809static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1810 u32 max_rb_num_per_se,
1811 u32 sh_per_se)
1812{
1813 u32 data, mask;
1814
1815 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1816 if (data & 1)
1817 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1818 else
1819 data = 0;
1820
1821 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1822
1823 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1824
1825 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1826
1827 return data & mask;
1828}
1829
1830static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1831 u32 se_num, u32 sh_per_se,
1832 u32 max_rb_num_per_se)
1833{
1834 int i, j;
1835 u32 data, mask;
1836 u32 disabled_rbs = 0;
1837 u32 enabled_rbs = 0;
1838
1839 mutex_lock(&adev->grbm_idx_mutex);
1840 for (i = 0; i < se_num; i++) {
1841 for (j = 0; j < sh_per_se; j++) {
1842 gfx_v8_0_select_se_sh(adev, i, j);
1843 data = gfx_v8_0_get_rb_disabled(adev,
1844 max_rb_num_per_se, sh_per_se);
1845 disabled_rbs |= data << ((i * sh_per_se + j) *
1846 RB_BITMAP_WIDTH_PER_SH);
1847 }
1848 }
1849 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1850 mutex_unlock(&adev->grbm_idx_mutex);
1851
1852 mask = 1;
1853 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1854 if (!(disabled_rbs & mask))
1855 enabled_rbs |= mask;
1856 mask <<= 1;
1857 }
1858
1859 adev->gfx.config.backend_enable_mask = enabled_rbs;
1860
1861 mutex_lock(&adev->grbm_idx_mutex);
1862 for (i = 0; i < se_num; i++) {
1863 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1864 data = 0;
1865 for (j = 0; j < sh_per_se; j++) {
1866 switch (enabled_rbs & 3) {
1867 case 0:
1868 if (j == 0)
1869 data |= (RASTER_CONFIG_RB_MAP_3 <<
1870 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1871 else
1872 data |= (RASTER_CONFIG_RB_MAP_0 <<
1873 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1874 break;
1875 case 1:
1876 data |= (RASTER_CONFIG_RB_MAP_0 <<
1877 (i * sh_per_se + j) * 2);
1878 break;
1879 case 2:
1880 data |= (RASTER_CONFIG_RB_MAP_3 <<
1881 (i * sh_per_se + j) * 2);
1882 break;
1883 case 3:
1884 default:
1885 data |= (RASTER_CONFIG_RB_MAP_2 <<
1886 (i * sh_per_se + j) * 2);
1887 break;
1888 }
1889 enabled_rbs >>= 2;
1890 }
1891 WREG32(mmPA_SC_RASTER_CONFIG, data);
1892 }
1893 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1894 mutex_unlock(&adev->grbm_idx_mutex);
1895}
1896
cd06bf68
BG		 1897/**
1898 * gmc_v8_0_init_compute_vmid - gart enable
1899 *
1900 * @rdev: amdgpu_device pointer
1901 *
1902 * Initialize compute vmid sh_mem registers
1903 *
1904 */
1905#define DEFAULT_SH_MEM_BASES (0x6000)
1906#define FIRST_COMPUTE_VMID (8)
1907#define LAST_COMPUTE_VMID (16)
1908static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
1909{
1910 int i;
1911 uint32_t sh_mem_config;
1912 uint32_t sh_mem_bases;
1913
1914 /*
1915 * Configure apertures:
1916 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1917 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1918 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1919 */
1920 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1921
1922 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
1923 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
1924 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1925 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
1926 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
1927 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
1928
1929 mutex_lock(&adev->srbm_mutex);
1930 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1931 vi_srbm_select(adev, 0, 0, 0, i);
1932 /* CP and shaders */
1933 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1934 WREG32(mmSH_MEM_APE1_BASE, 1);
1935 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1936 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1937 }
1938 vi_srbm_select(adev, 0, 0, 0, 0);
1939 mutex_unlock(&adev->srbm_mutex);
1940}
1941
aaa36a97
AD		 1942static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1943{
1944 u32 gb_addr_config;
1945 u32 mc_shared_chmap, mc_arb_ramcfg;
1946 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1947 u32 tmp;
1948 int i;
1949
1950 switch (adev->asic_type) {
1951 case CHIP_TOPAZ:
1952 adev->gfx.config.max_shader_engines = 1;
1953 adev->gfx.config.max_tile_pipes = 2;
1954 adev->gfx.config.max_cu_per_sh = 6;
1955 adev->gfx.config.max_sh_per_se = 1;
1956 adev->gfx.config.max_backends_per_se = 2;
1957 adev->gfx.config.max_texture_channel_caches = 2;
1958 adev->gfx.config.max_gprs = 256;
1959 adev->gfx.config.max_gs_threads = 32;
1960 adev->gfx.config.max_hw_contexts = 8;
1961
1962 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1963 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1964 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1965 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1966 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1967 break;
1968 case CHIP_TONGA:
1969 adev->gfx.config.max_shader_engines = 4;
1970 adev->gfx.config.max_tile_pipes = 8;
1971 adev->gfx.config.max_cu_per_sh = 8;
1972 adev->gfx.config.max_sh_per_se = 1;
1973 adev->gfx.config.max_backends_per_se = 2;
1974 adev->gfx.config.max_texture_channel_caches = 8;
1975 adev->gfx.config.max_gprs = 256;
1976 adev->gfx.config.max_gs_threads = 32;
1977 adev->gfx.config.max_hw_contexts = 8;
1978
1979 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1980 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1981 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1982 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1983 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1984 break;
1985 case CHIP_CARRIZO:
1986 adev->gfx.config.max_shader_engines = 1;
1987 adev->gfx.config.max_tile_pipes = 2;
aaa36a97 1988 adev->gfx.config.max_sh_per_se = 1;
bd5c97bc
AD		 1989
1990 switch (adev->pdev->revision) {
1991 case 0xc4:
1992 case 0x84:
1993 case 0xc8:
1994 case 0xcc:
1995 /* B10 */
1996 adev->gfx.config.max_cu_per_sh = 8;
1997 adev->gfx.config.max_backends_per_se = 2;
1998 break;
1999 case 0xc5:
2000 case 0x81:
2001 case 0x85:
2002 case 0xc9:
2003 case 0xcd:
2004 /* B8 */
2005 adev->gfx.config.max_cu_per_sh = 6;
2006 adev->gfx.config.max_backends_per_se = 2;
2007 break;
2008 case 0xc6:
2009 case 0xca:
2010 case 0xce:
2011 /* B6 */
2012 adev->gfx.config.max_cu_per_sh = 6;
2013 adev->gfx.config.max_backends_per_se = 2;
2014 break;
2015 case 0xc7:
2016 case 0x87:
2017 case 0xcb:
2018 default:
2019 /* B4 */
2020 adev->gfx.config.max_cu_per_sh = 4;
2021 adev->gfx.config.max_backends_per_se = 1;
2022 break;
2023 }
2024
aaa36a97
AD		 2025 adev->gfx.config.max_texture_channel_caches = 2;
2026 adev->gfx.config.max_gprs = 256;
2027 adev->gfx.config.max_gs_threads = 32;
2028 adev->gfx.config.max_hw_contexts = 8;
2029
2030 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2031 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2032 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2033 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2034 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2035 break;
2036 default:
2037 adev->gfx.config.max_shader_engines = 2;
2038 adev->gfx.config.max_tile_pipes = 4;
2039 adev->gfx.config.max_cu_per_sh = 2;
2040 adev->gfx.config.max_sh_per_se = 1;
2041 adev->gfx.config.max_backends_per_se = 2;
2042 adev->gfx.config.max_texture_channel_caches = 4;
2043 adev->gfx.config.max_gprs = 256;
2044 adev->gfx.config.max_gs_threads = 32;
2045 adev->gfx.config.max_hw_contexts = 8;
2046
2047 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2048 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2049 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2050 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2051 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2052 break;
2053 }
2054
2055 tmp = RREG32(mmGRBM_CNTL);
2056 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2057 WREG32(mmGRBM_CNTL, tmp);
2058
2059 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2060 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2061 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2062
2063 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2064 adev->gfx.config.mem_max_burst_length_bytes = 256;
2065 if (adev->flags & AMDGPU_IS_APU) {
2066 /* Get memory bank mapping mode. */
2067 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2068 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2069 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2070
2071 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2072 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2073 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2074
2075 /* Validate settings in case only one DIMM installed. */
2076 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2077 dimm00_addr_map = 0;
2078 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2079 dimm01_addr_map = 0;
2080 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2081 dimm10_addr_map = 0;
2082 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2083 dimm11_addr_map = 0;
2084
2085 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2086 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2087 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2088 adev->gfx.config.mem_row_size_in_kb = 2;
2089 else
2090 adev->gfx.config.mem_row_size_in_kb = 1;
2091 } else {
2092 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2093 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2094 if (adev->gfx.config.mem_row_size_in_kb > 4)
2095 adev->gfx.config.mem_row_size_in_kb = 4;
2096 }
2097
2098 adev->gfx.config.shader_engine_tile_size = 32;
2099 adev->gfx.config.num_gpus = 1;
2100 adev->gfx.config.multi_gpu_tile_size = 64;
2101
2102 /* fix up row size */
2103 switch (adev->gfx.config.mem_row_size_in_kb) {
2104 case 1:
2105 default:
2106 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2107 break;
2108 case 2:
2109 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2110 break;
2111 case 4:
2112 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2113 break;
2114 }
2115 adev->gfx.config.gb_addr_config = gb_addr_config;
2116
2117 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2118 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2119 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2120 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2121 gb_addr_config & 0x70);
2122 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2123 gb_addr_config & 0x70);
2124 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2125 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2126 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2127
2128 gfx_v8_0_tiling_mode_table_init(adev);
2129
2130 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2131 adev->gfx.config.max_sh_per_se,
2132 adev->gfx.config.max_backends_per_se);
2133
2134 /* XXX SH_MEM regs */
2135 /* where to put LDS, scratch, GPUVM in FSA64 space */
2136 mutex_lock(&adev->srbm_mutex);
2137 for (i = 0; i < 16; i++) {
2138 vi_srbm_select(adev, 0, 0, 0, i);
2139 /* CP and shaders */
2140 if (i == 0) {
2141 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2142 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
74a5d165
JX		 2143 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2144 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 2145 WREG32(mmSH_MEM_CONFIG, tmp);
2146 } else {
2147 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2148 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
74a5d165
JX		 2149 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2150 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 2151 WREG32(mmSH_MEM_CONFIG, tmp);
2152 }
2153
2154 WREG32(mmSH_MEM_APE1_BASE, 1);
2155 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2156 WREG32(mmSH_MEM_BASES, 0);
2157 }
2158 vi_srbm_select(adev, 0, 0, 0, 0);
2159 mutex_unlock(&adev->srbm_mutex);
2160
cd06bf68
BG		 2161 gmc_v8_0_init_compute_vmid(adev);
2162
aaa36a97
AD		 2163 mutex_lock(&adev->grbm_idx_mutex);
2164 /*
2165 * making sure that the following register writes will be broadcasted
2166 * to all the shaders
2167 */
2168 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2169
2170 WREG32(mmPA_SC_FIFO_SIZE,
2171 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2172 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2173 (adev->gfx.config.sc_prim_fifo_size_backend <<
2174 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2175 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2176 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2177 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2178 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2179 mutex_unlock(&adev->grbm_idx_mutex);
2180
2181}
2182
2183static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2184{
2185 u32 i, j, k;
2186 u32 mask;
2187
2188 mutex_lock(&adev->grbm_idx_mutex);
2189 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2190 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2191 gfx_v8_0_select_se_sh(adev, i, j);
2192 for (k = 0; k < adev->usec_timeout; k++) {
2193 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2194 break;
2195 udelay(1);
2196 }
2197 }
2198 }
2199 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2200 mutex_unlock(&adev->grbm_idx_mutex);
2201
2202 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2203 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2204 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2205 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2206 for (k = 0; k < adev->usec_timeout; k++) {
2207 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2208 break;
2209 udelay(1);
2210 }
2211}
2212
2213static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2214 bool enable)
2215{
2216 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2217
2218 if (enable) {
2219 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2220 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2221 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2222 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2223 } else {
2224 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2225 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2226 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2227 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2228 }
2229 WREG32(mmCP_INT_CNTL_RING0, tmp);
2230}
2231
2232void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2233{
2234 u32 tmp = RREG32(mmRLC_CNTL);
2235
2236 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2237 WREG32(mmRLC_CNTL, tmp);
2238
2239 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2240
2241 gfx_v8_0_wait_for_rlc_serdes(adev);
2242}
2243
2244static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2245{
2246 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2247
2248 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2249 WREG32(mmGRBM_SOFT_RESET, tmp);
2250 udelay(50);
2251 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2252 WREG32(mmGRBM_SOFT_RESET, tmp);
2253 udelay(50);
2254}
2255
2256static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2257{
2258 u32 tmp = RREG32(mmRLC_CNTL);
2259
2260 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2261 WREG32(mmRLC_CNTL, tmp);
2262
2263 /* carrizo do enable cp interrupt after cp inited */
2264 if (adev->asic_type != CHIP_CARRIZO)
2265 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2266
2267 udelay(50);
2268}
2269
2270static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2271{
2272 const struct rlc_firmware_header_v2_0 *hdr;
2273 const __le32 *fw_data;
2274 unsigned i, fw_size;
2275
2276 if (!adev->gfx.rlc_fw)
2277 return -EINVAL;
2278
2279 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2280 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2281 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
2282
2283 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2284 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2285 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2286
2287 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2288 for (i = 0; i < fw_size; i++)
2289 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2290 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2291
2292 return 0;
2293}
2294
2295static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2296{
2297 int r;
2298
2299 gfx_v8_0_rlc_stop(adev);
2300
2301 /* disable CG */
2302 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2303
2304 /* disable PG */
2305 WREG32(mmRLC_PG_CNTL, 0);
2306
2307 gfx_v8_0_rlc_reset(adev);
2308
2309 if (!adev->firmware.smu_load) {
2310 /* legacy rlc firmware loading */
2311 r = gfx_v8_0_rlc_load_microcode(adev);
2312 if (r)
2313 return r;
2314 } else {
2315 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2316 AMDGPU_UCODE_ID_RLC_G);
2317 if (r)
2318 return -EINVAL;
2319 }
2320
2321 gfx_v8_0_rlc_start(adev);
2322
2323 return 0;
2324}
2325
2326static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2327{
2328 int i;
2329 u32 tmp = RREG32(mmCP_ME_CNTL);
2330
2331 if (enable) {
2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2334 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2335 } else {
2336 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2337 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2338 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2339 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2340 adev->gfx.gfx_ring[i].ready = false;
2341 }
2342 WREG32(mmCP_ME_CNTL, tmp);
2343 udelay(50);
2344}
2345
2346static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2347{
2348 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2349 const struct gfx_firmware_header_v1_0 *ce_hdr;
2350 const struct gfx_firmware_header_v1_0 *me_hdr;
2351 const __le32 *fw_data;
2352 unsigned i, fw_size;
2353
2354 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2355 return -EINVAL;
2356
2357 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2358 adev->gfx.pfp_fw->data;
2359 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2360 adev->gfx.ce_fw->data;
2361 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2362 adev->gfx.me_fw->data;
2363
2364 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2365 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2366 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2367 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2368 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2369 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2370 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2371 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2372 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
aaa36a97
AD		 2373
2374 gfx_v8_0_cp_gfx_enable(adev, false);
2375
2376 /* PFP */
2377 fw_data = (const __le32 *)
2378 (adev->gfx.pfp_fw->data +
2379 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2380 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2381 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2382 for (i = 0; i < fw_size; i++)
2383 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2384 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2385
2386 /* CE */
2387 fw_data = (const __le32 *)
2388 (adev->gfx.ce_fw->data +
2389 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2390 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2391 WREG32(mmCP_CE_UCODE_ADDR, 0);
2392 for (i = 0; i < fw_size; i++)
2393 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2394 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2395
2396 /* ME */
2397 fw_data = (const __le32 *)
2398 (adev->gfx.me_fw->data +
2399 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2400 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2401 WREG32(mmCP_ME_RAM_WADDR, 0);
2402 for (i = 0; i < fw_size; i++)
2403 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2404 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2405
2406 return 0;
2407}
2408
2409static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2410{
2411 u32 count = 0;
2412 const struct cs_section_def *sect = NULL;
2413 const struct cs_extent_def *ext = NULL;
2414
2415 /* begin clear state */
2416 count += 2;
2417 /* context control state */
2418 count += 3;
2419
2420 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2421 for (ext = sect->section; ext->extent != NULL; ++ext) {
2422 if (sect->id == SECT_CONTEXT)
2423 count += 2 + ext->reg_count;
2424 else
2425 return 0;
2426 }
2427 }
2428 /* pa_sc_raster_config/pa_sc_raster_config1 */
2429 count += 4;
2430 /* end clear state */
2431 count += 2;
2432 /* clear state */
2433 count += 2;
2434
2435 return count;
2436}
2437
2438static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2439{
2440 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2441 const struct cs_section_def *sect = NULL;
2442 const struct cs_extent_def *ext = NULL;
2443 int r, i;
2444
2445 /* init the CP */
2446 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2447 WREG32(mmCP_ENDIAN_SWAP, 0);
2448 WREG32(mmCP_DEVICE_ID, 1);
2449
2450 gfx_v8_0_cp_gfx_enable(adev, true);
2451
2452 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2453 if (r) {
2454 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2455 return r;
2456 }
2457
2458 /* clear state buffer */
2459 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2460 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2461
2462 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2463 amdgpu_ring_write(ring, 0x80000000);
2464 amdgpu_ring_write(ring, 0x80000000);
2465
2466 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2467 for (ext = sect->section; ext->extent != NULL; ++ext) {
2468 if (sect->id == SECT_CONTEXT) {
2469 amdgpu_ring_write(ring,
2470 PACKET3(PACKET3_SET_CONTEXT_REG,
2471 ext->reg_count));
2472 amdgpu_ring_write(ring,
2473 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2474 for (i = 0; i < ext->reg_count; i++)
2475 amdgpu_ring_write(ring, ext->extent[i]);
2476 }
2477 }
2478 }
2479
2480 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2481 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2482 switch (adev->asic_type) {
2483 case CHIP_TONGA:
2484 amdgpu_ring_write(ring, 0x16000012);
2485 amdgpu_ring_write(ring, 0x0000002A);
2486 break;
2487 case CHIP_TOPAZ:
2488 case CHIP_CARRIZO:
2489 amdgpu_ring_write(ring, 0x00000002);
2490 amdgpu_ring_write(ring, 0x00000000);
2491 break;
2492 default:
2493 BUG();
2494 }
2495
2496 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2497 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2498
2499 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2500 amdgpu_ring_write(ring, 0);
2501
2502 /* init the CE partitions */
2503 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2504 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2505 amdgpu_ring_write(ring, 0x8000);
2506 amdgpu_ring_write(ring, 0x8000);
2507
2508 amdgpu_ring_unlock_commit(ring);
2509
2510 return 0;
2511}
2512
2513static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2514{
2515 struct amdgpu_ring *ring;
2516 u32 tmp;
2517 u32 rb_bufsz;
2518 u64 rb_addr, rptr_addr;
2519 int r;
2520
2521 /* Set the write pointer delay */
2522 WREG32(mmCP_RB_WPTR_DELAY, 0);
2523
2524 /* set the RB to use vmid 0 */
2525 WREG32(mmCP_RB_VMID, 0);
2526
2527 /* Set ring buffer size */
2528 ring = &adev->gfx.gfx_ring[0];
2529 rb_bufsz = order_base_2(ring->ring_size / 8);
2530 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2531 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2532 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2533 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2534#ifdef __BIG_ENDIAN
2535 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2536#endif
2537 WREG32(mmCP_RB0_CNTL, tmp);
2538
2539 /* Initialize the ring buffer's read and write pointers */
2540 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2541 ring->wptr = 0;
2542 WREG32(mmCP_RB0_WPTR, ring->wptr);
2543
2544 /* set the wb address wether it's enabled or not */
2545 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2546 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2547 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2548
2549 mdelay(1);
2550 WREG32(mmCP_RB0_CNTL, tmp);
2551
2552 rb_addr = ring->gpu_addr >> 8;
2553 WREG32(mmCP_RB0_BASE, rb_addr);
2554 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2555
2556 /* no gfx doorbells on iceland */
2557 if (adev->asic_type != CHIP_TOPAZ) {
2558 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2559 if (ring->use_doorbell) {
2560 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2561 DOORBELL_OFFSET, ring->doorbell_index);
2562 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2563 DOORBELL_EN, 1);
2564 } else {
2565 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2566 DOORBELL_EN, 0);
2567 }
2568 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2569
2570 if (adev->asic_type == CHIP_TONGA) {
2571 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2572 DOORBELL_RANGE_LOWER,
2573 AMDGPU_DOORBELL_GFX_RING0);
2574 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2575
2576 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2577 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2578 }
2579
2580 }
2581
2582 /* start the ring */
2583 gfx_v8_0_cp_gfx_start(adev);
2584 ring->ready = true;
2585 r = amdgpu_ring_test_ring(ring);
2586 if (r) {
2587 ring->ready = false;
2588 return r;
2589 }
2590
2591 return 0;
2592}
2593
2594static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2595{
2596 int i;
2597
2598 if (enable) {
2599 WREG32(mmCP_MEC_CNTL, 0);
2600 } else {
2601 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2602 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2603 adev->gfx.compute_ring[i].ready = false;
2604 }
2605 udelay(50);
2606}
2607
2608static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2609{
2610 gfx_v8_0_cp_compute_enable(adev, true);
2611
2612 return 0;
2613}
2614
2615static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2616{
2617 const struct gfx_firmware_header_v1_0 *mec_hdr;
2618 const __le32 *fw_data;
2619 unsigned i, fw_size;
2620
2621 if (!adev->gfx.mec_fw)
2622 return -EINVAL;
2623
2624 gfx_v8_0_cp_compute_enable(adev, false);
2625
2626 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2627 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2628 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2629
2630 fw_data = (const __le32 *)
2631 (adev->gfx.mec_fw->data +
2632 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2633 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2634
2635 /* MEC1 */
2636 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2637 for (i = 0; i < fw_size; i++)
2638 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2639 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2640
2641 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2642 if (adev->gfx.mec2_fw) {
2643 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2644
2645 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2646 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2647 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2648
2649 fw_data = (const __le32 *)
2650 (adev->gfx.mec2_fw->data +
2651 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2652 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2653
2654 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2655 for (i = 0; i < fw_size; i++)
2656 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2657 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2658 }
2659
2660 return 0;
2661}
2662
2663struct vi_mqd {
2664 uint32_t header; /* ordinal0 */
2665 uint32_t compute_dispatch_initiator; /* ordinal1 */
2666 uint32_t compute_dim_x; /* ordinal2 */
2667 uint32_t compute_dim_y; /* ordinal3 */
2668 uint32_t compute_dim_z; /* ordinal4 */
2669 uint32_t compute_start_x; /* ordinal5 */
2670 uint32_t compute_start_y; /* ordinal6 */
2671 uint32_t compute_start_z; /* ordinal7 */
2672 uint32_t compute_num_thread_x; /* ordinal8 */
2673 uint32_t compute_num_thread_y; /* ordinal9 */
2674 uint32_t compute_num_thread_z; /* ordinal10 */
2675 uint32_t compute_pipelinestat_enable; /* ordinal11 */
2676 uint32_t compute_perfcount_enable; /* ordinal12 */
2677 uint32_t compute_pgm_lo; /* ordinal13 */
2678 uint32_t compute_pgm_hi; /* ordinal14 */
2679 uint32_t compute_tba_lo; /* ordinal15 */
2680 uint32_t compute_tba_hi; /* ordinal16 */
2681 uint32_t compute_tma_lo; /* ordinal17 */
2682 uint32_t compute_tma_hi; /* ordinal18 */
2683 uint32_t compute_pgm_rsrc1; /* ordinal19 */
2684 uint32_t compute_pgm_rsrc2; /* ordinal20 */
2685 uint32_t compute_vmid; /* ordinal21 */
2686 uint32_t compute_resource_limits; /* ordinal22 */
2687 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
2688 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
2689 uint32_t compute_tmpring_size; /* ordinal25 */
2690 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
2691 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
2692 uint32_t compute_restart_x; /* ordinal28 */
2693 uint32_t compute_restart_y; /* ordinal29 */
2694 uint32_t compute_restart_z; /* ordinal30 */
2695 uint32_t compute_thread_trace_enable; /* ordinal31 */
2696 uint32_t compute_misc_reserved; /* ordinal32 */
2697 uint32_t compute_dispatch_id; /* ordinal33 */
2698 uint32_t compute_threadgroup_id; /* ordinal34 */
2699 uint32_t compute_relaunch; /* ordinal35 */
2700 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
2701 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
2702 uint32_t compute_wave_restore_control; /* ordinal38 */
2703 uint32_t reserved9; /* ordinal39 */
2704 uint32_t reserved10; /* ordinal40 */
2705 uint32_t reserved11; /* ordinal41 */
2706 uint32_t reserved12; /* ordinal42 */
2707 uint32_t reserved13; /* ordinal43 */
2708 uint32_t reserved14; /* ordinal44 */
2709 uint32_t reserved15; /* ordinal45 */
2710 uint32_t reserved16; /* ordinal46 */
2711 uint32_t reserved17; /* ordinal47 */
2712 uint32_t reserved18; /* ordinal48 */
2713 uint32_t reserved19; /* ordinal49 */
2714 uint32_t reserved20; /* ordinal50 */
2715 uint32_t reserved21; /* ordinal51 */
2716 uint32_t reserved22; /* ordinal52 */
2717 uint32_t reserved23; /* ordinal53 */
2718 uint32_t reserved24; /* ordinal54 */
2719 uint32_t reserved25; /* ordinal55 */
2720 uint32_t reserved26; /* ordinal56 */
2721 uint32_t reserved27; /* ordinal57 */
2722 uint32_t reserved28; /* ordinal58 */
2723 uint32_t reserved29; /* ordinal59 */
2724 uint32_t reserved30; /* ordinal60 */
2725 uint32_t reserved31; /* ordinal61 */
2726 uint32_t reserved32; /* ordinal62 */
2727 uint32_t reserved33; /* ordinal63 */
2728 uint32_t reserved34; /* ordinal64 */
2729 uint32_t compute_user_data_0; /* ordinal65 */
2730 uint32_t compute_user_data_1; /* ordinal66 */
2731 uint32_t compute_user_data_2; /* ordinal67 */
2732 uint32_t compute_user_data_3; /* ordinal68 */
2733 uint32_t compute_user_data_4; /* ordinal69 */
2734 uint32_t compute_user_data_5; /* ordinal70 */
2735 uint32_t compute_user_data_6; /* ordinal71 */
2736 uint32_t compute_user_data_7; /* ordinal72 */
2737 uint32_t compute_user_data_8; /* ordinal73 */
2738 uint32_t compute_user_data_9; /* ordinal74 */
2739 uint32_t compute_user_data_10; /* ordinal75 */
2740 uint32_t compute_user_data_11; /* ordinal76 */
2741 uint32_t compute_user_data_12; /* ordinal77 */
2742 uint32_t compute_user_data_13; /* ordinal78 */
2743 uint32_t compute_user_data_14; /* ordinal79 */
2744 uint32_t compute_user_data_15; /* ordinal80 */
2745 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
2746 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
2747 uint32_t reserved35; /* ordinal83 */
2748 uint32_t reserved36; /* ordinal84 */
2749 uint32_t reserved37; /* ordinal85 */
2750 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
2751 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
2752 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
2753 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
2754 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
2755 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
2756 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
2757 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
2758 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
2759 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
2760 uint32_t reserved38; /* ordinal96 */
2761 uint32_t reserved39; /* ordinal97 */
2762 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
2763 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
2764 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
2765 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
2766 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
2767 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
2768 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
2769 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
2770 uint32_t reserved40; /* ordinal106 */
2771 uint32_t reserved41; /* ordinal107 */
2772 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
2773 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
2774 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
2775 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
2776 uint32_t reserved42; /* ordinal112 */
2777 uint32_t reserved43; /* ordinal113 */
2778 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
2779 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
2780 uint32_t cp_packet_id_lo; /* ordinal116 */
2781 uint32_t cp_packet_id_hi; /* ordinal117 */
2782 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
2783 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
2784 uint32_t gds_save_base_addr_lo; /* ordinal120 */
2785 uint32_t gds_save_base_addr_hi; /* ordinal121 */
2786 uint32_t gds_save_mask_lo; /* ordinal122 */
2787 uint32_t gds_save_mask_hi; /* ordinal123 */
2788 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
2789 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
2790 uint32_t reserved44; /* ordinal126 */
2791 uint32_t reserved45; /* ordinal127 */
2792 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
2793 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
2794 uint32_t cp_hqd_active; /* ordinal130 */
2795 uint32_t cp_hqd_vmid; /* ordinal131 */
2796 uint32_t cp_hqd_persistent_state; /* ordinal132 */
2797 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
2798 uint32_t cp_hqd_queue_priority; /* ordinal134 */
2799 uint32_t cp_hqd_quantum; /* ordinal135 */
2800 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
2801 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
2802 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
2803 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
2804 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
2805 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
2806 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
2807 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
2808 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
2809 uint32_t cp_hqd_pq_control; /* ordinal145 */
2810 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
2811 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
2812 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
2813 uint32_t cp_hqd_ib_control; /* ordinal149 */
2814 uint32_t cp_hqd_iq_timer; /* ordinal150 */
2815 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
2816 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
2817 uint32_t cp_hqd_dma_offload; /* ordinal153 */
2818 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
2819 uint32_t cp_hqd_msg_type; /* ordinal155 */
2820 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
2821 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
2822 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
2823 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
2824 uint32_t cp_hqd_hq_status0; /* ordinal160 */
2825 uint32_t cp_hqd_hq_control0; /* ordinal161 */
2826 uint32_t cp_mqd_control; /* ordinal162 */
2827 uint32_t cp_hqd_hq_status1; /* ordinal163 */
2828 uint32_t cp_hqd_hq_control1; /* ordinal164 */
2829 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
2830 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
2831 uint32_t cp_hqd_eop_control; /* ordinal167 */
2832 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
2833 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
2834 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
2835 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
2836 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
2837 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
2838 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
2839 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
2840 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
2841 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
2842 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
2843 uint32_t cp_hqd_error; /* ordinal179 */
2844 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
2845 uint32_t cp_hqd_eop_dones; /* ordinal181 */
2846 uint32_t reserved46; /* ordinal182 */
2847 uint32_t reserved47; /* ordinal183 */
2848 uint32_t reserved48; /* ordinal184 */
2849 uint32_t reserved49; /* ordinal185 */
2850 uint32_t reserved50; /* ordinal186 */
2851 uint32_t reserved51; /* ordinal187 */
2852 uint32_t reserved52; /* ordinal188 */
2853 uint32_t reserved53; /* ordinal189 */
2854 uint32_t reserved54; /* ordinal190 */
2855 uint32_t reserved55; /* ordinal191 */
2856 uint32_t iqtimer_pkt_header; /* ordinal192 */
2857 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
2858 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
2859 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
2860 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
2861 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
2862 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
2863 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
2864 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
2865 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
2866 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
2867 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
2868 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
2869 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
2870 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
2871 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
2872 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
2873 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
2874 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
2875 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
2876 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
2877 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
2878 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
2879 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
2880 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
2881 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
2882 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
2883 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
2884 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
2885 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
2886 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
2887 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
2888 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
2889 uint32_t reserved56; /* ordinal225 */
2890 uint32_t reserved57; /* ordinal226 */
2891 uint32_t reserved58; /* ordinal227 */
2892 uint32_t set_resources_header; /* ordinal228 */
2893 uint32_t set_resources_dw1; /* ordinal229 */
2894 uint32_t set_resources_dw2; /* ordinal230 */
2895 uint32_t set_resources_dw3; /* ordinal231 */
2896 uint32_t set_resources_dw4; /* ordinal232 */
2897 uint32_t set_resources_dw5; /* ordinal233 */
2898 uint32_t set_resources_dw6; /* ordinal234 */
2899 uint32_t set_resources_dw7; /* ordinal235 */
2900 uint32_t reserved59; /* ordinal236 */
2901 uint32_t reserved60; /* ordinal237 */
2902 uint32_t reserved61; /* ordinal238 */
2903 uint32_t reserved62; /* ordinal239 */
2904 uint32_t reserved63; /* ordinal240 */
2905 uint32_t reserved64; /* ordinal241 */
2906 uint32_t reserved65; /* ordinal242 */
2907 uint32_t reserved66; /* ordinal243 */
2908 uint32_t reserved67; /* ordinal244 */
2909 uint32_t reserved68; /* ordinal245 */
2910 uint32_t reserved69; /* ordinal246 */
2911 uint32_t reserved70; /* ordinal247 */
2912 uint32_t reserved71; /* ordinal248 */
2913 uint32_t reserved72; /* ordinal249 */
2914 uint32_t reserved73; /* ordinal250 */
2915 uint32_t reserved74; /* ordinal251 */
2916 uint32_t reserved75; /* ordinal252 */
2917 uint32_t reserved76; /* ordinal253 */
2918 uint32_t reserved77; /* ordinal254 */
2919 uint32_t reserved78; /* ordinal255 */
2920
2921 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
2922};
2923
2924static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
2925{
2926 int i, r;
2927
2928 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2929 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2930
2931 if (ring->mqd_obj) {
2932 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2933 if (unlikely(r != 0))
2934 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2935
2936 amdgpu_bo_unpin(ring->mqd_obj);
2937 amdgpu_bo_unreserve(ring->mqd_obj);
2938
2939 amdgpu_bo_unref(&ring->mqd_obj);
2940 ring->mqd_obj = NULL;
2941 }
2942 }
2943}
2944
2945static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
2946{
2947 int r, i, j;
2948 u32 tmp;
2949 bool use_doorbell = true;
2950 u64 hqd_gpu_addr;
2951 u64 mqd_gpu_addr;
2952 u64 eop_gpu_addr;
2953 u64 wb_gpu_addr;
2954 u32 *buf;
2955 struct vi_mqd *mqd;
2956
2957 /* init the pipes */
2958 mutex_lock(&adev->srbm_mutex);
2959 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2960 int me = (i < 4) ? 1 : 2;
2961 int pipe = (i < 4) ? i : (i - 4);
2962
2963 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
2964 eop_gpu_addr >>= 8;
2965
2966 vi_srbm_select(adev, me, pipe, 0, 0);
2967
2968 /* write the EOP addr */
2969 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
2970 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
2971
2972 /* set the VMID assigned */
2973 WREG32(mmCP_HQD_VMID, 0);
2974
2975 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2976 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
2977 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2978 (order_base_2(MEC_HPD_SIZE / 4) - 1));
2979 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
2980 }
2981 vi_srbm_select(adev, 0, 0, 0, 0);
2982 mutex_unlock(&adev->srbm_mutex);
2983
2984 /* init the queues. Just two for now. */
2985 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2986 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2987
2988 if (ring->mqd_obj == NULL) {
2989 r = amdgpu_bo_create(adev,
2990 sizeof(struct vi_mqd),
2991 PAGE_SIZE, true,
2992 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
2993 &ring->mqd_obj);
2994 if (r) {
2995 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2996 return r;
2997 }
2998 }
2999
3000 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3001 if (unlikely(r != 0)) {
3002 gfx_v8_0_cp_compute_fini(adev);
3003 return r;
3004 }
3005 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3006 &mqd_gpu_addr);
3007 if (r) {
3008 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3009 gfx_v8_0_cp_compute_fini(adev);
3010 return r;
3011 }
3012 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3013 if (r) {
3014 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3015 gfx_v8_0_cp_compute_fini(adev);
3016 return r;
3017 }
3018
3019 /* init the mqd struct */
3020 memset(buf, 0, sizeof(struct vi_mqd));
3021
3022 mqd = (struct vi_mqd *)buf;
3023 mqd->header = 0xC0310800;
3024 mqd->compute_pipelinestat_enable = 0x00000001;
3025 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3026 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3027 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3028 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3029 mqd->compute_misc_reserved = 0x00000003;
3030
3031 mutex_lock(&adev->srbm_mutex);
3032 vi_srbm_select(adev, ring->me,
3033 ring->pipe,
3034 ring->queue, 0);
3035
3036 /* disable wptr polling */
3037 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3038 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3039 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3040
3041 mqd->cp_hqd_eop_base_addr_lo =
3042 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3043 mqd->cp_hqd_eop_base_addr_hi =
3044 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3045
3046 /* enable doorbell? */
3047 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3048 if (use_doorbell) {
3049 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3050 } else {
3051 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3052 }
3053 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3054 mqd->cp_hqd_pq_doorbell_control = tmp;
3055
3056 /* disable the queue if it's active */
3057 mqd->cp_hqd_dequeue_request = 0;
3058 mqd->cp_hqd_pq_rptr = 0;
3059 mqd->cp_hqd_pq_wptr= 0;
3060 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3061 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3062 for (j = 0; j < adev->usec_timeout; j++) {
3063 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3064 break;
3065 udelay(1);
3066 }
3067 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3068 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3069 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3070 }
3071
3072 /* set the pointer to the MQD */
3073 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3074 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3075 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3076 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3077
3078 /* set MQD vmid to 0 */
3079 tmp = RREG32(mmCP_MQD_CONTROL);
3080 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3081 WREG32(mmCP_MQD_CONTROL, tmp);
3082 mqd->cp_mqd_control = tmp;
3083
3084 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3085 hqd_gpu_addr = ring->gpu_addr >> 8;
3086 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3087 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3088 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3089 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3090
3091 /* set up the HQD, this is similar to CP_RB0_CNTL */
3092 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3093 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3094 (order_base_2(ring->ring_size / 4) - 1));
3095 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3096 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3097#ifdef __BIG_ENDIAN
3098 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3099#endif
3100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3101 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3102 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3104 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3105 mqd->cp_hqd_pq_control = tmp;
3106
3107 /* set the wb address wether it's enabled or not */
3108 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3109 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3110 mqd->cp_hqd_pq_rptr_report_addr_hi =
3111 upper_32_bits(wb_gpu_addr) & 0xffff;
3112 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3113 mqd->cp_hqd_pq_rptr_report_addr_lo);
3114 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3115 mqd->cp_hqd_pq_rptr_report_addr_hi);
3116
3117 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3118 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3119 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3120 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3121 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3122 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3123 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3124
3125 /* enable the doorbell if requested */
3126 if (use_doorbell) {
3127 if (adev->asic_type == CHIP_CARRIZO) {
3128 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3129 AMDGPU_DOORBELL_KIQ << 2);
3130 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
78ad5cdd 3131 0x7FFFF << 2);
aaa36a97
AD		 3132 }
3133 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3134 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3135 DOORBELL_OFFSET, ring->doorbell_index);
3136 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3137 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3138 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3139 mqd->cp_hqd_pq_doorbell_control = tmp;
3140
3141 } else {
3142 mqd->cp_hqd_pq_doorbell_control = 0;
3143 }
3144 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3145 mqd->cp_hqd_pq_doorbell_control);
3146
845253e7
SJ		 3147 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3148 ring->wptr = 0;
3149 mqd->cp_hqd_pq_wptr = ring->wptr;
3150 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3151 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3152
aaa36a97
AD		 3153 /* set the vmid for the queue */
3154 mqd->cp_hqd_vmid = 0;
3155 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3156
3157 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3158 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3159 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3160 mqd->cp_hqd_persistent_state = tmp;
3161
3162 /* activate the queue */
3163 mqd->cp_hqd_active = 1;
3164 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3165
3166 vi_srbm_select(adev, 0, 0, 0, 0);
3167 mutex_unlock(&adev->srbm_mutex);
3168
3169 amdgpu_bo_kunmap(ring->mqd_obj);
3170 amdgpu_bo_unreserve(ring->mqd_obj);
3171 }
3172
3173 if (use_doorbell) {
3174 tmp = RREG32(mmCP_PQ_STATUS);
3175 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3176 WREG32(mmCP_PQ_STATUS, tmp);
3177 }
3178
3179 r = gfx_v8_0_cp_compute_start(adev);
3180 if (r)
3181 return r;
3182
3183 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3184 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3185
3186 ring->ready = true;
3187 r = amdgpu_ring_test_ring(ring);
3188 if (r)
3189 ring->ready = false;
3190 }
3191
3192 return 0;
3193}
3194
3195static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3196{
3197 int r;
3198
3199 if (adev->asic_type != CHIP_CARRIZO)
3200 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3201
3202 if (!adev->firmware.smu_load) {
3203 /* legacy firmware loading */
3204 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3205 if (r)
3206 return r;
3207
3208 r = gfx_v8_0_cp_compute_load_microcode(adev);
3209 if (r)
3210 return r;
3211 } else {
3212 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3213 AMDGPU_UCODE_ID_CP_CE);
3214 if (r)
3215 return -EINVAL;
3216
3217 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3218 AMDGPU_UCODE_ID_CP_PFP);
3219 if (r)
3220 return -EINVAL;
3221
3222 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3223 AMDGPU_UCODE_ID_CP_ME);
3224 if (r)
3225 return -EINVAL;
3226
3227 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3228 AMDGPU_UCODE_ID_CP_MEC1);
3229 if (r)
3230 return -EINVAL;
3231 }
3232
3233 r = gfx_v8_0_cp_gfx_resume(adev);
3234 if (r)
3235 return r;
3236
3237 r = gfx_v8_0_cp_compute_resume(adev);
3238 if (r)
3239 return r;
3240
3241 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3242
3243 return 0;
3244}
3245
3246static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3247{
3248 gfx_v8_0_cp_gfx_enable(adev, enable);
3249 gfx_v8_0_cp_compute_enable(adev, enable);
3250}
3251
5fc3aeeb 3252static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 3253{
3254 int r;
5fc3aeeb 3255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3256
3257 gfx_v8_0_init_golden_registers(adev);
3258
3259 gfx_v8_0_gpu_init(adev);
3260
3261 r = gfx_v8_0_rlc_resume(adev);
3262 if (r)
3263 return r;
3264
3265 r = gfx_v8_0_cp_resume(adev);
3266 if (r)
3267 return r;
3268
3269 return r;
3270}
3271
5fc3aeeb 3272static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 3273{
5fc3aeeb 3274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3275
aaa36a97
AD		 3276 gfx_v8_0_cp_enable(adev, false);
3277 gfx_v8_0_rlc_stop(adev);
3278 gfx_v8_0_cp_compute_fini(adev);
3279
3280 return 0;
3281}
3282
5fc3aeeb 3283static int gfx_v8_0_suspend(void *handle)
aaa36a97 3284{
5fc3aeeb 3285 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3286
aaa36a97
AD		 3287 return gfx_v8_0_hw_fini(adev);
3288}
3289
5fc3aeeb 3290static int gfx_v8_0_resume(void *handle)
aaa36a97 3291{
5fc3aeeb 3292 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3293
aaa36a97
AD		 3294 return gfx_v8_0_hw_init(adev);
3295}
3296
5fc3aeeb 3297static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 3298{
5fc3aeeb 3299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3300
aaa36a97
AD		 3301 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3302 return false;
3303 else
3304 return true;
3305}
3306
5fc3aeeb 3307static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 3308{
3309 unsigned i;
3310 u32 tmp;
5fc3aeeb 3311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3312
3313 for (i = 0; i < adev->usec_timeout; i++) {
3314 /* read MC_STATUS */
3315 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3316
3317 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3318 return 0;
3319 udelay(1);
3320 }
3321 return -ETIMEDOUT;
3322}
3323
5fc3aeeb 3324static void gfx_v8_0_print_status(void *handle)
aaa36a97
AD		 3325{
3326 int i;
5fc3aeeb 3327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3328
3329 dev_info(adev->dev, "GFX 8.x registers\n");
3330 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3331 RREG32(mmGRBM_STATUS));
3332 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3333 RREG32(mmGRBM_STATUS2));
3334 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3335 RREG32(mmGRBM_STATUS_SE0));
3336 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3337 RREG32(mmGRBM_STATUS_SE1));
3338 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3339 RREG32(mmGRBM_STATUS_SE2));
3340 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3341 RREG32(mmGRBM_STATUS_SE3));
3342 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3343 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3344 RREG32(mmCP_STALLED_STAT1));
3345 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3346 RREG32(mmCP_STALLED_STAT2));
3347 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3348 RREG32(mmCP_STALLED_STAT3));
3349 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3350 RREG32(mmCP_CPF_BUSY_STAT));
3351 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3352 RREG32(mmCP_CPF_STALLED_STAT1));
3353 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3354 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3355 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3356 RREG32(mmCP_CPC_STALLED_STAT1));
3357 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3358
3359 for (i = 0; i < 32; i++) {
3360 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3361 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3362 }
3363 for (i = 0; i < 16; i++) {
3364 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3365 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3366 }
3367 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3368 dev_info(adev->dev, " se: %d\n", i);
3369 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3370 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3371 RREG32(mmPA_SC_RASTER_CONFIG));
3372 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3373 RREG32(mmPA_SC_RASTER_CONFIG_1));
3374 }
3375 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3376
3377 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3378 RREG32(mmGB_ADDR_CONFIG));
3379 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3380 RREG32(mmHDP_ADDR_CONFIG));
3381 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3382 RREG32(mmDMIF_ADDR_CALC));
3383 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
3384 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3385 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
3386 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3387 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3388 RREG32(mmUVD_UDEC_ADDR_CONFIG));
3389 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3390 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3391 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3392 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3393
3394 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3395 RREG32(mmCP_MEQ_THRESHOLDS));
3396 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3397 RREG32(mmSX_DEBUG_1));
3398 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3399 RREG32(mmTA_CNTL_AUX));
3400 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3401 RREG32(mmSPI_CONFIG_CNTL));
3402 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3403 RREG32(mmSQ_CONFIG));
3404 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3405 RREG32(mmDB_DEBUG));
3406 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3407 RREG32(mmDB_DEBUG2));
3408 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3409 RREG32(mmDB_DEBUG3));
3410 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3411 RREG32(mmCB_HW_CONTROL));
3412 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3413 RREG32(mmSPI_CONFIG_CNTL_1));
3414 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3415 RREG32(mmPA_SC_FIFO_SIZE));
3416 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3417 RREG32(mmVGT_NUM_INSTANCES));
3418 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3419 RREG32(mmCP_PERFMON_CNTL));
3420 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3421 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3422 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3423 RREG32(mmVGT_CACHE_INVALIDATION));
3424 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3425 RREG32(mmVGT_GS_VERTEX_REUSE));
3426 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3427 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3428 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3429 RREG32(mmPA_CL_ENHANCE));
3430 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3431 RREG32(mmPA_SC_ENHANCE));
3432
3433 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3434 RREG32(mmCP_ME_CNTL));
3435 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3436 RREG32(mmCP_MAX_CONTEXT));
3437 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3438 RREG32(mmCP_ENDIAN_SWAP));
3439 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3440 RREG32(mmCP_DEVICE_ID));
3441
3442 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
3443 RREG32(mmCP_SEM_WAIT_TIMER));
3444
3445 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
3446 RREG32(mmCP_RB_WPTR_DELAY));
3447 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
3448 RREG32(mmCP_RB_VMID));
3449 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3450 RREG32(mmCP_RB0_CNTL));
3451 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
3452 RREG32(mmCP_RB0_WPTR));
3453 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
3454 RREG32(mmCP_RB0_RPTR_ADDR));
3455 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3456 RREG32(mmCP_RB0_RPTR_ADDR_HI));
3457 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3458 RREG32(mmCP_RB0_CNTL));
3459 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
3460 RREG32(mmCP_RB0_BASE));
3461 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
3462 RREG32(mmCP_RB0_BASE_HI));
3463 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
3464 RREG32(mmCP_MEC_CNTL));
3465 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
3466 RREG32(mmCP_CPF_DEBUG));
3467
3468 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
3469 RREG32(mmSCRATCH_ADDR));
3470 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
3471 RREG32(mmSCRATCH_UMSK));
3472
3473 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
3474 RREG32(mmCP_INT_CNTL_RING0));
3475 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3476 RREG32(mmRLC_LB_CNTL));
3477 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
3478 RREG32(mmRLC_CNTL));
3479 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
3480 RREG32(mmRLC_CGCG_CGLS_CTRL));
3481 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
3482 RREG32(mmRLC_LB_CNTR_INIT));
3483 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
3484 RREG32(mmRLC_LB_CNTR_MAX));
3485 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
3486 RREG32(mmRLC_LB_INIT_CU_MASK));
3487 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
3488 RREG32(mmRLC_LB_PARAMS));
3489 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3490 RREG32(mmRLC_LB_CNTL));
3491 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
3492 RREG32(mmRLC_MC_CNTL));
3493 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
3494 RREG32(mmRLC_UCODE_CNTL));
3495
3496 mutex_lock(&adev->srbm_mutex);
3497 for (i = 0; i < 16; i++) {
3498 vi_srbm_select(adev, 0, 0, 0, i);
3499 dev_info(adev->dev, " VM %d:\n", i);
3500 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
3501 RREG32(mmSH_MEM_CONFIG));
3502 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
3503 RREG32(mmSH_MEM_APE1_BASE));
3504 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
3505 RREG32(mmSH_MEM_APE1_LIMIT));
3506 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
3507 RREG32(mmSH_MEM_BASES));
3508 }
3509 vi_srbm_select(adev, 0, 0, 0, 0);
3510 mutex_unlock(&adev->srbm_mutex);
3511}
3512
5fc3aeeb 3513static int gfx_v8_0_soft_reset(void *handle)
aaa36a97
AD		 3514{
3515 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3516 u32 tmp;
5fc3aeeb 3517 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3518
3519 /* GRBM_STATUS */
3520 tmp = RREG32(mmGRBM_STATUS);
3521 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3522 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3523 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3524 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3525 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3526 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3527 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3528 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3529 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3530 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3531 }
3532
3533 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3534 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3535 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3536 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3537 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3538 }
3539
3540 /* GRBM_STATUS2 */
3541 tmp = RREG32(mmGRBM_STATUS2);
3542 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3543 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3544 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3545
3546 /* SRBM_STATUS */
3547 tmp = RREG32(mmSRBM_STATUS);
3548 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3549 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3550 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3551
3552 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 3553 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 3554 /* stop the rlc */
3555 gfx_v8_0_rlc_stop(adev);
3556
3557 /* Disable GFX parsing/prefetching */
3558 gfx_v8_0_cp_gfx_enable(adev, false);
3559
3560 /* Disable MEC parsing/prefetching */
3561 /* XXX todo */
3562
3563 if (grbm_soft_reset) {
3564 tmp = RREG32(mmGRBM_SOFT_RESET);
3565 tmp |= grbm_soft_reset;
3566 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3567 WREG32(mmGRBM_SOFT_RESET, tmp);
3568 tmp = RREG32(mmGRBM_SOFT_RESET);
3569
3570 udelay(50);
3571
3572 tmp &= ~grbm_soft_reset;
3573 WREG32(mmGRBM_SOFT_RESET, tmp);
3574 tmp = RREG32(mmGRBM_SOFT_RESET);
3575 }
3576
3577 if (srbm_soft_reset) {
3578 tmp = RREG32(mmSRBM_SOFT_RESET);
3579 tmp |= srbm_soft_reset;
3580 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3581 WREG32(mmSRBM_SOFT_RESET, tmp);
3582 tmp = RREG32(mmSRBM_SOFT_RESET);
3583
3584 udelay(50);
3585
3586 tmp &= ~srbm_soft_reset;
3587 WREG32(mmSRBM_SOFT_RESET, tmp);
3588 tmp = RREG32(mmSRBM_SOFT_RESET);
3589 }
3590 /* Wait a little for things to settle down */
3591 udelay(50);
5fc3aeeb 3592 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 3593 }
3594 return 0;
3595}
3596
3597/**
3598 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3599 *
3600 * @adev: amdgpu_device pointer
3601 *
3602 * Fetches a GPU clock counter snapshot.
3603 * Returns the 64 bit clock counter snapshot.
3604 */
3605uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3606{
3607 uint64_t clock;
3608
3609 mutex_lock(&adev->gfx.gpu_clock_mutex);
3610 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3611 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3612 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3613 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3614 return clock;
3615}
3616
3617static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3618 uint32_t vmid,
3619 uint32_t gds_base, uint32_t gds_size,
3620 uint32_t gws_base, uint32_t gws_size,
3621 uint32_t oa_base, uint32_t oa_size)
3622{
3623 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3624 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3625
3626 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3627 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3628
3629 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3630 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3631
3632 /* GDS Base */
3633 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3634 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3635 WRITE_DATA_DST_SEL(0)));
3636 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3637 amdgpu_ring_write(ring, 0);
3638 amdgpu_ring_write(ring, gds_base);
3639
3640 /* GDS Size */
3641 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3642 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3643 WRITE_DATA_DST_SEL(0)));
3644 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3645 amdgpu_ring_write(ring, 0);
3646 amdgpu_ring_write(ring, gds_size);
3647
3648 /* GWS */
3649 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3650 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3651 WRITE_DATA_DST_SEL(0)));
3652 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3653 amdgpu_ring_write(ring, 0);
3654 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3655
3656 /* OA */
3657 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3658 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3659 WRITE_DATA_DST_SEL(0)));
3660 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3661 amdgpu_ring_write(ring, 0);
3662 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3663}
3664
5fc3aeeb 3665static int gfx_v8_0_early_init(void *handle)
aaa36a97 3666{
5fc3aeeb 3667 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3668
3669 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3670 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3671 gfx_v8_0_set_ring_funcs(adev);
3672 gfx_v8_0_set_irq_funcs(adev);
3673 gfx_v8_0_set_gds_init(adev);
3674
3675 return 0;
3676}
3677
5fc3aeeb 3678static int gfx_v8_0_set_powergating_state(void *handle,
3679 enum amd_powergating_state state)
aaa36a97
AD		 3680{
3681 return 0;
3682}
3683
5fc3aeeb 3684static int gfx_v8_0_set_clockgating_state(void *handle,
3685 enum amd_clockgating_state state)
aaa36a97
AD		 3686{
3687 return 0;
3688}
3689
3690static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3691{
3692 u32 rptr;
3693
3694 rptr = ring->adev->wb.wb[ring->rptr_offs];
3695
3696 return rptr;
3697}
3698
3699static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3700{
3701 struct amdgpu_device *adev = ring->adev;
3702 u32 wptr;
3703
3704 if (ring->use_doorbell)
3705 /* XXX check if swapping is necessary on BE */
3706 wptr = ring->adev->wb.wb[ring->wptr_offs];
3707 else
3708 wptr = RREG32(mmCP_RB0_WPTR);
3709
3710 return wptr;
3711}
3712
3713static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3714{
3715 struct amdgpu_device *adev = ring->adev;
3716
3717 if (ring->use_doorbell) {
3718 /* XXX check if swapping is necessary on BE */
3719 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3720 WDOORBELL32(ring->doorbell_index, ring->wptr);
3721 } else {
3722 WREG32(mmCP_RB0_WPTR, ring->wptr);
3723 (void)RREG32(mmCP_RB0_WPTR);
3724 }
3725}
3726
d2edb07b 3727static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 3728{
3729 u32 ref_and_mask, reg_mem_engine;
3730
3731 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3732 switch (ring->me) {
3733 case 1:
3734 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3735 break;
3736 case 2:
3737 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3738 break;
3739 default:
3740 return;
3741 }
3742 reg_mem_engine = 0;
3743 } else {
3744 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3745 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3746 }
3747
3748 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3749 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3750 WAIT_REG_MEM_FUNCTION(3) | /* == */
3751 reg_mem_engine));
3752 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3753 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3754 amdgpu_ring_write(ring, ref_and_mask);
3755 amdgpu_ring_write(ring, ref_and_mask);
3756 amdgpu_ring_write(ring, 0x20); /* poll interval */
3757}
3758
3759static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3760 struct amdgpu_ib *ib)
3761{
3cb485f3 3762 bool need_ctx_switch = ring->current_ctx != ib->ctx;
aaa36a97
AD		 3763 u32 header, control = 0;
3764 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 3765
3766 /* drop the CE preamble IB for the same context */
3767 if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
3768 (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
3cb485f3 3769 !need_ctx_switch)
aa2bdb24
JZ		 3770 return;
3771
aaa36a97
AD		 3772 if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
3773 control |= INDIRECT_BUFFER_VALID;
3774
3cb485f3 3775 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
aaa36a97
AD		 3776 next_rptr += 2;
3777
3778 next_rptr += 4;
3779 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3780 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3781 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3782 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3783 amdgpu_ring_write(ring, next_rptr);
3784
aaa36a97 3785 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3cb485f3 3786 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
aaa36a97
AD		 3787 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3788 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 3789 }
3790
de807f81 3791 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 3792 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3793 else
3794 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3795
3796 control |= ib->length_dw |
3797 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3798
3799 amdgpu_ring_write(ring, header);
3800 amdgpu_ring_write(ring,
3801#ifdef __BIG_ENDIAN
3802 (2 << 0) |
3803#endif
3804 (ib->gpu_addr & 0xFFFFFFFC));
3805 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3806 amdgpu_ring_write(ring, control);
3807}
3808
3809static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 3810 u64 seq, unsigned flags)
aaa36a97 3811{
890ee23f
CZ		 3812 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3813 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3814
aaa36a97
AD		 3815 /* EVENT_WRITE_EOP - flush caches, send int */
3816 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3817 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3818 EOP_TC_ACTION_EN |
3819 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3820 EVENT_INDEX(5)));
3821 amdgpu_ring_write(ring, addr & 0xfffffffc);
3822 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 3823 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 3824 amdgpu_ring_write(ring, lower_32_bits(seq));
3825 amdgpu_ring_write(ring, upper_32_bits(seq));
3826}
3827
3828/**
3829 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3830 *
3831 * @ring: amdgpu ring buffer object
3832 * @semaphore: amdgpu semaphore object
3833 * @emit_wait: Is this a sempahore wait?
3834 *
3835 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3836 * from running ahead of semaphore waits.
3837 */
3838static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3839 struct amdgpu_semaphore *semaphore,
3840 bool emit_wait)
3841{
3842 uint64_t addr = semaphore->gpu_addr;
3843 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3844
3845 if (ring->adev->asic_type == CHIP_TOPAZ ||
147dbfbc
DZ		 3846 ring->adev->asic_type == CHIP_TONGA)
3847 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3848 return false;
3849 else {
aaa36a97
AD		 3850 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3851 amdgpu_ring_write(ring, lower_32_bits(addr));
3852 amdgpu_ring_write(ring, upper_32_bits(addr));
3853 amdgpu_ring_write(ring, sel);
3854 }
3855
3856 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3857 /* Prevent the PFP from running ahead of the semaphore wait */
3858 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3859 amdgpu_ring_write(ring, 0x0);
3860 }
3861
3862 return true;
3863}
3864
3865static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
3866{
3867 struct amdgpu_device *adev = ring->adev;
3868 u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3869
3870 /* instruct DE to set a magic number */
3871 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3872 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3873 WRITE_DATA_DST_SEL(5)));
3874 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3875 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3876 amdgpu_ring_write(ring, 1);
3877
3878 /* let CE wait till condition satisfied */
3879 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3880 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3881 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3882 WAIT_REG_MEM_FUNCTION(3) | /* == */
3883 WAIT_REG_MEM_ENGINE(2))); /* ce */
3884 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3885 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3886 amdgpu_ring_write(ring, 1);
3887 amdgpu_ring_write(ring, 0xffffffff);
3888 amdgpu_ring_write(ring, 4); /* poll interval */
3889
3890 /* instruct CE to reset wb of ce_sync to zero */
3891 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3892 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3893 WRITE_DATA_DST_SEL(5) |
3894 WR_CONFIRM));
3895 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3896 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3897 amdgpu_ring_write(ring, 0);
3898}
3899
3900static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3901 unsigned vm_id, uint64_t pd_addr)
3902{
3903 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
aaa36a97
AD		 3904
3905 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3906 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3907 WRITE_DATA_DST_SEL(0)));
3908 if (vm_id < 8) {
3909 amdgpu_ring_write(ring,
3910 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3911 } else {
3912 amdgpu_ring_write(ring,
3913 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3914 }
3915 amdgpu_ring_write(ring, 0);
3916 amdgpu_ring_write(ring, pd_addr >> 12);
3917
aaa36a97
AD		 3918 /* bits 0-15 are the VM contexts0-15 */
3919 /* invalidate the cache */
3920 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3921 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3922 WRITE_DATA_DST_SEL(0)));
3923 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3924 amdgpu_ring_write(ring, 0);
3925 amdgpu_ring_write(ring, 1 << vm_id);
3926
3927 /* wait for the invalidate to complete */
3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3929 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3930 WAIT_REG_MEM_FUNCTION(0) | /* always */
3931 WAIT_REG_MEM_ENGINE(0))); /* me */
3932 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3933 amdgpu_ring_write(ring, 0);
3934 amdgpu_ring_write(ring, 0); /* ref */
3935 amdgpu_ring_write(ring, 0); /* mask */
3936 amdgpu_ring_write(ring, 0x20); /* poll interval */
3937
3938 /* compute doesn't have PFP */
3939 if (usepfp) {
3940 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3941 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3942 amdgpu_ring_write(ring, 0x0);
3943
3944 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3945 gfx_v8_0_ce_sync_me(ring);
3946 }
3947}
3948
3949static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
3950{
3951 if (gfx_v8_0_is_idle(ring->adev)) {
3952 amdgpu_ring_lockup_update(ring);
3953 return false;
3954 }
3955 return amdgpu_ring_test_lockup(ring);
3956}
3957
3958static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3959{
3960 return ring->adev->wb.wb[ring->rptr_offs];
3961}
3962
3963static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3964{
3965 return ring->adev->wb.wb[ring->wptr_offs];
3966}
3967
3968static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3969{
3970 struct amdgpu_device *adev = ring->adev;
3971
3972 /* XXX check if swapping is necessary on BE */
3973 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3974 WDOORBELL32(ring->doorbell_index, ring->wptr);
3975}
3976
3977static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
3978 u64 addr, u64 seq,
890ee23f 3979 unsigned flags)
aaa36a97 3980{
890ee23f
CZ		 3981 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3982 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3983
aaa36a97
AD		 3984 /* RELEASE_MEM - flush caches, send int */
3985 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3986 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3987 EOP_TC_ACTION_EN |
3988 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3989 EVENT_INDEX(5)));
890ee23f 3990 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 3991 amdgpu_ring_write(ring, addr & 0xfffffffc);
3992 amdgpu_ring_write(ring, upper_32_bits(addr));
3993 amdgpu_ring_write(ring, lower_32_bits(seq));
3994 amdgpu_ring_write(ring, upper_32_bits(seq));
3995}
3996
3997static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3998 enum amdgpu_interrupt_state state)
3999{
4000 u32 cp_int_cntl;
4001
4002 switch (state) {
4003 case AMDGPU_IRQ_STATE_DISABLE:
4004 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4005 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4006 TIME_STAMP_INT_ENABLE, 0);
4007 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4008 break;
4009 case AMDGPU_IRQ_STATE_ENABLE:
4010 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4011 cp_int_cntl =
4012 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4013 TIME_STAMP_INT_ENABLE, 1);
4014 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4015 break;
4016 default:
4017 break;
4018 }
4019}
4020
4021static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4022 int me, int pipe,
4023 enum amdgpu_interrupt_state state)
4024{
4025 u32 mec_int_cntl, mec_int_cntl_reg;
4026
4027 /*
4028 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4029 * handles the setting of interrupts for this specific pipe. All other
4030 * pipes' interrupts are set by amdkfd.
4031 */
4032
4033 if (me == 1) {
4034 switch (pipe) {
4035 case 0:
4036 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4037 break;
4038 default:
4039 DRM_DEBUG("invalid pipe %d\n", pipe);
4040 return;
4041 }
4042 } else {
4043 DRM_DEBUG("invalid me %d\n", me);
4044 return;
4045 }
4046
4047 switch (state) {
4048 case AMDGPU_IRQ_STATE_DISABLE:
4049 mec_int_cntl = RREG32(mec_int_cntl_reg);
4050 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4051 TIME_STAMP_INT_ENABLE, 0);
4052 WREG32(mec_int_cntl_reg, mec_int_cntl);
4053 break;
4054 case AMDGPU_IRQ_STATE_ENABLE:
4055 mec_int_cntl = RREG32(mec_int_cntl_reg);
4056 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4057 TIME_STAMP_INT_ENABLE, 1);
4058 WREG32(mec_int_cntl_reg, mec_int_cntl);
4059 break;
4060 default:
4061 break;
4062 }
4063}
4064
4065static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4066 struct amdgpu_irq_src *source,
4067 unsigned type,
4068 enum amdgpu_interrupt_state state)
4069{
4070 u32 cp_int_cntl;
4071
4072 switch (state) {
4073 case AMDGPU_IRQ_STATE_DISABLE:
4074 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4075 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4076 PRIV_REG_INT_ENABLE, 0);
4077 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4078 break;
4079 case AMDGPU_IRQ_STATE_ENABLE:
4080 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4081 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4082 PRIV_REG_INT_ENABLE, 0);
4083 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4084 break;
4085 default:
4086 break;
4087 }
4088
4089 return 0;
4090}
4091
4092static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4093 struct amdgpu_irq_src *source,
4094 unsigned type,
4095 enum amdgpu_interrupt_state state)
4096{
4097 u32 cp_int_cntl;
4098
4099 switch (state) {
4100 case AMDGPU_IRQ_STATE_DISABLE:
4101 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4102 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4103 PRIV_INSTR_INT_ENABLE, 0);
4104 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4105 break;
4106 case AMDGPU_IRQ_STATE_ENABLE:
4107 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4108 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4109 PRIV_INSTR_INT_ENABLE, 1);
4110 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4111 break;
4112 default:
4113 break;
4114 }
4115
4116 return 0;
4117}
4118
4119static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4120 struct amdgpu_irq_src *src,
4121 unsigned type,
4122 enum amdgpu_interrupt_state state)
4123{
4124 switch (type) {
4125 case AMDGPU_CP_IRQ_GFX_EOP:
4126 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4127 break;
4128 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4129 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4130 break;
4131 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4132 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4133 break;
4134 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4135 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4136 break;
4137 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4138 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4139 break;
4140 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4141 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4142 break;
4143 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4144 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4145 break;
4146 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4147 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4148 break;
4149 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4150 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4151 break;
4152 default:
4153 break;
4154 }
4155 return 0;
4156}
4157
4158static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4159 struct amdgpu_irq_src *source,
4160 struct amdgpu_iv_entry *entry)
4161{
4162 int i;
4163 u8 me_id, pipe_id, queue_id;
4164 struct amdgpu_ring *ring;
4165
4166 DRM_DEBUG("IH: CP EOP\n");
4167 me_id = (entry->ring_id & 0x0c) >> 2;
4168 pipe_id = (entry->ring_id & 0x03) >> 0;
4169 queue_id = (entry->ring_id & 0x70) >> 4;
4170
4171 switch (me_id) {
4172 case 0:
4173 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4174 break;
4175 case 1:
4176 case 2:
4177 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4178 ring = &adev->gfx.compute_ring[i];
4179 /* Per-queue interrupt is supported for MEC starting from VI.
4180 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4181 */
4182 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4183 amdgpu_fence_process(ring);
4184 }
4185 break;
4186 }
4187 return 0;
4188}
4189
4190static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4191 struct amdgpu_irq_src *source,
4192 struct amdgpu_iv_entry *entry)
4193{
4194 DRM_ERROR("Illegal register access in command stream\n");
4195 schedule_work(&adev->reset_work);
4196 return 0;
4197}
4198
4199static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4200 struct amdgpu_irq_src *source,
4201 struct amdgpu_iv_entry *entry)
4202{
4203 DRM_ERROR("Illegal instruction in command stream\n");
4204 schedule_work(&adev->reset_work);
4205 return 0;
4206}
4207
5fc3aeeb 4208const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
aaa36a97
AD		 4209 .early_init = gfx_v8_0_early_init,
4210 .late_init = NULL,
4211 .sw_init = gfx_v8_0_sw_init,
4212 .sw_fini = gfx_v8_0_sw_fini,
4213 .hw_init = gfx_v8_0_hw_init,
4214 .hw_fini = gfx_v8_0_hw_fini,
4215 .suspend = gfx_v8_0_suspend,
4216 .resume = gfx_v8_0_resume,
4217 .is_idle = gfx_v8_0_is_idle,
4218 .wait_for_idle = gfx_v8_0_wait_for_idle,
4219 .soft_reset = gfx_v8_0_soft_reset,
4220 .print_status = gfx_v8_0_print_status,
4221 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4222 .set_powergating_state = gfx_v8_0_set_powergating_state,
4223};
4224
4225static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4226 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4227 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4228 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4229 .parse_cs = NULL,
4230 .emit_ib = gfx_v8_0_ring_emit_ib,
4231 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4232 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4233 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4234 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 4235 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
aaa36a97
AD		 4236 .test_ring = gfx_v8_0_ring_test_ring,
4237 .test_ib = gfx_v8_0_ring_test_ib,
4238 .is_lockup = gfx_v8_0_ring_is_lockup,
4239};
4240
4241static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4242 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4243 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4244 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4245 .parse_cs = NULL,
4246 .emit_ib = gfx_v8_0_ring_emit_ib,
4247 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4248 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4249 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4250 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 4251 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
aaa36a97
AD		 4252 .test_ring = gfx_v8_0_ring_test_ring,
4253 .test_ib = gfx_v8_0_ring_test_ib,
4254 .is_lockup = gfx_v8_0_ring_is_lockup,
4255};
4256
4257static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4258{
4259 int i;
4260
4261 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4262 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4263
4264 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4265 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4266}
4267
4268static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4269 .set = gfx_v8_0_set_eop_interrupt_state,
4270 .process = gfx_v8_0_eop_irq,
4271};
4272
4273static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4274 .set = gfx_v8_0_set_priv_reg_fault_state,
4275 .process = gfx_v8_0_priv_reg_irq,
4276};
4277
4278static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4279 .set = gfx_v8_0_set_priv_inst_fault_state,
4280 .process = gfx_v8_0_priv_inst_irq,
4281};
4282
4283static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4284{
4285 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4286 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4287
4288 adev->gfx.priv_reg_irq.num_types = 1;
4289 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4290
4291 adev->gfx.priv_inst_irq.num_types = 1;
4292 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4293}
4294
4295static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4296{
4297 /* init asci gds info */
4298 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4299 adev->gds.gws.total_size = 64;
4300 adev->gds.oa.total_size = 16;
4301
4302 if (adev->gds.mem.total_size == 64 * 1024) {
4303 adev->gds.mem.gfx_partition_size = 4096;
4304 adev->gds.mem.cs_partition_size = 4096;
4305
4306 adev->gds.gws.gfx_partition_size = 4;
4307 adev->gds.gws.cs_partition_size = 4;
4308
4309 adev->gds.oa.gfx_partition_size = 4;
4310 adev->gds.oa.cs_partition_size = 1;
4311 } else {
4312 adev->gds.mem.gfx_partition_size = 1024;
4313 adev->gds.mem.cs_partition_size = 1024;
4314
4315 adev->gds.gws.gfx_partition_size = 16;
4316 adev->gds.gws.cs_partition_size = 16;
4317
4318 adev->gds.oa.gfx_partition_size = 4;
4319 adev->gds.oa.cs_partition_size = 4;
4320 }
4321}
4322
4323static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4324 u32 se, u32 sh)
4325{
4326 u32 mask = 0, tmp, tmp1;
4327 int i;
4328
4329 gfx_v8_0_select_se_sh(adev, se, sh);
4330 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4331 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4332 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4333
4334 tmp &= 0xffff0000;
4335
4336 tmp |= tmp1;
4337 tmp >>= 16;
4338
4339 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4340 mask <<= 1;
4341 mask |= 1;
4342 }
4343
4344 return (~tmp) & mask;
4345}
4346
4347int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4348 struct amdgpu_cu_info *cu_info)
4349{
4350 int i, j, k, counter, active_cu_number = 0;
4351 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4352
4353 if (!adev || !cu_info)
4354 return -EINVAL;
4355
4356 mutex_lock(&adev->grbm_idx_mutex);
4357 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4358 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4359 mask = 1;
4360 ao_bitmap = 0;
4361 counter = 0;
4362 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4363 cu_info->bitmap[i][j] = bitmap;
4364
4365 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4366 if (bitmap & mask) {
4367 if (counter < 2)
4368 ao_bitmap |= mask;
4369 counter ++;
4370 }
4371 mask <<= 1;
4372 }
4373 active_cu_number += counter;
4374 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4375 }
4376 }
4377
4378 cu_info->number = active_cu_number;
4379 cu_info->ao_cu_mask = ao_cu_mask;
4380 mutex_unlock(&adev->grbm_idx_mutex);
4381 return 0;
4382}
Linux kernel - Deliverables
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