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drm/amdgpu: free the job immediately after dispatching it
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_vi.h"
31
32#include "gmc/gmc_8_2_d.h"
33#include "gmc/gmc_8_2_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44#include "gca/gfx_8_0_enum.h"
45
46#include "uvd/uvd_5_0_d.h"
47#include "uvd/uvd_5_0_sh_mask.h"
48
49#include "dce/dce_10_0_d.h"
50#include "dce/dce_10_0_sh_mask.h"
51
52#define GFX8_NUM_GFX_RINGS 1
53#define GFX8_NUM_COMPUTE_RINGS 8
54
55#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
56#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
57#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
58
59#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
60#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
61#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
62#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
63#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
64#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
65#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
66#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
67#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
68
c65444fe
JZ		 69MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
70MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
71MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
72MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
75
76MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
77MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
78MODULE_FIRMWARE("amdgpu/tonga_me.bin");
79MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
80MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
81MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
82
83MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
84MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
85MODULE_FIRMWARE("amdgpu/topaz_me.bin");
86MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
87MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
88MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97 89
af15a2d5
DZ		 90MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
91MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
92MODULE_FIRMWARE("amdgpu/fiji_me.bin");
93MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
94MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
95MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
96
aaa36a97
AD		 97static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
98{
99 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
100 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
101 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
102 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
103 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
104 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
105 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
106 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
107 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
108 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
109 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
110 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
111 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
112 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
113 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
114 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
115};
116
117static const u32 golden_settings_tonga_a11[] =
118{
119 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
120 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
121 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
122 mmGB_GPU_ID, 0x0000000f, 0x00000000,
123 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
124 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
125 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 126 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 127 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
128 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 129 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 130 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
131 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
132 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 133 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 134};
135
136static const u32 tonga_golden_common_all[] =
137{
138 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
139 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
140 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
141 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
142 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
143 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
144 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
145 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
146};
147
148static const u32 tonga_mgcg_cgcg_init[] =
149{
150 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
151 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
152 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
153 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
154 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
155 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
156 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
157 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
158 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
159 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
160 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
161 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
162 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
163 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
164 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
165 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
166 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
167 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
168 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
169 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
170 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
171 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
172 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
173 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
174 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
175 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
176 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
177 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
178 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
179 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
180 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
181 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
182 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
183 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
184 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
185 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
186 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
187 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
188 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
189 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
190 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
191 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
192 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
193 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
194 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
195 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
196 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
197 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
198 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
199 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
200 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
201 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
202 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
203 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
204 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
205 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
206 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
207 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
208 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
209 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
210 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
211 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
212 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
213 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
214 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
215 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
216 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
217 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
218 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
219 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
220 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
221 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
222 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
223 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
224 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
225};
226
af15a2d5
DZ		 227static const u32 fiji_golden_common_all[] =
228{
229 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
230 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
231 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
232 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
233 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
234 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
235 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
236 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
237};
238
239static const u32 golden_settings_fiji_a10[] =
240{
241 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
242 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
243 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
244 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
245 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
246 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
247 mmTCC_CTRL, 0x00100000, 0xf30fff7f,
248 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
249 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
250 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
251};
252
253static const u32 fiji_mgcg_cgcg_init[] =
254{
255 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
256 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
257 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
258 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
259 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
260 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
261 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
262 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
263 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
264 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
265 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
266 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
267 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
268 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
269 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
270 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
271 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
272 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
273 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
274 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
275 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
276 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
277 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
278 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
279 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
280 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
281 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
282 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
283 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
284 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
285 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
286 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
287 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
288 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
289 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
290};
291
aaa36a97
AD		 292static const u32 golden_settings_iceland_a11[] =
293{
294 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
295 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
296 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
297 mmGB_GPU_ID, 0x0000000f, 0x00000000,
298 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
299 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
300 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
301 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
6a00a09e 302 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 303 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
304 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 305 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 306 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
307 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
308 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
309};
310
311static const u32 iceland_golden_common_all[] =
312{
313 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
314 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
315 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
316 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
317 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
318 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
319 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
320 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
321};
322
323static const u32 iceland_mgcg_cgcg_init[] =
324{
325 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
326 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
327 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
328 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
329 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
330 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
331 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
332 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
333 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
334 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
335 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
336 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
337 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
338 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
339 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
340 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
341 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
342 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
343 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
344 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
345 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
346 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
347 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
348 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
349 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
350 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
351 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
352 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
353 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
354 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
355 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
356 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
357 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
358 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
359 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
360 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
361 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
362 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
363 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
364 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
365 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
366 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
367 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
368 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
369 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
370 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
371 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
372 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
373 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
374 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
375 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
376 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
377 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
378 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
379 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
380 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
381 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
382 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
383 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
384 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
385 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
386 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
387 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
388 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
389};
390
391static const u32 cz_golden_settings_a11[] =
392{
393 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
394 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
395 mmGB_GPU_ID, 0x0000000f, 0x00000000,
396 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
397 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 398 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 399 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
6a00a09e 400 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 401 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
402 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
403};
404
405static const u32 cz_golden_common_all[] =
406{
407 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
408 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
409 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
410 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
411 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
412 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
413 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
414 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
415};
416
417static const u32 cz_mgcg_cgcg_init[] =
418{
419 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
420 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
421 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
422 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
423 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
424 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
425 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
426 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
427 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
428 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
429 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
430 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
431 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
432 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
433 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
434 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
435 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
436 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
437 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
438 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
439 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
440 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
441 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
444 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
445 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
446 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
447 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
448 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
449 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
450 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
451 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
452 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
453 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
454 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
455 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
456 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
457 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
458 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
459 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
460 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
461 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
462 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
463 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
464 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
465 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
466 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
467 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
468 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
469 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
470 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
471 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
472 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
473 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
474 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
475 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
476 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
477 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
478 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
479 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
480 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
481 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
482 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
483 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
484 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
485 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
486 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
487 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
488 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
489 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
490 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
491 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
492 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
493 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
494};
495
496static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
497static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
498static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
499
500static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
501{
502 switch (adev->asic_type) {
503 case CHIP_TOPAZ:
504 amdgpu_program_register_sequence(adev,
505 iceland_mgcg_cgcg_init,
506 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
507 amdgpu_program_register_sequence(adev,
508 golden_settings_iceland_a11,
509 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
510 amdgpu_program_register_sequence(adev,
511 iceland_golden_common_all,
512 (const u32)ARRAY_SIZE(iceland_golden_common_all));
513 break;
af15a2d5
DZ		 514 case CHIP_FIJI:
515 amdgpu_program_register_sequence(adev,
516 fiji_mgcg_cgcg_init,
517 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
518 amdgpu_program_register_sequence(adev,
519 golden_settings_fiji_a10,
520 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
521 amdgpu_program_register_sequence(adev,
522 fiji_golden_common_all,
523 (const u32)ARRAY_SIZE(fiji_golden_common_all));
524 break;
525
aaa36a97
AD		 526 case CHIP_TONGA:
527 amdgpu_program_register_sequence(adev,
528 tonga_mgcg_cgcg_init,
529 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
530 amdgpu_program_register_sequence(adev,
531 golden_settings_tonga_a11,
532 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
533 amdgpu_program_register_sequence(adev,
534 tonga_golden_common_all,
535 (const u32)ARRAY_SIZE(tonga_golden_common_all));
536 break;
537 case CHIP_CARRIZO:
538 amdgpu_program_register_sequence(adev,
539 cz_mgcg_cgcg_init,
540 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
541 amdgpu_program_register_sequence(adev,
542 cz_golden_settings_a11,
543 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
544 amdgpu_program_register_sequence(adev,
545 cz_golden_common_all,
546 (const u32)ARRAY_SIZE(cz_golden_common_all));
547 break;
548 default:
549 break;
550 }
551}
552
553static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
554{
555 int i;
556
557 adev->gfx.scratch.num_reg = 7;
558 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
559 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
560 adev->gfx.scratch.free[i] = true;
561 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
562 }
563}
564
565static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
566{
567 struct amdgpu_device *adev = ring->adev;
568 uint32_t scratch;
569 uint32_t tmp = 0;
570 unsigned i;
571 int r;
572
573 r = amdgpu_gfx_scratch_get(adev, &scratch);
574 if (r) {
575 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
576 return r;
577 }
578 WREG32(scratch, 0xCAFEDEAD);
579 r = amdgpu_ring_lock(ring, 3);
580 if (r) {
581 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
582 ring->idx, r);
583 amdgpu_gfx_scratch_free(adev, scratch);
584 return r;
585 }
586 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
587 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
588 amdgpu_ring_write(ring, 0xDEADBEEF);
589 amdgpu_ring_unlock_commit(ring);
590
591 for (i = 0; i < adev->usec_timeout; i++) {
592 tmp = RREG32(scratch);
593 if (tmp == 0xDEADBEEF)
594 break;
595 DRM_UDELAY(1);
596 }
597 if (i < adev->usec_timeout) {
598 DRM_INFO("ring test on %d succeeded in %d usecs\n",
599 ring->idx, i);
600 } else {
601 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
602 ring->idx, scratch, tmp);
603 r = -EINVAL;
604 }
605 amdgpu_gfx_scratch_free(adev, scratch);
606 return r;
607}
608
609static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
610{
611 struct amdgpu_device *adev = ring->adev;
612 struct amdgpu_ib ib;
1763552e 613 struct fence *f = NULL;
aaa36a97
AD		 614 uint32_t scratch;
615 uint32_t tmp = 0;
616 unsigned i;
617 int r;
618
619 r = amdgpu_gfx_scratch_get(adev, &scratch);
620 if (r) {
621 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
622 return r;
623 }
624 WREG32(scratch, 0xCAFEDEAD);
625 r = amdgpu_ib_get(ring, NULL, 256, &ib);
626 if (r) {
627 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 628 goto err1;
aaa36a97
AD		 629 }
630 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
631 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
632 ib.ptr[2] = 0xDEADBEEF;
633 ib.length_dw = 3;
42d13693
CZ		 634
635 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
1763552e
CZ		 636 AMDGPU_FENCE_OWNER_UNDEFINED,
637 &f);
42d13693
CZ		 638 if (r)
639 goto err2;
640
1763552e 641 r = fence_wait(f, false);
aaa36a97
AD		 642 if (r) {
643 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 644 goto err2;
aaa36a97
AD		 645 }
646 for (i = 0; i < adev->usec_timeout; i++) {
647 tmp = RREG32(scratch);
648 if (tmp == 0xDEADBEEF)
649 break;
650 DRM_UDELAY(1);
651 }
652 if (i < adev->usec_timeout) {
653 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 654 ring->idx, i);
655 goto err2;
aaa36a97
AD		 656 } else {
657 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
658 scratch, tmp);
659 r = -EINVAL;
660 }
42d13693 661err2:
281b4223 662 fence_put(f);
aaa36a97 663 amdgpu_ib_free(adev, &ib);
42d13693
CZ		 664err1:
665 amdgpu_gfx_scratch_free(adev, scratch);
aaa36a97
AD		 666 return r;
667}
668
669static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
670{
671 const char *chip_name;
672 char fw_name[30];
673 int err;
674 struct amdgpu_firmware_info *info = NULL;
675 const struct common_firmware_header *header = NULL;
595fd013 676 const struct gfx_firmware_header_v1_0 *cp_hdr;
aaa36a97
AD		 677
678 DRM_DEBUG("\n");
679
680 switch (adev->asic_type) {
681 case CHIP_TOPAZ:
682 chip_name = "topaz";
683 break;
684 case CHIP_TONGA:
685 chip_name = "tonga";
686 break;
687 case CHIP_CARRIZO:
688 chip_name = "carrizo";
689 break;
af15a2d5
DZ		 690 case CHIP_FIJI:
691 chip_name = "fiji";
692 break;
aaa36a97
AD		 693 default:
694 BUG();
695 }
696
c65444fe 697 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 698 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
699 if (err)
700 goto out;
701 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
702 if (err)
703 goto out;
595fd013
JZ		 704 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
705 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
706 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 707
c65444fe 708 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 709 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
710 if (err)
711 goto out;
712 err = amdgpu_ucode_validate(adev->gfx.me_fw);
713 if (err)
714 goto out;
595fd013
JZ		 715 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
716 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
717 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 718
c65444fe 719 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 720 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
721 if (err)
722 goto out;
723 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
724 if (err)
725 goto out;
595fd013
JZ		 726 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
727 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
728 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 729
c65444fe 730 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 731 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
732 if (err)
733 goto out;
734 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
595fd013
JZ		 735 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
736 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
737 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 738
c65444fe 739 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 740 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
741 if (err)
742 goto out;
743 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
744 if (err)
745 goto out;
595fd013
JZ		 746 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
747 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
748 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 749
c65444fe 750 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
aaa36a97
AD		 751 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
752 if (!err) {
753 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
754 if (err)
755 goto out;
595fd013
JZ		 756 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
757 adev->gfx.mec2_fw->data;
758 adev->gfx.mec2_fw_version = le32_to_cpu(
759 cp_hdr->header.ucode_version);
760 adev->gfx.mec2_feature_version = le32_to_cpu(
761 cp_hdr->ucode_feature_version);
aaa36a97
AD		 762 } else {
763 err = 0;
764 adev->gfx.mec2_fw = NULL;
765 }
766
767 if (adev->firmware.smu_load) {
768 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
769 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
770 info->fw = adev->gfx.pfp_fw;
771 header = (const struct common_firmware_header *)info->fw->data;
772 adev->firmware.fw_size +=
773 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
774
775 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
776 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
777 info->fw = adev->gfx.me_fw;
778 header = (const struct common_firmware_header *)info->fw->data;
779 adev->firmware.fw_size +=
780 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
781
782 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
783 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
784 info->fw = adev->gfx.ce_fw;
785 header = (const struct common_firmware_header *)info->fw->data;
786 adev->firmware.fw_size +=
787 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
788
789 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
790 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
791 info->fw = adev->gfx.rlc_fw;
792 header = (const struct common_firmware_header *)info->fw->data;
793 adev->firmware.fw_size +=
794 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
795
796 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
797 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
798 info->fw = adev->gfx.mec_fw;
799 header = (const struct common_firmware_header *)info->fw->data;
800 adev->firmware.fw_size +=
801 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
802
803 if (adev->gfx.mec2_fw) {
804 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
805 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
806 info->fw = adev->gfx.mec2_fw;
807 header = (const struct common_firmware_header *)info->fw->data;
808 adev->firmware.fw_size +=
809 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
810 }
811
812 }
813
814out:
815 if (err) {
816 dev_err(adev->dev,
817 "gfx8: Failed to load firmware \"%s\"\n",
818 fw_name);
819 release_firmware(adev->gfx.pfp_fw);
820 adev->gfx.pfp_fw = NULL;
821 release_firmware(adev->gfx.me_fw);
822 adev->gfx.me_fw = NULL;
823 release_firmware(adev->gfx.ce_fw);
824 adev->gfx.ce_fw = NULL;
825 release_firmware(adev->gfx.rlc_fw);
826 adev->gfx.rlc_fw = NULL;
827 release_firmware(adev->gfx.mec_fw);
828 adev->gfx.mec_fw = NULL;
829 release_firmware(adev->gfx.mec2_fw);
830 adev->gfx.mec2_fw = NULL;
831 }
832 return err;
833}
834
835static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
836{
837 int r;
838
839 if (adev->gfx.mec.hpd_eop_obj) {
840 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
841 if (unlikely(r != 0))
842 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
843 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
844 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
845
846 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
847 adev->gfx.mec.hpd_eop_obj = NULL;
848 }
849}
850
851#define MEC_HPD_SIZE 2048
852
853static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
854{
855 int r;
856 u32 *hpd;
857
858 /*
859 * we assign only 1 pipe because all other pipes will
860 * be handled by KFD
861 */
862 adev->gfx.mec.num_mec = 1;
863 adev->gfx.mec.num_pipe = 1;
864 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
865
866 if (adev->gfx.mec.hpd_eop_obj == NULL) {
867 r = amdgpu_bo_create(adev,
868 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
869 PAGE_SIZE, true,
870 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
871 &adev->gfx.mec.hpd_eop_obj);
872 if (r) {
873 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
874 return r;
875 }
876 }
877
878 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
879 if (unlikely(r != 0)) {
880 gfx_v8_0_mec_fini(adev);
881 return r;
882 }
883 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
884 &adev->gfx.mec.hpd_eop_gpu_addr);
885 if (r) {
886 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
887 gfx_v8_0_mec_fini(adev);
888 return r;
889 }
890 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
891 if (r) {
892 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
893 gfx_v8_0_mec_fini(adev);
894 return r;
895 }
896
897 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
898
899 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
900 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
901
902 return 0;
903}
904
5fc3aeeb 905static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 906{
907 int i, r;
908 struct amdgpu_ring *ring;
5fc3aeeb 909 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 910
911 /* EOP Event */
912 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
913 if (r)
914 return r;
915
916 /* Privileged reg */
917 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
918 if (r)
919 return r;
920
921 /* Privileged inst */
922 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
923 if (r)
924 return r;
925
926 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
927
928 gfx_v8_0_scratch_init(adev);
929
930 r = gfx_v8_0_init_microcode(adev);
931 if (r) {
932 DRM_ERROR("Failed to load gfx firmware!\n");
933 return r;
934 }
935
936 r = gfx_v8_0_mec_init(adev);
937 if (r) {
938 DRM_ERROR("Failed to init MEC BOs!\n");
939 return r;
940 }
941
942 r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
943 if (r) {
944 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
945 return r;
946 }
947
948 /* set up the gfx ring */
949 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
950 ring = &adev->gfx.gfx_ring[i];
951 ring->ring_obj = NULL;
952 sprintf(ring->name, "gfx");
953 /* no gfx doorbells on iceland */
954 if (adev->asic_type != CHIP_TOPAZ) {
955 ring->use_doorbell = true;
956 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
957 }
958
959 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
960 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
961 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
962 AMDGPU_RING_TYPE_GFX);
963 if (r)
964 return r;
965 }
966
967 /* set up the compute queues */
968 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
969 unsigned irq_type;
970
971 /* max 32 queues per MEC */
972 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
973 DRM_ERROR("Too many (%d) compute rings!\n", i);
974 break;
975 }
976 ring = &adev->gfx.compute_ring[i];
977 ring->ring_obj = NULL;
978 ring->use_doorbell = true;
979 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
980 ring->me = 1; /* first MEC */
981 ring->pipe = i / 8;
982 ring->queue = i % 8;
983 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
984 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
985 /* type-2 packets are deprecated on MEC, use type-3 instead */
986 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
987 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
988 &adev->gfx.eop_irq, irq_type,
989 AMDGPU_RING_TYPE_COMPUTE);
990 if (r)
991 return r;
992 }
993
994 /* reserve GDS, GWS and OA resource for gfx */
995 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
996 PAGE_SIZE, true,
997 AMDGPU_GEM_DOMAIN_GDS, 0,
998 NULL, &adev->gds.gds_gfx_bo);
999 if (r)
1000 return r;
1001
1002 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1003 PAGE_SIZE, true,
1004 AMDGPU_GEM_DOMAIN_GWS, 0,
1005 NULL, &adev->gds.gws_gfx_bo);
1006 if (r)
1007 return r;
1008
1009 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1010 PAGE_SIZE, true,
1011 AMDGPU_GEM_DOMAIN_OA, 0,
1012 NULL, &adev->gds.oa_gfx_bo);
1013 if (r)
1014 return r;
1015
a101a899
KW		 1016 adev->gfx.ce_ram_size = 0x8000;
1017
aaa36a97
AD		 1018 return 0;
1019}
1020
5fc3aeeb 1021static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 1022{
1023 int i;
5fc3aeeb 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1025
1026 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1027 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1028 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1029
1030 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1031 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1032 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1033 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1034
1035 amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
1036
1037 gfx_v8_0_mec_fini(adev);
1038
1039 return 0;
1040}
1041
1042static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1043{
1044 const u32 num_tile_mode_states = 32;
1045 const u32 num_secondary_tile_mode_states = 16;
1046 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1047
1048 switch (adev->gfx.config.mem_row_size_in_kb) {
1049 case 1:
1050 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1051 break;
1052 case 2:
1053 default:
1054 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1055 break;
1056 case 4:
1057 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1058 break;
1059 }
1060
1061 switch (adev->asic_type) {
1062 case CHIP_TOPAZ:
1063 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1064 switch (reg_offset) {
1065 case 0:
1066 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067 PIPE_CONFIG(ADDR_SURF_P2) |
1068 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1070 break;
1071 case 1:
1072 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1073 PIPE_CONFIG(ADDR_SURF_P2) |
1074 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076 break;
1077 case 2:
1078 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1079 PIPE_CONFIG(ADDR_SURF_P2) |
1080 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1082 break;
1083 case 3:
1084 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P2) |
1086 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1087 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1088 break;
1089 case 4:
1090 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P2) |
1092 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1093 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1094 break;
1095 case 5:
1096 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P2) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1099 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1100 break;
1101 case 6:
1102 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P2) |
1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1105 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1106 break;
1107 case 8:
1108 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1109 PIPE_CONFIG(ADDR_SURF_P2));
1110 break;
1111 case 9:
1112 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1113 PIPE_CONFIG(ADDR_SURF_P2) |
1114 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1115 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1116 break;
1117 case 10:
1118 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1119 PIPE_CONFIG(ADDR_SURF_P2) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1122 break;
1123 case 11:
1124 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1125 PIPE_CONFIG(ADDR_SURF_P2) |
1126 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1127 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1128 break;
1129 case 13:
1130 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P2) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1134 break;
1135 case 14:
1136 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1137 PIPE_CONFIG(ADDR_SURF_P2) |
1138 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1139 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1140 break;
1141 case 15:
1142 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1143 PIPE_CONFIG(ADDR_SURF_P2) |
1144 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1145 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1146 break;
1147 case 16:
1148 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1149 PIPE_CONFIG(ADDR_SURF_P2) |
1150 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1152 break;
1153 case 18:
1154 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1155 PIPE_CONFIG(ADDR_SURF_P2) |
1156 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1157 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1158 break;
1159 case 19:
1160 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1161 PIPE_CONFIG(ADDR_SURF_P2) |
1162 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1163 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1164 break;
1165 case 20:
1166 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1167 PIPE_CONFIG(ADDR_SURF_P2) |
1168 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1169 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1170 break;
1171 case 21:
1172 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1173 PIPE_CONFIG(ADDR_SURF_P2) |
1174 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1175 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1176 break;
1177 case 22:
1178 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1179 PIPE_CONFIG(ADDR_SURF_P2) |
1180 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1181 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1182 break;
1183 case 24:
1184 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1185 PIPE_CONFIG(ADDR_SURF_P2) |
1186 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1187 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1188 break;
1189 case 25:
1190 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1191 PIPE_CONFIG(ADDR_SURF_P2) |
1192 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1193 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1194 break;
1195 case 26:
1196 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1197 PIPE_CONFIG(ADDR_SURF_P2) |
1198 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1199 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1200 break;
1201 case 27:
1202 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1203 PIPE_CONFIG(ADDR_SURF_P2) |
1204 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1205 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1206 break;
1207 case 28:
1208 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P2) |
1210 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1211 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1212 break;
1213 case 29:
1214 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1215 PIPE_CONFIG(ADDR_SURF_P2) |
1216 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1217 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1218 break;
1219 case 7:
1220 case 12:
1221 case 17:
1222 case 23:
1223 /* unused idx */
1224 continue;
1225 default:
1226 gb_tile_moden = 0;
1227 break;
1228 };
1229 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1230 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1231 }
1232 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1233 switch (reg_offset) {
1234 case 0:
1235 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1238 NUM_BANKS(ADDR_SURF_8_BANK));
1239 break;
1240 case 1:
1241 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1244 NUM_BANKS(ADDR_SURF_8_BANK));
1245 break;
1246 case 2:
1247 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1250 NUM_BANKS(ADDR_SURF_8_BANK));
1251 break;
1252 case 3:
1253 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1256 NUM_BANKS(ADDR_SURF_8_BANK));
1257 break;
1258 case 4:
1259 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1262 NUM_BANKS(ADDR_SURF_8_BANK));
1263 break;
1264 case 5:
1265 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1266 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1267 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1268 NUM_BANKS(ADDR_SURF_8_BANK));
1269 break;
1270 case 6:
1271 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1272 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1273 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1274 NUM_BANKS(ADDR_SURF_8_BANK));
1275 break;
1276 case 8:
1277 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1280 NUM_BANKS(ADDR_SURF_16_BANK));
1281 break;
1282 case 9:
1283 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1284 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1285 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1286 NUM_BANKS(ADDR_SURF_16_BANK));
1287 break;
1288 case 10:
1289 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1292 NUM_BANKS(ADDR_SURF_16_BANK));
1293 break;
1294 case 11:
1295 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1296 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1297 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1298 NUM_BANKS(ADDR_SURF_16_BANK));
1299 break;
1300 case 12:
1301 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1302 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1303 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1304 NUM_BANKS(ADDR_SURF_16_BANK));
1305 break;
1306 case 13:
1307 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1310 NUM_BANKS(ADDR_SURF_16_BANK));
1311 break;
1312 case 14:
1313 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1314 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1315 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1316 NUM_BANKS(ADDR_SURF_8_BANK));
1317 break;
1318 case 7:
1319 /* unused idx */
1320 continue;
1321 default:
1322 gb_tile_moden = 0;
1323 break;
1324 };
1325 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1326 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1327 }
af15a2d5 1328 case CHIP_FIJI:
aaa36a97
AD		 1329 case CHIP_TONGA:
1330 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1331 switch (reg_offset) {
1332 case 0:
1333 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1335 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1337 break;
1338 case 1:
1339 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1340 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1341 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1342 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1343 break;
1344 case 2:
1345 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1347 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1348 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1349 break;
1350 case 3:
1351 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1352 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1353 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1354 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1355 break;
1356 case 4:
1357 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1358 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1359 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1360 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1361 break;
1362 case 5:
1363 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1364 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1365 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1366 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1367 break;
1368 case 6:
1369 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1370 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1371 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1372 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1373 break;
1374 case 7:
1375 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1376 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1378 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1379 break;
1380 case 8:
1381 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1382 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1383 break;
1384 case 9:
1385 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1386 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1387 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1388 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1389 break;
1390 case 10:
1391 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1392 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1394 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1395 break;
1396 case 11:
1397 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1398 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1399 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1400 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1401 break;
1402 case 12:
1403 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1404 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1405 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1406 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1407 break;
1408 case 13:
1409 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1410 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1411 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1412 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1413 break;
1414 case 14:
1415 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1416 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1418 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1419 break;
1420 case 15:
1421 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1422 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1423 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1424 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1425 break;
1426 case 16:
1427 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1431 break;
1432 case 17:
1433 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1434 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1435 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1436 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1437 break;
1438 case 18:
1439 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1440 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1443 break;
1444 case 19:
1445 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1446 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1447 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1448 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1449 break;
1450 case 20:
1451 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1452 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1455 break;
1456 case 21:
1457 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1458 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1459 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1461 break;
1462 case 22:
1463 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1464 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 break;
1468 case 23:
1469 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1470 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1471 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1473 break;
1474 case 24:
1475 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1476 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479 break;
1480 case 25:
1481 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1482 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1483 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1484 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1485 break;
1486 case 26:
1487 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1488 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1491 break;
1492 case 27:
1493 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1494 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1495 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1496 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1497 break;
1498 case 28:
1499 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503 break;
1504 case 29:
1505 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1506 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1507 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1508 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1509 break;
1510 case 30:
1511 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1512 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1513 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1514 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1515 break;
1516 default:
1517 gb_tile_moden = 0;
1518 break;
1519 };
1520 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1521 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1522 }
1523 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1524 switch (reg_offset) {
1525 case 0:
1526 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1529 NUM_BANKS(ADDR_SURF_16_BANK));
1530 break;
1531 case 1:
1532 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1535 NUM_BANKS(ADDR_SURF_16_BANK));
1536 break;
1537 case 2:
1538 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1541 NUM_BANKS(ADDR_SURF_16_BANK));
1542 break;
1543 case 3:
1544 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1547 NUM_BANKS(ADDR_SURF_16_BANK));
1548 break;
1549 case 4:
1550 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1553 NUM_BANKS(ADDR_SURF_16_BANK));
1554 break;
1555 case 5:
1556 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1559 NUM_BANKS(ADDR_SURF_16_BANK));
1560 break;
1561 case 6:
1562 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1565 NUM_BANKS(ADDR_SURF_16_BANK));
1566 break;
1567 case 8:
1568 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1569 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1571 NUM_BANKS(ADDR_SURF_16_BANK));
1572 break;
1573 case 9:
1574 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1575 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1576 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1577 NUM_BANKS(ADDR_SURF_16_BANK));
1578 break;
1579 case 10:
1580 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1582 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1583 NUM_BANKS(ADDR_SURF_16_BANK));
1584 break;
1585 case 11:
1586 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1589 NUM_BANKS(ADDR_SURF_16_BANK));
1590 break;
1591 case 12:
1592 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1595 NUM_BANKS(ADDR_SURF_8_BANK));
1596 break;
1597 case 13:
1598 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1599 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1600 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1601 NUM_BANKS(ADDR_SURF_4_BANK));
1602 break;
1603 case 14:
1604 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1605 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1607 NUM_BANKS(ADDR_SURF_4_BANK));
1608 break;
1609 case 7:
1610 /* unused idx */
1611 continue;
1612 default:
1613 gb_tile_moden = 0;
1614 break;
1615 };
1616 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1617 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1618 }
1619 break;
1620 case CHIP_CARRIZO:
1621 default:
1622 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1623 switch (reg_offset) {
1624 case 0:
1625 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1626 PIPE_CONFIG(ADDR_SURF_P2) |
1627 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1628 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1629 break;
1630 case 1:
1631 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1632 PIPE_CONFIG(ADDR_SURF_P2) |
1633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1634 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1635 break;
1636 case 2:
1637 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1638 PIPE_CONFIG(ADDR_SURF_P2) |
1639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1640 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1641 break;
1642 case 3:
1643 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1644 PIPE_CONFIG(ADDR_SURF_P2) |
1645 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1646 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1647 break;
1648 case 4:
1649 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1650 PIPE_CONFIG(ADDR_SURF_P2) |
1651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1652 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1653 break;
1654 case 5:
1655 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1656 PIPE_CONFIG(ADDR_SURF_P2) |
1657 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1658 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1659 break;
1660 case 6:
1661 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1662 PIPE_CONFIG(ADDR_SURF_P2) |
1663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1664 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1665 break;
1666 case 8:
1667 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1668 PIPE_CONFIG(ADDR_SURF_P2));
1669 break;
1670 case 9:
1671 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1672 PIPE_CONFIG(ADDR_SURF_P2) |
1673 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1674 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1675 break;
1676 case 10:
1677 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1678 PIPE_CONFIG(ADDR_SURF_P2) |
1679 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1680 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1681 break;
1682 case 11:
1683 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1684 PIPE_CONFIG(ADDR_SURF_P2) |
1685 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1686 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1687 break;
1688 case 13:
1689 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1690 PIPE_CONFIG(ADDR_SURF_P2) |
1691 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1692 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1693 break;
1694 case 14:
1695 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1696 PIPE_CONFIG(ADDR_SURF_P2) |
1697 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1698 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1699 break;
1700 case 15:
1701 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1702 PIPE_CONFIG(ADDR_SURF_P2) |
1703 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1704 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1705 break;
1706 case 16:
1707 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1708 PIPE_CONFIG(ADDR_SURF_P2) |
1709 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1710 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1711 break;
1712 case 18:
1713 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1714 PIPE_CONFIG(ADDR_SURF_P2) |
1715 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1716 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1717 break;
1718 case 19:
1719 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1720 PIPE_CONFIG(ADDR_SURF_P2) |
1721 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1722 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1723 break;
1724 case 20:
1725 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1726 PIPE_CONFIG(ADDR_SURF_P2) |
1727 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1728 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1729 break;
1730 case 21:
1731 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1732 PIPE_CONFIG(ADDR_SURF_P2) |
1733 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1734 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1735 break;
1736 case 22:
1737 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1738 PIPE_CONFIG(ADDR_SURF_P2) |
1739 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1740 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1741 break;
1742 case 24:
1743 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1744 PIPE_CONFIG(ADDR_SURF_P2) |
1745 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1746 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1747 break;
1748 case 25:
1749 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1750 PIPE_CONFIG(ADDR_SURF_P2) |
1751 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1752 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1753 break;
1754 case 26:
1755 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1756 PIPE_CONFIG(ADDR_SURF_P2) |
1757 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1758 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1759 break;
1760 case 27:
1761 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1762 PIPE_CONFIG(ADDR_SURF_P2) |
1763 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1764 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1765 break;
1766 case 28:
1767 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1768 PIPE_CONFIG(ADDR_SURF_P2) |
1769 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1770 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1771 break;
1772 case 29:
1773 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1774 PIPE_CONFIG(ADDR_SURF_P2) |
1775 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1776 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1777 break;
1778 case 7:
1779 case 12:
1780 case 17:
1781 case 23:
1782 /* unused idx */
1783 continue;
1784 default:
1785 gb_tile_moden = 0;
1786 break;
1787 };
1788 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1789 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1790 }
1791 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1792 switch (reg_offset) {
1793 case 0:
1794 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1795 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1796 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1797 NUM_BANKS(ADDR_SURF_8_BANK));
1798 break;
1799 case 1:
1800 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1801 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1802 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1803 NUM_BANKS(ADDR_SURF_8_BANK));
1804 break;
1805 case 2:
1806 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1809 NUM_BANKS(ADDR_SURF_8_BANK));
1810 break;
1811 case 3:
1812 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1815 NUM_BANKS(ADDR_SURF_8_BANK));
1816 break;
1817 case 4:
1818 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1821 NUM_BANKS(ADDR_SURF_8_BANK));
1822 break;
1823 case 5:
1824 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1825 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1826 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1827 NUM_BANKS(ADDR_SURF_8_BANK));
1828 break;
1829 case 6:
1830 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1831 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1832 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1833 NUM_BANKS(ADDR_SURF_8_BANK));
1834 break;
1835 case 8:
1836 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1837 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1838 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1839 NUM_BANKS(ADDR_SURF_16_BANK));
1840 break;
1841 case 9:
1842 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1843 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1844 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1845 NUM_BANKS(ADDR_SURF_16_BANK));
1846 break;
1847 case 10:
1848 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1851 NUM_BANKS(ADDR_SURF_16_BANK));
1852 break;
1853 case 11:
1854 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1857 NUM_BANKS(ADDR_SURF_16_BANK));
1858 break;
1859 case 12:
1860 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1861 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1862 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1863 NUM_BANKS(ADDR_SURF_16_BANK));
1864 break;
1865 case 13:
1866 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1867 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1868 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1869 NUM_BANKS(ADDR_SURF_16_BANK));
1870 break;
1871 case 14:
1872 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1873 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1874 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1875 NUM_BANKS(ADDR_SURF_8_BANK));
1876 break;
1877 case 7:
1878 /* unused idx */
1879 continue;
1880 default:
1881 gb_tile_moden = 0;
1882 break;
1883 };
1884 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1885 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1886 }
1887 }
1888}
1889
1890static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1891{
1892 u32 i, mask = 0;
1893
1894 for (i = 0; i < bit_width; i++) {
1895 mask <<= 1;
1896 mask |= 1;
1897 }
1898 return mask;
1899}
1900
1901void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1902{
1903 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1904
1905 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1906 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1907 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1908 } else if (se_num == 0xffffffff) {
1909 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1910 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1911 } else if (sh_num == 0xffffffff) {
1912 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1913 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1914 } else {
1915 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1916 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1917 }
1918 WREG32(mmGRBM_GFX_INDEX, data);
1919}
1920
1921static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1922 u32 max_rb_num_per_se,
1923 u32 sh_per_se)
1924{
1925 u32 data, mask;
1926
1927 data = RREG32(mmCC_RB_BACKEND_DISABLE);
4f2d3ad6 1928 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
aaa36a97
AD		 1929
1930 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1931
1932 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1933
1934 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1935
1936 return data & mask;
1937}
1938
1939static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1940 u32 se_num, u32 sh_per_se,
1941 u32 max_rb_num_per_se)
1942{
1943 int i, j;
1944 u32 data, mask;
1945 u32 disabled_rbs = 0;
1946 u32 enabled_rbs = 0;
1947
1948 mutex_lock(&adev->grbm_idx_mutex);
1949 for (i = 0; i < se_num; i++) {
1950 for (j = 0; j < sh_per_se; j++) {
1951 gfx_v8_0_select_se_sh(adev, i, j);
1952 data = gfx_v8_0_get_rb_disabled(adev,
1953 max_rb_num_per_se, sh_per_se);
1954 disabled_rbs |= data << ((i * sh_per_se + j) *
1955 RB_BITMAP_WIDTH_PER_SH);
1956 }
1957 }
1958 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1959 mutex_unlock(&adev->grbm_idx_mutex);
1960
1961 mask = 1;
1962 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1963 if (!(disabled_rbs & mask))
1964 enabled_rbs |= mask;
1965 mask <<= 1;
1966 }
1967
1968 adev->gfx.config.backend_enable_mask = enabled_rbs;
1969
1970 mutex_lock(&adev->grbm_idx_mutex);
1971 for (i = 0; i < se_num; i++) {
1972 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1973 data = 0;
1974 for (j = 0; j < sh_per_se; j++) {
1975 switch (enabled_rbs & 3) {
1976 case 0:
1977 if (j == 0)
1978 data |= (RASTER_CONFIG_RB_MAP_3 <<
1979 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1980 else
1981 data |= (RASTER_CONFIG_RB_MAP_0 <<
1982 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1983 break;
1984 case 1:
1985 data |= (RASTER_CONFIG_RB_MAP_0 <<
1986 (i * sh_per_se + j) * 2);
1987 break;
1988 case 2:
1989 data |= (RASTER_CONFIG_RB_MAP_3 <<
1990 (i * sh_per_se + j) * 2);
1991 break;
1992 case 3:
1993 default:
1994 data |= (RASTER_CONFIG_RB_MAP_2 <<
1995 (i * sh_per_se + j) * 2);
1996 break;
1997 }
1998 enabled_rbs >>= 2;
1999 }
2000 WREG32(mmPA_SC_RASTER_CONFIG, data);
2001 }
2002 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2003 mutex_unlock(&adev->grbm_idx_mutex);
2004}
2005
cd06bf68
BG		 2006/**
2007 * gmc_v8_0_init_compute_vmid - gart enable
2008 *
2009 * @rdev: amdgpu_device pointer
2010 *
2011 * Initialize compute vmid sh_mem registers
2012 *
2013 */
2014#define DEFAULT_SH_MEM_BASES (0x6000)
2015#define FIRST_COMPUTE_VMID (8)
2016#define LAST_COMPUTE_VMID (16)
2017static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2018{
2019 int i;
2020 uint32_t sh_mem_config;
2021 uint32_t sh_mem_bases;
2022
2023 /*
2024 * Configure apertures:
2025 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2026 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2027 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2028 */
2029 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2030
2031 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2032 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2033 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2034 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2035 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2036 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2037
2038 mutex_lock(&adev->srbm_mutex);
2039 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2040 vi_srbm_select(adev, 0, 0, 0, i);
2041 /* CP and shaders */
2042 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2043 WREG32(mmSH_MEM_APE1_BASE, 1);
2044 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2045 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2046 }
2047 vi_srbm_select(adev, 0, 0, 0, 0);
2048 mutex_unlock(&adev->srbm_mutex);
2049}
2050
aaa36a97
AD		 2051static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2052{
2053 u32 gb_addr_config;
2054 u32 mc_shared_chmap, mc_arb_ramcfg;
2055 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2056 u32 tmp;
2057 int i;
2058
2059 switch (adev->asic_type) {
2060 case CHIP_TOPAZ:
2061 adev->gfx.config.max_shader_engines = 1;
2062 adev->gfx.config.max_tile_pipes = 2;
2063 adev->gfx.config.max_cu_per_sh = 6;
2064 adev->gfx.config.max_sh_per_se = 1;
2065 adev->gfx.config.max_backends_per_se = 2;
2066 adev->gfx.config.max_texture_channel_caches = 2;
2067 adev->gfx.config.max_gprs = 256;
2068 adev->gfx.config.max_gs_threads = 32;
2069 adev->gfx.config.max_hw_contexts = 8;
2070
2071 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2072 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2073 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2074 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2075 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
2076 break;
af15a2d5
DZ		 2077 case CHIP_FIJI:
2078 adev->gfx.config.max_shader_engines = 4;
2079 adev->gfx.config.max_tile_pipes = 16;
2080 adev->gfx.config.max_cu_per_sh = 16;
2081 adev->gfx.config.max_sh_per_se = 1;
2082 adev->gfx.config.max_backends_per_se = 4;
2083 adev->gfx.config.max_texture_channel_caches = 8;
2084 adev->gfx.config.max_gprs = 256;
2085 adev->gfx.config.max_gs_threads = 32;
2086 adev->gfx.config.max_hw_contexts = 8;
2087
2088 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2089 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2090 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2091 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2092 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2093 break;
aaa36a97
AD		 2094 case CHIP_TONGA:
2095 adev->gfx.config.max_shader_engines = 4;
2096 adev->gfx.config.max_tile_pipes = 8;
2097 adev->gfx.config.max_cu_per_sh = 8;
2098 adev->gfx.config.max_sh_per_se = 1;
2099 adev->gfx.config.max_backends_per_se = 2;
2100 adev->gfx.config.max_texture_channel_caches = 8;
2101 adev->gfx.config.max_gprs = 256;
2102 adev->gfx.config.max_gs_threads = 32;
2103 adev->gfx.config.max_hw_contexts = 8;
2104
2105 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2106 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2107 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2108 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2109 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2110 break;
2111 case CHIP_CARRIZO:
2112 adev->gfx.config.max_shader_engines = 1;
2113 adev->gfx.config.max_tile_pipes = 2;
aaa36a97 2114 adev->gfx.config.max_sh_per_se = 1;
a0e2f50b 2115 adev->gfx.config.max_backends_per_se = 2;
bd5c97bc
AD		 2116
2117 switch (adev->pdev->revision) {
2118 case 0xc4:
2119 case 0x84:
2120 case 0xc8:
2121 case 0xcc:
2122 /* B10 */
2123 adev->gfx.config.max_cu_per_sh = 8;
bd5c97bc
AD		 2124 break;
2125 case 0xc5:
2126 case 0x81:
2127 case 0x85:
2128 case 0xc9:
2129 case 0xcd:
2130 /* B8 */
2131 adev->gfx.config.max_cu_per_sh = 6;
bd5c97bc
AD		 2132 break;
2133 case 0xc6:
2134 case 0xca:
2135 case 0xce:
2136 /* B6 */
2137 adev->gfx.config.max_cu_per_sh = 6;
bd5c97bc
AD		 2138 break;
2139 case 0xc7:
2140 case 0x87:
2141 case 0xcb:
2142 default:
2143 /* B4 */
2144 adev->gfx.config.max_cu_per_sh = 4;
bd5c97bc
AD		 2145 break;
2146 }
2147
aaa36a97
AD		 2148 adev->gfx.config.max_texture_channel_caches = 2;
2149 adev->gfx.config.max_gprs = 256;
2150 adev->gfx.config.max_gs_threads = 32;
2151 adev->gfx.config.max_hw_contexts = 8;
2152
2153 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2154 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2155 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2156 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2157 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2158 break;
2159 default:
2160 adev->gfx.config.max_shader_engines = 2;
2161 adev->gfx.config.max_tile_pipes = 4;
2162 adev->gfx.config.max_cu_per_sh = 2;
2163 adev->gfx.config.max_sh_per_se = 1;
2164 adev->gfx.config.max_backends_per_se = 2;
2165 adev->gfx.config.max_texture_channel_caches = 4;
2166 adev->gfx.config.max_gprs = 256;
2167 adev->gfx.config.max_gs_threads = 32;
2168 adev->gfx.config.max_hw_contexts = 8;
2169
2170 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2171 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2172 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2173 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2174 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2175 break;
2176 }
2177
2178 tmp = RREG32(mmGRBM_CNTL);
2179 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2180 WREG32(mmGRBM_CNTL, tmp);
2181
2182 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2183 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2184 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2185
2186 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2187 adev->gfx.config.mem_max_burst_length_bytes = 256;
2f7d10b3 2188 if (adev->flags & AMD_IS_APU) {
aaa36a97
AD		 2189 /* Get memory bank mapping mode. */
2190 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2191 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2192 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2193
2194 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2195 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2196 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2197
2198 /* Validate settings in case only one DIMM installed. */
2199 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2200 dimm00_addr_map = 0;
2201 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2202 dimm01_addr_map = 0;
2203 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2204 dimm10_addr_map = 0;
2205 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2206 dimm11_addr_map = 0;
2207
2208 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2209 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2210 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2211 adev->gfx.config.mem_row_size_in_kb = 2;
2212 else
2213 adev->gfx.config.mem_row_size_in_kb = 1;
2214 } else {
2215 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2216 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2217 if (adev->gfx.config.mem_row_size_in_kb > 4)
2218 adev->gfx.config.mem_row_size_in_kb = 4;
2219 }
2220
2221 adev->gfx.config.shader_engine_tile_size = 32;
2222 adev->gfx.config.num_gpus = 1;
2223 adev->gfx.config.multi_gpu_tile_size = 64;
2224
2225 /* fix up row size */
2226 switch (adev->gfx.config.mem_row_size_in_kb) {
2227 case 1:
2228 default:
2229 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2230 break;
2231 case 2:
2232 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2233 break;
2234 case 4:
2235 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2236 break;
2237 }
2238 adev->gfx.config.gb_addr_config = gb_addr_config;
2239
2240 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2241 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2242 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2243 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2244 gb_addr_config & 0x70);
2245 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2246 gb_addr_config & 0x70);
2247 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2248 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2249 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2250
2251 gfx_v8_0_tiling_mode_table_init(adev);
2252
2253 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2254 adev->gfx.config.max_sh_per_se,
2255 adev->gfx.config.max_backends_per_se);
2256
2257 /* XXX SH_MEM regs */
2258 /* where to put LDS, scratch, GPUVM in FSA64 space */
2259 mutex_lock(&adev->srbm_mutex);
2260 for (i = 0; i < 16; i++) {
2261 vi_srbm_select(adev, 0, 0, 0, i);
2262 /* CP and shaders */
2263 if (i == 0) {
2264 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2265 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
74a5d165
JX		 2266 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2267 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 2268 WREG32(mmSH_MEM_CONFIG, tmp);
2269 } else {
2270 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2271 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
74a5d165
JX		 2272 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2273 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 2274 WREG32(mmSH_MEM_CONFIG, tmp);
2275 }
2276
2277 WREG32(mmSH_MEM_APE1_BASE, 1);
2278 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2279 WREG32(mmSH_MEM_BASES, 0);
2280 }
2281 vi_srbm_select(adev, 0, 0, 0, 0);
2282 mutex_unlock(&adev->srbm_mutex);
2283
cd06bf68
BG		 2284 gmc_v8_0_init_compute_vmid(adev);
2285
aaa36a97
AD		 2286 mutex_lock(&adev->grbm_idx_mutex);
2287 /*
2288 * making sure that the following register writes will be broadcasted
2289 * to all the shaders
2290 */
2291 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2292
2293 WREG32(mmPA_SC_FIFO_SIZE,
2294 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2295 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2296 (adev->gfx.config.sc_prim_fifo_size_backend <<
2297 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2298 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2299 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2300 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2301 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2302 mutex_unlock(&adev->grbm_idx_mutex);
2303
2304}
2305
2306static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2307{
2308 u32 i, j, k;
2309 u32 mask;
2310
2311 mutex_lock(&adev->grbm_idx_mutex);
2312 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2313 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2314 gfx_v8_0_select_se_sh(adev, i, j);
2315 for (k = 0; k < adev->usec_timeout; k++) {
2316 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2317 break;
2318 udelay(1);
2319 }
2320 }
2321 }
2322 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2323 mutex_unlock(&adev->grbm_idx_mutex);
2324
2325 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2326 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2327 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2328 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2329 for (k = 0; k < adev->usec_timeout; k++) {
2330 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2331 break;
2332 udelay(1);
2333 }
2334}
2335
2336static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2337 bool enable)
2338{
2339 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2340
2341 if (enable) {
2342 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2343 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2344 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2345 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2346 } else {
2347 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2348 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2349 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2350 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2351 }
2352 WREG32(mmCP_INT_CNTL_RING0, tmp);
2353}
2354
2355void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2356{
2357 u32 tmp = RREG32(mmRLC_CNTL);
2358
2359 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2360 WREG32(mmRLC_CNTL, tmp);
2361
2362 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2363
2364 gfx_v8_0_wait_for_rlc_serdes(adev);
2365}
2366
2367static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2368{
2369 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2370
2371 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2372 WREG32(mmGRBM_SOFT_RESET, tmp);
2373 udelay(50);
2374 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2375 WREG32(mmGRBM_SOFT_RESET, tmp);
2376 udelay(50);
2377}
2378
2379static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2380{
2381 u32 tmp = RREG32(mmRLC_CNTL);
2382
2383 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2384 WREG32(mmRLC_CNTL, tmp);
2385
2386 /* carrizo do enable cp interrupt after cp inited */
2387 if (adev->asic_type != CHIP_CARRIZO)
2388 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2389
2390 udelay(50);
2391}
2392
2393static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2394{
2395 const struct rlc_firmware_header_v2_0 *hdr;
2396 const __le32 *fw_data;
2397 unsigned i, fw_size;
2398
2399 if (!adev->gfx.rlc_fw)
2400 return -EINVAL;
2401
2402 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2403 amdgpu_ucode_print_rlc_hdr(&hdr->header);
aaa36a97
AD		 2404
2405 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2406 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2407 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2408
2409 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2410 for (i = 0; i < fw_size; i++)
2411 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2412 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2413
2414 return 0;
2415}
2416
2417static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2418{
2419 int r;
2420
2421 gfx_v8_0_rlc_stop(adev);
2422
2423 /* disable CG */
2424 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2425
2426 /* disable PG */
2427 WREG32(mmRLC_PG_CNTL, 0);
2428
2429 gfx_v8_0_rlc_reset(adev);
2430
2431 if (!adev->firmware.smu_load) {
2432 /* legacy rlc firmware loading */
2433 r = gfx_v8_0_rlc_load_microcode(adev);
2434 if (r)
2435 return r;
2436 } else {
2437 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2438 AMDGPU_UCODE_ID_RLC_G);
2439 if (r)
2440 return -EINVAL;
2441 }
2442
2443 gfx_v8_0_rlc_start(adev);
2444
2445 return 0;
2446}
2447
2448static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2449{
2450 int i;
2451 u32 tmp = RREG32(mmCP_ME_CNTL);
2452
2453 if (enable) {
2454 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2455 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2456 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2457 } else {
2458 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2459 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2460 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2461 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2462 adev->gfx.gfx_ring[i].ready = false;
2463 }
2464 WREG32(mmCP_ME_CNTL, tmp);
2465 udelay(50);
2466}
2467
2468static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2469{
2470 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2471 const struct gfx_firmware_header_v1_0 *ce_hdr;
2472 const struct gfx_firmware_header_v1_0 *me_hdr;
2473 const __le32 *fw_data;
2474 unsigned i, fw_size;
2475
2476 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2477 return -EINVAL;
2478
2479 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2480 adev->gfx.pfp_fw->data;
2481 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2482 adev->gfx.ce_fw->data;
2483 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2484 adev->gfx.me_fw->data;
2485
2486 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2487 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2488 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
aaa36a97
AD		 2489
2490 gfx_v8_0_cp_gfx_enable(adev, false);
2491
2492 /* PFP */
2493 fw_data = (const __le32 *)
2494 (adev->gfx.pfp_fw->data +
2495 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2496 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2497 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2498 for (i = 0; i < fw_size; i++)
2499 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2500 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2501
2502 /* CE */
2503 fw_data = (const __le32 *)
2504 (adev->gfx.ce_fw->data +
2505 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2506 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2507 WREG32(mmCP_CE_UCODE_ADDR, 0);
2508 for (i = 0; i < fw_size; i++)
2509 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2510 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2511
2512 /* ME */
2513 fw_data = (const __le32 *)
2514 (adev->gfx.me_fw->data +
2515 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2516 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2517 WREG32(mmCP_ME_RAM_WADDR, 0);
2518 for (i = 0; i < fw_size; i++)
2519 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2520 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2521
2522 return 0;
2523}
2524
2525static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2526{
2527 u32 count = 0;
2528 const struct cs_section_def *sect = NULL;
2529 const struct cs_extent_def *ext = NULL;
2530
2531 /* begin clear state */
2532 count += 2;
2533 /* context control state */
2534 count += 3;
2535
2536 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2537 for (ext = sect->section; ext->extent != NULL; ++ext) {
2538 if (sect->id == SECT_CONTEXT)
2539 count += 2 + ext->reg_count;
2540 else
2541 return 0;
2542 }
2543 }
2544 /* pa_sc_raster_config/pa_sc_raster_config1 */
2545 count += 4;
2546 /* end clear state */
2547 count += 2;
2548 /* clear state */
2549 count += 2;
2550
2551 return count;
2552}
2553
2554static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2555{
2556 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2557 const struct cs_section_def *sect = NULL;
2558 const struct cs_extent_def *ext = NULL;
2559 int r, i;
2560
2561 /* init the CP */
2562 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2563 WREG32(mmCP_ENDIAN_SWAP, 0);
2564 WREG32(mmCP_DEVICE_ID, 1);
2565
2566 gfx_v8_0_cp_gfx_enable(adev, true);
2567
2568 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2569 if (r) {
2570 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2571 return r;
2572 }
2573
2574 /* clear state buffer */
2575 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2576 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2577
2578 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2579 amdgpu_ring_write(ring, 0x80000000);
2580 amdgpu_ring_write(ring, 0x80000000);
2581
2582 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2583 for (ext = sect->section; ext->extent != NULL; ++ext) {
2584 if (sect->id == SECT_CONTEXT) {
2585 amdgpu_ring_write(ring,
2586 PACKET3(PACKET3_SET_CONTEXT_REG,
2587 ext->reg_count));
2588 amdgpu_ring_write(ring,
2589 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2590 for (i = 0; i < ext->reg_count; i++)
2591 amdgpu_ring_write(ring, ext->extent[i]);
2592 }
2593 }
2594 }
2595
2596 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2597 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2598 switch (adev->asic_type) {
2599 case CHIP_TONGA:
af15a2d5 2600 case CHIP_FIJI:
aaa36a97
AD		 2601 amdgpu_ring_write(ring, 0x16000012);
2602 amdgpu_ring_write(ring, 0x0000002A);
2603 break;
2604 case CHIP_TOPAZ:
2605 case CHIP_CARRIZO:
2606 amdgpu_ring_write(ring, 0x00000002);
2607 amdgpu_ring_write(ring, 0x00000000);
2608 break;
2609 default:
2610 BUG();
2611 }
2612
2613 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2614 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2615
2616 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2617 amdgpu_ring_write(ring, 0);
2618
2619 /* init the CE partitions */
2620 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2621 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2622 amdgpu_ring_write(ring, 0x8000);
2623 amdgpu_ring_write(ring, 0x8000);
2624
2625 amdgpu_ring_unlock_commit(ring);
2626
2627 return 0;
2628}
2629
2630static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2631{
2632 struct amdgpu_ring *ring;
2633 u32 tmp;
2634 u32 rb_bufsz;
2635 u64 rb_addr, rptr_addr;
2636 int r;
2637
2638 /* Set the write pointer delay */
2639 WREG32(mmCP_RB_WPTR_DELAY, 0);
2640
2641 /* set the RB to use vmid 0 */
2642 WREG32(mmCP_RB_VMID, 0);
2643
2644 /* Set ring buffer size */
2645 ring = &adev->gfx.gfx_ring[0];
2646 rb_bufsz = order_base_2(ring->ring_size / 8);
2647 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2648 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2649 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2650 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2651#ifdef __BIG_ENDIAN
2652 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2653#endif
2654 WREG32(mmCP_RB0_CNTL, tmp);
2655
2656 /* Initialize the ring buffer's read and write pointers */
2657 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2658 ring->wptr = 0;
2659 WREG32(mmCP_RB0_WPTR, ring->wptr);
2660
2661 /* set the wb address wether it's enabled or not */
2662 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2663 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2664 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2665
2666 mdelay(1);
2667 WREG32(mmCP_RB0_CNTL, tmp);
2668
2669 rb_addr = ring->gpu_addr >> 8;
2670 WREG32(mmCP_RB0_BASE, rb_addr);
2671 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2672
2673 /* no gfx doorbells on iceland */
2674 if (adev->asic_type != CHIP_TOPAZ) {
2675 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2676 if (ring->use_doorbell) {
2677 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2678 DOORBELL_OFFSET, ring->doorbell_index);
2679 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2680 DOORBELL_EN, 1);
2681 } else {
2682 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2683 DOORBELL_EN, 0);
2684 }
2685 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2686
2687 if (adev->asic_type == CHIP_TONGA) {
2688 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2689 DOORBELL_RANGE_LOWER,
2690 AMDGPU_DOORBELL_GFX_RING0);
2691 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2692
2693 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2694 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2695 }
2696
2697 }
2698
2699 /* start the ring */
2700 gfx_v8_0_cp_gfx_start(adev);
2701 ring->ready = true;
2702 r = amdgpu_ring_test_ring(ring);
2703 if (r) {
2704 ring->ready = false;
2705 return r;
2706 }
2707
2708 return 0;
2709}
2710
2711static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2712{
2713 int i;
2714
2715 if (enable) {
2716 WREG32(mmCP_MEC_CNTL, 0);
2717 } else {
2718 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2719 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2720 adev->gfx.compute_ring[i].ready = false;
2721 }
2722 udelay(50);
2723}
2724
2725static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2726{
2727 gfx_v8_0_cp_compute_enable(adev, true);
2728
2729 return 0;
2730}
2731
2732static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2733{
2734 const struct gfx_firmware_header_v1_0 *mec_hdr;
2735 const __le32 *fw_data;
2736 unsigned i, fw_size;
2737
2738 if (!adev->gfx.mec_fw)
2739 return -EINVAL;
2740
2741 gfx_v8_0_cp_compute_enable(adev, false);
2742
2743 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2744 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
aaa36a97
AD		 2745
2746 fw_data = (const __le32 *)
2747 (adev->gfx.mec_fw->data +
2748 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2749 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2750
2751 /* MEC1 */
2752 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2753 for (i = 0; i < fw_size; i++)
2754 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2755 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2756
2757 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2758 if (adev->gfx.mec2_fw) {
2759 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2760
2761 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2762 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
aaa36a97
AD		 2763
2764 fw_data = (const __le32 *)
2765 (adev->gfx.mec2_fw->data +
2766 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2767 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2768
2769 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2770 for (i = 0; i < fw_size; i++)
2771 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2772 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2773 }
2774
2775 return 0;
2776}
2777
2778struct vi_mqd {
2779 uint32_t header; /* ordinal0 */
2780 uint32_t compute_dispatch_initiator; /* ordinal1 */
2781 uint32_t compute_dim_x; /* ordinal2 */
2782 uint32_t compute_dim_y; /* ordinal3 */
2783 uint32_t compute_dim_z; /* ordinal4 */
2784 uint32_t compute_start_x; /* ordinal5 */
2785 uint32_t compute_start_y; /* ordinal6 */
2786 uint32_t compute_start_z; /* ordinal7 */
2787 uint32_t compute_num_thread_x; /* ordinal8 */
2788 uint32_t compute_num_thread_y; /* ordinal9 */
2789 uint32_t compute_num_thread_z; /* ordinal10 */
2790 uint32_t compute_pipelinestat_enable; /* ordinal11 */
2791 uint32_t compute_perfcount_enable; /* ordinal12 */
2792 uint32_t compute_pgm_lo; /* ordinal13 */
2793 uint32_t compute_pgm_hi; /* ordinal14 */
2794 uint32_t compute_tba_lo; /* ordinal15 */
2795 uint32_t compute_tba_hi; /* ordinal16 */
2796 uint32_t compute_tma_lo; /* ordinal17 */
2797 uint32_t compute_tma_hi; /* ordinal18 */
2798 uint32_t compute_pgm_rsrc1; /* ordinal19 */
2799 uint32_t compute_pgm_rsrc2; /* ordinal20 */
2800 uint32_t compute_vmid; /* ordinal21 */
2801 uint32_t compute_resource_limits; /* ordinal22 */
2802 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
2803 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
2804 uint32_t compute_tmpring_size; /* ordinal25 */
2805 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
2806 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
2807 uint32_t compute_restart_x; /* ordinal28 */
2808 uint32_t compute_restart_y; /* ordinal29 */
2809 uint32_t compute_restart_z; /* ordinal30 */
2810 uint32_t compute_thread_trace_enable; /* ordinal31 */
2811 uint32_t compute_misc_reserved; /* ordinal32 */
2812 uint32_t compute_dispatch_id; /* ordinal33 */
2813 uint32_t compute_threadgroup_id; /* ordinal34 */
2814 uint32_t compute_relaunch; /* ordinal35 */
2815 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
2816 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
2817 uint32_t compute_wave_restore_control; /* ordinal38 */
2818 uint32_t reserved9; /* ordinal39 */
2819 uint32_t reserved10; /* ordinal40 */
2820 uint32_t reserved11; /* ordinal41 */
2821 uint32_t reserved12; /* ordinal42 */
2822 uint32_t reserved13; /* ordinal43 */
2823 uint32_t reserved14; /* ordinal44 */
2824 uint32_t reserved15; /* ordinal45 */
2825 uint32_t reserved16; /* ordinal46 */
2826 uint32_t reserved17; /* ordinal47 */
2827 uint32_t reserved18; /* ordinal48 */
2828 uint32_t reserved19; /* ordinal49 */
2829 uint32_t reserved20; /* ordinal50 */
2830 uint32_t reserved21; /* ordinal51 */
2831 uint32_t reserved22; /* ordinal52 */
2832 uint32_t reserved23; /* ordinal53 */
2833 uint32_t reserved24; /* ordinal54 */
2834 uint32_t reserved25; /* ordinal55 */
2835 uint32_t reserved26; /* ordinal56 */
2836 uint32_t reserved27; /* ordinal57 */
2837 uint32_t reserved28; /* ordinal58 */
2838 uint32_t reserved29; /* ordinal59 */
2839 uint32_t reserved30; /* ordinal60 */
2840 uint32_t reserved31; /* ordinal61 */
2841 uint32_t reserved32; /* ordinal62 */
2842 uint32_t reserved33; /* ordinal63 */
2843 uint32_t reserved34; /* ordinal64 */
2844 uint32_t compute_user_data_0; /* ordinal65 */
2845 uint32_t compute_user_data_1; /* ordinal66 */
2846 uint32_t compute_user_data_2; /* ordinal67 */
2847 uint32_t compute_user_data_3; /* ordinal68 */
2848 uint32_t compute_user_data_4; /* ordinal69 */
2849 uint32_t compute_user_data_5; /* ordinal70 */
2850 uint32_t compute_user_data_6; /* ordinal71 */
2851 uint32_t compute_user_data_7; /* ordinal72 */
2852 uint32_t compute_user_data_8; /* ordinal73 */
2853 uint32_t compute_user_data_9; /* ordinal74 */
2854 uint32_t compute_user_data_10; /* ordinal75 */
2855 uint32_t compute_user_data_11; /* ordinal76 */
2856 uint32_t compute_user_data_12; /* ordinal77 */
2857 uint32_t compute_user_data_13; /* ordinal78 */
2858 uint32_t compute_user_data_14; /* ordinal79 */
2859 uint32_t compute_user_data_15; /* ordinal80 */
2860 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
2861 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
2862 uint32_t reserved35; /* ordinal83 */
2863 uint32_t reserved36; /* ordinal84 */
2864 uint32_t reserved37; /* ordinal85 */
2865 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
2866 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
2867 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
2868 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
2869 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
2870 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
2871 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
2872 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
2873 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
2874 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
2875 uint32_t reserved38; /* ordinal96 */
2876 uint32_t reserved39; /* ordinal97 */
2877 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
2878 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
2879 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
2880 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
2881 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
2882 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
2883 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
2884 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
2885 uint32_t reserved40; /* ordinal106 */
2886 uint32_t reserved41; /* ordinal107 */
2887 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
2888 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
2889 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
2890 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
2891 uint32_t reserved42; /* ordinal112 */
2892 uint32_t reserved43; /* ordinal113 */
2893 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
2894 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
2895 uint32_t cp_packet_id_lo; /* ordinal116 */
2896 uint32_t cp_packet_id_hi; /* ordinal117 */
2897 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
2898 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
2899 uint32_t gds_save_base_addr_lo; /* ordinal120 */
2900 uint32_t gds_save_base_addr_hi; /* ordinal121 */
2901 uint32_t gds_save_mask_lo; /* ordinal122 */
2902 uint32_t gds_save_mask_hi; /* ordinal123 */
2903 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
2904 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
2905 uint32_t reserved44; /* ordinal126 */
2906 uint32_t reserved45; /* ordinal127 */
2907 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
2908 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
2909 uint32_t cp_hqd_active; /* ordinal130 */
2910 uint32_t cp_hqd_vmid; /* ordinal131 */
2911 uint32_t cp_hqd_persistent_state; /* ordinal132 */
2912 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
2913 uint32_t cp_hqd_queue_priority; /* ordinal134 */
2914 uint32_t cp_hqd_quantum; /* ordinal135 */
2915 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
2916 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
2917 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
2918 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
2919 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
2920 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
2921 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
2922 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
2923 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
2924 uint32_t cp_hqd_pq_control; /* ordinal145 */
2925 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
2926 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
2927 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
2928 uint32_t cp_hqd_ib_control; /* ordinal149 */
2929 uint32_t cp_hqd_iq_timer; /* ordinal150 */
2930 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
2931 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
2932 uint32_t cp_hqd_dma_offload; /* ordinal153 */
2933 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
2934 uint32_t cp_hqd_msg_type; /* ordinal155 */
2935 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
2936 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
2937 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
2938 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
2939 uint32_t cp_hqd_hq_status0; /* ordinal160 */
2940 uint32_t cp_hqd_hq_control0; /* ordinal161 */
2941 uint32_t cp_mqd_control; /* ordinal162 */
2942 uint32_t cp_hqd_hq_status1; /* ordinal163 */
2943 uint32_t cp_hqd_hq_control1; /* ordinal164 */
2944 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
2945 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
2946 uint32_t cp_hqd_eop_control; /* ordinal167 */
2947 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
2948 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
2949 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
2950 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
2951 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
2952 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
2953 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
2954 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
2955 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
2956 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
2957 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
2958 uint32_t cp_hqd_error; /* ordinal179 */
2959 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
2960 uint32_t cp_hqd_eop_dones; /* ordinal181 */
2961 uint32_t reserved46; /* ordinal182 */
2962 uint32_t reserved47; /* ordinal183 */
2963 uint32_t reserved48; /* ordinal184 */
2964 uint32_t reserved49; /* ordinal185 */
2965 uint32_t reserved50; /* ordinal186 */
2966 uint32_t reserved51; /* ordinal187 */
2967 uint32_t reserved52; /* ordinal188 */
2968 uint32_t reserved53; /* ordinal189 */
2969 uint32_t reserved54; /* ordinal190 */
2970 uint32_t reserved55; /* ordinal191 */
2971 uint32_t iqtimer_pkt_header; /* ordinal192 */
2972 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
2973 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
2974 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
2975 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
2976 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
2977 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
2978 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
2979 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
2980 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
2981 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
2982 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
2983 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
2984 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
2985 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
2986 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
2987 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
2988 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
2989 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
2990 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
2991 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
2992 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
2993 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
2994 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
2995 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
2996 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
2997 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
2998 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
2999 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
3000 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
3001 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
3002 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
3003 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
3004 uint32_t reserved56; /* ordinal225 */
3005 uint32_t reserved57; /* ordinal226 */
3006 uint32_t reserved58; /* ordinal227 */
3007 uint32_t set_resources_header; /* ordinal228 */
3008 uint32_t set_resources_dw1; /* ordinal229 */
3009 uint32_t set_resources_dw2; /* ordinal230 */
3010 uint32_t set_resources_dw3; /* ordinal231 */
3011 uint32_t set_resources_dw4; /* ordinal232 */
3012 uint32_t set_resources_dw5; /* ordinal233 */
3013 uint32_t set_resources_dw6; /* ordinal234 */
3014 uint32_t set_resources_dw7; /* ordinal235 */
3015 uint32_t reserved59; /* ordinal236 */
3016 uint32_t reserved60; /* ordinal237 */
3017 uint32_t reserved61; /* ordinal238 */
3018 uint32_t reserved62; /* ordinal239 */
3019 uint32_t reserved63; /* ordinal240 */
3020 uint32_t reserved64; /* ordinal241 */
3021 uint32_t reserved65; /* ordinal242 */
3022 uint32_t reserved66; /* ordinal243 */
3023 uint32_t reserved67; /* ordinal244 */
3024 uint32_t reserved68; /* ordinal245 */
3025 uint32_t reserved69; /* ordinal246 */
3026 uint32_t reserved70; /* ordinal247 */
3027 uint32_t reserved71; /* ordinal248 */
3028 uint32_t reserved72; /* ordinal249 */
3029 uint32_t reserved73; /* ordinal250 */
3030 uint32_t reserved74; /* ordinal251 */
3031 uint32_t reserved75; /* ordinal252 */
3032 uint32_t reserved76; /* ordinal253 */
3033 uint32_t reserved77; /* ordinal254 */
3034 uint32_t reserved78; /* ordinal255 */
3035
3036 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3037};
3038
3039static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3040{
3041 int i, r;
3042
3043 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3044 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3045
3046 if (ring->mqd_obj) {
3047 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3048 if (unlikely(r != 0))
3049 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3050
3051 amdgpu_bo_unpin(ring->mqd_obj);
3052 amdgpu_bo_unreserve(ring->mqd_obj);
3053
3054 amdgpu_bo_unref(&ring->mqd_obj);
3055 ring->mqd_obj = NULL;
3056 }
3057 }
3058}
3059
3060static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3061{
3062 int r, i, j;
3063 u32 tmp;
3064 bool use_doorbell = true;
3065 u64 hqd_gpu_addr;
3066 u64 mqd_gpu_addr;
3067 u64 eop_gpu_addr;
3068 u64 wb_gpu_addr;
3069 u32 *buf;
3070 struct vi_mqd *mqd;
3071
3072 /* init the pipes */
3073 mutex_lock(&adev->srbm_mutex);
3074 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3075 int me = (i < 4) ? 1 : 2;
3076 int pipe = (i < 4) ? i : (i - 4);
3077
3078 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3079 eop_gpu_addr >>= 8;
3080
3081 vi_srbm_select(adev, me, pipe, 0, 0);
3082
3083 /* write the EOP addr */
3084 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3085 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3086
3087 /* set the VMID assigned */
3088 WREG32(mmCP_HQD_VMID, 0);
3089
3090 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3091 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3092 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3093 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3094 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3095 }
3096 vi_srbm_select(adev, 0, 0, 0, 0);
3097 mutex_unlock(&adev->srbm_mutex);
3098
3099 /* init the queues. Just two for now. */
3100 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3101 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3102
3103 if (ring->mqd_obj == NULL) {
3104 r = amdgpu_bo_create(adev,
3105 sizeof(struct vi_mqd),
3106 PAGE_SIZE, true,
3107 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3108 &ring->mqd_obj);
3109 if (r) {
3110 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3111 return r;
3112 }
3113 }
3114
3115 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3116 if (unlikely(r != 0)) {
3117 gfx_v8_0_cp_compute_fini(adev);
3118 return r;
3119 }
3120 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3121 &mqd_gpu_addr);
3122 if (r) {
3123 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3124 gfx_v8_0_cp_compute_fini(adev);
3125 return r;
3126 }
3127 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3128 if (r) {
3129 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3130 gfx_v8_0_cp_compute_fini(adev);
3131 return r;
3132 }
3133
3134 /* init the mqd struct */
3135 memset(buf, 0, sizeof(struct vi_mqd));
3136
3137 mqd = (struct vi_mqd *)buf;
3138 mqd->header = 0xC0310800;
3139 mqd->compute_pipelinestat_enable = 0x00000001;
3140 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3141 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3142 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3143 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3144 mqd->compute_misc_reserved = 0x00000003;
3145
3146 mutex_lock(&adev->srbm_mutex);
3147 vi_srbm_select(adev, ring->me,
3148 ring->pipe,
3149 ring->queue, 0);
3150
3151 /* disable wptr polling */
3152 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3153 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3154 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3155
3156 mqd->cp_hqd_eop_base_addr_lo =
3157 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3158 mqd->cp_hqd_eop_base_addr_hi =
3159 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3160
3161 /* enable doorbell? */
3162 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3163 if (use_doorbell) {
3164 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3165 } else {
3166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3167 }
3168 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3169 mqd->cp_hqd_pq_doorbell_control = tmp;
3170
3171 /* disable the queue if it's active */
3172 mqd->cp_hqd_dequeue_request = 0;
3173 mqd->cp_hqd_pq_rptr = 0;
3174 mqd->cp_hqd_pq_wptr= 0;
3175 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3176 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3177 for (j = 0; j < adev->usec_timeout; j++) {
3178 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3179 break;
3180 udelay(1);
3181 }
3182 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3183 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3184 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3185 }
3186
3187 /* set the pointer to the MQD */
3188 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3189 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3190 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3191 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3192
3193 /* set MQD vmid to 0 */
3194 tmp = RREG32(mmCP_MQD_CONTROL);
3195 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3196 WREG32(mmCP_MQD_CONTROL, tmp);
3197 mqd->cp_mqd_control = tmp;
3198
3199 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3200 hqd_gpu_addr = ring->gpu_addr >> 8;
3201 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3202 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3203 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3204 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3205
3206 /* set up the HQD, this is similar to CP_RB0_CNTL */
3207 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3209 (order_base_2(ring->ring_size / 4) - 1));
3210 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3211 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3212#ifdef __BIG_ENDIAN
3213 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3214#endif
3215 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3216 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3217 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3218 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3219 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3220 mqd->cp_hqd_pq_control = tmp;
3221
3222 /* set the wb address wether it's enabled or not */
3223 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3224 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3225 mqd->cp_hqd_pq_rptr_report_addr_hi =
3226 upper_32_bits(wb_gpu_addr) & 0xffff;
3227 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3228 mqd->cp_hqd_pq_rptr_report_addr_lo);
3229 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3230 mqd->cp_hqd_pq_rptr_report_addr_hi);
3231
3232 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3233 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3234 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3235 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3236 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3237 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3238 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3239
3240 /* enable the doorbell if requested */
3241 if (use_doorbell) {
3242 if (adev->asic_type == CHIP_CARRIZO) {
3243 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3244 AMDGPU_DOORBELL_KIQ << 2);
3245 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
b8826b0c 3246 AMDGPU_DOORBELL_MEC_RING7 << 2);
aaa36a97
AD		 3247 }
3248 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3250 DOORBELL_OFFSET, ring->doorbell_index);
3251 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3252 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3254 mqd->cp_hqd_pq_doorbell_control = tmp;
3255
3256 } else {
3257 mqd->cp_hqd_pq_doorbell_control = 0;
3258 }
3259 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3260 mqd->cp_hqd_pq_doorbell_control);
3261
845253e7
SJ		 3262 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3263 ring->wptr = 0;
3264 mqd->cp_hqd_pq_wptr = ring->wptr;
3265 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3266 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3267
aaa36a97
AD		 3268 /* set the vmid for the queue */
3269 mqd->cp_hqd_vmid = 0;
3270 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3271
3272 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3273 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3274 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3275 mqd->cp_hqd_persistent_state = tmp;
3276
3277 /* activate the queue */
3278 mqd->cp_hqd_active = 1;
3279 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3280
3281 vi_srbm_select(adev, 0, 0, 0, 0);
3282 mutex_unlock(&adev->srbm_mutex);
3283
3284 amdgpu_bo_kunmap(ring->mqd_obj);
3285 amdgpu_bo_unreserve(ring->mqd_obj);
3286 }
3287
3288 if (use_doorbell) {
3289 tmp = RREG32(mmCP_PQ_STATUS);
3290 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3291 WREG32(mmCP_PQ_STATUS, tmp);
3292 }
3293
3294 r = gfx_v8_0_cp_compute_start(adev);
3295 if (r)
3296 return r;
3297
3298 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3299 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3300
3301 ring->ready = true;
3302 r = amdgpu_ring_test_ring(ring);
3303 if (r)
3304 ring->ready = false;
3305 }
3306
3307 return 0;
3308}
3309
3310static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3311{
3312 int r;
3313
3314 if (adev->asic_type != CHIP_CARRIZO)
3315 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3316
3317 if (!adev->firmware.smu_load) {
3318 /* legacy firmware loading */
3319 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3320 if (r)
3321 return r;
3322
3323 r = gfx_v8_0_cp_compute_load_microcode(adev);
3324 if (r)
3325 return r;
3326 } else {
3327 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3328 AMDGPU_UCODE_ID_CP_CE);
3329 if (r)
3330 return -EINVAL;
3331
3332 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3333 AMDGPU_UCODE_ID_CP_PFP);
3334 if (r)
3335 return -EINVAL;
3336
3337 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3338 AMDGPU_UCODE_ID_CP_ME);
3339 if (r)
3340 return -EINVAL;
3341
3342 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3343 AMDGPU_UCODE_ID_CP_MEC1);
3344 if (r)
3345 return -EINVAL;
3346 }
3347
3348 r = gfx_v8_0_cp_gfx_resume(adev);
3349 if (r)
3350 return r;
3351
3352 r = gfx_v8_0_cp_compute_resume(adev);
3353 if (r)
3354 return r;
3355
3356 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3357
3358 return 0;
3359}
3360
3361static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3362{
3363 gfx_v8_0_cp_gfx_enable(adev, enable);
3364 gfx_v8_0_cp_compute_enable(adev, enable);
3365}
3366
5fc3aeeb 3367static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 3368{
3369 int r;
5fc3aeeb 3370 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3371
3372 gfx_v8_0_init_golden_registers(adev);
3373
3374 gfx_v8_0_gpu_init(adev);
3375
3376 r = gfx_v8_0_rlc_resume(adev);
3377 if (r)
3378 return r;
3379
3380 r = gfx_v8_0_cp_resume(adev);
3381 if (r)
3382 return r;
3383
3384 return r;
3385}
3386
5fc3aeeb 3387static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 3388{
5fc3aeeb 3389 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3390
aaa36a97
AD		 3391 gfx_v8_0_cp_enable(adev, false);
3392 gfx_v8_0_rlc_stop(adev);
3393 gfx_v8_0_cp_compute_fini(adev);
3394
3395 return 0;
3396}
3397
5fc3aeeb 3398static int gfx_v8_0_suspend(void *handle)
aaa36a97 3399{
5fc3aeeb 3400 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3401
aaa36a97
AD		 3402 return gfx_v8_0_hw_fini(adev);
3403}
3404
5fc3aeeb 3405static int gfx_v8_0_resume(void *handle)
aaa36a97 3406{
5fc3aeeb 3407 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3408
aaa36a97
AD		 3409 return gfx_v8_0_hw_init(adev);
3410}
3411
5fc3aeeb 3412static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 3413{
5fc3aeeb 3414 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3415
aaa36a97
AD		 3416 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3417 return false;
3418 else
3419 return true;
3420}
3421
5fc3aeeb 3422static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 3423{
3424 unsigned i;
3425 u32 tmp;
5fc3aeeb 3426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3427
3428 for (i = 0; i < adev->usec_timeout; i++) {
3429 /* read MC_STATUS */
3430 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3431
3432 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3433 return 0;
3434 udelay(1);
3435 }
3436 return -ETIMEDOUT;
3437}
3438
5fc3aeeb 3439static void gfx_v8_0_print_status(void *handle)
aaa36a97
AD		 3440{
3441 int i;
5fc3aeeb 3442 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3443
3444 dev_info(adev->dev, "GFX 8.x registers\n");
3445 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3446 RREG32(mmGRBM_STATUS));
3447 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3448 RREG32(mmGRBM_STATUS2));
3449 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3450 RREG32(mmGRBM_STATUS_SE0));
3451 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3452 RREG32(mmGRBM_STATUS_SE1));
3453 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3454 RREG32(mmGRBM_STATUS_SE2));
3455 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3456 RREG32(mmGRBM_STATUS_SE3));
3457 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3458 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3459 RREG32(mmCP_STALLED_STAT1));
3460 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3461 RREG32(mmCP_STALLED_STAT2));
3462 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3463 RREG32(mmCP_STALLED_STAT3));
3464 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3465 RREG32(mmCP_CPF_BUSY_STAT));
3466 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3467 RREG32(mmCP_CPF_STALLED_STAT1));
3468 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3469 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3470 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3471 RREG32(mmCP_CPC_STALLED_STAT1));
3472 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3473
3474 for (i = 0; i < 32; i++) {
3475 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3476 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3477 }
3478 for (i = 0; i < 16; i++) {
3479 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3480 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3481 }
3482 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3483 dev_info(adev->dev, " se: %d\n", i);
3484 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3485 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3486 RREG32(mmPA_SC_RASTER_CONFIG));
3487 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3488 RREG32(mmPA_SC_RASTER_CONFIG_1));
3489 }
3490 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3491
3492 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3493 RREG32(mmGB_ADDR_CONFIG));
3494 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3495 RREG32(mmHDP_ADDR_CONFIG));
3496 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3497 RREG32(mmDMIF_ADDR_CALC));
3498 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
3499 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3500 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
3501 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3502 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3503 RREG32(mmUVD_UDEC_ADDR_CONFIG));
3504 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3505 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3506 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3507 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3508
3509 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3510 RREG32(mmCP_MEQ_THRESHOLDS));
3511 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3512 RREG32(mmSX_DEBUG_1));
3513 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3514 RREG32(mmTA_CNTL_AUX));
3515 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3516 RREG32(mmSPI_CONFIG_CNTL));
3517 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3518 RREG32(mmSQ_CONFIG));
3519 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3520 RREG32(mmDB_DEBUG));
3521 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3522 RREG32(mmDB_DEBUG2));
3523 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3524 RREG32(mmDB_DEBUG3));
3525 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3526 RREG32(mmCB_HW_CONTROL));
3527 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3528 RREG32(mmSPI_CONFIG_CNTL_1));
3529 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3530 RREG32(mmPA_SC_FIFO_SIZE));
3531 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3532 RREG32(mmVGT_NUM_INSTANCES));
3533 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3534 RREG32(mmCP_PERFMON_CNTL));
3535 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3536 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3537 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3538 RREG32(mmVGT_CACHE_INVALIDATION));
3539 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3540 RREG32(mmVGT_GS_VERTEX_REUSE));
3541 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3542 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3543 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3544 RREG32(mmPA_CL_ENHANCE));
3545 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3546 RREG32(mmPA_SC_ENHANCE));
3547
3548 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3549 RREG32(mmCP_ME_CNTL));
3550 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3551 RREG32(mmCP_MAX_CONTEXT));
3552 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3553 RREG32(mmCP_ENDIAN_SWAP));
3554 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3555 RREG32(mmCP_DEVICE_ID));
3556
3557 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
3558 RREG32(mmCP_SEM_WAIT_TIMER));
3559
3560 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
3561 RREG32(mmCP_RB_WPTR_DELAY));
3562 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
3563 RREG32(mmCP_RB_VMID));
3564 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3565 RREG32(mmCP_RB0_CNTL));
3566 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
3567 RREG32(mmCP_RB0_WPTR));
3568 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
3569 RREG32(mmCP_RB0_RPTR_ADDR));
3570 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3571 RREG32(mmCP_RB0_RPTR_ADDR_HI));
3572 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3573 RREG32(mmCP_RB0_CNTL));
3574 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
3575 RREG32(mmCP_RB0_BASE));
3576 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
3577 RREG32(mmCP_RB0_BASE_HI));
3578 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
3579 RREG32(mmCP_MEC_CNTL));
3580 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
3581 RREG32(mmCP_CPF_DEBUG));
3582
3583 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
3584 RREG32(mmSCRATCH_ADDR));
3585 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
3586 RREG32(mmSCRATCH_UMSK));
3587
3588 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
3589 RREG32(mmCP_INT_CNTL_RING0));
3590 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3591 RREG32(mmRLC_LB_CNTL));
3592 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
3593 RREG32(mmRLC_CNTL));
3594 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
3595 RREG32(mmRLC_CGCG_CGLS_CTRL));
3596 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
3597 RREG32(mmRLC_LB_CNTR_INIT));
3598 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
3599 RREG32(mmRLC_LB_CNTR_MAX));
3600 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
3601 RREG32(mmRLC_LB_INIT_CU_MASK));
3602 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
3603 RREG32(mmRLC_LB_PARAMS));
3604 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3605 RREG32(mmRLC_LB_CNTL));
3606 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
3607 RREG32(mmRLC_MC_CNTL));
3608 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
3609 RREG32(mmRLC_UCODE_CNTL));
3610
3611 mutex_lock(&adev->srbm_mutex);
3612 for (i = 0; i < 16; i++) {
3613 vi_srbm_select(adev, 0, 0, 0, i);
3614 dev_info(adev->dev, " VM %d:\n", i);
3615 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
3616 RREG32(mmSH_MEM_CONFIG));
3617 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
3618 RREG32(mmSH_MEM_APE1_BASE));
3619 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
3620 RREG32(mmSH_MEM_APE1_LIMIT));
3621 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
3622 RREG32(mmSH_MEM_BASES));
3623 }
3624 vi_srbm_select(adev, 0, 0, 0, 0);
3625 mutex_unlock(&adev->srbm_mutex);
3626}
3627
5fc3aeeb 3628static int gfx_v8_0_soft_reset(void *handle)
aaa36a97
AD		 3629{
3630 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3631 u32 tmp;
5fc3aeeb 3632 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3633
3634 /* GRBM_STATUS */
3635 tmp = RREG32(mmGRBM_STATUS);
3636 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3637 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3638 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3639 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3640 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3641 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3642 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3643 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3644 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3645 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3646 }
3647
3648 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3649 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3650 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3651 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3652 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3653 }
3654
3655 /* GRBM_STATUS2 */
3656 tmp = RREG32(mmGRBM_STATUS2);
3657 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3658 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3659 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3660
3661 /* SRBM_STATUS */
3662 tmp = RREG32(mmSRBM_STATUS);
3663 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3664 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3665 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3666
3667 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 3668 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 3669 /* stop the rlc */
3670 gfx_v8_0_rlc_stop(adev);
3671
3672 /* Disable GFX parsing/prefetching */
3673 gfx_v8_0_cp_gfx_enable(adev, false);
3674
3675 /* Disable MEC parsing/prefetching */
3676 /* XXX todo */
3677
3678 if (grbm_soft_reset) {
3679 tmp = RREG32(mmGRBM_SOFT_RESET);
3680 tmp |= grbm_soft_reset;
3681 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3682 WREG32(mmGRBM_SOFT_RESET, tmp);
3683 tmp = RREG32(mmGRBM_SOFT_RESET);
3684
3685 udelay(50);
3686
3687 tmp &= ~grbm_soft_reset;
3688 WREG32(mmGRBM_SOFT_RESET, tmp);
3689 tmp = RREG32(mmGRBM_SOFT_RESET);
3690 }
3691
3692 if (srbm_soft_reset) {
3693 tmp = RREG32(mmSRBM_SOFT_RESET);
3694 tmp |= srbm_soft_reset;
3695 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3696 WREG32(mmSRBM_SOFT_RESET, tmp);
3697 tmp = RREG32(mmSRBM_SOFT_RESET);
3698
3699 udelay(50);
3700
3701 tmp &= ~srbm_soft_reset;
3702 WREG32(mmSRBM_SOFT_RESET, tmp);
3703 tmp = RREG32(mmSRBM_SOFT_RESET);
3704 }
3705 /* Wait a little for things to settle down */
3706 udelay(50);
5fc3aeeb 3707 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 3708 }
3709 return 0;
3710}
3711
3712/**
3713 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3714 *
3715 * @adev: amdgpu_device pointer
3716 *
3717 * Fetches a GPU clock counter snapshot.
3718 * Returns the 64 bit clock counter snapshot.
3719 */
3720uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3721{
3722 uint64_t clock;
3723
3724 mutex_lock(&adev->gfx.gpu_clock_mutex);
3725 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3726 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3727 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3728 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3729 return clock;
3730}
3731
3732static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3733 uint32_t vmid,
3734 uint32_t gds_base, uint32_t gds_size,
3735 uint32_t gws_base, uint32_t gws_size,
3736 uint32_t oa_base, uint32_t oa_size)
3737{
3738 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3739 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3740
3741 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3742 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3743
3744 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3745 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3746
3747 /* GDS Base */
3748 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3749 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3750 WRITE_DATA_DST_SEL(0)));
3751 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3752 amdgpu_ring_write(ring, 0);
3753 amdgpu_ring_write(ring, gds_base);
3754
3755 /* GDS Size */
3756 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3757 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3758 WRITE_DATA_DST_SEL(0)));
3759 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3760 amdgpu_ring_write(ring, 0);
3761 amdgpu_ring_write(ring, gds_size);
3762
3763 /* GWS */
3764 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3765 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3766 WRITE_DATA_DST_SEL(0)));
3767 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3768 amdgpu_ring_write(ring, 0);
3769 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3770
3771 /* OA */
3772 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3773 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3774 WRITE_DATA_DST_SEL(0)));
3775 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3776 amdgpu_ring_write(ring, 0);
3777 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3778}
3779
5fc3aeeb 3780static int gfx_v8_0_early_init(void *handle)
aaa36a97 3781{
5fc3aeeb 3782 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3783
3784 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3785 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3786 gfx_v8_0_set_ring_funcs(adev);
3787 gfx_v8_0_set_irq_funcs(adev);
3788 gfx_v8_0_set_gds_init(adev);
3789
3790 return 0;
3791}
3792
5fc3aeeb 3793static int gfx_v8_0_set_powergating_state(void *handle,
3794 enum amd_powergating_state state)
aaa36a97
AD		 3795{
3796 return 0;
3797}
3798
5fc3aeeb 3799static int gfx_v8_0_set_clockgating_state(void *handle,
3800 enum amd_clockgating_state state)
aaa36a97
AD		 3801{
3802 return 0;
3803}
3804
3805static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3806{
3807 u32 rptr;
3808
3809 rptr = ring->adev->wb.wb[ring->rptr_offs];
3810
3811 return rptr;
3812}
3813
3814static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3815{
3816 struct amdgpu_device *adev = ring->adev;
3817 u32 wptr;
3818
3819 if (ring->use_doorbell)
3820 /* XXX check if swapping is necessary on BE */
3821 wptr = ring->adev->wb.wb[ring->wptr_offs];
3822 else
3823 wptr = RREG32(mmCP_RB0_WPTR);
3824
3825 return wptr;
3826}
3827
3828static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3829{
3830 struct amdgpu_device *adev = ring->adev;
3831
3832 if (ring->use_doorbell) {
3833 /* XXX check if swapping is necessary on BE */
3834 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3835 WDOORBELL32(ring->doorbell_index, ring->wptr);
3836 } else {
3837 WREG32(mmCP_RB0_WPTR, ring->wptr);
3838 (void)RREG32(mmCP_RB0_WPTR);
3839 }
3840}
3841
d2edb07b 3842static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 3843{
3844 u32 ref_and_mask, reg_mem_engine;
3845
3846 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3847 switch (ring->me) {
3848 case 1:
3849 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3850 break;
3851 case 2:
3852 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3853 break;
3854 default:
3855 return;
3856 }
3857 reg_mem_engine = 0;
3858 } else {
3859 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3860 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3861 }
3862
3863 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3864 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3865 WAIT_REG_MEM_FUNCTION(3) | /* == */
3866 reg_mem_engine));
3867 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3868 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3869 amdgpu_ring_write(ring, ref_and_mask);
3870 amdgpu_ring_write(ring, ref_and_mask);
3871 amdgpu_ring_write(ring, 0x20); /* poll interval */
3872}
3873
93323131 3874static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
aaa36a97
AD		 3875 struct amdgpu_ib *ib)
3876{
3cb485f3 3877 bool need_ctx_switch = ring->current_ctx != ib->ctx;
aaa36a97
AD		 3878 u32 header, control = 0;
3879 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 3880
3881 /* drop the CE preamble IB for the same context */
93323131 3882 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
aa2bdb24
JZ		 3883 return;
3884
93323131 3885 if (need_ctx_switch)
aaa36a97
AD		 3886 next_rptr += 2;
3887
3888 next_rptr += 4;
3889 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3890 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3891 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3892 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3893 amdgpu_ring_write(ring, next_rptr);
3894
aaa36a97 3895 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
93323131 3896 if (need_ctx_switch) {
aaa36a97
AD		 3897 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3898 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 3899 }
3900
de807f81 3901 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 3902 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3903 else
3904 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3905
3906 control |= ib->length_dw |
3907 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3908
3909 amdgpu_ring_write(ring, header);
3910 amdgpu_ring_write(ring,
3911#ifdef __BIG_ENDIAN
3912 (2 << 0) |
3913#endif
3914 (ib->gpu_addr & 0xFFFFFFFC));
3915 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3916 amdgpu_ring_write(ring, control);
3917}
3918
93323131 3919static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3920 struct amdgpu_ib *ib)
3921{
3922 u32 header, control = 0;
3923 u32 next_rptr = ring->wptr + 5;
3924
3925 control |= INDIRECT_BUFFER_VALID;
3926
3927 next_rptr += 4;
3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3929 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3930 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3931 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3932 amdgpu_ring_write(ring, next_rptr);
3933
3934 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3935
3936 control |= ib->length_dw |
3937 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3938
3939 amdgpu_ring_write(ring, header);
3940 amdgpu_ring_write(ring,
3941#ifdef __BIG_ENDIAN
3942 (2 << 0) |
3943#endif
3944 (ib->gpu_addr & 0xFFFFFFFC));
3945 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3946 amdgpu_ring_write(ring, control);
3947}
3948
aaa36a97 3949static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 3950 u64 seq, unsigned flags)
aaa36a97 3951{
890ee23f
CZ		 3952 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3953 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3954
aaa36a97
AD		 3955 /* EVENT_WRITE_EOP - flush caches, send int */
3956 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3957 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3958 EOP_TC_ACTION_EN |
3959 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3960 EVENT_INDEX(5)));
3961 amdgpu_ring_write(ring, addr & 0xfffffffc);
3962 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 3963 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 3964 amdgpu_ring_write(ring, lower_32_bits(seq));
3965 amdgpu_ring_write(ring, upper_32_bits(seq));
3966}
3967
3968/**
3969 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3970 *
3971 * @ring: amdgpu ring buffer object
3972 * @semaphore: amdgpu semaphore object
3973 * @emit_wait: Is this a sempahore wait?
3974 *
3975 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3976 * from running ahead of semaphore waits.
3977 */
3978static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3979 struct amdgpu_semaphore *semaphore,
3980 bool emit_wait)
3981{
3982 uint64_t addr = semaphore->gpu_addr;
3983 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3984
3985 if (ring->adev->asic_type == CHIP_TOPAZ ||
af15a2d5
DZ		 3986 ring->adev->asic_type == CHIP_TONGA ||
3987 ring->adev->asic_type == CHIP_FIJI)
147dbfbc
DZ		 3988 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3989 return false;
3990 else {
aaa36a97
AD		 3991 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3992 amdgpu_ring_write(ring, lower_32_bits(addr));
3993 amdgpu_ring_write(ring, upper_32_bits(addr));
3994 amdgpu_ring_write(ring, sel);
3995 }
3996
3997 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3998 /* Prevent the PFP from running ahead of the semaphore wait */
3999 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4000 amdgpu_ring_write(ring, 0x0);
4001 }
4002
4003 return true;
4004}
4005
4006static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
4007{
4008 struct amdgpu_device *adev = ring->adev;
4009 u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
4010
4011 /* instruct DE to set a magic number */
4012 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4013 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4014 WRITE_DATA_DST_SEL(5)));
4015 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4016 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4017 amdgpu_ring_write(ring, 1);
4018
4019 /* let CE wait till condition satisfied */
4020 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4021 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4022 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4023 WAIT_REG_MEM_FUNCTION(3) | /* == */
4024 WAIT_REG_MEM_ENGINE(2))); /* ce */
4025 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4026 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4027 amdgpu_ring_write(ring, 1);
4028 amdgpu_ring_write(ring, 0xffffffff);
4029 amdgpu_ring_write(ring, 4); /* poll interval */
4030
4031 /* instruct CE to reset wb of ce_sync to zero */
4032 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4033 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4034 WRITE_DATA_DST_SEL(5) |
4035 WR_CONFIRM));
4036 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4037 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4038 amdgpu_ring_write(ring, 0);
4039}
4040
4041static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4042 unsigned vm_id, uint64_t pd_addr)
4043{
4044 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
aaa36a97
AD		 4045
4046 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4047 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4048 WRITE_DATA_DST_SEL(0)));
4049 if (vm_id < 8) {
4050 amdgpu_ring_write(ring,
4051 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4052 } else {
4053 amdgpu_ring_write(ring,
4054 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4055 }
4056 amdgpu_ring_write(ring, 0);
4057 amdgpu_ring_write(ring, pd_addr >> 12);
4058
aaa36a97
AD		 4059 /* bits 0-15 are the VM contexts0-15 */
4060 /* invalidate the cache */
4061 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4062 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4063 WRITE_DATA_DST_SEL(0)));
4064 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4065 amdgpu_ring_write(ring, 0);
4066 amdgpu_ring_write(ring, 1 << vm_id);
4067
4068 /* wait for the invalidate to complete */
4069 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4070 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4071 WAIT_REG_MEM_FUNCTION(0) | /* always */
4072 WAIT_REG_MEM_ENGINE(0))); /* me */
4073 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4074 amdgpu_ring_write(ring, 0);
4075 amdgpu_ring_write(ring, 0); /* ref */
4076 amdgpu_ring_write(ring, 0); /* mask */
4077 amdgpu_ring_write(ring, 0x20); /* poll interval */
4078
4079 /* compute doesn't have PFP */
4080 if (usepfp) {
4081 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4082 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4083 amdgpu_ring_write(ring, 0x0);
4084
4085 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4086 gfx_v8_0_ce_sync_me(ring);
4087 }
4088}
4089
4090static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4091{
4092 if (gfx_v8_0_is_idle(ring->adev)) {
4093 amdgpu_ring_lockup_update(ring);
4094 return false;
4095 }
4096 return amdgpu_ring_test_lockup(ring);
4097}
4098
4099static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4100{
4101 return ring->adev->wb.wb[ring->rptr_offs];
4102}
4103
4104static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4105{
4106 return ring->adev->wb.wb[ring->wptr_offs];
4107}
4108
4109static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4110{
4111 struct amdgpu_device *adev = ring->adev;
4112
4113 /* XXX check if swapping is necessary on BE */
4114 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4115 WDOORBELL32(ring->doorbell_index, ring->wptr);
4116}
4117
4118static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4119 u64 addr, u64 seq,
890ee23f 4120 unsigned flags)
aaa36a97 4121{
890ee23f
CZ		 4122 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4123 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4124
aaa36a97
AD		 4125 /* RELEASE_MEM - flush caches, send int */
4126 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4127 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4128 EOP_TC_ACTION_EN |
4129 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4130 EVENT_INDEX(5)));
890ee23f 4131 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 4132 amdgpu_ring_write(ring, addr & 0xfffffffc);
4133 amdgpu_ring_write(ring, upper_32_bits(addr));
4134 amdgpu_ring_write(ring, lower_32_bits(seq));
4135 amdgpu_ring_write(ring, upper_32_bits(seq));
4136}
4137
4138static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4139 enum amdgpu_interrupt_state state)
4140{
4141 u32 cp_int_cntl;
4142
4143 switch (state) {
4144 case AMDGPU_IRQ_STATE_DISABLE:
4145 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4146 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4147 TIME_STAMP_INT_ENABLE, 0);
4148 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4149 break;
4150 case AMDGPU_IRQ_STATE_ENABLE:
4151 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4152 cp_int_cntl =
4153 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4154 TIME_STAMP_INT_ENABLE, 1);
4155 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4156 break;
4157 default:
4158 break;
4159 }
4160}
4161
4162static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4163 int me, int pipe,
4164 enum amdgpu_interrupt_state state)
4165{
4166 u32 mec_int_cntl, mec_int_cntl_reg;
4167
4168 /*
4169 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4170 * handles the setting of interrupts for this specific pipe. All other
4171 * pipes' interrupts are set by amdkfd.
4172 */
4173
4174 if (me == 1) {
4175 switch (pipe) {
4176 case 0:
4177 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4178 break;
4179 default:
4180 DRM_DEBUG("invalid pipe %d\n", pipe);
4181 return;
4182 }
4183 } else {
4184 DRM_DEBUG("invalid me %d\n", me);
4185 return;
4186 }
4187
4188 switch (state) {
4189 case AMDGPU_IRQ_STATE_DISABLE:
4190 mec_int_cntl = RREG32(mec_int_cntl_reg);
4191 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4192 TIME_STAMP_INT_ENABLE, 0);
4193 WREG32(mec_int_cntl_reg, mec_int_cntl);
4194 break;
4195 case AMDGPU_IRQ_STATE_ENABLE:
4196 mec_int_cntl = RREG32(mec_int_cntl_reg);
4197 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4198 TIME_STAMP_INT_ENABLE, 1);
4199 WREG32(mec_int_cntl_reg, mec_int_cntl);
4200 break;
4201 default:
4202 break;
4203 }
4204}
4205
4206static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4207 struct amdgpu_irq_src *source,
4208 unsigned type,
4209 enum amdgpu_interrupt_state state)
4210{
4211 u32 cp_int_cntl;
4212
4213 switch (state) {
4214 case AMDGPU_IRQ_STATE_DISABLE:
4215 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4216 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4217 PRIV_REG_INT_ENABLE, 0);
4218 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4219 break;
4220 case AMDGPU_IRQ_STATE_ENABLE:
4221 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4222 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4223 PRIV_REG_INT_ENABLE, 0);
4224 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4225 break;
4226 default:
4227 break;
4228 }
4229
4230 return 0;
4231}
4232
4233static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4234 struct amdgpu_irq_src *source,
4235 unsigned type,
4236 enum amdgpu_interrupt_state state)
4237{
4238 u32 cp_int_cntl;
4239
4240 switch (state) {
4241 case AMDGPU_IRQ_STATE_DISABLE:
4242 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4243 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4244 PRIV_INSTR_INT_ENABLE, 0);
4245 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4246 break;
4247 case AMDGPU_IRQ_STATE_ENABLE:
4248 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4249 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4250 PRIV_INSTR_INT_ENABLE, 1);
4251 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4252 break;
4253 default:
4254 break;
4255 }
4256
4257 return 0;
4258}
4259
4260static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4261 struct amdgpu_irq_src *src,
4262 unsigned type,
4263 enum amdgpu_interrupt_state state)
4264{
4265 switch (type) {
4266 case AMDGPU_CP_IRQ_GFX_EOP:
4267 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4268 break;
4269 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4270 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4271 break;
4272 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4273 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4274 break;
4275 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4276 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4277 break;
4278 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4279 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4280 break;
4281 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4282 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4283 break;
4284 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4285 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4286 break;
4287 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4288 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4289 break;
4290 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4291 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4292 break;
4293 default:
4294 break;
4295 }
4296 return 0;
4297}
4298
4299static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4300 struct amdgpu_irq_src *source,
4301 struct amdgpu_iv_entry *entry)
4302{
4303 int i;
4304 u8 me_id, pipe_id, queue_id;
4305 struct amdgpu_ring *ring;
4306
4307 DRM_DEBUG("IH: CP EOP\n");
4308 me_id = (entry->ring_id & 0x0c) >> 2;
4309 pipe_id = (entry->ring_id & 0x03) >> 0;
4310 queue_id = (entry->ring_id & 0x70) >> 4;
4311
4312 switch (me_id) {
4313 case 0:
4314 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4315 break;
4316 case 1:
4317 case 2:
4318 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4319 ring = &adev->gfx.compute_ring[i];
4320 /* Per-queue interrupt is supported for MEC starting from VI.
4321 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4322 */
4323 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4324 amdgpu_fence_process(ring);
4325 }
4326 break;
4327 }
4328 return 0;
4329}
4330
4331static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4332 struct amdgpu_irq_src *source,
4333 struct amdgpu_iv_entry *entry)
4334{
4335 DRM_ERROR("Illegal register access in command stream\n");
4336 schedule_work(&adev->reset_work);
4337 return 0;
4338}
4339
4340static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4341 struct amdgpu_irq_src *source,
4342 struct amdgpu_iv_entry *entry)
4343{
4344 DRM_ERROR("Illegal instruction in command stream\n");
4345 schedule_work(&adev->reset_work);
4346 return 0;
4347}
4348
5fc3aeeb 4349const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
aaa36a97
AD		 4350 .early_init = gfx_v8_0_early_init,
4351 .late_init = NULL,
4352 .sw_init = gfx_v8_0_sw_init,
4353 .sw_fini = gfx_v8_0_sw_fini,
4354 .hw_init = gfx_v8_0_hw_init,
4355 .hw_fini = gfx_v8_0_hw_fini,
4356 .suspend = gfx_v8_0_suspend,
4357 .resume = gfx_v8_0_resume,
4358 .is_idle = gfx_v8_0_is_idle,
4359 .wait_for_idle = gfx_v8_0_wait_for_idle,
4360 .soft_reset = gfx_v8_0_soft_reset,
4361 .print_status = gfx_v8_0_print_status,
4362 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4363 .set_powergating_state = gfx_v8_0_set_powergating_state,
4364};
4365
4366static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4367 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4368 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4369 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4370 .parse_cs = NULL,
93323131 4371 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
aaa36a97
AD		 4372 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4373 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4374 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4375 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 4376 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
aaa36a97
AD		 4377 .test_ring = gfx_v8_0_ring_test_ring,
4378 .test_ib = gfx_v8_0_ring_test_ib,
4379 .is_lockup = gfx_v8_0_ring_is_lockup,
4380};
4381
4382static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4383 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4384 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4385 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4386 .parse_cs = NULL,
93323131 4387 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
aaa36a97
AD		 4388 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4389 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4390 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4391 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 4392 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
aaa36a97
AD		 4393 .test_ring = gfx_v8_0_ring_test_ring,
4394 .test_ib = gfx_v8_0_ring_test_ib,
4395 .is_lockup = gfx_v8_0_ring_is_lockup,
4396};
4397
4398static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4399{
4400 int i;
4401
4402 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4403 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4404
4405 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4406 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4407}
4408
4409static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4410 .set = gfx_v8_0_set_eop_interrupt_state,
4411 .process = gfx_v8_0_eop_irq,
4412};
4413
4414static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4415 .set = gfx_v8_0_set_priv_reg_fault_state,
4416 .process = gfx_v8_0_priv_reg_irq,
4417};
4418
4419static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4420 .set = gfx_v8_0_set_priv_inst_fault_state,
4421 .process = gfx_v8_0_priv_inst_irq,
4422};
4423
4424static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4425{
4426 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4427 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4428
4429 adev->gfx.priv_reg_irq.num_types = 1;
4430 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4431
4432 adev->gfx.priv_inst_irq.num_types = 1;
4433 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4434}
4435
4436static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4437{
4438 /* init asci gds info */
4439 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4440 adev->gds.gws.total_size = 64;
4441 adev->gds.oa.total_size = 16;
4442
4443 if (adev->gds.mem.total_size == 64 * 1024) {
4444 adev->gds.mem.gfx_partition_size = 4096;
4445 adev->gds.mem.cs_partition_size = 4096;
4446
4447 adev->gds.gws.gfx_partition_size = 4;
4448 adev->gds.gws.cs_partition_size = 4;
4449
4450 adev->gds.oa.gfx_partition_size = 4;
4451 adev->gds.oa.cs_partition_size = 1;
4452 } else {
4453 adev->gds.mem.gfx_partition_size = 1024;
4454 adev->gds.mem.cs_partition_size = 1024;
4455
4456 adev->gds.gws.gfx_partition_size = 16;
4457 adev->gds.gws.cs_partition_size = 16;
4458
4459 adev->gds.oa.gfx_partition_size = 4;
4460 adev->gds.oa.cs_partition_size = 4;
4461 }
4462}
4463
4464static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4465 u32 se, u32 sh)
4466{
4467 u32 mask = 0, tmp, tmp1;
4468 int i;
4469
4470 gfx_v8_0_select_se_sh(adev, se, sh);
4471 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4472 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4473 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4474
4475 tmp &= 0xffff0000;
4476
4477 tmp |= tmp1;
4478 tmp >>= 16;
4479
4480 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4481 mask <<= 1;
4482 mask |= 1;
4483 }
4484
4485 return (~tmp) & mask;
4486}
4487
4488int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4489 struct amdgpu_cu_info *cu_info)
4490{
4491 int i, j, k, counter, active_cu_number = 0;
4492 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4493
4494 if (!adev || !cu_info)
4495 return -EINVAL;
4496
4497 mutex_lock(&adev->grbm_idx_mutex);
4498 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4499 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4500 mask = 1;
4501 ao_bitmap = 0;
4502 counter = 0;
4503 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4504 cu_info->bitmap[i][j] = bitmap;
4505
4506 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4507 if (bitmap & mask) {
4508 if (counter < 2)
4509 ao_bitmap |= mask;
4510 counter ++;
4511 }
4512 mask <<= 1;
4513 }
4514 active_cu_number += counter;
4515 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4516 }
4517 }
4518
4519 cu_info->number = active_cu_number;
4520 cu_info->ao_cu_mask = ao_cu_mask;
4521 mutex_unlock(&adev->grbm_idx_mutex);
4522 return 0;
4523}
Linux kernel - Deliverables
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