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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "vi.h"
30#include "vid.h"
31
32#include "oss/oss_3_0_d.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "gca/gfx_8_0_d.h"
74a5d165 39#include "gca/gfx_8_0_enum.h"
aaa36a97
AD		 40#include "gca/gfx_8_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "tonga_sdma_pkt_open.h"
46
47static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
c65444fe
JZ		 52MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
1a5bbb66
DZ		 56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
aaa36a97
AD		 58
59static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
60{
61 SDMA0_REGISTER_OFFSET,
62 SDMA1_REGISTER_OFFSET
63};
64
65static const u32 golden_settings_tonga_a11[] =
66{
67 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
68 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
69 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
70 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
71 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
72 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
73 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
74 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
75 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
77};
78
79static const u32 tonga_mgcg_cgcg_init[] =
80{
81 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
82 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
83};
84
1a5bbb66
DZ		 85static const u32 golden_settings_fiji_a10[] =
86{
87 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
88 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
89 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
90 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
91 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
92 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
93 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
94 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
95};
96
97static const u32 fiji_mgcg_cgcg_init[] =
98{
99 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
100 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
101};
102
aaa36a97
AD		 103static const u32 cz_golden_settings_a11[] =
104{
105 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
106 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
107 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
108 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
109 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
110 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
111 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
112 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
113 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
114 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
115 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
116 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
117};
118
119static const u32 cz_mgcg_cgcg_init[] =
120{
121 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
122 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
123};
124
125/*
126 * sDMA - System DMA
127 * Starting with CIK, the GPU has new asynchronous
128 * DMA engines. These engines are used for compute
129 * and gfx. There are two DMA engines (SDMA0, SDMA1)
130 * and each one supports 1 ring buffer used for gfx
131 * and 2 queues used for compute.
132 *
133 * The programming model is very similar to the CP
134 * (ring buffer, IBs, etc.), but sDMA has it's own
135 * packet format that is different from the PM4 format
136 * used by the CP. sDMA supports copying data, writing
137 * embedded data, solid fills, and a number of other
138 * things. It also has support for tiling/detiling of
139 * buffers.
140 */
141
142static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
143{
144 switch (adev->asic_type) {
1a5bbb66
DZ		 145 case CHIP_FIJI:
146 amdgpu_program_register_sequence(adev,
147 fiji_mgcg_cgcg_init,
148 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
149 amdgpu_program_register_sequence(adev,
150 golden_settings_fiji_a10,
151 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
152 break;
aaa36a97
AD		 153 case CHIP_TONGA:
154 amdgpu_program_register_sequence(adev,
155 tonga_mgcg_cgcg_init,
156 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
157 amdgpu_program_register_sequence(adev,
158 golden_settings_tonga_a11,
159 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
160 break;
161 case CHIP_CARRIZO:
162 amdgpu_program_register_sequence(adev,
163 cz_mgcg_cgcg_init,
164 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
165 amdgpu_program_register_sequence(adev,
166 cz_golden_settings_a11,
167 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
168 break;
169 default:
170 break;
171 }
172}
173
174/**
175 * sdma_v3_0_init_microcode - load ucode images from disk
176 *
177 * @adev: amdgpu_device pointer
178 *
179 * Use the firmware interface to load the ucode images into
180 * the driver (not loaded into hw).
181 * Returns 0 on success, error on failure.
182 */
183static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
184{
185 const char *chip_name;
186 char fw_name[30];
187 int err, i;
188 struct amdgpu_firmware_info *info = NULL;
189 const struct common_firmware_header *header = NULL;
595fd013 190 const struct sdma_firmware_header_v1_0 *hdr;
aaa36a97
AD		 191
192 DRM_DEBUG("\n");
193
194 switch (adev->asic_type) {
195 case CHIP_TONGA:
196 chip_name = "tonga";
197 break;
1a5bbb66
DZ		 198 case CHIP_FIJI:
199 chip_name = "fiji";
200 break;
aaa36a97
AD		 201 case CHIP_CARRIZO:
202 chip_name = "carrizo";
203 break;
204 default: BUG();
205 }
206
207 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
208 if (i == 0)
c65444fe 209 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
aaa36a97 210 else
c65444fe 211 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
aaa36a97
AD		 212 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
213 if (err)
214 goto out;
215 err = amdgpu_ucode_validate(adev->sdma[i].fw);
216 if (err)
217 goto out;
595fd013
JZ		 218 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
219 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
220 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
18111de0
JZ		 221 if (adev->sdma[i].feature_version >= 20)
222 adev->sdma[i].burst_nop = true;
aaa36a97
AD		 223
224 if (adev->firmware.smu_load) {
225 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
226 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
227 info->fw = adev->sdma[i].fw;
228 header = (const struct common_firmware_header *)info->fw->data;
229 adev->firmware.fw_size +=
230 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
231 }
232 }
233out:
234 if (err) {
235 printk(KERN_ERR
236 "sdma_v3_0: Failed to load firmware \"%s\"\n",
237 fw_name);
238 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
239 release_firmware(adev->sdma[i].fw);
240 adev->sdma[i].fw = NULL;
241 }
242 }
243 return err;
244}
245
246/**
247 * sdma_v3_0_ring_get_rptr - get the current read pointer
248 *
249 * @ring: amdgpu ring pointer
250 *
251 * Get the current rptr from the hardware (VI+).
252 */
253static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
254{
255 u32 rptr;
256
257 /* XXX check if swapping is necessary on BE */
258 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
259
260 return rptr;
261}
262
263/**
264 * sdma_v3_0_ring_get_wptr - get the current write pointer
265 *
266 * @ring: amdgpu ring pointer
267 *
268 * Get the current wptr from the hardware (VI+).
269 */
270static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
271{
272 struct amdgpu_device *adev = ring->adev;
273 u32 wptr;
274
275 if (ring->use_doorbell) {
276 /* XXX check if swapping is necessary on BE */
277 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
278 } else {
279 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
280
281 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
282 }
283
284 return wptr;
285}
286
287/**
288 * sdma_v3_0_ring_set_wptr - commit the write pointer
289 *
290 * @ring: amdgpu ring pointer
291 *
292 * Write the wptr back to the hardware (VI+).
293 */
294static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
295{
296 struct amdgpu_device *adev = ring->adev;
297
298 if (ring->use_doorbell) {
299 /* XXX check if swapping is necessary on BE */
300 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
301 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
302 } else {
303 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
304
305 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
306 }
307}
308
ac01db3d
JZ		 309static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
310{
311 struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring);
312 int i;
313
314 for (i = 0; i < count; i++)
315 if (sdma && sdma->burst_nop && (i == 0))
316 amdgpu_ring_write(ring, ring->nop |
317 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
318 else
319 amdgpu_ring_write(ring, ring->nop);
320}
321
aaa36a97
AD		 322/**
323 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
324 *
325 * @ring: amdgpu ring pointer
326 * @ib: IB object to schedule
327 *
328 * Schedule an IB in the DMA ring (VI).
329 */
330static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
331 struct amdgpu_ib *ib)
332{
333 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
334 u32 next_rptr = ring->wptr + 5;
335
aaa36a97
AD		 336 while ((next_rptr & 7) != 2)
337 next_rptr++;
338 next_rptr += 6;
339
340 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
341 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
342 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
343 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
344 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
345 amdgpu_ring_write(ring, next_rptr);
346
aaa36a97 347 /* IB packet must end on a 8 DW boundary */
ac01db3d 348 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
aaa36a97
AD		 349
350 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
351 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
352 /* base must be 32 byte aligned */
353 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
354 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
355 amdgpu_ring_write(ring, ib->length_dw);
356 amdgpu_ring_write(ring, 0);
357 amdgpu_ring_write(ring, 0);
358
359}
360
361/**
d2edb07b 362 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
aaa36a97
AD		 363 *
364 * @ring: amdgpu ring pointer
365 *
366 * Emit an hdp flush packet on the requested DMA ring.
367 */
d2edb07b 368static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 369{
370 u32 ref_and_mask = 0;
371
372 if (ring == &ring->adev->sdma[0].ring)
373 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
374 else
375 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
376
377 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
378 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
379 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
380 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
381 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
382 amdgpu_ring_write(ring, ref_and_mask); /* reference */
383 amdgpu_ring_write(ring, ref_and_mask); /* mask */
384 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
385 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
386}
387
388/**
389 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
390 *
391 * @ring: amdgpu ring pointer
392 * @fence: amdgpu fence object
393 *
394 * Add a DMA fence packet to the ring to write
395 * the fence seq number and DMA trap packet to generate
396 * an interrupt if needed (VI).
397 */
398static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 399 unsigned flags)
aaa36a97 400{
890ee23f 401 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
aaa36a97
AD		 402 /* write the fence */
403 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
404 amdgpu_ring_write(ring, lower_32_bits(addr));
405 amdgpu_ring_write(ring, upper_32_bits(addr));
406 amdgpu_ring_write(ring, lower_32_bits(seq));
407
408 /* optionally write high bits as well */
890ee23f 409 if (write64bit) {
aaa36a97
AD		 410 addr += 4;
411 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
412 amdgpu_ring_write(ring, lower_32_bits(addr));
413 amdgpu_ring_write(ring, upper_32_bits(addr));
414 amdgpu_ring_write(ring, upper_32_bits(seq));
415 }
416
417 /* generate an interrupt */
418 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
419 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
420}
421
422
423/**
424 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
425 *
426 * @ring: amdgpu_ring structure holding ring information
427 * @semaphore: amdgpu semaphore object
428 * @emit_wait: wait or signal semaphore
429 *
430 * Add a DMA semaphore packet to the ring wait on or signal
431 * other rings (VI).
432 */
433static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
434 struct amdgpu_semaphore *semaphore,
435 bool emit_wait)
436{
437 u64 addr = semaphore->gpu_addr;
438 u32 sig = emit_wait ? 0 : 1;
439
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
441 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
442 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
443 amdgpu_ring_write(ring, upper_32_bits(addr));
444
445 return true;
446}
447
448/**
449 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
450 *
451 * @adev: amdgpu_device pointer
452 *
453 * Stop the gfx async dma ring buffers (VI).
454 */
455static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
456{
457 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
458 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
459 u32 rb_cntl, ib_cntl;
460 int i;
461
462 if ((adev->mman.buffer_funcs_ring == sdma0) ||
463 (adev->mman.buffer_funcs_ring == sdma1))
464 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
465
466 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
467 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
468 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
469 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
470 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
471 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
472 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
473 }
474 sdma0->ready = false;
475 sdma1->ready = false;
476}
477
478/**
479 * sdma_v3_0_rlc_stop - stop the compute async dma engines
480 *
481 * @adev: amdgpu_device pointer
482 *
483 * Stop the compute async dma queues (VI).
484 */
485static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
486{
487 /* XXX todo */
488}
489
cd06bf68
BG		 490/**
491 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
492 *
493 * @adev: amdgpu_device pointer
494 * @enable: enable/disable the DMA MEs context switch.
495 *
496 * Halt or unhalt the async dma engines context switch (VI).
497 */
498static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
499{
500 u32 f32_cntl;
501 int i;
502
503 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
504 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
505 if (enable)
506 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
507 AUTO_CTXSW_ENABLE, 1);
508 else
509 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
510 AUTO_CTXSW_ENABLE, 0);
511 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
512 }
513}
514
aaa36a97
AD		 515/**
516 * sdma_v3_0_enable - stop the async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 * @enable: enable/disable the DMA MEs.
520 *
521 * Halt or unhalt the async dma engines (VI).
522 */
523static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
524{
525 u32 f32_cntl;
526 int i;
527
528 if (enable == false) {
529 sdma_v3_0_gfx_stop(adev);
530 sdma_v3_0_rlc_stop(adev);
531 }
532
533 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
534 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
535 if (enable)
536 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
537 else
538 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
539 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
540 }
541}
542
543/**
544 * sdma_v3_0_gfx_resume - setup and start the async dma engines
545 *
546 * @adev: amdgpu_device pointer
547 *
548 * Set up the gfx DMA ring buffers and enable them (VI).
549 * Returns 0 for success, error for failure.
550 */
551static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
552{
553 struct amdgpu_ring *ring;
554 u32 rb_cntl, ib_cntl;
555 u32 rb_bufsz;
556 u32 wb_offset;
557 u32 doorbell;
558 int i, j, r;
559
560 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
561 ring = &adev->sdma[i].ring;
562 wb_offset = (ring->rptr_offs * 4);
563
564 mutex_lock(&adev->srbm_mutex);
565 for (j = 0; j < 16; j++) {
566 vi_srbm_select(adev, 0, 0, 0, j);
567 /* SDMA GFX */
568 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
569 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
570 }
571 vi_srbm_select(adev, 0, 0, 0, 0);
572 mutex_unlock(&adev->srbm_mutex);
573
574 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
575
576 /* Set ring buffer size in dwords */
577 rb_bufsz = order_base_2(ring->ring_size / 4);
578 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
579 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
580#ifdef __BIG_ENDIAN
581 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
582 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
583 RPTR_WRITEBACK_SWAP_ENABLE, 1);
584#endif
585 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
586
587 /* Initialize the ring buffer's read and write pointers */
588 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
589 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
590
591 /* set the wb address whether it's enabled or not */
592 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
593 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
594 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
595 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
596
597 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
598
599 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
600 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
601
602 ring->wptr = 0;
603 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
604
605 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
606
607 if (ring->use_doorbell) {
608 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
609 OFFSET, ring->doorbell_index);
610 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
611 } else {
612 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
613 }
614 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
615
616 /* enable DMA RB */
617 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
618 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
619
620 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
621 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
622#ifdef __BIG_ENDIAN
623 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
624#endif
625 /* enable DMA IBs */
626 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
627
628 ring->ready = true;
629
630 r = amdgpu_ring_test_ring(ring);
631 if (r) {
632 ring->ready = false;
633 return r;
634 }
635
636 if (adev->mman.buffer_funcs_ring == ring)
637 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
638 }
639
640 return 0;
641}
642
643/**
644 * sdma_v3_0_rlc_resume - setup and start the async dma engines
645 *
646 * @adev: amdgpu_device pointer
647 *
648 * Set up the compute DMA queues and enable them (VI).
649 * Returns 0 for success, error for failure.
650 */
651static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
652{
653 /* XXX todo */
654 return 0;
655}
656
657/**
658 * sdma_v3_0_load_microcode - load the sDMA ME ucode
659 *
660 * @adev: amdgpu_device pointer
661 *
662 * Loads the sDMA0/1 ucode.
663 * Returns 0 for success, -EINVAL if the ucode is not available.
664 */
665static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
666{
667 const struct sdma_firmware_header_v1_0 *hdr;
668 const __le32 *fw_data;
669 u32 fw_size;
670 int i, j;
671
672 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
673 return -EINVAL;
674
675 /* halt the MEs */
676 sdma_v3_0_enable(adev, false);
677
678 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
679 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
680 amdgpu_ucode_print_sdma_hdr(&hdr->header);
681 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
aaa36a97
AD		 682 fw_data = (const __le32 *)
683 (adev->sdma[i].fw->data +
684 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
685 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
686 for (j = 0; j < fw_size; j++)
687 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
688 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
689 }
690
691 return 0;
692}
693
694/**
695 * sdma_v3_0_start - setup and start the async dma engines
696 *
697 * @adev: amdgpu_device pointer
698 *
699 * Set up the DMA engines and enable them (VI).
700 * Returns 0 for success, error for failure.
701 */
702static int sdma_v3_0_start(struct amdgpu_device *adev)
703{
704 int r;
705
706 if (!adev->firmware.smu_load) {
707 r = sdma_v3_0_load_microcode(adev);
708 if (r)
709 return r;
710 } else {
711 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
712 AMDGPU_UCODE_ID_SDMA0);
713 if (r)
714 return -EINVAL;
715 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
716 AMDGPU_UCODE_ID_SDMA1);
717 if (r)
718 return -EINVAL;
719 }
720
721 /* unhalt the MEs */
722 sdma_v3_0_enable(adev, true);
cd06bf68
BG		 723 /* enable sdma ring preemption */
724 sdma_v3_0_ctx_switch_enable(adev, true);
aaa36a97
AD		 725
726 /* start the gfx rings and rlc compute queues */
727 r = sdma_v3_0_gfx_resume(adev);
728 if (r)
729 return r;
730 r = sdma_v3_0_rlc_resume(adev);
731 if (r)
732 return r;
733
734 return 0;
735}
736
737/**
738 * sdma_v3_0_ring_test_ring - simple async dma engine test
739 *
740 * @ring: amdgpu_ring structure holding ring information
741 *
742 * Test the DMA engine by writing using it to write an
743 * value to memory. (VI).
744 * Returns 0 for success, error for failure.
745 */
746static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
747{
748 struct amdgpu_device *adev = ring->adev;
749 unsigned i;
750 unsigned index;
751 int r;
752 u32 tmp;
753 u64 gpu_addr;
754
755 r = amdgpu_wb_get(adev, &index);
756 if (r) {
757 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
758 return r;
759 }
760
761 gpu_addr = adev->wb.gpu_addr + (index * 4);
762 tmp = 0xCAFEDEAD;
763 adev->wb.wb[index] = cpu_to_le32(tmp);
764
765 r = amdgpu_ring_lock(ring, 5);
766 if (r) {
767 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
768 amdgpu_wb_free(adev, index);
769 return r;
770 }
771
772 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
773 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
774 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
775 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
776 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
777 amdgpu_ring_write(ring, 0xDEADBEEF);
778 amdgpu_ring_unlock_commit(ring);
779
780 for (i = 0; i < adev->usec_timeout; i++) {
781 tmp = le32_to_cpu(adev->wb.wb[index]);
782 if (tmp == 0xDEADBEEF)
783 break;
784 DRM_UDELAY(1);
785 }
786
787 if (i < adev->usec_timeout) {
788 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
789 } else {
790 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
791 ring->idx, tmp);
792 r = -EINVAL;
793 }
794 amdgpu_wb_free(adev, index);
795
796 return r;
797}
798
799/**
800 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
801 *
802 * @ring: amdgpu_ring structure holding ring information
803 *
804 * Test a simple IB in the DMA ring (VI).
805 * Returns 0 on success, error on failure.
806 */
807static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
808{
809 struct amdgpu_device *adev = ring->adev;
810 struct amdgpu_ib ib;
1763552e 811 struct fence *f = NULL;
aaa36a97
AD		 812 unsigned i;
813 unsigned index;
814 int r;
815 u32 tmp = 0;
816 u64 gpu_addr;
817
818 r = amdgpu_wb_get(adev, &index);
819 if (r) {
820 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
821 return r;
822 }
823
824 gpu_addr = adev->wb.gpu_addr + (index * 4);
825 tmp = 0xCAFEDEAD;
826 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 827 memset(&ib, 0, sizeof(ib));
aaa36a97
AD		 828 r = amdgpu_ib_get(ring, NULL, 256, &ib);
829 if (r) {
aaa36a97 830 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
0011fdaa 831 goto err0;
aaa36a97
AD		 832 }
833
834 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
835 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
836 ib.ptr[1] = lower_32_bits(gpu_addr);
837 ib.ptr[2] = upper_32_bits(gpu_addr);
838 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
839 ib.ptr[4] = 0xDEADBEEF;
840 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
841 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
842 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
843 ib.length_dw = 8;
844
0011fdaa 845 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
1763552e
CZ		 846 AMDGPU_FENCE_OWNER_UNDEFINED,
847 &f);
0011fdaa
CZ		 848 if (r)
849 goto err1;
850
1763552e 851 r = fence_wait(f, false);
aaa36a97 852 if (r) {
aaa36a97 853 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
0011fdaa 854 goto err1;
aaa36a97
AD		 855 }
856 for (i = 0; i < adev->usec_timeout; i++) {
857 tmp = le32_to_cpu(adev->wb.wb[index]);
858 if (tmp == 0xDEADBEEF)
859 break;
860 DRM_UDELAY(1);
861 }
862 if (i < adev->usec_timeout) {
863 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
0011fdaa
CZ		 864 ring->idx, i);
865 goto err1;
aaa36a97
AD		 866 } else {
867 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
868 r = -EINVAL;
869 }
0011fdaa 870err1:
281b4223 871 fence_put(f);
aaa36a97 872 amdgpu_ib_free(adev, &ib);
0011fdaa 873err0:
aaa36a97
AD		 874 amdgpu_wb_free(adev, index);
875 return r;
876}
877
878/**
879 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
880 *
881 * @ib: indirect buffer to fill with commands
882 * @pe: addr of the page entry
883 * @src: src addr to copy from
884 * @count: number of page entries to update
885 *
886 * Update PTEs by copying them from the GART using sDMA (CIK).
887 */
888static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
889 uint64_t pe, uint64_t src,
890 unsigned count)
891{
892 while (count) {
893 unsigned bytes = count * 8;
894 if (bytes > 0x1FFFF8)
895 bytes = 0x1FFFF8;
896
897 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
898 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
899 ib->ptr[ib->length_dw++] = bytes;
900 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
901 ib->ptr[ib->length_dw++] = lower_32_bits(src);
902 ib->ptr[ib->length_dw++] = upper_32_bits(src);
903 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
904 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
905
906 pe += bytes;
907 src += bytes;
908 count -= bytes / 8;
909 }
910}
911
912/**
913 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
914 *
915 * @ib: indirect buffer to fill with commands
916 * @pe: addr of the page entry
917 * @addr: dst addr to write into pe
918 * @count: number of page entries to update
919 * @incr: increase next addr by incr bytes
920 * @flags: access flags
921 *
922 * Update PTEs by writing them manually using sDMA (CIK).
923 */
924static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
925 uint64_t pe,
926 uint64_t addr, unsigned count,
927 uint32_t incr, uint32_t flags)
928{
929 uint64_t value;
930 unsigned ndw;
931
932 while (count) {
933 ndw = count * 2;
934 if (ndw > 0xFFFFE)
935 ndw = 0xFFFFE;
936
937 /* for non-physically contiguous pages (system) */
938 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
939 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
940 ib->ptr[ib->length_dw++] = pe;
941 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
942 ib->ptr[ib->length_dw++] = ndw;
943 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
944 if (flags & AMDGPU_PTE_SYSTEM) {
945 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
946 value &= 0xFFFFFFFFFFFFF000ULL;
947 } else if (flags & AMDGPU_PTE_VALID) {
948 value = addr;
949 } else {
950 value = 0;
951 }
952 addr += incr;
953 value |= flags;
954 ib->ptr[ib->length_dw++] = value;
955 ib->ptr[ib->length_dw++] = upper_32_bits(value);
956 }
957 }
958}
959
960/**
961 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
962 *
963 * @ib: indirect buffer to fill with commands
964 * @pe: addr of the page entry
965 * @addr: dst addr to write into pe
966 * @count: number of page entries to update
967 * @incr: increase next addr by incr bytes
968 * @flags: access flags
969 *
970 * Update the page tables using sDMA (CIK).
971 */
972static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
973 uint64_t pe,
974 uint64_t addr, unsigned count,
975 uint32_t incr, uint32_t flags)
976{
977 uint64_t value;
978 unsigned ndw;
979
980 while (count) {
981 ndw = count;
982 if (ndw > 0x7FFFF)
983 ndw = 0x7FFFF;
984
985 if (flags & AMDGPU_PTE_VALID)
986 value = addr;
987 else
988 value = 0;
989
990 /* for physically contiguous pages (vram) */
991 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
992 ib->ptr[ib->length_dw++] = pe; /* dst addr */
993 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
994 ib->ptr[ib->length_dw++] = flags; /* mask */
995 ib->ptr[ib->length_dw++] = 0;
996 ib->ptr[ib->length_dw++] = value; /* value */
997 ib->ptr[ib->length_dw++] = upper_32_bits(value);
998 ib->ptr[ib->length_dw++] = incr; /* increment size */
999 ib->ptr[ib->length_dw++] = 0;
1000 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1001
1002 pe += ndw * 8;
1003 addr += ndw * incr;
1004 count -= ndw;
1005 }
1006}
1007
1008/**
1009 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
1010 *
1011 * @ib: indirect buffer to fill with padding
1012 *
1013 */
1014static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
1015{
ac01db3d
JZ		 1016 struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring);
1017 u32 pad_count;
1018 int i;
1019
1020 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1021 for (i = 0; i < pad_count; i++)
1022 if (sdma && sdma->burst_nop && (i == 0))
1023 ib->ptr[ib->length_dw++] =
1024 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1025 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1026 else
1027 ib->ptr[ib->length_dw++] =
1028 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
aaa36a97
AD		 1029}
1030
1031/**
1032 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1033 *
1034 * @ring: amdgpu_ring pointer
1035 * @vm: amdgpu_vm pointer
1036 *
1037 * Update the page table base and flush the VM TLB
1038 * using sDMA (VI).
1039 */
1040static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1041 unsigned vm_id, uint64_t pd_addr)
1042{
aaa36a97
AD		 1043 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1044 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1045 if (vm_id < 8) {
1046 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1047 } else {
1048 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1049 }
1050 amdgpu_ring_write(ring, pd_addr >> 12);
1051
aaa36a97
AD		 1052 /* flush TLB */
1053 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1054 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1055 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1056 amdgpu_ring_write(ring, 1 << vm_id);
1057
1058 /* wait for flush */
1059 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1060 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1061 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1062 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1063 amdgpu_ring_write(ring, 0);
1064 amdgpu_ring_write(ring, 0); /* reference */
1065 amdgpu_ring_write(ring, 0); /* mask */
1066 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1067 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1068}
1069
5fc3aeeb 1070static int sdma_v3_0_early_init(void *handle)
aaa36a97 1071{
5fc3aeeb 1072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1073
aaa36a97
AD		 1074 sdma_v3_0_set_ring_funcs(adev);
1075 sdma_v3_0_set_buffer_funcs(adev);
1076 sdma_v3_0_set_vm_pte_funcs(adev);
1077 sdma_v3_0_set_irq_funcs(adev);
1078
1079 return 0;
1080}
1081
5fc3aeeb 1082static int sdma_v3_0_sw_init(void *handle)
aaa36a97
AD		 1083{
1084 struct amdgpu_ring *ring;
1085 int r;
5fc3aeeb 1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1087
1088 /* SDMA trap event */
1089 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
1090 if (r)
1091 return r;
1092
1093 /* SDMA Privileged inst */
1094 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
1095 if (r)
1096 return r;
1097
1098 /* SDMA Privileged inst */
1099 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
1100 if (r)
1101 return r;
1102
1103 r = sdma_v3_0_init_microcode(adev);
1104 if (r) {
1105 DRM_ERROR("Failed to load sdma firmware!\n");
1106 return r;
1107 }
1108
1109 ring = &adev->sdma[0].ring;
1110 ring->ring_obj = NULL;
1111 ring->use_doorbell = true;
1112 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
1113
1114 ring = &adev->sdma[1].ring;
1115 ring->ring_obj = NULL;
1116 ring->use_doorbell = true;
1117 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
1118
1119 ring = &adev->sdma[0].ring;
1120 sprintf(ring->name, "sdma0");
1121 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1122 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1123 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1124 AMDGPU_RING_TYPE_SDMA);
1125 if (r)
1126 return r;
1127
1128 ring = &adev->sdma[1].ring;
1129 sprintf(ring->name, "sdma1");
1130 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1131 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1132 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1133 AMDGPU_RING_TYPE_SDMA);
1134 if (r)
1135 return r;
1136
1137 return r;
1138}
1139
5fc3aeeb 1140static int sdma_v3_0_sw_fini(void *handle)
aaa36a97 1141{
5fc3aeeb 1142 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143
aaa36a97
AD		 1144 amdgpu_ring_fini(&adev->sdma[0].ring);
1145 amdgpu_ring_fini(&adev->sdma[1].ring);
1146
1147 return 0;
1148}
1149
5fc3aeeb 1150static int sdma_v3_0_hw_init(void *handle)
aaa36a97
AD		 1151{
1152 int r;
5fc3aeeb 1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1154
1155 sdma_v3_0_init_golden_registers(adev);
1156
1157 r = sdma_v3_0_start(adev);
1158 if (r)
1159 return r;
1160
1161 return r;
1162}
1163
5fc3aeeb 1164static int sdma_v3_0_hw_fini(void *handle)
aaa36a97 1165{
5fc3aeeb 1166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
cd06bf68 1168 sdma_v3_0_ctx_switch_enable(adev, false);
aaa36a97
AD		 1169 sdma_v3_0_enable(adev, false);
1170
1171 return 0;
1172}
1173
5fc3aeeb 1174static int sdma_v3_0_suspend(void *handle)
aaa36a97 1175{
5fc3aeeb 1176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1177
1178 return sdma_v3_0_hw_fini(adev);
1179}
1180
5fc3aeeb 1181static int sdma_v3_0_resume(void *handle)
aaa36a97 1182{
5fc3aeeb 1183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1184
1185 return sdma_v3_0_hw_init(adev);
1186}
1187
5fc3aeeb 1188static bool sdma_v3_0_is_idle(void *handle)
aaa36a97 1189{
5fc3aeeb 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1191 u32 tmp = RREG32(mmSRBM_STATUS2);
1192
1193 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1194 SRBM_STATUS2__SDMA1_BUSY_MASK))
1195 return false;
1196
1197 return true;
1198}
1199
5fc3aeeb 1200static int sdma_v3_0_wait_for_idle(void *handle)
aaa36a97
AD		 1201{
1202 unsigned i;
1203 u32 tmp;
5fc3aeeb 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1205
1206 for (i = 0; i < adev->usec_timeout; i++) {
1207 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1208 SRBM_STATUS2__SDMA1_BUSY_MASK);
1209
1210 if (!tmp)
1211 return 0;
1212 udelay(1);
1213 }
1214 return -ETIMEDOUT;
1215}
1216
5fc3aeeb 1217static void sdma_v3_0_print_status(void *handle)
aaa36a97
AD		 1218{
1219 int i, j;
5fc3aeeb 1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1221
1222 dev_info(adev->dev, "VI SDMA registers\n");
1223 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1224 RREG32(mmSRBM_STATUS2));
1225 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1226 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1227 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1228 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1229 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1230 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1231 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1232 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1233 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1234 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1235 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1236 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1237 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1238 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1239 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1240 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1241 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1242 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1243 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1244 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1245 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1246 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1247 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1248 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1249 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1250 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
1251 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1252 mutex_lock(&adev->srbm_mutex);
1253 for (j = 0; j < 16; j++) {
1254 vi_srbm_select(adev, 0, 0, 0, j);
1255 dev_info(adev->dev, " VM %d:\n", j);
1256 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1257 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1258 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1259 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1260 }
1261 vi_srbm_select(adev, 0, 0, 0, 0);
1262 mutex_unlock(&adev->srbm_mutex);
1263 }
1264}
1265
5fc3aeeb 1266static int sdma_v3_0_soft_reset(void *handle)
aaa36a97
AD		 1267{
1268 u32 srbm_soft_reset = 0;
5fc3aeeb 1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1270 u32 tmp = RREG32(mmSRBM_STATUS2);
1271
1272 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1273 /* sdma0 */
1274 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1275 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1276 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1277 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1278 }
1279 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1280 /* sdma1 */
1281 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1282 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1283 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1284 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1285 }
1286
1287 if (srbm_soft_reset) {
5fc3aeeb 1288 sdma_v3_0_print_status((void *)adev);
aaa36a97
AD		 1289
1290 tmp = RREG32(mmSRBM_SOFT_RESET);
1291 tmp |= srbm_soft_reset;
1292 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1293 WREG32(mmSRBM_SOFT_RESET, tmp);
1294 tmp = RREG32(mmSRBM_SOFT_RESET);
1295
1296 udelay(50);
1297
1298 tmp &= ~srbm_soft_reset;
1299 WREG32(mmSRBM_SOFT_RESET, tmp);
1300 tmp = RREG32(mmSRBM_SOFT_RESET);
1301
1302 /* Wait a little for things to settle down */
1303 udelay(50);
1304
5fc3aeeb 1305 sdma_v3_0_print_status((void *)adev);
aaa36a97
AD		 1306 }
1307
1308 return 0;
1309}
1310
1311static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1312 struct amdgpu_irq_src *source,
1313 unsigned type,
1314 enum amdgpu_interrupt_state state)
1315{
1316 u32 sdma_cntl;
1317
1318 switch (type) {
1319 case AMDGPU_SDMA_IRQ_TRAP0:
1320 switch (state) {
1321 case AMDGPU_IRQ_STATE_DISABLE:
1322 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1323 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1324 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1325 break;
1326 case AMDGPU_IRQ_STATE_ENABLE:
1327 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1328 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1329 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1330 break;
1331 default:
1332 break;
1333 }
1334 break;
1335 case AMDGPU_SDMA_IRQ_TRAP1:
1336 switch (state) {
1337 case AMDGPU_IRQ_STATE_DISABLE:
1338 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1339 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1340 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1341 break;
1342 case AMDGPU_IRQ_STATE_ENABLE:
1343 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1344 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1345 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1346 break;
1347 default:
1348 break;
1349 }
1350 break;
1351 default:
1352 break;
1353 }
1354 return 0;
1355}
1356
1357static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1358 struct amdgpu_irq_src *source,
1359 struct amdgpu_iv_entry *entry)
1360{
1361 u8 instance_id, queue_id;
1362
1363 instance_id = (entry->ring_id & 0x3) >> 0;
1364 queue_id = (entry->ring_id & 0xc) >> 2;
1365 DRM_DEBUG("IH: SDMA trap\n");
1366 switch (instance_id) {
1367 case 0:
1368 switch (queue_id) {
1369 case 0:
1370 amdgpu_fence_process(&adev->sdma[0].ring);
1371 break;
1372 case 1:
1373 /* XXX compute */
1374 break;
1375 case 2:
1376 /* XXX compute */
1377 break;
1378 }
1379 break;
1380 case 1:
1381 switch (queue_id) {
1382 case 0:
1383 amdgpu_fence_process(&adev->sdma[1].ring);
1384 break;
1385 case 1:
1386 /* XXX compute */
1387 break;
1388 case 2:
1389 /* XXX compute */
1390 break;
1391 }
1392 break;
1393 }
1394 return 0;
1395}
1396
1397static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1398 struct amdgpu_irq_src *source,
1399 struct amdgpu_iv_entry *entry)
1400{
1401 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1402 schedule_work(&adev->reset_work);
1403 return 0;
1404}
1405
5fc3aeeb 1406static int sdma_v3_0_set_clockgating_state(void *handle,
1407 enum amd_clockgating_state state)
aaa36a97 1408{
aaa36a97
AD		 1409 return 0;
1410}
1411
5fc3aeeb 1412static int sdma_v3_0_set_powergating_state(void *handle,
1413 enum amd_powergating_state state)
aaa36a97
AD		 1414{
1415 return 0;
1416}
1417
5fc3aeeb 1418const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
aaa36a97
AD		 1419 .early_init = sdma_v3_0_early_init,
1420 .late_init = NULL,
1421 .sw_init = sdma_v3_0_sw_init,
1422 .sw_fini = sdma_v3_0_sw_fini,
1423 .hw_init = sdma_v3_0_hw_init,
1424 .hw_fini = sdma_v3_0_hw_fini,
1425 .suspend = sdma_v3_0_suspend,
1426 .resume = sdma_v3_0_resume,
1427 .is_idle = sdma_v3_0_is_idle,
1428 .wait_for_idle = sdma_v3_0_wait_for_idle,
1429 .soft_reset = sdma_v3_0_soft_reset,
1430 .print_status = sdma_v3_0_print_status,
1431 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1432 .set_powergating_state = sdma_v3_0_set_powergating_state,
1433};
1434
1435/**
1436 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
1437 *
1438 * @ring: amdgpu_ring structure holding ring information
1439 *
1440 * Check if the async DMA engine is locked up (VI).
1441 * Returns true if the engine appears to be locked up, false if not.
1442 */
1443static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
1444{
1445
1446 if (sdma_v3_0_is_idle(ring->adev)) {
1447 amdgpu_ring_lockup_update(ring);
1448 return false;
1449 }
1450 return amdgpu_ring_test_lockup(ring);
1451}
1452
1453static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1454 .get_rptr = sdma_v3_0_ring_get_rptr,
1455 .get_wptr = sdma_v3_0_ring_get_wptr,
1456 .set_wptr = sdma_v3_0_ring_set_wptr,
1457 .parse_cs = NULL,
1458 .emit_ib = sdma_v3_0_ring_emit_ib,
1459 .emit_fence = sdma_v3_0_ring_emit_fence,
1460 .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1461 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
d2edb07b 1462 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
aaa36a97
AD		 1463 .test_ring = sdma_v3_0_ring_test_ring,
1464 .test_ib = sdma_v3_0_ring_test_ib,
1465 .is_lockup = sdma_v3_0_ring_is_lockup,
ac01db3d 1466 .insert_nop = sdma_v3_0_ring_insert_nop,
aaa36a97
AD		 1467};
1468
1469static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1470{
1471 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
1472 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
1473}
1474
1475static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1476 .set = sdma_v3_0_set_trap_irq_state,
1477 .process = sdma_v3_0_process_trap_irq,
1478};
1479
1480static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1481 .process = sdma_v3_0_process_illegal_inst_irq,
1482};
1483
1484static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1485{
1486 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1487 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1488 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1489}
1490
1491/**
1492 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1493 *
1494 * @ring: amdgpu_ring structure holding ring information
1495 * @src_offset: src GPU address
1496 * @dst_offset: dst GPU address
1497 * @byte_count: number of bytes to xfer
1498 *
1499 * Copy GPU buffers using the DMA engine (VI).
1500 * Used by the amdgpu ttm implementation to move pages if
1501 * registered as the asic copy callback.
1502 */
c7ae72c0 1503static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
aaa36a97
AD		 1504 uint64_t src_offset,
1505 uint64_t dst_offset,
1506 uint32_t byte_count)
1507{
c7ae72c0
CZ		 1508 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1509 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1510 ib->ptr[ib->length_dw++] = byte_count;
1511 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1512 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1513 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1514 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1515 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
aaa36a97
AD		 1516}
1517
1518/**
1519 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1520 *
1521 * @ring: amdgpu_ring structure holding ring information
1522 * @src_data: value to write to buffer
1523 * @dst_offset: dst GPU address
1524 * @byte_count: number of bytes to xfer
1525 *
1526 * Fill GPU buffers using the DMA engine (VI).
1527 */
6e7a3840 1528static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
aaa36a97
AD		 1529 uint32_t src_data,
1530 uint64_t dst_offset,
1531 uint32_t byte_count)
1532{
6e7a3840
CZ		 1533 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1534 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1535 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1536 ib->ptr[ib->length_dw++] = src_data;
1537 ib->ptr[ib->length_dw++] = byte_count;
aaa36a97
AD		 1538}
1539
1540static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1541 .copy_max_bytes = 0x1fffff,
1542 .copy_num_dw = 7,
1543 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1544
1545 .fill_max_bytes = 0x1fffff,
1546 .fill_num_dw = 5,
1547 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1548};
1549
1550static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1551{
1552 if (adev->mman.buffer_funcs == NULL) {
1553 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1554 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1555 }
1556}
1557
1558static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1559 .copy_pte = sdma_v3_0_vm_copy_pte,
1560 .write_pte = sdma_v3_0_vm_write_pte,
1561 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1562 .pad_ib = sdma_v3_0_vm_pad_ib,
1563};
1564
1565static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1566{
1567 if (adev->vm_manager.vm_pte_funcs == NULL) {
1568 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1569 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
4274f5d4 1570 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
aaa36a97
AD		 1571 }
1572}
Linux kernel - Deliverables
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