drm/amdgpu: move UVD IB test into common code v2
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
CommitLineData
aaa36a97
AD
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "vi.h"
30#include "vid.h"
31
32#include "oss/oss_3_0_d.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "gca/gfx_8_0_d.h"
74a5d165 39#include "gca/gfx_8_0_enum.h"
aaa36a97
AD
40#include "gca/gfx_8_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "tonga_sdma_pkt_open.h"
46
47static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
c65444fe
JZ
52MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
1a5bbb66
DZ
56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
bb16e3b6 58MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
2cc0c0b5
FC
59MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
2cea03de 63
aaa36a97
AD
64
65static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
66{
67 SDMA0_REGISTER_OFFSET,
68 SDMA1_REGISTER_OFFSET
69};
70
71static const u32 golden_settings_tonga_a11[] =
72{
73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
83};
84
85static const u32 tonga_mgcg_cgcg_init[] =
86{
87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
89};
90
1a5bbb66
DZ
91static const u32 golden_settings_fiji_a10[] =
92{
93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
101};
102
103static const u32 fiji_mgcg_cgcg_init[] =
104{
105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
107};
108
2cc0c0b5 109static const u32 golden_settings_polaris11_a11[] =
2cea03de
FC
110{
111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
b9934878 112 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
2cea03de
FC
113 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
114 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
115 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
116 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
b9934878 117 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
2cea03de
FC
118 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
121};
122
2cc0c0b5 123static const u32 golden_settings_polaris10_a11[] =
2cea03de
FC
124{
125 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
126 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
127 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
129 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
130 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
131 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
132 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
133 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
134 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
135};
136
aaa36a97
AD
137static const u32 cz_golden_settings_a11[] =
138{
139 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
140 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
142 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
143 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
144 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
145 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
146 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
147 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
148 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
149 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
150 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
151};
152
153static const u32 cz_mgcg_cgcg_init[] =
154{
155 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
156 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
157};
158
bb16e3b6
SL
159static const u32 stoney_golden_settings_a11[] =
160{
161 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
162 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
163 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
164 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
165};
166
167static const u32 stoney_mgcg_cgcg_init[] =
168{
169 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
170};
171
aaa36a97
AD
172/*
173 * sDMA - System DMA
174 * Starting with CIK, the GPU has new asynchronous
175 * DMA engines. These engines are used for compute
176 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 * and each one supports 1 ring buffer used for gfx
178 * and 2 queues used for compute.
179 *
180 * The programming model is very similar to the CP
181 * (ring buffer, IBs, etc.), but sDMA has it's own
182 * packet format that is different from the PM4 format
183 * used by the CP. sDMA supports copying data, writing
184 * embedded data, solid fills, and a number of other
185 * things. It also has support for tiling/detiling of
186 * buffers.
187 */
188
189static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
190{
191 switch (adev->asic_type) {
1a5bbb66
DZ
192 case CHIP_FIJI:
193 amdgpu_program_register_sequence(adev,
194 fiji_mgcg_cgcg_init,
195 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
196 amdgpu_program_register_sequence(adev,
197 golden_settings_fiji_a10,
198 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
199 break;
aaa36a97
AD
200 case CHIP_TONGA:
201 amdgpu_program_register_sequence(adev,
202 tonga_mgcg_cgcg_init,
203 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
204 amdgpu_program_register_sequence(adev,
205 golden_settings_tonga_a11,
206 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
207 break;
2cc0c0b5 208 case CHIP_POLARIS11:
2cea03de 209 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC
210 golden_settings_polaris11_a11,
211 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
2cea03de 212 break;
2cc0c0b5 213 case CHIP_POLARIS10:
2cea03de 214 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC
215 golden_settings_polaris10_a11,
216 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
2cea03de 217 break;
aaa36a97
AD
218 case CHIP_CARRIZO:
219 amdgpu_program_register_sequence(adev,
220 cz_mgcg_cgcg_init,
221 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
222 amdgpu_program_register_sequence(adev,
223 cz_golden_settings_a11,
224 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
225 break;
bb16e3b6
SL
226 case CHIP_STONEY:
227 amdgpu_program_register_sequence(adev,
228 stoney_mgcg_cgcg_init,
229 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
230 amdgpu_program_register_sequence(adev,
231 stoney_golden_settings_a11,
232 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
233 break;
aaa36a97
AD
234 default:
235 break;
236 }
237}
238
14d83e78
ML
239static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
240{
241 int i;
242 for (i = 0; i < adev->sdma.num_instances; i++) {
243 release_firmware(adev->sdma.instance[i].fw);
244 adev->sdma.instance[i].fw = NULL;
245 }
246}
247
aaa36a97
AD
248/**
249 * sdma_v3_0_init_microcode - load ucode images from disk
250 *
251 * @adev: amdgpu_device pointer
252 *
253 * Use the firmware interface to load the ucode images into
254 * the driver (not loaded into hw).
255 * Returns 0 on success, error on failure.
256 */
257static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
258{
259 const char *chip_name;
260 char fw_name[30];
c113ea1c 261 int err = 0, i;
aaa36a97
AD
262 struct amdgpu_firmware_info *info = NULL;
263 const struct common_firmware_header *header = NULL;
595fd013 264 const struct sdma_firmware_header_v1_0 *hdr;
aaa36a97
AD
265
266 DRM_DEBUG("\n");
267
268 switch (adev->asic_type) {
269 case CHIP_TONGA:
270 chip_name = "tonga";
271 break;
1a5bbb66
DZ
272 case CHIP_FIJI:
273 chip_name = "fiji";
274 break;
2cc0c0b5
FC
275 case CHIP_POLARIS11:
276 chip_name = "polaris11";
2cea03de 277 break;
2cc0c0b5
FC
278 case CHIP_POLARIS10:
279 chip_name = "polaris10";
2cea03de 280 break;
aaa36a97
AD
281 case CHIP_CARRIZO:
282 chip_name = "carrizo";
283 break;
bb16e3b6
SL
284 case CHIP_STONEY:
285 chip_name = "stoney";
286 break;
aaa36a97
AD
287 default: BUG();
288 }
289
c113ea1c 290 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97 291 if (i == 0)
c65444fe 292 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
aaa36a97 293 else
c65444fe 294 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
c113ea1c 295 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
aaa36a97
AD
296 if (err)
297 goto out;
c113ea1c 298 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
aaa36a97
AD
299 if (err)
300 goto out;
c113ea1c
AD
301 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
302 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
303 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
304 if (adev->sdma.instance[i].feature_version >= 20)
305 adev->sdma.instance[i].burst_nop = true;
aaa36a97
AD
306
307 if (adev->firmware.smu_load) {
308 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
309 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
c113ea1c 310 info->fw = adev->sdma.instance[i].fw;
aaa36a97
AD
311 header = (const struct common_firmware_header *)info->fw->data;
312 adev->firmware.fw_size +=
313 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
314 }
315 }
316out:
317 if (err) {
318 printk(KERN_ERR
319 "sdma_v3_0: Failed to load firmware \"%s\"\n",
320 fw_name);
c113ea1c
AD
321 for (i = 0; i < adev->sdma.num_instances; i++) {
322 release_firmware(adev->sdma.instance[i].fw);
323 adev->sdma.instance[i].fw = NULL;
aaa36a97
AD
324 }
325 }
326 return err;
327}
328
329/**
330 * sdma_v3_0_ring_get_rptr - get the current read pointer
331 *
332 * @ring: amdgpu ring pointer
333 *
334 * Get the current rptr from the hardware (VI+).
335 */
336static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
337{
338 u32 rptr;
339
340 /* XXX check if swapping is necessary on BE */
341 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
342
343 return rptr;
344}
345
346/**
347 * sdma_v3_0_ring_get_wptr - get the current write pointer
348 *
349 * @ring: amdgpu ring pointer
350 *
351 * Get the current wptr from the hardware (VI+).
352 */
353static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
354{
355 struct amdgpu_device *adev = ring->adev;
356 u32 wptr;
357
358 if (ring->use_doorbell) {
359 /* XXX check if swapping is necessary on BE */
360 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
361 } else {
c113ea1c 362 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
aaa36a97
AD
363
364 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
365 }
366
367 return wptr;
368}
369
370/**
371 * sdma_v3_0_ring_set_wptr - commit the write pointer
372 *
373 * @ring: amdgpu ring pointer
374 *
375 * Write the wptr back to the hardware (VI+).
376 */
377static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
378{
379 struct amdgpu_device *adev = ring->adev;
380
381 if (ring->use_doorbell) {
382 /* XXX check if swapping is necessary on BE */
383 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
384 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
385 } else {
c113ea1c 386 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
aaa36a97
AD
387
388 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
389 }
390}
391
ac01db3d
JZ
392static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
393{
c113ea1c 394 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ
395 int i;
396
397 for (i = 0; i < count; i++)
398 if (sdma && sdma->burst_nop && (i == 0))
399 amdgpu_ring_write(ring, ring->nop |
400 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
401 else
402 amdgpu_ring_write(ring, ring->nop);
403}
404
aaa36a97
AD
405/**
406 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
407 *
408 * @ring: amdgpu ring pointer
409 * @ib: IB object to schedule
410 *
411 * Schedule an IB in the DMA ring (VI).
412 */
413static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
d88bf583
CK
414 struct amdgpu_ib *ib,
415 unsigned vm_id, bool ctx_switch)
aaa36a97 416{
d88bf583 417 u32 vmid = vm_id & 0xf;
aaa36a97 418
aaa36a97 419 /* IB packet must end on a 8 DW boundary */
ac01db3d 420 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
aaa36a97
AD
421
422 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
423 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
424 /* base must be 32 byte aligned */
425 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
426 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
427 amdgpu_ring_write(ring, ib->length_dw);
428 amdgpu_ring_write(ring, 0);
429 amdgpu_ring_write(ring, 0);
430
431}
432
433/**
d2edb07b 434 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
aaa36a97
AD
435 *
436 * @ring: amdgpu ring pointer
437 *
438 * Emit an hdp flush packet on the requested DMA ring.
439 */
d2edb07b 440static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD
441{
442 u32 ref_and_mask = 0;
443
c113ea1c 444 if (ring == &ring->adev->sdma.instance[0].ring)
aaa36a97
AD
445 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
446 else
447 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
448
449 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
450 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
451 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
452 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
453 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
454 amdgpu_ring_write(ring, ref_and_mask); /* reference */
455 amdgpu_ring_write(ring, ref_and_mask); /* mask */
456 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
457 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
458}
459
cc958e67
CZ
460static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
461{
462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
463 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
464 amdgpu_ring_write(ring, mmHDP_DEBUG0);
465 amdgpu_ring_write(ring, 1);
466}
467
aaa36a97
AD
468/**
469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
470 *
471 * @ring: amdgpu ring pointer
472 * @fence: amdgpu fence object
473 *
474 * Add a DMA fence packet to the ring to write
475 * the fence seq number and DMA trap packet to generate
476 * an interrupt if needed (VI).
477 */
478static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 479 unsigned flags)
aaa36a97 480{
890ee23f 481 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
aaa36a97
AD
482 /* write the fence */
483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
484 amdgpu_ring_write(ring, lower_32_bits(addr));
485 amdgpu_ring_write(ring, upper_32_bits(addr));
486 amdgpu_ring_write(ring, lower_32_bits(seq));
487
488 /* optionally write high bits as well */
890ee23f 489 if (write64bit) {
aaa36a97
AD
490 addr += 4;
491 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
492 amdgpu_ring_write(ring, lower_32_bits(addr));
493 amdgpu_ring_write(ring, upper_32_bits(addr));
494 amdgpu_ring_write(ring, upper_32_bits(seq));
495 }
496
497 /* generate an interrupt */
498 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
499 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
500}
501
03ccf481
ML
502unsigned init_cond_exec(struct amdgpu_ring *ring)
503{
504 unsigned ret;
505 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
506 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
507 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
508 amdgpu_ring_write(ring, 1);
509 ret = ring->wptr;/* this is the offset we need patch later */
510 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
511 return ret;
512}
513
514void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
515{
516 unsigned cur;
517 BUG_ON(ring->ring[offset] != 0x55aa55aa);
518
519 cur = ring->wptr - 1;
520 if (likely(cur > offset))
521 ring->ring[offset] = cur - offset;
522 else
523 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
524}
525
526
aaa36a97
AD
527/**
528 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
529 *
530 * @adev: amdgpu_device pointer
531 *
532 * Stop the gfx async dma ring buffers (VI).
533 */
534static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
535{
c113ea1c
AD
536 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
537 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
aaa36a97
AD
538 u32 rb_cntl, ib_cntl;
539 int i;
540
541 if ((adev->mman.buffer_funcs_ring == sdma0) ||
542 (adev->mman.buffer_funcs_ring == sdma1))
543 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
544
c113ea1c 545 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97
AD
546 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
547 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
548 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
549 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
550 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
551 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
552 }
553 sdma0->ready = false;
554 sdma1->ready = false;
555}
556
557/**
558 * sdma_v3_0_rlc_stop - stop the compute async dma engines
559 *
560 * @adev: amdgpu_device pointer
561 *
562 * Stop the compute async dma queues (VI).
563 */
564static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
565{
566 /* XXX todo */
567}
568
cd06bf68
BG
569/**
570 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
571 *
572 * @adev: amdgpu_device pointer
573 * @enable: enable/disable the DMA MEs context switch.
574 *
575 * Halt or unhalt the async dma engines context switch (VI).
576 */
577static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
578{
579 u32 f32_cntl;
580 int i;
581
c113ea1c 582 for (i = 0; i < adev->sdma.num_instances; i++) {
cd06bf68
BG
583 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
584 if (enable)
585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
586 AUTO_CTXSW_ENABLE, 1);
587 else
588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
589 AUTO_CTXSW_ENABLE, 0);
590 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
591 }
592}
593
aaa36a97
AD
594/**
595 * sdma_v3_0_enable - stop the async dma engines
596 *
597 * @adev: amdgpu_device pointer
598 * @enable: enable/disable the DMA MEs.
599 *
600 * Halt or unhalt the async dma engines (VI).
601 */
602static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
603{
604 u32 f32_cntl;
605 int i;
606
004e29cc 607 if (!enable) {
aaa36a97
AD
608 sdma_v3_0_gfx_stop(adev);
609 sdma_v3_0_rlc_stop(adev);
610 }
611
c113ea1c 612 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97
AD
613 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
614 if (enable)
615 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
616 else
617 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
618 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
619 }
620}
621
622/**
623 * sdma_v3_0_gfx_resume - setup and start the async dma engines
624 *
625 * @adev: amdgpu_device pointer
626 *
627 * Set up the gfx DMA ring buffers and enable them (VI).
628 * Returns 0 for success, error for failure.
629 */
630static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
631{
632 struct amdgpu_ring *ring;
633 u32 rb_cntl, ib_cntl;
634 u32 rb_bufsz;
635 u32 wb_offset;
636 u32 doorbell;
637 int i, j, r;
638
c113ea1c
AD
639 for (i = 0; i < adev->sdma.num_instances; i++) {
640 ring = &adev->sdma.instance[i].ring;
aaa36a97
AD
641 wb_offset = (ring->rptr_offs * 4);
642
643 mutex_lock(&adev->srbm_mutex);
644 for (j = 0; j < 16; j++) {
645 vi_srbm_select(adev, 0, 0, 0, j);
646 /* SDMA GFX */
647 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
648 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
649 }
650 vi_srbm_select(adev, 0, 0, 0, 0);
651 mutex_unlock(&adev->srbm_mutex);
652
c458fe94
AD
653 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
654 adev->gfx.config.gb_addr_config & 0x70);
655
aaa36a97
AD
656 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
657
658 /* Set ring buffer size in dwords */
659 rb_bufsz = order_base_2(ring->ring_size / 4);
660 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
661 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
662#ifdef __BIG_ENDIAN
663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
665 RPTR_WRITEBACK_SWAP_ENABLE, 1);
666#endif
667 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
668
669 /* Initialize the ring buffer's read and write pointers */
670 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
671 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
d72f7c06
ML
672 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
673 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
aaa36a97
AD
674
675 /* set the wb address whether it's enabled or not */
676 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
677 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
678 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
679 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
680
681 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
682
683 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
684 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
685
686 ring->wptr = 0;
687 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
688
689 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
690
691 if (ring->use_doorbell) {
692 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
693 OFFSET, ring->doorbell_index);
694 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
695 } else {
696 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
697 }
698 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
699
700 /* enable DMA RB */
701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
702 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
703
704 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
705 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
706#ifdef __BIG_ENDIAN
707 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
708#endif
709 /* enable DMA IBs */
710 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
711
712 ring->ready = true;
505dfe76 713 }
aaa36a97 714
505dfe76
ML
715 /* unhalt the MEs */
716 sdma_v3_0_enable(adev, true);
717 /* enable sdma ring preemption */
718 sdma_v3_0_ctx_switch_enable(adev, true);
719
720 for (i = 0; i < adev->sdma.num_instances; i++) {
721 ring = &adev->sdma.instance[i].ring;
aaa36a97
AD
722 r = amdgpu_ring_test_ring(ring);
723 if (r) {
724 ring->ready = false;
725 return r;
726 }
727
728 if (adev->mman.buffer_funcs_ring == ring)
729 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
730 }
731
732 return 0;
733}
734
735/**
736 * sdma_v3_0_rlc_resume - setup and start the async dma engines
737 *
738 * @adev: amdgpu_device pointer
739 *
740 * Set up the compute DMA queues and enable them (VI).
741 * Returns 0 for success, error for failure.
742 */
743static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
744{
745 /* XXX todo */
746 return 0;
747}
748
749/**
750 * sdma_v3_0_load_microcode - load the sDMA ME ucode
751 *
752 * @adev: amdgpu_device pointer
753 *
754 * Loads the sDMA0/1 ucode.
755 * Returns 0 for success, -EINVAL if the ucode is not available.
756 */
757static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
758{
759 const struct sdma_firmware_header_v1_0 *hdr;
760 const __le32 *fw_data;
761 u32 fw_size;
762 int i, j;
763
aaa36a97
AD
764 /* halt the MEs */
765 sdma_v3_0_enable(adev, false);
766
c113ea1c
AD
767 for (i = 0; i < adev->sdma.num_instances; i++) {
768 if (!adev->sdma.instance[i].fw)
769 return -EINVAL;
770 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
aaa36a97
AD
771 amdgpu_ucode_print_sdma_hdr(&hdr->header);
772 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
aaa36a97 773 fw_data = (const __le32 *)
c113ea1c 774 (adev->sdma.instance[i].fw->data +
aaa36a97
AD
775 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
776 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
777 for (j = 0; j < fw_size; j++)
778 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
c113ea1c 779 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
aaa36a97
AD
780 }
781
782 return 0;
783}
784
785/**
786 * sdma_v3_0_start - setup and start the async dma engines
787 *
788 * @adev: amdgpu_device pointer
789 *
790 * Set up the DMA engines and enable them (VI).
791 * Returns 0 for success, error for failure.
792 */
793static int sdma_v3_0_start(struct amdgpu_device *adev)
794{
c113ea1c 795 int r, i;
aaa36a97 796
e61710c5 797 if (!adev->pp_enabled) {
ba5c2a87
RZ
798 if (!adev->firmware.smu_load) {
799 r = sdma_v3_0_load_microcode(adev);
c113ea1c 800 if (r)
ba5c2a87
RZ
801 return r;
802 } else {
803 for (i = 0; i < adev->sdma.num_instances; i++) {
804 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
805 (i == 0) ?
806 AMDGPU_UCODE_ID_SDMA0 :
807 AMDGPU_UCODE_ID_SDMA1);
808 if (r)
809 return -EINVAL;
810 }
c113ea1c 811 }
aaa36a97
AD
812 }
813
505dfe76
ML
814 /* disble sdma engine before programing it */
815 sdma_v3_0_ctx_switch_enable(adev, false);
816 sdma_v3_0_enable(adev, false);
aaa36a97
AD
817
818 /* start the gfx rings and rlc compute queues */
819 r = sdma_v3_0_gfx_resume(adev);
820 if (r)
821 return r;
822 r = sdma_v3_0_rlc_resume(adev);
823 if (r)
824 return r;
825
826 return 0;
827}
828
829/**
830 * sdma_v3_0_ring_test_ring - simple async dma engine test
831 *
832 * @ring: amdgpu_ring structure holding ring information
833 *
834 * Test the DMA engine by writing using it to write an
835 * value to memory. (VI).
836 * Returns 0 for success, error for failure.
837 */
838static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
839{
840 struct amdgpu_device *adev = ring->adev;
841 unsigned i;
842 unsigned index;
843 int r;
844 u32 tmp;
845 u64 gpu_addr;
846
847 r = amdgpu_wb_get(adev, &index);
848 if (r) {
849 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
850 return r;
851 }
852
853 gpu_addr = adev->wb.gpu_addr + (index * 4);
854 tmp = 0xCAFEDEAD;
855 adev->wb.wb[index] = cpu_to_le32(tmp);
856
a27de35c 857 r = amdgpu_ring_alloc(ring, 5);
aaa36a97
AD
858 if (r) {
859 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
860 amdgpu_wb_free(adev, index);
861 return r;
862 }
863
864 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
865 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
866 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
867 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
868 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
869 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 870 amdgpu_ring_commit(ring);
aaa36a97
AD
871
872 for (i = 0; i < adev->usec_timeout; i++) {
873 tmp = le32_to_cpu(adev->wb.wb[index]);
874 if (tmp == 0xDEADBEEF)
875 break;
876 DRM_UDELAY(1);
877 }
878
879 if (i < adev->usec_timeout) {
880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
881 } else {
882 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
883 ring->idx, tmp);
884 r = -EINVAL;
885 }
886 amdgpu_wb_free(adev, index);
887
888 return r;
889}
890
891/**
892 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
893 *
894 * @ring: amdgpu_ring structure holding ring information
895 *
896 * Test a simple IB in the DMA ring (VI).
897 * Returns 0 on success, error on failure.
898 */
899static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
900{
901 struct amdgpu_device *adev = ring->adev;
902 struct amdgpu_ib ib;
1763552e 903 struct fence *f = NULL;
aaa36a97
AD
904 unsigned index;
905 int r;
906 u32 tmp = 0;
907 u64 gpu_addr;
908
909 r = amdgpu_wb_get(adev, &index);
910 if (r) {
911 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
912 return r;
913 }
914
915 gpu_addr = adev->wb.gpu_addr + (index * 4);
916 tmp = 0xCAFEDEAD;
917 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 918 memset(&ib, 0, sizeof(ib));
b07c60c0 919 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97 920 if (r) {
aaa36a97 921 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
0011fdaa 922 goto err0;
aaa36a97
AD
923 }
924
925 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
926 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
927 ib.ptr[1] = lower_32_bits(gpu_addr);
928 ib.ptr[2] = upper_32_bits(gpu_addr);
929 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
930 ib.ptr[4] = 0xDEADBEEF;
931 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
932 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
933 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
934 ib.length_dw = 8;
935
c5637837 936 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
0011fdaa
CZ
937 if (r)
938 goto err1;
939
1763552e 940 r = fence_wait(f, false);
aaa36a97 941 if (r) {
aaa36a97 942 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
0011fdaa 943 goto err1;
aaa36a97 944 }
6d44565d
CK
945 tmp = le32_to_cpu(adev->wb.wb[index]);
946 if (tmp == 0xDEADBEEF) {
947 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
aaa36a97
AD
948 } else {
949 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
950 r = -EINVAL;
951 }
0011fdaa 952err1:
cc55c45d 953 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 954 fence_put(f);
0011fdaa 955err0:
aaa36a97
AD
956 amdgpu_wb_free(adev, index);
957 return r;
958}
959
960/**
961 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
962 *
963 * @ib: indirect buffer to fill with commands
964 * @pe: addr of the page entry
965 * @src: src addr to copy from
966 * @count: number of page entries to update
967 *
968 * Update PTEs by copying them from the GART using sDMA (CIK).
969 */
970static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
971 uint64_t pe, uint64_t src,
972 unsigned count)
973{
974 while (count) {
975 unsigned bytes = count * 8;
976 if (bytes > 0x1FFFF8)
977 bytes = 0x1FFFF8;
978
979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
981 ib->ptr[ib->length_dw++] = bytes;
982 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
983 ib->ptr[ib->length_dw++] = lower_32_bits(src);
984 ib->ptr[ib->length_dw++] = upper_32_bits(src);
985 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
986 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
987
988 pe += bytes;
989 src += bytes;
990 count -= bytes / 8;
991 }
992}
993
994/**
995 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
996 *
997 * @ib: indirect buffer to fill with commands
998 * @pe: addr of the page entry
999 * @addr: dst addr to write into pe
1000 * @count: number of page entries to update
1001 * @incr: increase next addr by incr bytes
1002 * @flags: access flags
1003 *
1004 * Update PTEs by writing them manually using sDMA (CIK).
1005 */
1006static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
b07c9d2a 1007 const dma_addr_t *pages_addr, uint64_t pe,
aaa36a97
AD
1008 uint64_t addr, unsigned count,
1009 uint32_t incr, uint32_t flags)
1010{
1011 uint64_t value;
1012 unsigned ndw;
1013
1014 while (count) {
1015 ndw = count * 2;
1016 if (ndw > 0xFFFFE)
1017 ndw = 0xFFFFE;
1018
1019 /* for non-physically contiguous pages (system) */
1020 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1021 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1022 ib->ptr[ib->length_dw++] = pe;
1023 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1024 ib->ptr[ib->length_dw++] = ndw;
1025 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
b07c9d2a 1026 value = amdgpu_vm_map_gart(pages_addr, addr);
aaa36a97
AD
1027 addr += incr;
1028 value |= flags;
1029 ib->ptr[ib->length_dw++] = value;
1030 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1031 }
1032 }
1033}
1034
1035/**
1036 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1037 *
1038 * @ib: indirect buffer to fill with commands
1039 * @pe: addr of the page entry
1040 * @addr: dst addr to write into pe
1041 * @count: number of page entries to update
1042 * @incr: increase next addr by incr bytes
1043 * @flags: access flags
1044 *
1045 * Update the page tables using sDMA (CIK).
1046 */
1047static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1048 uint64_t pe,
1049 uint64_t addr, unsigned count,
1050 uint32_t incr, uint32_t flags)
1051{
1052 uint64_t value;
1053 unsigned ndw;
1054
1055 while (count) {
1056 ndw = count;
1057 if (ndw > 0x7FFFF)
1058 ndw = 0x7FFFF;
1059
1060 if (flags & AMDGPU_PTE_VALID)
1061 value = addr;
1062 else
1063 value = 0;
1064
1065 /* for physically contiguous pages (vram) */
1066 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1067 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1068 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1069 ib->ptr[ib->length_dw++] = flags; /* mask */
1070 ib->ptr[ib->length_dw++] = 0;
1071 ib->ptr[ib->length_dw++] = value; /* value */
1072 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1073 ib->ptr[ib->length_dw++] = incr; /* increment size */
1074 ib->ptr[ib->length_dw++] = 0;
1075 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1076
1077 pe += ndw * 8;
1078 addr += ndw * incr;
1079 count -= ndw;
1080 }
1081}
1082
1083/**
9e5d5309 1084 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
aaa36a97
AD
1085 *
1086 * @ib: indirect buffer to fill with padding
1087 *
1088 */
9e5d5309 1089static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
aaa36a97 1090{
9e5d5309 1091 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ
1092 u32 pad_count;
1093 int i;
1094
1095 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1096 for (i = 0; i < pad_count; i++)
1097 if (sdma && sdma->burst_nop && (i == 0))
1098 ib->ptr[ib->length_dw++] =
1099 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1100 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1101 else
1102 ib->ptr[ib->length_dw++] =
1103 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
aaa36a97
AD
1104}
1105
1106/**
00b7c4ff 1107 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
aaa36a97
AD
1108 *
1109 * @ring: amdgpu_ring pointer
aaa36a97 1110 *
00b7c4ff 1111 * Make sure all previous operations are completed (CIK).
aaa36a97 1112 */
00b7c4ff 1113static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97 1114{
5c55db83
CZ
1115 uint32_t seq = ring->fence_drv.sync_seq;
1116 uint64_t addr = ring->fence_drv.gpu_addr;
1117
1118 /* wait for idle */
1119 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1120 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1121 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1122 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1123 amdgpu_ring_write(ring, addr & 0xfffffffc);
1124 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1125 amdgpu_ring_write(ring, seq); /* reference */
1126 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1127 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1128 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
00b7c4ff 1129}
5c55db83 1130
00b7c4ff
CK
1131/**
1132 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1133 *
1134 * @ring: amdgpu_ring pointer
1135 * @vm: amdgpu_vm pointer
1136 *
1137 * Update the page table base and flush the VM TLB
1138 * using sDMA (VI).
1139 */
1140static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1141 unsigned vm_id, uint64_t pd_addr)
1142{
aaa36a97
AD
1143 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1144 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1145 if (vm_id < 8) {
1146 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1147 } else {
1148 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1149 }
1150 amdgpu_ring_write(ring, pd_addr >> 12);
1151
aaa36a97
AD
1152 /* flush TLB */
1153 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1154 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1155 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1156 amdgpu_ring_write(ring, 1 << vm_id);
1157
1158 /* wait for flush */
1159 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1160 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1161 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1162 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1163 amdgpu_ring_write(ring, 0);
1164 amdgpu_ring_write(ring, 0); /* reference */
1165 amdgpu_ring_write(ring, 0); /* mask */
1166 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1167 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1168}
1169
5fc3aeeb 1170static int sdma_v3_0_early_init(void *handle)
aaa36a97 1171{
5fc3aeeb 1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173
c113ea1c 1174 switch (adev->asic_type) {
bb16e3b6
SL
1175 case CHIP_STONEY:
1176 adev->sdma.num_instances = 1;
1177 break;
c113ea1c
AD
1178 default:
1179 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1180 break;
1181 }
1182
aaa36a97
AD
1183 sdma_v3_0_set_ring_funcs(adev);
1184 sdma_v3_0_set_buffer_funcs(adev);
1185 sdma_v3_0_set_vm_pte_funcs(adev);
1186 sdma_v3_0_set_irq_funcs(adev);
1187
1188 return 0;
1189}
1190
5fc3aeeb 1191static int sdma_v3_0_sw_init(void *handle)
aaa36a97
AD
1192{
1193 struct amdgpu_ring *ring;
c113ea1c 1194 int r, i;
5fc3aeeb 1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1196
1197 /* SDMA trap event */
c113ea1c 1198 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
aaa36a97
AD
1199 if (r)
1200 return r;
1201
1202 /* SDMA Privileged inst */
c113ea1c 1203 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
aaa36a97
AD
1204 if (r)
1205 return r;
1206
1207 /* SDMA Privileged inst */
c113ea1c 1208 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
aaa36a97
AD
1209 if (r)
1210 return r;
1211
1212 r = sdma_v3_0_init_microcode(adev);
1213 if (r) {
1214 DRM_ERROR("Failed to load sdma firmware!\n");
1215 return r;
1216 }
1217
c113ea1c
AD
1218 for (i = 0; i < adev->sdma.num_instances; i++) {
1219 ring = &adev->sdma.instance[i].ring;
1220 ring->ring_obj = NULL;
1221 ring->use_doorbell = true;
1222 ring->doorbell_index = (i == 0) ?
1223 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1224
1225 sprintf(ring->name, "sdma%d", i);
b38d99c4 1226 r = amdgpu_ring_init(adev, ring, 1024,
c113ea1c
AD
1227 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1228 &adev->sdma.trap_irq,
1229 (i == 0) ?
1230 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1231 AMDGPU_RING_TYPE_SDMA);
1232 if (r)
1233 return r;
1234 }
aaa36a97
AD
1235
1236 return r;
1237}
1238
5fc3aeeb 1239static int sdma_v3_0_sw_fini(void *handle)
aaa36a97 1240{
5fc3aeeb 1241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 1242 int i;
5fc3aeeb 1243
c113ea1c
AD
1244 for (i = 0; i < adev->sdma.num_instances; i++)
1245 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
aaa36a97 1246
14d83e78 1247 sdma_v3_0_free_microcode(adev);
aaa36a97
AD
1248 return 0;
1249}
1250
5fc3aeeb 1251static int sdma_v3_0_hw_init(void *handle)
aaa36a97
AD
1252{
1253 int r;
5fc3aeeb 1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1255
1256 sdma_v3_0_init_golden_registers(adev);
1257
1258 r = sdma_v3_0_start(adev);
1259 if (r)
1260 return r;
1261
1262 return r;
1263}
1264
5fc3aeeb 1265static int sdma_v3_0_hw_fini(void *handle)
aaa36a97 1266{
5fc3aeeb 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268
cd06bf68 1269 sdma_v3_0_ctx_switch_enable(adev, false);
aaa36a97
AD
1270 sdma_v3_0_enable(adev, false);
1271
1272 return 0;
1273}
1274
5fc3aeeb 1275static int sdma_v3_0_suspend(void *handle)
aaa36a97 1276{
5fc3aeeb 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1278
1279 return sdma_v3_0_hw_fini(adev);
1280}
1281
5fc3aeeb 1282static int sdma_v3_0_resume(void *handle)
aaa36a97 1283{
5fc3aeeb 1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1285
1286 return sdma_v3_0_hw_init(adev);
1287}
1288
5fc3aeeb 1289static bool sdma_v3_0_is_idle(void *handle)
aaa36a97 1290{
5fc3aeeb 1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1292 u32 tmp = RREG32(mmSRBM_STATUS2);
1293
1294 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1295 SRBM_STATUS2__SDMA1_BUSY_MASK))
1296 return false;
1297
1298 return true;
1299}
1300
5fc3aeeb 1301static int sdma_v3_0_wait_for_idle(void *handle)
aaa36a97
AD
1302{
1303 unsigned i;
1304 u32 tmp;
5fc3aeeb 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1306
1307 for (i = 0; i < adev->usec_timeout; i++) {
1308 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1309 SRBM_STATUS2__SDMA1_BUSY_MASK);
1310
1311 if (!tmp)
1312 return 0;
1313 udelay(1);
1314 }
1315 return -ETIMEDOUT;
1316}
1317
5fc3aeeb 1318static int sdma_v3_0_soft_reset(void *handle)
aaa36a97
AD
1319{
1320 u32 srbm_soft_reset = 0;
5fc3aeeb 1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD
1322 u32 tmp = RREG32(mmSRBM_STATUS2);
1323
1324 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1325 /* sdma0 */
1326 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1327 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1328 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1329 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1330 }
1331 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1332 /* sdma1 */
1333 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1334 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1335 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1336 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1337 }
1338
1339 if (srbm_soft_reset) {
aaa36a97
AD
1340 tmp = RREG32(mmSRBM_SOFT_RESET);
1341 tmp |= srbm_soft_reset;
1342 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1343 WREG32(mmSRBM_SOFT_RESET, tmp);
1344 tmp = RREG32(mmSRBM_SOFT_RESET);
1345
1346 udelay(50);
1347
1348 tmp &= ~srbm_soft_reset;
1349 WREG32(mmSRBM_SOFT_RESET, tmp);
1350 tmp = RREG32(mmSRBM_SOFT_RESET);
1351
1352 /* Wait a little for things to settle down */
1353 udelay(50);
aaa36a97
AD
1354 }
1355
1356 return 0;
1357}
1358
1359static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1360 struct amdgpu_irq_src *source,
1361 unsigned type,
1362 enum amdgpu_interrupt_state state)
1363{
1364 u32 sdma_cntl;
1365
1366 switch (type) {
1367 case AMDGPU_SDMA_IRQ_TRAP0:
1368 switch (state) {
1369 case AMDGPU_IRQ_STATE_DISABLE:
1370 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1371 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1372 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1373 break;
1374 case AMDGPU_IRQ_STATE_ENABLE:
1375 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1376 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1377 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1378 break;
1379 default:
1380 break;
1381 }
1382 break;
1383 case AMDGPU_SDMA_IRQ_TRAP1:
1384 switch (state) {
1385 case AMDGPU_IRQ_STATE_DISABLE:
1386 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1387 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1388 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1389 break;
1390 case AMDGPU_IRQ_STATE_ENABLE:
1391 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1392 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1393 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1394 break;
1395 default:
1396 break;
1397 }
1398 break;
1399 default:
1400 break;
1401 }
1402 return 0;
1403}
1404
1405static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1406 struct amdgpu_irq_src *source,
1407 struct amdgpu_iv_entry *entry)
1408{
1409 u8 instance_id, queue_id;
1410
1411 instance_id = (entry->ring_id & 0x3) >> 0;
1412 queue_id = (entry->ring_id & 0xc) >> 2;
1413 DRM_DEBUG("IH: SDMA trap\n");
1414 switch (instance_id) {
1415 case 0:
1416 switch (queue_id) {
1417 case 0:
c113ea1c 1418 amdgpu_fence_process(&adev->sdma.instance[0].ring);
aaa36a97
AD
1419 break;
1420 case 1:
1421 /* XXX compute */
1422 break;
1423 case 2:
1424 /* XXX compute */
1425 break;
1426 }
1427 break;
1428 case 1:
1429 switch (queue_id) {
1430 case 0:
c113ea1c 1431 amdgpu_fence_process(&adev->sdma.instance[1].ring);
aaa36a97
AD
1432 break;
1433 case 1:
1434 /* XXX compute */
1435 break;
1436 case 2:
1437 /* XXX compute */
1438 break;
1439 }
1440 break;
1441 }
1442 return 0;
1443}
1444
1445static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1446 struct amdgpu_irq_src *source,
1447 struct amdgpu_iv_entry *entry)
1448{
1449 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1450 schedule_work(&adev->reset_work);
1451 return 0;
1452}
1453
ce22362b 1454static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
3c997d24
EH
1455 struct amdgpu_device *adev,
1456 bool enable)
1457{
1458 uint32_t temp, data;
ce22362b 1459 int i;
3c997d24 1460
e08d53cb 1461 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
ce22362b
AD
1462 for (i = 0; i < adev->sdma.num_instances; i++) {
1463 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1464 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1466 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1472 if (data != temp)
1473 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1474 }
3c997d24 1475 } else {
ce22362b
AD
1476 for (i = 0; i < adev->sdma.num_instances; i++) {
1477 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1478 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
3c997d24
EH
1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1486
ce22362b
AD
1487 if (data != temp)
1488 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1489 }
3c997d24
EH
1490 }
1491}
1492
ce22362b 1493static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
3c997d24
EH
1494 struct amdgpu_device *adev,
1495 bool enable)
1496{
1497 uint32_t temp, data;
ce22362b 1498 int i;
3c997d24 1499
e08d53cb 1500 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
ce22362b
AD
1501 for (i = 0; i < adev->sdma.num_instances; i++) {
1502 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1503 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
3c997d24 1504
ce22362b
AD
1505 if (temp != data)
1506 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1507 }
3c997d24 1508 } else {
ce22362b
AD
1509 for (i = 0; i < adev->sdma.num_instances; i++) {
1510 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1511 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
3c997d24 1512
ce22362b
AD
1513 if (temp != data)
1514 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1515 }
3c997d24
EH
1516 }
1517}
1518
5fc3aeeb 1519static int sdma_v3_0_set_clockgating_state(void *handle,
1520 enum amd_clockgating_state state)
aaa36a97 1521{
3c997d24
EH
1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523
1524 switch (adev->asic_type) {
1525 case CHIP_FIJI:
ce22362b
AD
1526 case CHIP_CARRIZO:
1527 case CHIP_STONEY:
1528 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
3c997d24 1529 state == AMD_CG_STATE_GATE ? true : false);
ce22362b 1530 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
3c997d24
EH
1531 state == AMD_CG_STATE_GATE ? true : false);
1532 break;
1533 default:
1534 break;
1535 }
aaa36a97
AD
1536 return 0;
1537}
1538
5fc3aeeb 1539static int sdma_v3_0_set_powergating_state(void *handle,
1540 enum amd_powergating_state state)
aaa36a97
AD
1541{
1542 return 0;
1543}
1544
5fc3aeeb 1545const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
88a907d6 1546 .name = "sdma_v3_0",
aaa36a97
AD
1547 .early_init = sdma_v3_0_early_init,
1548 .late_init = NULL,
1549 .sw_init = sdma_v3_0_sw_init,
1550 .sw_fini = sdma_v3_0_sw_fini,
1551 .hw_init = sdma_v3_0_hw_init,
1552 .hw_fini = sdma_v3_0_hw_fini,
1553 .suspend = sdma_v3_0_suspend,
1554 .resume = sdma_v3_0_resume,
1555 .is_idle = sdma_v3_0_is_idle,
1556 .wait_for_idle = sdma_v3_0_wait_for_idle,
1557 .soft_reset = sdma_v3_0_soft_reset,
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AD
1558 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1559 .set_powergating_state = sdma_v3_0_set_powergating_state,
1560};
1561
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1562static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1563 .get_rptr = sdma_v3_0_ring_get_rptr,
1564 .get_wptr = sdma_v3_0_ring_get_wptr,
1565 .set_wptr = sdma_v3_0_ring_set_wptr,
1566 .parse_cs = NULL,
1567 .emit_ib = sdma_v3_0_ring_emit_ib,
1568 .emit_fence = sdma_v3_0_ring_emit_fence,
00b7c4ff 1569 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
aaa36a97 1570 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
d2edb07b 1571 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
cc958e67 1572 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
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1573 .test_ring = sdma_v3_0_ring_test_ring,
1574 .test_ib = sdma_v3_0_ring_test_ib,
ac01db3d 1575 .insert_nop = sdma_v3_0_ring_insert_nop,
9e5d5309 1576 .pad_ib = sdma_v3_0_ring_pad_ib,
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1577};
1578
1579static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1580{
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1581 int i;
1582
1583 for (i = 0; i < adev->sdma.num_instances; i++)
1584 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
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1585}
1586
1587static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1588 .set = sdma_v3_0_set_trap_irq_state,
1589 .process = sdma_v3_0_process_trap_irq,
1590};
1591
1592static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1593 .process = sdma_v3_0_process_illegal_inst_irq,
1594};
1595
1596static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1597{
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1598 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1599 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1600 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
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1601}
1602
1603/**
1604 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1605 *
1606 * @ring: amdgpu_ring structure holding ring information
1607 * @src_offset: src GPU address
1608 * @dst_offset: dst GPU address
1609 * @byte_count: number of bytes to xfer
1610 *
1611 * Copy GPU buffers using the DMA engine (VI).
1612 * Used by the amdgpu ttm implementation to move pages if
1613 * registered as the asic copy callback.
1614 */
c7ae72c0 1615static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
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1616 uint64_t src_offset,
1617 uint64_t dst_offset,
1618 uint32_t byte_count)
1619{
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1620 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1621 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1622 ib->ptr[ib->length_dw++] = byte_count;
1623 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1624 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1625 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1626 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1627 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
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1628}
1629
1630/**
1631 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1632 *
1633 * @ring: amdgpu_ring structure holding ring information
1634 * @src_data: value to write to buffer
1635 * @dst_offset: dst GPU address
1636 * @byte_count: number of bytes to xfer
1637 *
1638 * Fill GPU buffers using the DMA engine (VI).
1639 */
6e7a3840 1640static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
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1641 uint32_t src_data,
1642 uint64_t dst_offset,
1643 uint32_t byte_count)
1644{
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1645 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1646 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1647 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1648 ib->ptr[ib->length_dw++] = src_data;
1649 ib->ptr[ib->length_dw++] = byte_count;
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1650}
1651
1652static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1653 .copy_max_bytes = 0x1fffff,
1654 .copy_num_dw = 7,
1655 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1656
1657 .fill_max_bytes = 0x1fffff,
1658 .fill_num_dw = 5,
1659 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1660};
1661
1662static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1663{
1664 if (adev->mman.buffer_funcs == NULL) {
1665 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
c113ea1c 1666 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
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1667 }
1668}
1669
1670static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1671 .copy_pte = sdma_v3_0_vm_copy_pte,
1672 .write_pte = sdma_v3_0_vm_write_pte,
1673 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
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1674};
1675
1676static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1677{
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1678 unsigned i;
1679
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1680 if (adev->vm_manager.vm_pte_funcs == NULL) {
1681 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
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1682 for (i = 0; i < adev->sdma.num_instances; i++)
1683 adev->vm_manager.vm_pte_rings[i] =
1684 &adev->sdma.instance[i].ring;
1685
1686 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
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1687 }
1688}
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