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1 | // CZ Ucode Loading Definitions |
2 | #ifndef SMU_UCODE_XFER_CZ_H | |
3 | #define SMU_UCODE_XFER_CZ_H | |
4 | ||
5 | #define NUM_JOBLIST_ENTRIES 32 | |
6 | ||
7 | #define TASK_TYPE_NO_ACTION 0 | |
8 | #define TASK_TYPE_UCODE_LOAD 1 | |
9 | #define TASK_TYPE_UCODE_SAVE 2 | |
10 | #define TASK_TYPE_REG_LOAD 3 | |
11 | #define TASK_TYPE_REG_SAVE 4 | |
12 | #define TASK_TYPE_INITIALIZE 5 | |
13 | ||
14 | #define TASK_ARG_REG_SMCIND 0 | |
15 | #define TASK_ARG_REG_MMIO 1 | |
16 | #define TASK_ARG_REG_FCH 2 | |
17 | #define TASK_ARG_REG_UNB 3 | |
18 | ||
19 | #define TASK_ARG_INIT_MM_PWR_LOG 0 | |
20 | #define TASK_ARG_INIT_CLK_TABLE 1 | |
21 | ||
22 | #define JOB_GFX_SAVE 0 | |
23 | #define JOB_GFX_RESTORE 1 | |
24 | #define JOB_FCH_SAVE 2 | |
25 | #define JOB_FCH_RESTORE 3 | |
26 | #define JOB_UNB_SAVE 4 | |
27 | #define JOB_UNB_RESTORE 5 | |
28 | #define JOB_GMC_SAVE 6 | |
29 | #define JOB_GMC_RESTORE 7 | |
30 | #define JOB_GNB_SAVE 8 | |
31 | #define JOB_GNB_RESTORE 9 | |
32 | ||
33 | #define IGNORE_JOB 0xff | |
34 | #define END_OF_TASK_LIST (uint16_t)0xffff | |
35 | ||
36 | // Size of DRAM regions (in bytes) requested by SMU: | |
37 | #define SMU_DRAM_REQ_MM_PWR_LOG 48 | |
38 | ||
39 | #define UCODE_ID_SDMA0 0 | |
40 | #define UCODE_ID_SDMA1 1 | |
41 | #define UCODE_ID_CP_CE 2 | |
42 | #define UCODE_ID_CP_PFP 3 | |
43 | #define UCODE_ID_CP_ME 4 | |
44 | #define UCODE_ID_CP_MEC_JT1 5 | |
45 | #define UCODE_ID_CP_MEC_JT2 6 | |
46 | #define UCODE_ID_GMCON_RENG 7 | |
47 | #define UCODE_ID_RLC_G 8 | |
48 | #define UCODE_ID_RLC_SCRATCH 9 | |
49 | #define UCODE_ID_RLC_SRM_ARAM 10 | |
50 | #define UCODE_ID_RLC_SRM_DRAM 11 | |
51 | #define UCODE_ID_DMCU_ERAM 12 | |
52 | #define UCODE_ID_DMCU_IRAM 13 | |
53 | ||
54 | #define UCODE_ID_SDMA0_MASK 0x00000001 | |
55 | #define UCODE_ID_SDMA1_MASK 0x00000002 | |
56 | #define UCODE_ID_CP_CE_MASK 0x00000004 | |
57 | #define UCODE_ID_CP_PFP_MASK 0x00000008 | |
58 | #define UCODE_ID_CP_ME_MASK 0x00000010 | |
59 | #define UCODE_ID_CP_MEC_JT1_MASK 0x00000020 | |
60 | #define UCODE_ID_CP_MEC_JT2_MASK 0x00000040 | |
61 | #define UCODE_ID_GMCON_RENG_MASK 0x00000080 | |
62 | #define UCODE_ID_RLC_G_MASK 0x00000100 | |
63 | #define UCODE_ID_RLC_SCRATCH_MASK 0x00000200 | |
64 | #define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400 | |
65 | #define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800 | |
66 | #define UCODE_ID_DMCU_ERAM_MASK 0x00001000 | |
67 | #define UCODE_ID_DMCU_IRAM_MASK 0x00002000 | |
68 | ||
69 | #define UCODE_ID_SDMA0_SIZE_BYTE 10368 | |
70 | #define UCODE_ID_SDMA1_SIZE_BYTE 10368 | |
71 | #define UCODE_ID_CP_CE_SIZE_BYTE 8576 | |
72 | #define UCODE_ID_CP_PFP_SIZE_BYTE 16768 | |
73 | #define UCODE_ID_CP_ME_SIZE_BYTE 16768 | |
74 | #define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384 | |
75 | #define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384 | |
76 | #define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096 | |
77 | #define UCODE_ID_RLC_G_SIZE_BYTE 2048 | |
78 | #define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132 | |
79 | #define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192 | |
80 | #define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096 | |
81 | #define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576 | |
82 | #define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024 | |
83 | ||
84 | #define NUM_UCODES 14 | |
85 | ||
86 | typedef struct { | |
87 | uint32_t high; | |
88 | uint32_t low; | |
89 | } data_64_t; | |
90 | ||
91 | struct SMU_Task { | |
92 | uint8_t type; | |
93 | uint8_t arg; | |
94 | uint16_t next; | |
95 | data_64_t addr; | |
96 | uint32_t size_bytes; | |
97 | }; | |
98 | typedef struct SMU_Task SMU_Task; | |
99 | ||
100 | struct TOC { | |
101 | uint8_t JobList[NUM_JOBLIST_ENTRIES]; | |
102 | SMU_Task tasks[1]; | |
103 | }; | |
104 | ||
105 | // META DATA COMMAND Definitions | |
106 | #define METADATA_CMD_MODE0 0x00000103 | |
107 | #define METADATA_CMD_MODE1 0x00000113 | |
108 | #define METADATA_CMD_MODE2 0x00000123 | |
109 | #define METADATA_CMD_MODE3 0x00000133 | |
110 | #define METADATA_CMD_DELAY 0x00000203 | |
111 | #define METADATA_CMD_CHNG_REGSPACE 0x00000303 | |
112 | #define METADATA_PERFORM_ON_SAVE 0x00001000 | |
113 | #define METADATA_PERFORM_ON_LOAD 0x00002000 | |
114 | #define METADATA_CMD_ARG_MASK 0xFFFF0000 | |
115 | #define METADATA_CMD_ARG_SHIFT 16 | |
116 | ||
117 | // Simple register addr/data fields | |
118 | struct SMU_MetaData_Mode0 { | |
119 | uint32_t register_address; | |
120 | uint32_t register_data; | |
121 | }; | |
122 | typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0; | |
123 | ||
124 | // Register addr/data with mask | |
125 | struct SMU_MetaData_Mode1 { | |
126 | uint32_t register_address; | |
127 | uint32_t register_mask; | |
128 | uint32_t register_data; | |
129 | }; | |
130 | typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1; | |
131 | ||
132 | struct SMU_MetaData_Mode2 { | |
133 | uint32_t register_address; | |
134 | uint32_t register_mask; | |
135 | uint32_t target_value; | |
136 | }; | |
137 | typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2; | |
138 | ||
139 | // Always write data (even on a save operation) | |
140 | struct SMU_MetaData_Mode3 { | |
141 | uint32_t register_address; | |
142 | uint32_t register_mask; | |
143 | uint32_t register_data; | |
144 | }; | |
145 | typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3; | |
146 | ||
147 | #endif |