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a2e73f56 AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König <christian.koenig@amd.com> | |
23 | */ | |
24 | ||
25 | #include <linux/firmware.h> | |
26 | #include <drm/drmP.h> | |
27 | #include "amdgpu.h" | |
28 | #include "amdgpu_uvd.h" | |
29 | #include "cikd.h" | |
30 | ||
31 | #include "uvd/uvd_4_2_d.h" | |
32 | #include "uvd/uvd_4_2_sh_mask.h" | |
33 | ||
34 | #include "oss/oss_2_0_d.h" | |
35 | #include "oss/oss_2_0_sh_mask.h" | |
36 | ||
d5b4e25d CK |
37 | #include "bif/bif_4_1_d.h" |
38 | ||
a2e73f56 AD |
39 | static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); |
40 | static void uvd_v4_2_init_cg(struct amdgpu_device *adev); | |
41 | static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); | |
42 | static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); | |
43 | static int uvd_v4_2_start(struct amdgpu_device *adev); | |
44 | static void uvd_v4_2_stop(struct amdgpu_device *adev); | |
45 | ||
46 | /** | |
47 | * uvd_v4_2_ring_get_rptr - get read pointer | |
48 | * | |
49 | * @ring: amdgpu_ring pointer | |
50 | * | |
51 | * Returns the current hardware read pointer | |
52 | */ | |
53 | static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) | |
54 | { | |
55 | struct amdgpu_device *adev = ring->adev; | |
56 | ||
57 | return RREG32(mmUVD_RBC_RB_RPTR); | |
58 | } | |
59 | ||
60 | /** | |
61 | * uvd_v4_2_ring_get_wptr - get write pointer | |
62 | * | |
63 | * @ring: amdgpu_ring pointer | |
64 | * | |
65 | * Returns the current hardware write pointer | |
66 | */ | |
67 | static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) | |
68 | { | |
69 | struct amdgpu_device *adev = ring->adev; | |
70 | ||
71 | return RREG32(mmUVD_RBC_RB_WPTR); | |
72 | } | |
73 | ||
74 | /** | |
75 | * uvd_v4_2_ring_set_wptr - set write pointer | |
76 | * | |
77 | * @ring: amdgpu_ring pointer | |
78 | * | |
79 | * Commits the write pointer to the hardware | |
80 | */ | |
81 | static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) | |
82 | { | |
83 | struct amdgpu_device *adev = ring->adev; | |
84 | ||
85 | WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); | |
86 | } | |
87 | ||
5fc3aeeb | 88 | static int uvd_v4_2_early_init(void *handle) |
a2e73f56 | 89 | { |
5fc3aeeb | 90 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
91 | ||
a2e73f56 AD |
92 | uvd_v4_2_set_ring_funcs(adev); |
93 | uvd_v4_2_set_irq_funcs(adev); | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
5fc3aeeb | 98 | static int uvd_v4_2_sw_init(void *handle) |
a2e73f56 AD |
99 | { |
100 | struct amdgpu_ring *ring; | |
5fc3aeeb | 101 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
102 | int r; |
103 | ||
104 | /* UVD TRAP */ | |
105 | r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); | |
106 | if (r) | |
107 | return r; | |
108 | ||
109 | r = amdgpu_uvd_sw_init(adev); | |
110 | if (r) | |
111 | return r; | |
112 | ||
113 | r = amdgpu_uvd_resume(adev); | |
114 | if (r) | |
115 | return r; | |
116 | ||
117 | ring = &adev->uvd.ring; | |
118 | sprintf(ring->name, "uvd"); | |
a3f1cf35 | 119 | r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, |
a2e73f56 AD |
120 | &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); |
121 | ||
122 | return r; | |
123 | } | |
124 | ||
5fc3aeeb | 125 | static int uvd_v4_2_sw_fini(void *handle) |
a2e73f56 AD |
126 | { |
127 | int r; | |
5fc3aeeb | 128 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
129 | |
130 | r = amdgpu_uvd_suspend(adev); | |
131 | if (r) | |
132 | return r; | |
133 | ||
134 | r = amdgpu_uvd_sw_fini(adev); | |
135 | if (r) | |
136 | return r; | |
137 | ||
138 | return r; | |
139 | } | |
140 | ||
141 | /** | |
142 | * uvd_v4_2_hw_init - start and test UVD block | |
143 | * | |
144 | * @adev: amdgpu_device pointer | |
145 | * | |
146 | * Initialize the hardware, boot up the VCPU and do some testing | |
147 | */ | |
5fc3aeeb | 148 | static int uvd_v4_2_hw_init(void *handle) |
a2e73f56 | 149 | { |
5fc3aeeb | 150 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
151 | struct amdgpu_ring *ring = &adev->uvd.ring; |
152 | uint32_t tmp; | |
153 | int r; | |
154 | ||
155 | /* raise clocks while booting up the VCPU */ | |
156 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
157 | ||
158 | r = uvd_v4_2_start(adev); | |
159 | if (r) | |
160 | goto done; | |
161 | ||
162 | ring->ready = true; | |
163 | r = amdgpu_ring_test_ring(ring); | |
164 | if (r) { | |
165 | ring->ready = false; | |
166 | goto done; | |
167 | } | |
168 | ||
a27de35c | 169 | r = amdgpu_ring_alloc(ring, 10); |
a2e73f56 AD |
170 | if (r) { |
171 | DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); | |
172 | goto done; | |
173 | } | |
174 | ||
175 | tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); | |
176 | amdgpu_ring_write(ring, tmp); | |
177 | amdgpu_ring_write(ring, 0xFFFFF); | |
178 | ||
179 | tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); | |
180 | amdgpu_ring_write(ring, tmp); | |
181 | amdgpu_ring_write(ring, 0xFFFFF); | |
182 | ||
183 | tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); | |
184 | amdgpu_ring_write(ring, tmp); | |
185 | amdgpu_ring_write(ring, 0xFFFFF); | |
186 | ||
187 | /* Clear timeout status bits */ | |
188 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); | |
189 | amdgpu_ring_write(ring, 0x8); | |
190 | ||
191 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); | |
192 | amdgpu_ring_write(ring, 3); | |
193 | ||
a27de35c | 194 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
195 | |
196 | done: | |
197 | /* lower clocks again */ | |
198 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
199 | ||
200 | if (!r) | |
201 | DRM_INFO("UVD initialized successfully.\n"); | |
202 | ||
203 | return r; | |
204 | } | |
205 | ||
206 | /** | |
207 | * uvd_v4_2_hw_fini - stop the hardware block | |
208 | * | |
209 | * @adev: amdgpu_device pointer | |
210 | * | |
211 | * Stop the UVD block, mark ring as not ready any more | |
212 | */ | |
5fc3aeeb | 213 | static int uvd_v4_2_hw_fini(void *handle) |
a2e73f56 | 214 | { |
5fc3aeeb | 215 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
216 | struct amdgpu_ring *ring = &adev->uvd.ring; |
217 | ||
218 | uvd_v4_2_stop(adev); | |
219 | ring->ready = false; | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
5fc3aeeb | 224 | static int uvd_v4_2_suspend(void *handle) |
a2e73f56 AD |
225 | { |
226 | int r; | |
5fc3aeeb | 227 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 228 | |
3f99dd81 | 229 | r = uvd_v4_2_hw_fini(adev); |
a2e73f56 AD |
230 | if (r) |
231 | return r; | |
232 | ||
3f99dd81 | 233 | r = amdgpu_uvd_suspend(adev); |
a2e73f56 AD |
234 | if (r) |
235 | return r; | |
236 | ||
237 | return r; | |
238 | } | |
239 | ||
5fc3aeeb | 240 | static int uvd_v4_2_resume(void *handle) |
a2e73f56 AD |
241 | { |
242 | int r; | |
5fc3aeeb | 243 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
244 | |
245 | r = amdgpu_uvd_resume(adev); | |
246 | if (r) | |
247 | return r; | |
248 | ||
249 | r = uvd_v4_2_hw_init(adev); | |
250 | if (r) | |
251 | return r; | |
252 | ||
253 | return r; | |
254 | } | |
255 | ||
256 | /** | |
257 | * uvd_v4_2_start - start UVD block | |
258 | * | |
259 | * @adev: amdgpu_device pointer | |
260 | * | |
261 | * Setup and start the UVD block | |
262 | */ | |
263 | static int uvd_v4_2_start(struct amdgpu_device *adev) | |
264 | { | |
265 | struct amdgpu_ring *ring = &adev->uvd.ring; | |
266 | uint32_t rb_bufsz; | |
267 | int i, j, r; | |
268 | ||
269 | /* disable byte swapping */ | |
270 | u32 lmi_swap_cntl = 0; | |
271 | u32 mp_swap_cntl = 0; | |
272 | ||
273 | uvd_v4_2_mc_resume(adev); | |
274 | ||
275 | /* disable clock gating */ | |
276 | WREG32(mmUVD_CGC_GATE, 0); | |
277 | ||
278 | /* disable interupt */ | |
279 | WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); | |
280 | ||
281 | /* Stall UMC and register bus before resetting VCPU */ | |
282 | WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); | |
283 | mdelay(1); | |
284 | ||
285 | /* put LMI, VCPU, RBC etc... into reset */ | |
286 | WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | | |
287 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | | |
288 | UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | | |
289 | UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | | |
290 | UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); | |
291 | mdelay(5); | |
292 | ||
293 | /* take UVD block out of reset */ | |
294 | WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); | |
295 | mdelay(5); | |
296 | ||
297 | /* initialize UVD memory controller */ | |
298 | WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | | |
299 | (1 << 21) | (1 << 9) | (1 << 20)); | |
300 | ||
301 | #ifdef __BIG_ENDIAN | |
302 | /* swap (8 in 32) RB and IB */ | |
303 | lmi_swap_cntl = 0xa; | |
304 | mp_swap_cntl = 0; | |
305 | #endif | |
306 | WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); | |
307 | WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); | |
308 | ||
309 | WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); | |
310 | WREG32(mmUVD_MPC_SET_MUXA1, 0x0); | |
311 | WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); | |
312 | WREG32(mmUVD_MPC_SET_MUXB1, 0x0); | |
313 | WREG32(mmUVD_MPC_SET_ALU, 0); | |
314 | WREG32(mmUVD_MPC_SET_MUX, 0x88); | |
315 | ||
316 | /* take all subblocks out of reset, except VCPU */ | |
317 | WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
318 | mdelay(5); | |
319 | ||
320 | /* enable VCPU clock */ | |
321 | WREG32(mmUVD_VCPU_CNTL, 1 << 9); | |
322 | ||
323 | /* enable UMC */ | |
324 | WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); | |
325 | ||
326 | /* boot up the VCPU */ | |
327 | WREG32(mmUVD_SOFT_RESET, 0); | |
328 | mdelay(10); | |
329 | ||
330 | for (i = 0; i < 10; ++i) { | |
331 | uint32_t status; | |
332 | for (j = 0; j < 100; ++j) { | |
333 | status = RREG32(mmUVD_STATUS); | |
334 | if (status & 2) | |
335 | break; | |
336 | mdelay(10); | |
337 | } | |
338 | r = 0; | |
339 | if (status & 2) | |
340 | break; | |
341 | ||
342 | DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); | |
343 | WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, | |
344 | ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
345 | mdelay(10); | |
346 | WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
347 | mdelay(10); | |
348 | r = -1; | |
349 | } | |
350 | ||
351 | if (r) { | |
352 | DRM_ERROR("UVD not responding, giving up!!!\n"); | |
353 | return r; | |
354 | } | |
355 | ||
356 | /* enable interupt */ | |
357 | WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); | |
358 | ||
359 | /* force RBC into idle state */ | |
360 | WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); | |
361 | ||
362 | /* Set the write pointer delay */ | |
363 | WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); | |
364 | ||
365 | /* programm the 4GB memory segment for rptr and ring buffer */ | |
366 | WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | | |
367 | (0x7 << 16) | (0x1 << 31)); | |
368 | ||
369 | /* Initialize the ring buffer's read and write pointers */ | |
370 | WREG32(mmUVD_RBC_RB_RPTR, 0x0); | |
371 | ||
372 | ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); | |
373 | WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); | |
374 | ||
375 | /* set the ring address */ | |
376 | WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); | |
377 | ||
378 | /* Set ring buffer size */ | |
379 | rb_bufsz = order_base_2(ring->ring_size); | |
380 | rb_bufsz = (0x1 << 8) | rb_bufsz; | |
381 | WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | /** | |
387 | * uvd_v4_2_stop - stop UVD block | |
388 | * | |
389 | * @adev: amdgpu_device pointer | |
390 | * | |
391 | * stop the UVD block | |
392 | */ | |
393 | static void uvd_v4_2_stop(struct amdgpu_device *adev) | |
394 | { | |
395 | /* force RBC into idle state */ | |
396 | WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); | |
397 | ||
398 | /* Stall UMC and register bus before resetting VCPU */ | |
399 | WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); | |
400 | mdelay(1); | |
401 | ||
402 | /* put VCPU into reset */ | |
403 | WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
404 | mdelay(5); | |
405 | ||
406 | /* disable VCPU clock */ | |
407 | WREG32(mmUVD_VCPU_CNTL, 0x0); | |
408 | ||
409 | /* Unstall UMC and register bus */ | |
410 | WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); | |
411 | } | |
412 | ||
413 | /** | |
414 | * uvd_v4_2_ring_emit_fence - emit an fence & trap command | |
415 | * | |
416 | * @ring: amdgpu_ring pointer | |
417 | * @fence: fence to emit | |
418 | * | |
419 | * Write a fence and a trap command to the ring. | |
420 | */ | |
421 | static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 422 | unsigned flags) |
a2e73f56 | 423 | { |
890ee23f | 424 | WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); |
a2e73f56 AD |
425 | |
426 | amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); | |
427 | amdgpu_ring_write(ring, seq); | |
428 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); | |
429 | amdgpu_ring_write(ring, addr & 0xffffffff); | |
430 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); | |
431 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); | |
432 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); | |
433 | amdgpu_ring_write(ring, 0); | |
434 | ||
435 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); | |
436 | amdgpu_ring_write(ring, 0); | |
437 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); | |
438 | amdgpu_ring_write(ring, 0); | |
439 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); | |
440 | amdgpu_ring_write(ring, 2); | |
441 | } | |
442 | ||
d5b4e25d CK |
443 | /** |
444 | * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush | |
445 | * | |
446 | * @ring: amdgpu_ring pointer | |
447 | * | |
448 | * Emits an hdp flush. | |
449 | */ | |
450 | static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) | |
451 | { | |
452 | amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); | |
453 | amdgpu_ring_write(ring, 0); | |
454 | } | |
455 | ||
456 | /** | |
457 | * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate | |
458 | * | |
459 | * @ring: amdgpu_ring pointer | |
460 | * | |
461 | * Emits an hdp invalidate. | |
462 | */ | |
463 | static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) | |
464 | { | |
465 | amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); | |
466 | amdgpu_ring_write(ring, 1); | |
467 | } | |
468 | ||
a2e73f56 AD |
469 | /** |
470 | * uvd_v4_2_ring_test_ring - register write test | |
471 | * | |
472 | * @ring: amdgpu_ring pointer | |
473 | * | |
474 | * Test if we can successfully write to the context register | |
475 | */ | |
476 | static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) | |
477 | { | |
478 | struct amdgpu_device *adev = ring->adev; | |
479 | uint32_t tmp = 0; | |
480 | unsigned i; | |
481 | int r; | |
482 | ||
483 | WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); | |
a27de35c | 484 | r = amdgpu_ring_alloc(ring, 3); |
a2e73f56 AD |
485 | if (r) { |
486 | DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", | |
487 | ring->idx, r); | |
488 | return r; | |
489 | } | |
490 | amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); | |
491 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 492 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
493 | for (i = 0; i < adev->usec_timeout; i++) { |
494 | tmp = RREG32(mmUVD_CONTEXT_ID); | |
495 | if (tmp == 0xDEADBEEF) | |
496 | break; | |
497 | DRM_UDELAY(1); | |
498 | } | |
499 | ||
500 | if (i < adev->usec_timeout) { | |
501 | DRM_INFO("ring test on %d succeeded in %d usecs\n", | |
502 | ring->idx, i); | |
503 | } else { | |
504 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
505 | ring->idx, tmp); | |
506 | r = -EINVAL; | |
507 | } | |
508 | return r; | |
509 | } | |
510 | ||
511 | /** | |
512 | * uvd_v4_2_ring_emit_ib - execute indirect buffer | |
513 | * | |
514 | * @ring: amdgpu_ring pointer | |
515 | * @ib: indirect buffer to execute | |
516 | * | |
517 | * Write ring commands to execute the indirect buffer | |
518 | */ | |
519 | static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, | |
d88bf583 CK |
520 | struct amdgpu_ib *ib, |
521 | unsigned vm_id, bool ctx_switch) | |
a2e73f56 AD |
522 | { |
523 | amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); | |
524 | amdgpu_ring_write(ring, ib->gpu_addr); | |
525 | amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); | |
526 | amdgpu_ring_write(ring, ib->length_dw); | |
527 | } | |
528 | ||
529 | /** | |
530 | * uvd_v4_2_ring_test_ib - test ib execution | |
531 | * | |
532 | * @ring: amdgpu_ring pointer | |
533 | * | |
534 | * Test if we can successfully execute an IB | |
535 | */ | |
536 | static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring) | |
537 | { | |
538 | struct amdgpu_device *adev = ring->adev; | |
0e3f154a | 539 | struct fence *fence = NULL; |
a2e73f56 AD |
540 | int r; |
541 | ||
542 | r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
543 | if (r) { | |
544 | DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); | |
545 | return r; | |
546 | } | |
547 | ||
548 | r = amdgpu_uvd_get_create_msg(ring, 1, NULL); | |
549 | if (r) { | |
550 | DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); | |
551 | goto error; | |
552 | } | |
553 | ||
d7af97db | 554 | r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); |
a2e73f56 AD |
555 | if (r) { |
556 | DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); | |
557 | goto error; | |
558 | } | |
559 | ||
0e3f154a | 560 | r = fence_wait(fence, false); |
a2e73f56 AD |
561 | if (r) { |
562 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); | |
563 | goto error; | |
564 | } | |
565 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); | |
566 | error: | |
0e3f154a | 567 | fence_put(fence); |
a2e73f56 AD |
568 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); |
569 | return r; | |
570 | } | |
571 | ||
572 | /** | |
573 | * uvd_v4_2_mc_resume - memory controller programming | |
574 | * | |
575 | * @adev: amdgpu_device pointer | |
576 | * | |
577 | * Let the UVD memory controller know it's offsets | |
578 | */ | |
579 | static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) | |
580 | { | |
581 | uint64_t addr; | |
582 | uint32_t size; | |
583 | ||
584 | /* programm the VCPU memory controller bits 0-27 */ | |
585 | addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; | |
586 | size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; | |
587 | WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); | |
588 | WREG32(mmUVD_VCPU_CACHE_SIZE0, size); | |
589 | ||
590 | addr += size; | |
c0365541 | 591 | size = AMDGPU_UVD_HEAP_SIZE >> 3; |
a2e73f56 AD |
592 | WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); |
593 | WREG32(mmUVD_VCPU_CACHE_SIZE1, size); | |
594 | ||
595 | addr += size; | |
c0365541 AN |
596 | size = (AMDGPU_UVD_STACK_SIZE + |
597 | (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; | |
a2e73f56 AD |
598 | WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); |
599 | WREG32(mmUVD_VCPU_CACHE_SIZE2, size); | |
600 | ||
601 | /* bits 28-31 */ | |
602 | addr = (adev->uvd.gpu_addr >> 28) & 0xF; | |
603 | WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); | |
604 | ||
605 | /* bits 32-39 */ | |
606 | addr = (adev->uvd.gpu_addr >> 32) & 0xFF; | |
607 | WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); | |
608 | ||
76ed6cb0 AD |
609 | WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); |
610 | WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); | |
611 | WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); | |
612 | ||
a2e73f56 AD |
613 | uvd_v4_2_init_cg(adev); |
614 | } | |
615 | ||
616 | static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, | |
617 | bool enable) | |
618 | { | |
619 | u32 orig, data; | |
620 | ||
e3b04bc7 | 621 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { |
a2e73f56 AD |
622 | data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); |
623 | data = 0xfff; | |
624 | WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); | |
625 | ||
626 | orig = data = RREG32(mmUVD_CGC_CTRL); | |
627 | data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; | |
628 | if (orig != data) | |
629 | WREG32(mmUVD_CGC_CTRL, data); | |
630 | } else { | |
631 | data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); | |
632 | data &= ~0xfff; | |
633 | WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); | |
634 | ||
635 | orig = data = RREG32(mmUVD_CGC_CTRL); | |
636 | data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; | |
637 | if (orig != data) | |
638 | WREG32(mmUVD_CGC_CTRL, data); | |
639 | } | |
640 | } | |
641 | ||
642 | static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, | |
643 | bool sw_mode) | |
644 | { | |
645 | u32 tmp, tmp2; | |
646 | ||
647 | tmp = RREG32(mmUVD_CGC_CTRL); | |
648 | tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); | |
649 | tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | | |
650 | (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | | |
651 | (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); | |
652 | ||
653 | if (sw_mode) { | |
654 | tmp &= ~0x7ffff800; | |
655 | tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | | |
656 | UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | | |
657 | (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); | |
658 | } else { | |
659 | tmp |= 0x7ffff800; | |
660 | tmp2 = 0; | |
661 | } | |
662 | ||
663 | WREG32(mmUVD_CGC_CTRL, tmp); | |
664 | WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); | |
665 | } | |
666 | ||
667 | static void uvd_v4_2_init_cg(struct amdgpu_device *adev) | |
668 | { | |
669 | bool hw_mode = true; | |
670 | ||
671 | if (hw_mode) { | |
672 | uvd_v4_2_set_dcm(adev, false); | |
673 | } else { | |
674 | u32 tmp = RREG32(mmUVD_CGC_CTRL); | |
675 | tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; | |
676 | WREG32(mmUVD_CGC_CTRL, tmp); | |
677 | } | |
678 | } | |
679 | ||
5fc3aeeb | 680 | static bool uvd_v4_2_is_idle(void *handle) |
a2e73f56 | 681 | { |
5fc3aeeb | 682 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
683 | ||
a2e73f56 AD |
684 | return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); |
685 | } | |
686 | ||
5fc3aeeb | 687 | static int uvd_v4_2_wait_for_idle(void *handle) |
a2e73f56 AD |
688 | { |
689 | unsigned i; | |
5fc3aeeb | 690 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
691 | |
692 | for (i = 0; i < adev->usec_timeout; i++) { | |
693 | if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) | |
694 | return 0; | |
695 | } | |
696 | return -ETIMEDOUT; | |
697 | } | |
698 | ||
5fc3aeeb | 699 | static int uvd_v4_2_soft_reset(void *handle) |
a2e73f56 | 700 | { |
5fc3aeeb | 701 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
702 | ||
a2e73f56 AD |
703 | uvd_v4_2_stop(adev); |
704 | ||
705 | WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, | |
706 | ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); | |
707 | mdelay(5); | |
708 | ||
709 | return uvd_v4_2_start(adev); | |
710 | } | |
711 | ||
a2e73f56 AD |
712 | static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, |
713 | struct amdgpu_irq_src *source, | |
714 | unsigned type, | |
715 | enum amdgpu_interrupt_state state) | |
716 | { | |
717 | // TODO | |
718 | return 0; | |
719 | } | |
720 | ||
721 | static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, | |
722 | struct amdgpu_irq_src *source, | |
723 | struct amdgpu_iv_entry *entry) | |
724 | { | |
725 | DRM_DEBUG("IH: UVD TRAP\n"); | |
726 | amdgpu_fence_process(&adev->uvd.ring); | |
727 | return 0; | |
728 | } | |
729 | ||
5fc3aeeb | 730 | static int uvd_v4_2_set_clockgating_state(void *handle, |
731 | enum amd_clockgating_state state) | |
a2e73f56 AD |
732 | { |
733 | bool gate = false; | |
5fc3aeeb | 734 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 735 | |
e3b04bc7 | 736 | if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) |
35e5912d AD |
737 | return 0; |
738 | ||
5fc3aeeb | 739 | if (state == AMD_CG_STATE_GATE) |
a2e73f56 AD |
740 | gate = true; |
741 | ||
742 | uvd_v4_2_enable_mgcg(adev, gate); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
5fc3aeeb | 747 | static int uvd_v4_2_set_powergating_state(void *handle, |
748 | enum amd_powergating_state state) | |
a2e73f56 AD |
749 | { |
750 | /* This doesn't actually powergate the UVD block. | |
751 | * That's done in the dpm code via the SMC. This | |
752 | * just re-inits the block as necessary. The actual | |
753 | * gating still happens in the dpm code. We should | |
754 | * revisit this when there is a cleaner line between | |
755 | * the smc and the hw blocks | |
756 | */ | |
b6df77fc AD |
757 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
758 | ||
e3b04bc7 | 759 | if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) |
b6df77fc | 760 | return 0; |
5fc3aeeb | 761 | |
762 | if (state == AMD_PG_STATE_GATE) { | |
a2e73f56 AD |
763 | uvd_v4_2_stop(adev); |
764 | return 0; | |
765 | } else { | |
766 | return uvd_v4_2_start(adev); | |
767 | } | |
768 | } | |
769 | ||
5fc3aeeb | 770 | const struct amd_ip_funcs uvd_v4_2_ip_funcs = { |
88a907d6 | 771 | .name = "uvd_v4_2", |
a2e73f56 AD |
772 | .early_init = uvd_v4_2_early_init, |
773 | .late_init = NULL, | |
774 | .sw_init = uvd_v4_2_sw_init, | |
775 | .sw_fini = uvd_v4_2_sw_fini, | |
776 | .hw_init = uvd_v4_2_hw_init, | |
777 | .hw_fini = uvd_v4_2_hw_fini, | |
778 | .suspend = uvd_v4_2_suspend, | |
779 | .resume = uvd_v4_2_resume, | |
780 | .is_idle = uvd_v4_2_is_idle, | |
781 | .wait_for_idle = uvd_v4_2_wait_for_idle, | |
782 | .soft_reset = uvd_v4_2_soft_reset, | |
a2e73f56 AD |
783 | .set_clockgating_state = uvd_v4_2_set_clockgating_state, |
784 | .set_powergating_state = uvd_v4_2_set_powergating_state, | |
785 | }; | |
786 | ||
787 | static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { | |
788 | .get_rptr = uvd_v4_2_ring_get_rptr, | |
789 | .get_wptr = uvd_v4_2_ring_get_wptr, | |
790 | .set_wptr = uvd_v4_2_ring_set_wptr, | |
791 | .parse_cs = amdgpu_uvd_ring_parse_cs, | |
792 | .emit_ib = uvd_v4_2_ring_emit_ib, | |
793 | .emit_fence = uvd_v4_2_ring_emit_fence, | |
d5b4e25d CK |
794 | .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, |
795 | .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, | |
a2e73f56 AD |
796 | .test_ring = uvd_v4_2_ring_test_ring, |
797 | .test_ib = uvd_v4_2_ring_test_ib, | |
edff0e28 | 798 | .insert_nop = amdgpu_ring_insert_nop, |
9e5d5309 | 799 | .pad_ib = amdgpu_ring_generic_pad_ib, |
a2e73f56 AD |
800 | }; |
801 | ||
802 | static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) | |
803 | { | |
804 | adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; | |
805 | } | |
806 | ||
807 | static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { | |
808 | .set = uvd_v4_2_set_interrupt_state, | |
809 | .process = uvd_v4_2_process_interrupt, | |
810 | }; | |
811 | ||
812 | static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) | |
813 | { | |
814 | adev->uvd.irq.num_types = 1; | |
815 | adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; | |
816 | } |