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a22fc854 BG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include "kfd_device_queue_manager.h" | |
25 | #include "cik_regs.h" | |
26 | ||
27 | static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, | |
28 | struct qcm_process_device *qpd, | |
29 | enum cache_policy default_policy, | |
30 | enum cache_policy alternate_policy, | |
31 | void __user *alternate_aperture_base, | |
32 | uint64_t alternate_aperture_size); | |
33 | static int register_process_cik(struct device_queue_manager *dqm, | |
34 | struct qcm_process_device *qpd); | |
35 | static int initialize_cpsch_cik(struct device_queue_manager *dqm); | |
3e3f6e1a OG |
36 | static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, |
37 | struct qcm_process_device *qpd); | |
a22fc854 | 38 | |
d42af779 | 39 | void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops) |
a22fc854 BG |
40 | { |
41 | ops->set_cache_memory_policy = set_cache_memory_policy_cik; | |
42 | ops->register_process = register_process_cik; | |
43 | ops->initialize = initialize_cpsch_cik; | |
3e3f6e1a | 44 | ops->init_sdma_vm = init_sdma_vm; |
a22fc854 BG |
45 | } |
46 | ||
47 | static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) | |
48 | { | |
49 | /* In 64-bit mode, we can only control the top 3 bits of the LDS, | |
50 | * scratch and GPUVM apertures. | |
51 | * The hardware fills in the remaining 59 bits according to the | |
52 | * following pattern: | |
53 | * LDS: X0000000'00000000 - X0000001'00000000 (4GB) | |
54 | * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) | |
55 | * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) | |
56 | * | |
57 | * (where X/Y is the configurable nybble with the low-bit 0) | |
58 | * | |
59 | * LDS and scratch will have the same top nybble programmed in the | |
60 | * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. | |
61 | * GPUVM can have a different top nybble programmed in the | |
62 | * top 3 bits of SH_MEM_BASES.SHARED_BASE. | |
63 | * We don't bother to support different top nybbles | |
64 | * for LDS/Scratch and GPUVM. | |
65 | */ | |
66 | ||
67 | BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || | |
68 | top_address_nybble == 0); | |
69 | ||
70 | return PRIVATE_BASE(top_address_nybble << 12) | | |
71 | SHARED_BASE(top_address_nybble << 12); | |
72 | } | |
73 | ||
74 | static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, | |
75 | struct qcm_process_device *qpd, | |
76 | enum cache_policy default_policy, | |
77 | enum cache_policy alternate_policy, | |
78 | void __user *alternate_aperture_base, | |
79 | uint64_t alternate_aperture_size) | |
80 | { | |
81 | uint32_t default_mtype; | |
82 | uint32_t ape1_mtype; | |
83 | ||
84 | default_mtype = (default_policy == cache_policy_coherent) ? | |
85 | MTYPE_NONCACHED : | |
86 | MTYPE_CACHED; | |
87 | ||
88 | ape1_mtype = (alternate_policy == cache_policy_coherent) ? | |
89 | MTYPE_NONCACHED : | |
90 | MTYPE_CACHED; | |
91 | ||
92 | qpd->sh_mem_config = (qpd->sh_mem_config & PTR32) | |
93 | | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | |
94 | | DEFAULT_MTYPE(default_mtype) | |
95 | | APE1_MTYPE(ape1_mtype); | |
96 | ||
97 | return true; | |
98 | } | |
99 | ||
100 | static int register_process_cik(struct device_queue_manager *dqm, | |
101 | struct qcm_process_device *qpd) | |
102 | { | |
103 | struct kfd_process_device *pdd; | |
104 | unsigned int temp; | |
105 | ||
106 | BUG_ON(!dqm || !qpd); | |
107 | ||
108 | pdd = qpd_to_pdd(qpd); | |
109 | ||
110 | /* check if sh_mem_config register already configured */ | |
111 | if (qpd->sh_mem_config == 0) { | |
112 | qpd->sh_mem_config = | |
113 | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | | |
114 | DEFAULT_MTYPE(MTYPE_NONCACHED) | | |
115 | APE1_MTYPE(MTYPE_NONCACHED); | |
116 | qpd->sh_mem_ape1_limit = 0; | |
117 | qpd->sh_mem_ape1_base = 0; | |
118 | } | |
119 | ||
120 | if (qpd->pqm->process->is_32bit_user_mode) { | |
121 | temp = get_sh_mem_bases_32(pdd); | |
122 | qpd->sh_mem_bases = SHARED_BASE(temp); | |
123 | qpd->sh_mem_config |= PTR32; | |
124 | } else { | |
125 | temp = get_sh_mem_bases_nybble_64(pdd); | |
126 | qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); | |
127 | } | |
128 | ||
129 | pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", | |
130 | qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
3e3f6e1a OG |
135 | static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, |
136 | struct qcm_process_device *qpd) | |
137 | { | |
138 | uint32_t value = SDMA_ATC; | |
139 | ||
140 | if (q->process->is_32bit_user_mode) | |
141 | value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd)); | |
142 | else | |
143 | value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64( | |
144 | qpd_to_pdd(qpd))); | |
145 | q->properties.sdma_vm_addr = value; | |
146 | } | |
147 | ||
a22fc854 BG |
148 | static int initialize_cpsch_cik(struct device_queue_manager *dqm) |
149 | { | |
1365aa62 | 150 | return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm)); |
a22fc854 | 151 | } |