projects / deliverable / linux.git / blame
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| 2d8f1f33 BG |
1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef F32_MES_PM4_PACKETS_H | |
| 25 | #define F32_MES_PM4_PACKETS_H | |
| 26 | ||
| 27 | #ifndef PM4_MES_HEADER_DEFINED | |
| 28 | #define PM4_MES_HEADER_DEFINED | |
| 29 | union PM4_MES_TYPE_3_HEADER { | |
| 30 | struct { | |
| 31 | uint32_t reserved1 : 8; /* < reserved */ | |
| 32 | uint32_t opcode : 8; /* < IT opcode */ | |
| 33 | uint32_t count : 14;/* < number of DWORDs - 1 in the | |
| 34 | information body. */ | |
| 35 | uint32_t type : 2; /* < packet identifier. | |
| 36 | It should be 3 for type 3 packets */ | |
| 37 | }; | |
| 38 | uint32_t u32All; | |
| 39 | }; | |
| 40 | #endif /* PM4_MES_HEADER_DEFINED */ | |
| 41 | ||
| 42 | /*--------------------MES_SET_RESOURCES--------------------*/ | |
| 43 | ||
| 44 | #ifndef PM4_MES_SET_RESOURCES_DEFINED | |
| 45 | #define PM4_MES_SET_RESOURCES_DEFINED | |
| 46 | enum mes_set_resources_queue_type_enum { | |
| 47 | queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, | |
| 48 | queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, | |
| 49 | queue_type__mes_set_resources__hsa_debug_interface_queue = 4 | |
| 50 | }; | |
| 51 | ||
| 52 | ||
| 53 | struct pm4_mes_set_resources { | |
| 54 | union { | |
| 55 | union PM4_MES_TYPE_3_HEADER header; /* header */ | |
| 56 | uint32_t ordinal1; | |
| 57 | }; | |
| 58 | ||
| 59 | union { | |
| 60 | struct { | |
| 61 | uint32_t vmid_mask:16; | |
| 62 | uint32_t unmap_latency:8; | |
| 63 | uint32_t reserved1:5; | |
| 64 | enum mes_set_resources_queue_type_enum queue_type:3; | |
| 65 | } bitfields2; | |
| 66 | uint32_t ordinal2; | |
| 67 | }; | |
| 68 | ||
| 69 | uint32_t queue_mask_lo; | |
| 70 | uint32_t queue_mask_hi; | |
| 71 | uint32_t gws_mask_lo; | |
| 72 | uint32_t gws_mask_hi; | |
| 73 | ||
| 74 | union { | |
| 75 | struct { | |
| 76 | uint32_t oac_mask:16; | |
| 77 | uint32_t reserved2:16; | |
| 78 | } bitfields7; | |
| 79 | uint32_t ordinal7; | |
| 80 | }; | |
| 81 | ||
| 82 | union { | |
| 83 | struct { | |
| 84 | uint32_t gds_heap_base:6; | |
| 85 | uint32_t reserved3:5; | |
| 86 | uint32_t gds_heap_size:6; | |
| 87 | uint32_t reserved4:15; | |
| 88 | } bitfields8; | |
| 89 | uint32_t ordinal8; | |
| 90 | }; | |
| 91 | ||
| 92 | }; | |
| 93 | #endif | |
| 94 | ||
| 95 | /*--------------------MES_RUN_LIST--------------------*/ | |
| 96 | ||
| 97 | #ifndef PM4_MES_RUN_LIST_DEFINED | |
| 98 | #define PM4_MES_RUN_LIST_DEFINED | |
| 99 | ||
| 100 | struct pm4_mes_runlist { | |
| 101 | union { | |
| 102 | union PM4_MES_TYPE_3_HEADER header; /* header */ | |
| 103 | uint32_t ordinal1; | |
| 104 | }; | |
| 105 | ||
| 106 | union { | |
| 107 | struct { | |
| 108 | uint32_t reserved1:2; | |
| 109 | uint32_t ib_base_lo:30; | |
| 110 | } bitfields2; | |
| 111 | uint32_t ordinal2; | |
| 112 | }; | |
| 113 | ||
| 114 | union { | |
| 115 | struct { | |
| 116 | uint32_t ib_base_hi:16; | |
| 117 | uint32_t reserved2:16; | |
| 118 | } bitfields3; | |
| 119 | uint32_t ordinal3; | |
| 120 | }; | |
| 121 | ||
| 122 | union { | |
| 123 | struct { | |
| 124 | uint32_t ib_size:20; | |
| 125 | uint32_t chain:1; | |
| 126 | uint32_t offload_polling:1; | |
| 127 | uint32_t reserved3:1; | |
| 128 | uint32_t valid:1; | |
| 129 | uint32_t reserved4:8; | |
| 130 | } bitfields4; | |
| 131 | uint32_t ordinal4; | |
| 132 | }; | |
| 133 | ||
| 134 | }; | |
| 135 | #endif | |
| 136 | ||
| 137 | /*--------------------MES_MAP_PROCESS--------------------*/ | |
| 138 | ||
| 139 | #ifndef PM4_MES_MAP_PROCESS_DEFINED | |
| 140 | #define PM4_MES_MAP_PROCESS_DEFINED | |
| 141 | ||
| 142 | struct pm4_mes_map_process { | |
| 143 | union { | |
| 144 | union PM4_MES_TYPE_3_HEADER header; /* header */ | |
| 145 | uint32_t ordinal1; | |
| 146 | }; | |
| 147 | ||
| 148 | union { | |
| 149 | struct { | |
| 150 | uint32_t pasid:16; | |
| 151 | uint32_t reserved1:8; | |
| 152 | uint32_t diq_enable:1; | |
| 153 | uint32_t process_quantum:7; | |
| 154 | } bitfields2; | |
| 155 | uint32_t ordinal2; | |
| 156 | }; | |
| 157 | ||
| 158 | union { | |
| 159 | struct { | |
| 160 | uint32_t page_table_base:28; | |
| 161 | uint32_t reserved2:4; | |
| 162 | } bitfields3; | |
| 163 | uint32_t ordinal3; | |
| 164 | }; | |
| 165 | ||
| 166 | uint32_t sh_mem_bases; | |
| 167 | uint32_t sh_mem_ape1_base; | |
| 168 | uint32_t sh_mem_ape1_limit; | |
| 169 | uint32_t sh_mem_config; | |
| 170 | uint32_t gds_addr_lo; | |
| 171 | uint32_t gds_addr_hi; | |
| 172 | ||
| 173 | union { | |
| 174 | struct { | |
| 175 | uint32_t num_gws:6; | |
| 176 | uint32_t reserved3:2; | |
| 177 | uint32_t num_oac:4; | |
| 178 | uint32_t reserved4:4; | |
| 179 | uint32_t gds_size:6; | |
| 180 | uint32_t num_queues:10; | |
| 181 | } bitfields10; | |
| 182 | uint32_t ordinal10; | |
| 183 | }; | |
| 184 | ||
| 185 | }; | |
| 186 | #endif | |
| 187 | ||
| 188 | /*--------------------MES_MAP_QUEUES--------------------*/ | |
| 189 | ||
| 190 | #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED | |
| 191 | #define PM4_MES_MAP_QUEUES_VI_DEFINED | |
| 192 | enum mes_map_queues_queue_sel_vi_enum { | |
| 193 | queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, | |
| 194 | queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 | |
| 195 | }; | |
| 196 | ||
| 197 | enum mes_map_queues_queue_type_vi_enum { | |
| 198 | queue_type__mes_map_queues__normal_compute_vi = 0, | |
| 199 | queue_type__mes_map_queues__debug_interface_queue_vi = 1, | |
| 200 | queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, | |
| 201 | queue_type__mes_map_queues__low_latency_static_queue_vi = 3 | |
| 202 | }; | |
| 203 | ||
| 204 | enum mes_map_queues_alloc_format_vi_enum { | |
| 205 | alloc_format__mes_map_queues__one_per_pipe_vi = 0, | |
| 206 | alloc_format__mes_map_queues__all_on_one_pipe_vi = 1 | |
| 207 | }; | |
| 208 | ||
| 209 | enum mes_map_queues_engine_sel_vi_enum { | |
| 210 | engine_sel__mes_map_queues__compute_vi = 0, | |
| 211 | engine_sel__mes_map_queues__sdma0_vi = 2, | |
| 212 | engine_sel__mes_map_queues__sdma1_vi = 3 | |
| 213 | }; | |
| 214 | ||
| 215 | ||
| 216 | struct pm4_mes_map_queues { | |
| 217 | union { | |
| 218 | union PM4_MES_TYPE_3_HEADER header; /* header */ | |
| 219 | uint32_t ordinal1; | |
| 220 | }; | |
| 221 | ||
| 222 | union { | |
| 223 | struct { | |
| 224 | uint32_t reserved1:4; | |
| 225 | enum mes_map_queues_queue_sel_vi_enum queue_sel:2; | |
| 226 | uint32_t reserved2:15; | |
| 227 | enum mes_map_queues_queue_type_vi_enum queue_type:3; | |
| 228 | enum mes_map_queues_alloc_format_vi_enum alloc_format:2; | |
| 229 | enum mes_map_queues_engine_sel_vi_enum engine_sel:3; | |
| 230 | uint32_t num_queues:3; | |
| 231 | } bitfields2; | |
| 232 | uint32_t ordinal2; | |
| 233 | }; | |
| 234 | ||
| 235 | union { | |
| 236 | struct { | |
| 237 | uint32_t reserved3:1; | |
| 238 | uint32_t check_disable:1; | |
| 239 | uint32_t doorbell_offset:21; | |
| 240 | uint32_t reserved4:3; | |
| 241 | uint32_t queue:6; | |
| 242 | } bitfields3; | |
| 243 | uint32_t ordinal3; | |
| 244 | }; | |
| 245 | ||
| 246 | uint32_t mqd_addr_lo; | |
| 247 | uint32_t mqd_addr_hi; | |
| 248 | uint32_t wptr_addr_lo; | |
| 249 | uint32_t wptr_addr_hi; | |
| 250 | }; | |
| 251 | #endif | |
| 252 | ||
| 253 | /*--------------------MES_QUERY_STATUS--------------------*/ | |
| 254 | ||
| 255 | #ifndef PM4_MES_QUERY_STATUS_DEFINED | |
| 256 | #define PM4_MES_QUERY_STATUS_DEFINED | |
| 257 | enum mes_query_status_interrupt_sel_enum { | |
| 258 | interrupt_sel__mes_query_status__completion_status = 0, | |
| 259 | interrupt_sel__mes_query_status__process_status = 1, | |
| 260 | interrupt_sel__mes_query_status__queue_status = 2 | |
| 261 | }; | |
| 262 | ||
| 263 | enum mes_query_status_command_enum { | |
| 264 | command__mes_query_status__interrupt_only = 0, | |
| 265 | command__mes_query_status__fence_only_immediate = 1, | |
| 266 | command__mes_query_status__fence_only_after_write_ack = 2, | |
| 267 | command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 | |
| 268 | }; | |
| 269 | ||
| 270 | enum mes_query_status_engine_sel_enum { | |
| 271 | engine_sel__mes_query_status__compute = 0, | |
| 272 | engine_sel__mes_query_status__sdma0_queue = 2, | |
| 273 | engine_sel__mes_query_status__sdma1_queue = 3 | |
| 274 | }; | |
| 275 | ||
| 276 | struct pm4_mes_query_status { | |
| 277 | union { | |
| 278 | union PM4_MES_TYPE_3_HEADER header; /* header */ | |
| 279 | uint32_t ordinal1; | |
| 280 | }; | |
| 281 | ||
| 282 | union { | |
| 283 | struct { | |
| 284 | uint32_t context_id:28; | |
| 285 | enum mes_query_status_interrupt_sel_enum | |
| 286 | interrupt_sel:2; | |
| 287 | enum mes_query_status_command_enum command:2; | |
| 288 | } bitfields2; | |
| 289 | uint32_t ordinal2; | |
| 290 | }; | |
| 291 | ||
| 292 | union { | |
| 293 | struct { | |
| 294 | uint32_t pasid:16; | |
| 295 | uint32_t reserved1:16; | |
| 296 | } bitfields3a; | |
| 297 | struct { | |
| 298 | uint32_t reserved2:2; | |
| 299 | uint32_t doorbell_offset:21; | |
| 300 | uint32_t reserved3:2; | |
| 301 | enum mes_query_status_engine_sel_enum engine_sel:3; | |
| 302 | uint32_t reserved4:4; | |
| 303 | } bitfields3b; | |
| 304 | uint32_t ordinal3; | |
| 305 | }; | |
| 306 | ||
| 307 | uint32_t addr_lo; | |
| 308 | uint32_t addr_hi; | |
| 309 | uint32_t data_lo; | |
| 310 | uint32_t data_hi; | |
| 311 | }; | |
| 312 | #endif | |
| 313 | ||
| 314 | /*--------------------MES_UNMAP_QUEUES--------------------*/ | |
| 315 | ||
| 316 | #ifndef PM4_MES_UNMAP_QUEUES_DEFINED | |
| 317 | #define PM4_MES_UNMAP_QUEUES_DEFINED | |
| 318 | enum mes_unmap_queues_action_enum { | |
| 319 | action__mes_unmap_queues__preempt_queues = 0, | |
| 320 | action__mes_unmap_queues__reset_queues = 1, | |
| 321 | action__mes_unmap_queues__disable_process_queues = 2, | |
| 322 | action__mes_unmap_queues__reserved = 3 | |
| 323 | }; | |
| 324 | ||
| 325 | enum mes_unmap_queues_queue_sel_enum { | |
| 326 | queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, | |
| 327 | queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, | |
| 328 | queue_sel__mes_unmap_queues__unmap_all_queues = 2, | |
| 329 | queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 | |
| 330 | }; | |
| 331 | ||
| 332 | enum mes_unmap_queues_engine_sel_enum { | |
| 333 | engine_sel__mes_unmap_queues__compute = 0, | |
| 334 | engine_sel__mes_unmap_queues__sdma0 = 2, | |
| 335 | engine_sel__mes_unmap_queues__sdmal = 3 | |
| 336 | }; | |
| 337 | ||
| 338 | struct PM4_MES_UNMAP_QUEUES { | |
| 339 | union { | |
| 340 | union PM4_MES_TYPE_3_HEADER header; /* header */ | |
| 341 | uint32_t ordinal1; | |
| 342 | }; | |
| 343 | ||
| 344 | union { | |
| 345 | struct { | |
| 346 | enum mes_unmap_queues_action_enum action:2; | |
| 347 | uint32_t reserved1:2; | |
| 348 | enum mes_unmap_queues_queue_sel_enum queue_sel:2; | |
| 349 | uint32_t reserved2:20; | |
| 350 | enum mes_unmap_queues_engine_sel_enum engine_sel:3; | |
| 351 | uint32_t num_queues:3; | |
| 352 | } bitfields2; | |
| 353 | uint32_t ordinal2; | |
| 354 | }; | |
| 355 | ||
| 356 | union { | |
| 357 | struct { | |
| 358 | uint32_t pasid:16; | |
| 359 | uint32_t reserved3:16; | |
| 360 | } bitfields3a; | |
| 361 | struct { | |
| 362 | uint32_t reserved4:2; | |
| 363 | uint32_t doorbell_offset0:21; | |
| 364 | uint32_t reserved5:9; | |
| 365 | } bitfields3b; | |
| 366 | uint32_t ordinal3; | |
| 367 | }; | |
| 368 | ||
| 369 | union { | |
| 370 | struct { | |
| 371 | uint32_t reserved6:2; | |
| 372 | uint32_t doorbell_offset1:21; | |
| 373 | uint32_t reserved7:9; | |
| 374 | } bitfields4; | |
| 375 | uint32_t ordinal4; | |
| 376 | }; | |
| 377 | ||
| 378 | union { | |
| 379 | struct { | |
| 380 | uint32_t reserved8:2; | |
| 381 | uint32_t doorbell_offset2:21; | |
| 382 | uint32_t reserved9:9; | |
| 383 | } bitfields5; | |
| 384 | uint32_t ordinal5; | |
| 385 | }; | |
| 386 | ||
| 387 | union { | |
| 388 | struct { | |
| 389 | uint32_t reserved10:2; | |
| 390 | uint32_t doorbell_offset3:21; | |
| 391 | uint32_t reserved11:9; | |
| 392 | } bitfields6; | |
| 393 | uint32_t ordinal6; | |
| 394 | }; | |
| 395 | }; | |
| 396 | #endif | |
| 397 | ||
| 398 | #endif |