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1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #ifndef CIK_STRUCTS_H_ | |
25 | #define CIK_STRUCTS_H_ | |
26 | ||
27 | struct cik_mqd { | |
28 | uint32_t header; | |
29 | uint32_t compute_dispatch_initiator; | |
30 | uint32_t compute_dim_x; | |
31 | uint32_t compute_dim_y; | |
32 | uint32_t compute_dim_z; | |
33 | uint32_t compute_start_x; | |
34 | uint32_t compute_start_y; | |
35 | uint32_t compute_start_z; | |
36 | uint32_t compute_num_thread_x; | |
37 | uint32_t compute_num_thread_y; | |
38 | uint32_t compute_num_thread_z; | |
39 | uint32_t compute_pipelinestat_enable; | |
40 | uint32_t compute_perfcount_enable; | |
41 | uint32_t compute_pgm_lo; | |
42 | uint32_t compute_pgm_hi; | |
43 | uint32_t compute_tba_lo; | |
44 | uint32_t compute_tba_hi; | |
45 | uint32_t compute_tma_lo; | |
46 | uint32_t compute_tma_hi; | |
47 | uint32_t compute_pgm_rsrc1; | |
48 | uint32_t compute_pgm_rsrc2; | |
49 | uint32_t compute_vmid; | |
50 | uint32_t compute_resource_limits; | |
51 | uint32_t compute_static_thread_mgmt_se0; | |
52 | uint32_t compute_static_thread_mgmt_se1; | |
53 | uint32_t compute_tmpring_size; | |
54 | uint32_t compute_static_thread_mgmt_se2; | |
55 | uint32_t compute_static_thread_mgmt_se3; | |
56 | uint32_t compute_restart_x; | |
57 | uint32_t compute_restart_y; | |
58 | uint32_t compute_restart_z; | |
59 | uint32_t compute_thread_trace_enable; | |
60 | uint32_t compute_misc_reserved; | |
61 | uint32_t compute_user_data_0; | |
62 | uint32_t compute_user_data_1; | |
63 | uint32_t compute_user_data_2; | |
64 | uint32_t compute_user_data_3; | |
65 | uint32_t compute_user_data_4; | |
66 | uint32_t compute_user_data_5; | |
67 | uint32_t compute_user_data_6; | |
68 | uint32_t compute_user_data_7; | |
69 | uint32_t compute_user_data_8; | |
70 | uint32_t compute_user_data_9; | |
71 | uint32_t compute_user_data_10; | |
72 | uint32_t compute_user_data_11; | |
73 | uint32_t compute_user_data_12; | |
74 | uint32_t compute_user_data_13; | |
75 | uint32_t compute_user_data_14; | |
76 | uint32_t compute_user_data_15; | |
77 | uint32_t cp_compute_csinvoc_count_lo; | |
78 | uint32_t cp_compute_csinvoc_count_hi; | |
79 | uint32_t cp_mqd_base_addr_lo; | |
80 | uint32_t cp_mqd_base_addr_hi; | |
81 | uint32_t cp_hqd_active; | |
82 | uint32_t cp_hqd_vmid; | |
83 | uint32_t cp_hqd_persistent_state; | |
84 | uint32_t cp_hqd_pipe_priority; | |
85 | uint32_t cp_hqd_queue_priority; | |
86 | uint32_t cp_hqd_quantum; | |
87 | uint32_t cp_hqd_pq_base_lo; | |
88 | uint32_t cp_hqd_pq_base_hi; | |
89 | uint32_t cp_hqd_pq_rptr; | |
90 | uint32_t cp_hqd_pq_rptr_report_addr_lo; | |
91 | uint32_t cp_hqd_pq_rptr_report_addr_hi; | |
92 | uint32_t cp_hqd_pq_wptr_poll_addr_lo; | |
93 | uint32_t cp_hqd_pq_wptr_poll_addr_hi; | |
94 | uint32_t cp_hqd_pq_doorbell_control; | |
95 | uint32_t cp_hqd_pq_wptr; | |
96 | uint32_t cp_hqd_pq_control; | |
97 | uint32_t cp_hqd_ib_base_addr_lo; | |
98 | uint32_t cp_hqd_ib_base_addr_hi; | |
99 | uint32_t cp_hqd_ib_rptr; | |
100 | uint32_t cp_hqd_ib_control; | |
101 | uint32_t cp_hqd_iq_timer; | |
102 | uint32_t cp_hqd_iq_rptr; | |
103 | uint32_t cp_hqd_dequeue_request; | |
104 | uint32_t cp_hqd_dma_offload; | |
105 | uint32_t cp_hqd_sema_cmd; | |
106 | uint32_t cp_hqd_msg_type; | |
107 | uint32_t cp_hqd_atomic0_preop_lo; | |
108 | uint32_t cp_hqd_atomic0_preop_hi; | |
109 | uint32_t cp_hqd_atomic1_preop_lo; | |
110 | uint32_t cp_hqd_atomic1_preop_hi; | |
111 | uint32_t cp_hqd_hq_status0; | |
112 | uint32_t cp_hqd_hq_control0; | |
113 | uint32_t cp_mqd_control; | |
114 | uint32_t cp_mqd_query_time_lo; | |
115 | uint32_t cp_mqd_query_time_hi; | |
116 | uint32_t cp_mqd_connect_start_time_lo; | |
117 | uint32_t cp_mqd_connect_start_time_hi; | |
118 | uint32_t cp_mqd_connect_end_time_lo; | |
119 | uint32_t cp_mqd_connect_end_time_hi; | |
120 | uint32_t cp_mqd_connect_end_wf_count; | |
121 | uint32_t cp_mqd_connect_end_pq_rptr; | |
122 | uint32_t cp_mqd_connect_end_pq_wptr; | |
123 | uint32_t cp_mqd_connect_end_ib_rptr; | |
124 | uint32_t reserved_96; | |
125 | uint32_t reserved_97; | |
126 | uint32_t reserved_98; | |
127 | uint32_t reserved_99; | |
128 | uint32_t iqtimer_pkt_header; | |
129 | uint32_t iqtimer_pkt_dw0; | |
130 | uint32_t iqtimer_pkt_dw1; | |
131 | uint32_t iqtimer_pkt_dw2; | |
132 | uint32_t iqtimer_pkt_dw3; | |
133 | uint32_t iqtimer_pkt_dw4; | |
134 | uint32_t iqtimer_pkt_dw5; | |
135 | uint32_t iqtimer_pkt_dw6; | |
136 | uint32_t reserved_108; | |
137 | uint32_t reserved_109; | |
138 | uint32_t reserved_110; | |
139 | uint32_t reserved_111; | |
140 | uint32_t queue_doorbell_id0; | |
141 | uint32_t queue_doorbell_id1; | |
142 | uint32_t queue_doorbell_id2; | |
143 | uint32_t queue_doorbell_id3; | |
144 | uint32_t queue_doorbell_id4; | |
145 | uint32_t queue_doorbell_id5; | |
146 | uint32_t queue_doorbell_id6; | |
147 | uint32_t queue_doorbell_id7; | |
148 | uint32_t queue_doorbell_id8; | |
149 | uint32_t queue_doorbell_id9; | |
150 | uint32_t queue_doorbell_id10; | |
151 | uint32_t queue_doorbell_id11; | |
152 | uint32_t queue_doorbell_id12; | |
153 | uint32_t queue_doorbell_id13; | |
154 | uint32_t queue_doorbell_id14; | |
155 | uint32_t queue_doorbell_id15; | |
156 | }; | |
157 | ||
158 | struct cik_sdma_rlc_registers { | |
159 | uint32_t sdma_rlc_rb_cntl; | |
160 | uint32_t sdma_rlc_rb_base; | |
161 | uint32_t sdma_rlc_rb_base_hi; | |
162 | uint32_t sdma_rlc_rb_rptr; | |
163 | uint32_t sdma_rlc_rb_wptr; | |
164 | uint32_t sdma_rlc_rb_wptr_poll_cntl; | |
165 | uint32_t sdma_rlc_rb_wptr_poll_addr_hi; | |
166 | uint32_t sdma_rlc_rb_wptr_poll_addr_lo; | |
167 | uint32_t sdma_rlc_rb_rptr_addr_hi; | |
168 | uint32_t sdma_rlc_rb_rptr_addr_lo; | |
169 | uint32_t sdma_rlc_ib_cntl; | |
170 | uint32_t sdma_rlc_ib_rptr; | |
171 | uint32_t sdma_rlc_ib_offset; | |
172 | uint32_t sdma_rlc_ib_base_lo; | |
173 | uint32_t sdma_rlc_ib_base_hi; | |
174 | uint32_t sdma_rlc_ib_size; | |
175 | uint32_t sdma_rlc_skip_cntl; | |
176 | uint32_t sdma_rlc_context_status; | |
177 | uint32_t sdma_rlc_doorbell; | |
178 | uint32_t sdma_rlc_virtual_addr; | |
179 | uint32_t sdma_rlc_ape1_cntl; | |
180 | uint32_t sdma_rlc_doorbell_log; | |
181 | uint32_t reserved_22; | |
182 | uint32_t reserved_23; | |
183 | uint32_t reserved_24; | |
184 | uint32_t reserved_25; | |
185 | uint32_t reserved_26; | |
186 | uint32_t reserved_27; | |
187 | uint32_t reserved_28; | |
188 | uint32_t reserved_29; | |
189 | uint32_t reserved_30; | |
190 | uint32_t reserved_31; | |
191 | uint32_t reserved_32; | |
192 | uint32_t reserved_33; | |
193 | uint32_t reserved_34; | |
194 | uint32_t reserved_35; | |
195 | uint32_t reserved_36; | |
196 | uint32_t reserved_37; | |
197 | uint32_t reserved_38; | |
198 | uint32_t reserved_39; | |
199 | uint32_t reserved_40; | |
200 | uint32_t reserved_41; | |
201 | uint32_t reserved_42; | |
202 | uint32_t reserved_43; | |
203 | uint32_t reserved_44; | |
204 | uint32_t reserved_45; | |
205 | uint32_t reserved_46; | |
206 | uint32_t reserved_47; | |
207 | uint32_t reserved_48; | |
208 | uint32_t reserved_49; | |
209 | uint32_t reserved_50; | |
210 | uint32_t reserved_51; | |
211 | uint32_t reserved_52; | |
212 | uint32_t reserved_53; | |
213 | uint32_t reserved_54; | |
214 | uint32_t reserved_55; | |
215 | uint32_t reserved_56; | |
216 | uint32_t reserved_57; | |
217 | uint32_t reserved_58; | |
218 | uint32_t reserved_59; | |
219 | uint32_t reserved_60; | |
220 | uint32_t reserved_61; | |
221 | uint32_t reserved_62; | |
222 | uint32_t reserved_63; | |
223 | uint32_t reserved_64; | |
224 | uint32_t reserved_65; | |
225 | uint32_t reserved_66; | |
226 | uint32_t reserved_67; | |
227 | uint32_t reserved_68; | |
228 | uint32_t reserved_69; | |
229 | uint32_t reserved_70; | |
230 | uint32_t reserved_71; | |
231 | uint32_t reserved_72; | |
232 | uint32_t reserved_73; | |
233 | uint32_t reserved_74; | |
234 | uint32_t reserved_75; | |
235 | uint32_t reserved_76; | |
236 | uint32_t reserved_77; | |
237 | uint32_t reserved_78; | |
238 | uint32_t reserved_79; | |
239 | uint32_t reserved_80; | |
240 | uint32_t reserved_81; | |
241 | uint32_t reserved_82; | |
242 | uint32_t reserved_83; | |
243 | uint32_t reserved_84; | |
244 | uint32_t reserved_85; | |
245 | uint32_t reserved_86; | |
246 | uint32_t reserved_87; | |
247 | uint32_t reserved_88; | |
248 | uint32_t reserved_89; | |
249 | uint32_t reserved_90; | |
250 | uint32_t reserved_91; | |
251 | uint32_t reserved_92; | |
252 | uint32_t reserved_93; | |
253 | uint32_t reserved_94; | |
254 | uint32_t reserved_95; | |
255 | uint32_t reserved_96; | |
256 | uint32_t reserved_97; | |
257 | uint32_t reserved_98; | |
258 | uint32_t reserved_99; | |
259 | uint32_t reserved_100; | |
260 | uint32_t reserved_101; | |
261 | uint32_t reserved_102; | |
262 | uint32_t reserved_103; | |
263 | uint32_t reserved_104; | |
264 | uint32_t reserved_105; | |
265 | uint32_t reserved_106; | |
266 | uint32_t reserved_107; | |
267 | uint32_t reserved_108; | |
268 | uint32_t reserved_109; | |
269 | uint32_t reserved_110; | |
270 | uint32_t reserved_111; | |
271 | uint32_t reserved_112; | |
272 | uint32_t reserved_113; | |
273 | uint32_t reserved_114; | |
274 | uint32_t reserved_115; | |
275 | uint32_t reserved_116; | |
276 | uint32_t reserved_117; | |
277 | uint32_t reserved_118; | |
278 | uint32_t reserved_119; | |
279 | uint32_t reserved_120; | |
280 | uint32_t reserved_121; | |
281 | uint32_t reserved_122; | |
282 | uint32_t reserved_123; | |
283 | uint32_t reserved_124; | |
284 | uint32_t reserved_125; | |
285 | uint32_t reserved_126; | |
286 | uint32_t reserved_127; | |
287 | uint32_t sdma_engine_id; | |
288 | uint32_t sdma_queue_id; | |
289 | }; | |
290 | ||
291 | ||
292 | ||
293 | #endif /* CIK_STRUCTS_H_ */ |