Commit | Line | Data |
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1f7371b2 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/types.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/gfp.h> | |
ac885b3a | 26 | #include <linux/slab.h> |
1f7371b2 AD |
27 | #include "amd_shared.h" |
28 | #include "amd_powerplay.h" | |
ac885b3a | 29 | #include "pp_instance.h" |
577bbe01 RZ |
30 | #include "power_state.h" |
31 | #include "eventmanager.h" | |
1f7371b2 AD |
32 | |
33 | static int pp_early_init(void *handle) | |
34 | { | |
35 | return 0; | |
36 | } | |
37 | ||
38 | static int pp_sw_init(void *handle) | |
39 | { | |
3bace359 JZ |
40 | struct pp_instance *pp_handle; |
41 | struct pp_hwmgr *hwmgr; | |
42 | int ret = 0; | |
43 | ||
44 | if (handle == NULL) | |
45 | return -EINVAL; | |
46 | ||
47 | pp_handle = (struct pp_instance *)handle; | |
48 | hwmgr = pp_handle->hwmgr; | |
49 | ||
50 | if (hwmgr == NULL || hwmgr->pptable_func == NULL || | |
51 | hwmgr->hwmgr_func == NULL || | |
52 | hwmgr->pptable_func->pptable_init == NULL || | |
53 | hwmgr->hwmgr_func->backend_init == NULL) | |
54 | return -EINVAL; | |
55 | ||
56 | ret = hwmgr->pptable_func->pptable_init(hwmgr); | |
e92a0370 | 57 | |
3bace359 JZ |
58 | if (ret == 0) |
59 | ret = hwmgr->hwmgr_func->backend_init(hwmgr); | |
60 | ||
61 | return ret; | |
1f7371b2 AD |
62 | } |
63 | ||
64 | static int pp_sw_fini(void *handle) | |
65 | { | |
3bace359 JZ |
66 | struct pp_instance *pp_handle; |
67 | struct pp_hwmgr *hwmgr; | |
68 | int ret = 0; | |
69 | ||
70 | if (handle == NULL) | |
71 | return -EINVAL; | |
72 | ||
73 | pp_handle = (struct pp_instance *)handle; | |
74 | hwmgr = pp_handle->hwmgr; | |
75 | ||
76 | if (hwmgr != NULL || hwmgr->hwmgr_func != NULL || | |
77 | hwmgr->hwmgr_func->backend_fini != NULL) | |
78 | ret = hwmgr->hwmgr_func->backend_fini(hwmgr); | |
79 | ||
80 | return ret; | |
1f7371b2 AD |
81 | } |
82 | ||
83 | static int pp_hw_init(void *handle) | |
84 | { | |
ac885b3a JZ |
85 | struct pp_instance *pp_handle; |
86 | struct pp_smumgr *smumgr; | |
e92a0370 | 87 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
88 | int ret = 0; |
89 | ||
90 | if (handle == NULL) | |
91 | return -EINVAL; | |
92 | ||
93 | pp_handle = (struct pp_instance *)handle; | |
94 | smumgr = pp_handle->smu_mgr; | |
95 | ||
96 | if (smumgr == NULL || smumgr->smumgr_funcs == NULL || | |
97 | smumgr->smumgr_funcs->smu_init == NULL || | |
98 | smumgr->smumgr_funcs->start_smu == NULL) | |
99 | return -EINVAL; | |
100 | ||
101 | ret = smumgr->smumgr_funcs->smu_init(smumgr); | |
102 | if (ret) { | |
103 | printk(KERN_ERR "[ powerplay ] smc initialization failed\n"); | |
104 | return ret; | |
105 | } | |
106 | ||
107 | ret = smumgr->smumgr_funcs->start_smu(smumgr); | |
108 | if (ret) { | |
109 | printk(KERN_ERR "[ powerplay ] smc start failed\n"); | |
110 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
111 | return ret; | |
112 | } | |
e92a0370 | 113 | |
3bace359 | 114 | hw_init_power_state_table(pp_handle->hwmgr); |
e92a0370 | 115 | eventmgr = pp_handle->eventmgr; |
3bace359 | 116 | |
e92a0370 RZ |
117 | if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) |
118 | return -EINVAL; | |
119 | ||
120 | ret = eventmgr->pp_eventmgr_init(eventmgr); | |
1f7371b2 AD |
121 | return 0; |
122 | } | |
123 | ||
124 | static int pp_hw_fini(void *handle) | |
125 | { | |
ac885b3a JZ |
126 | struct pp_instance *pp_handle; |
127 | struct pp_smumgr *smumgr; | |
e92a0370 | 128 | struct pp_eventmgr *eventmgr; |
ac885b3a JZ |
129 | |
130 | if (handle == NULL) | |
131 | return -EINVAL; | |
132 | ||
133 | pp_handle = (struct pp_instance *)handle; | |
e92a0370 RZ |
134 | eventmgr = pp_handle->eventmgr; |
135 | ||
136 | if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL) | |
137 | eventmgr->pp_eventmgr_fini(eventmgr); | |
138 | ||
ac885b3a JZ |
139 | smumgr = pp_handle->smu_mgr; |
140 | ||
141 | if (smumgr != NULL || smumgr->smumgr_funcs != NULL || | |
142 | smumgr->smumgr_funcs->smu_fini != NULL) | |
143 | smumgr->smumgr_funcs->smu_fini(smumgr); | |
144 | ||
1f7371b2 AD |
145 | return 0; |
146 | } | |
147 | ||
148 | static bool pp_is_idle(void *handle) | |
149 | { | |
150 | return 0; | |
151 | } | |
152 | ||
153 | static int pp_wait_for_idle(void *handle) | |
154 | { | |
155 | return 0; | |
156 | } | |
157 | ||
158 | static int pp_sw_reset(void *handle) | |
159 | { | |
160 | return 0; | |
161 | } | |
162 | ||
163 | static void pp_print_status(void *handle) | |
164 | { | |
165 | ||
166 | } | |
167 | ||
168 | static int pp_set_clockgating_state(void *handle, | |
169 | enum amd_clockgating_state state) | |
170 | { | |
171 | return 0; | |
172 | } | |
173 | ||
174 | static int pp_set_powergating_state(void *handle, | |
175 | enum amd_powergating_state state) | |
176 | { | |
177 | return 0; | |
178 | } | |
179 | ||
180 | static int pp_suspend(void *handle) | |
181 | { | |
577bbe01 RZ |
182 | struct pp_instance *pp_handle; |
183 | struct pp_eventmgr *eventmgr; | |
184 | struct pem_event_data event_data = { {0} }; | |
185 | ||
186 | if (handle == NULL) | |
187 | return -EINVAL; | |
188 | ||
189 | pp_handle = (struct pp_instance *)handle; | |
190 | eventmgr = pp_handle->eventmgr; | |
191 | pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); | |
1f7371b2 AD |
192 | return 0; |
193 | } | |
194 | ||
195 | static int pp_resume(void *handle) | |
196 | { | |
577bbe01 RZ |
197 | struct pp_instance *pp_handle; |
198 | struct pp_eventmgr *eventmgr; | |
199 | struct pem_event_data event_data = { {0} }; | |
200 | ||
201 | if (handle == NULL) | |
202 | return -EINVAL; | |
203 | ||
204 | pp_handle = (struct pp_instance *)handle; | |
205 | eventmgr = pp_handle->eventmgr; | |
206 | pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); | |
1f7371b2 AD |
207 | return 0; |
208 | } | |
209 | ||
210 | const struct amd_ip_funcs pp_ip_funcs = { | |
211 | .early_init = pp_early_init, | |
212 | .late_init = NULL, | |
213 | .sw_init = pp_sw_init, | |
214 | .sw_fini = pp_sw_fini, | |
215 | .hw_init = pp_hw_init, | |
216 | .hw_fini = pp_hw_fini, | |
217 | .suspend = pp_suspend, | |
218 | .resume = pp_resume, | |
219 | .is_idle = pp_is_idle, | |
220 | .wait_for_idle = pp_wait_for_idle, | |
221 | .soft_reset = pp_sw_reset, | |
222 | .print_status = pp_print_status, | |
223 | .set_clockgating_state = pp_set_clockgating_state, | |
224 | .set_powergating_state = pp_set_powergating_state, | |
225 | }; | |
226 | ||
227 | static int pp_dpm_load_fw(void *handle) | |
228 | { | |
229 | return 0; | |
230 | } | |
231 | ||
232 | static int pp_dpm_fw_loading_complete(void *handle) | |
233 | { | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static int pp_dpm_force_performance_level(void *handle, | |
238 | enum amd_dpm_forced_level level) | |
239 | { | |
577bbe01 RZ |
240 | struct pp_instance *pp_handle; |
241 | struct pp_hwmgr *hwmgr; | |
242 | ||
243 | if (handle == NULL) | |
244 | return -EINVAL; | |
245 | ||
246 | pp_handle = (struct pp_instance *)handle; | |
247 | ||
248 | hwmgr = pp_handle->hwmgr; | |
249 | ||
250 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
251 | hwmgr->hwmgr_func->force_dpm_level == NULL) | |
252 | return -EINVAL; | |
253 | ||
254 | hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); | |
255 | ||
1f7371b2 AD |
256 | return 0; |
257 | } | |
577bbe01 | 258 | |
1f7371b2 AD |
259 | static enum amd_dpm_forced_level pp_dpm_get_performance_level( |
260 | void *handle) | |
261 | { | |
577bbe01 RZ |
262 | struct pp_hwmgr *hwmgr; |
263 | ||
264 | if (handle == NULL) | |
265 | return -EINVAL; | |
266 | ||
267 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
268 | ||
269 | if (hwmgr == NULL) | |
270 | return -EINVAL; | |
271 | ||
272 | return (((struct pp_instance *)handle)->hwmgr->dpm_level); | |
1f7371b2 | 273 | } |
577bbe01 | 274 | |
1f7371b2 AD |
275 | static int pp_dpm_get_sclk(void *handle, bool low) |
276 | { | |
577bbe01 RZ |
277 | struct pp_hwmgr *hwmgr; |
278 | ||
279 | if (handle == NULL) | |
280 | return -EINVAL; | |
281 | ||
282 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
283 | ||
284 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
285 | hwmgr->hwmgr_func->get_sclk == NULL) | |
286 | return -EINVAL; | |
287 | ||
288 | return hwmgr->hwmgr_func->get_sclk(hwmgr, low); | |
1f7371b2 | 289 | } |
577bbe01 | 290 | |
1f7371b2 AD |
291 | static int pp_dpm_get_mclk(void *handle, bool low) |
292 | { | |
577bbe01 RZ |
293 | struct pp_hwmgr *hwmgr; |
294 | ||
295 | if (handle == NULL) | |
296 | return -EINVAL; | |
297 | ||
298 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
299 | ||
300 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
301 | hwmgr->hwmgr_func->get_mclk == NULL) | |
302 | return -EINVAL; | |
303 | ||
304 | return hwmgr->hwmgr_func->get_mclk(hwmgr, low); | |
1f7371b2 | 305 | } |
577bbe01 | 306 | |
1f7371b2 AD |
307 | static int pp_dpm_powergate_vce(void *handle, bool gate) |
308 | { | |
577bbe01 RZ |
309 | struct pp_hwmgr *hwmgr; |
310 | ||
311 | if (handle == NULL) | |
312 | return -EINVAL; | |
313 | ||
314 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
315 | ||
316 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
317 | hwmgr->hwmgr_func->powergate_vce == NULL) | |
318 | return -EINVAL; | |
319 | ||
320 | return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); | |
1f7371b2 | 321 | } |
577bbe01 | 322 | |
1f7371b2 AD |
323 | static int pp_dpm_powergate_uvd(void *handle, bool gate) |
324 | { | |
577bbe01 RZ |
325 | struct pp_hwmgr *hwmgr; |
326 | ||
327 | if (handle == NULL) | |
328 | return -EINVAL; | |
329 | ||
330 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
331 | ||
332 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
333 | hwmgr->hwmgr_func->powergate_uvd == NULL) | |
334 | return -EINVAL; | |
335 | ||
336 | return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); | |
337 | } | |
338 | ||
339 | static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) | |
340 | { | |
341 | switch (state) { | |
342 | case POWER_STATE_TYPE_BATTERY: | |
343 | return PP_StateUILabel_Battery; | |
344 | case POWER_STATE_TYPE_BALANCED: | |
345 | return PP_StateUILabel_Balanced; | |
346 | case POWER_STATE_TYPE_PERFORMANCE: | |
347 | return PP_StateUILabel_Performance; | |
348 | default: | |
349 | return PP_StateUILabel_None; | |
350 | } | |
1f7371b2 AD |
351 | } |
352 | ||
353 | int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) | |
354 | { | |
577bbe01 RZ |
355 | int ret = 0; |
356 | struct pp_instance *pp_handle; | |
357 | struct pem_event_data data = { {0} }; | |
358 | ||
359 | pp_handle = (struct pp_instance *)handle; | |
360 | ||
361 | if (pp_handle == NULL) | |
362 | return -EINVAL; | |
363 | ||
364 | switch (event_id) { | |
365 | case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: | |
366 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
367 | break; | |
368 | case AMD_PP_EVENT_ENABLE_USER_STATE: | |
369 | { | |
370 | enum amd_pm_state_type ps; | |
371 | ||
372 | if (input == NULL) | |
373 | return -EINVAL; | |
374 | ps = *(unsigned long *)input; | |
375 | ||
376 | data.requested_ui_label = power_state_convert(ps); | |
377 | ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); | |
378 | } | |
379 | break; | |
380 | default: | |
381 | break; | |
382 | } | |
383 | return ret; | |
1f7371b2 | 384 | } |
577bbe01 | 385 | |
1f7371b2 AD |
386 | enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) |
387 | { | |
577bbe01 RZ |
388 | struct pp_hwmgr *hwmgr; |
389 | struct pp_power_state *state; | |
390 | ||
391 | if (handle == NULL) | |
392 | return -EINVAL; | |
393 | ||
394 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
395 | ||
396 | if (hwmgr == NULL || hwmgr->current_ps == NULL) | |
397 | return -EINVAL; | |
398 | ||
399 | state = hwmgr->current_ps; | |
400 | ||
401 | switch (state->classification.ui_label) { | |
402 | case PP_StateUILabel_Battery: | |
403 | return POWER_STATE_TYPE_BATTERY; | |
404 | case PP_StateUILabel_Balanced: | |
405 | return POWER_STATE_TYPE_BALANCED; | |
406 | case PP_StateUILabel_Performance: | |
407 | return POWER_STATE_TYPE_PERFORMANCE; | |
408 | default: | |
409 | return POWER_STATE_TYPE_DEFAULT; | |
410 | } | |
1f7371b2 | 411 | } |
577bbe01 | 412 | |
1f7371b2 AD |
413 | static void |
414 | pp_debugfs_print_current_performance_level(void *handle, | |
415 | struct seq_file *m) | |
416 | { | |
577bbe01 RZ |
417 | struct pp_hwmgr *hwmgr; |
418 | ||
419 | if (handle == NULL) | |
420 | return; | |
421 | ||
422 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
423 | ||
424 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
425 | hwmgr->hwmgr_func->print_current_perforce_level == NULL) | |
426 | return; | |
427 | ||
428 | hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); | |
1f7371b2 | 429 | } |
3bace359 | 430 | |
cac9a199 RZ |
431 | static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) |
432 | { | |
433 | struct pp_hwmgr *hwmgr; | |
434 | ||
435 | if (handle == NULL) | |
436 | return -EINVAL; | |
437 | ||
438 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
439 | ||
440 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
441 | hwmgr->hwmgr_func->set_fan_control_mode == NULL) | |
442 | return -EINVAL; | |
443 | ||
444 | return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); | |
445 | } | |
446 | ||
447 | static int pp_dpm_get_fan_control_mode(void *handle) | |
448 | { | |
449 | struct pp_hwmgr *hwmgr; | |
450 | ||
451 | if (handle == NULL) | |
452 | return -EINVAL; | |
453 | ||
454 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
455 | ||
456 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
457 | hwmgr->hwmgr_func->get_fan_control_mode == NULL) | |
458 | return -EINVAL; | |
459 | ||
460 | return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); | |
461 | } | |
462 | ||
463 | static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) | |
464 | { | |
465 | struct pp_hwmgr *hwmgr; | |
466 | ||
467 | if (handle == NULL) | |
468 | return -EINVAL; | |
469 | ||
470 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
471 | ||
472 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
473 | hwmgr->hwmgr_func->set_fan_speed_percent == NULL) | |
474 | return -EINVAL; | |
475 | ||
476 | return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); | |
477 | } | |
478 | ||
479 | static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) | |
480 | { | |
481 | struct pp_hwmgr *hwmgr; | |
482 | ||
483 | if (handle == NULL) | |
484 | return -EINVAL; | |
485 | ||
486 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
487 | ||
488 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
489 | hwmgr->hwmgr_func->get_fan_speed_percent == NULL) | |
490 | return -EINVAL; | |
491 | ||
492 | return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); | |
493 | } | |
494 | ||
495 | static int pp_dpm_get_temperature(void *handle) | |
496 | { | |
497 | struct pp_hwmgr *hwmgr; | |
498 | ||
499 | if (handle == NULL) | |
500 | return -EINVAL; | |
501 | ||
502 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
503 | ||
504 | if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || | |
505 | hwmgr->hwmgr_func->get_temperature == NULL) | |
506 | return -EINVAL; | |
507 | ||
508 | return hwmgr->hwmgr_func->get_temperature(hwmgr); | |
509 | } | |
577bbe01 | 510 | |
1f7371b2 | 511 | const struct amd_powerplay_funcs pp_dpm_funcs = { |
cac9a199 | 512 | .get_temperature = pp_dpm_get_temperature, |
1f7371b2 AD |
513 | .load_firmware = pp_dpm_load_fw, |
514 | .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, | |
515 | .force_performance_level = pp_dpm_force_performance_level, | |
516 | .get_performance_level = pp_dpm_get_performance_level, | |
517 | .get_current_power_state = pp_dpm_get_current_power_state, | |
518 | .get_sclk = pp_dpm_get_sclk, | |
519 | .get_mclk = pp_dpm_get_mclk, | |
520 | .powergate_vce = pp_dpm_powergate_vce, | |
521 | .powergate_uvd = pp_dpm_powergate_uvd, | |
522 | .dispatch_tasks = pp_dpm_dispatch_tasks, | |
523 | .print_current_performance_level = pp_debugfs_print_current_performance_level, | |
cac9a199 RZ |
524 | .set_fan_control_mode = pp_dpm_set_fan_control_mode, |
525 | .get_fan_control_mode = pp_dpm_get_fan_control_mode, | |
526 | .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, | |
527 | .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, | |
1f7371b2 AD |
528 | }; |
529 | ||
ac885b3a JZ |
530 | static int amd_pp_instance_init(struct amd_pp_init *pp_init, |
531 | struct amd_powerplay *amd_pp) | |
532 | { | |
533 | int ret; | |
534 | struct pp_instance *handle; | |
535 | ||
536 | handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); | |
537 | if (handle == NULL) | |
538 | return -ENOMEM; | |
539 | ||
540 | ret = smum_init(pp_init, handle); | |
541 | if (ret) | |
3bace359 JZ |
542 | goto fail_smum; |
543 | ||
544 | ret = hwmgr_init(pp_init, handle); | |
545 | if (ret) | |
546 | goto fail_hwmgr; | |
ac885b3a | 547 | |
e92a0370 RZ |
548 | ret = eventmgr_init(handle); |
549 | if (ret) | |
550 | goto fail_eventmgr; | |
551 | ||
ac885b3a JZ |
552 | amd_pp->pp_handle = handle; |
553 | return 0; | |
3bace359 | 554 | |
e92a0370 RZ |
555 | fail_eventmgr: |
556 | hwmgr_fini(handle->hwmgr); | |
3bace359 JZ |
557 | fail_hwmgr: |
558 | smum_fini(handle->smu_mgr); | |
559 | fail_smum: | |
560 | kfree(handle); | |
561 | return ret; | |
ac885b3a JZ |
562 | } |
563 | ||
564 | static int amd_pp_instance_fini(void *handle) | |
565 | { | |
566 | struct pp_instance *instance = (struct pp_instance *)handle; | |
e92a0370 | 567 | |
ac885b3a JZ |
568 | if (instance == NULL) |
569 | return -EINVAL; | |
570 | ||
e92a0370 RZ |
571 | eventmgr_fini(instance->eventmgr); |
572 | ||
3bace359 JZ |
573 | hwmgr_fini(instance->hwmgr); |
574 | ||
ac885b3a JZ |
575 | smum_fini(instance->smu_mgr); |
576 | ||
577 | kfree(handle); | |
578 | return 0; | |
579 | } | |
580 | ||
1f7371b2 AD |
581 | int amd_powerplay_init(struct amd_pp_init *pp_init, |
582 | struct amd_powerplay *amd_pp) | |
583 | { | |
ac885b3a JZ |
584 | int ret; |
585 | ||
1f7371b2 AD |
586 | if (pp_init == NULL || amd_pp == NULL) |
587 | return -EINVAL; | |
588 | ||
ac885b3a JZ |
589 | ret = amd_pp_instance_init(pp_init, amd_pp); |
590 | ||
591 | if (ret) | |
592 | return ret; | |
593 | ||
1f7371b2 AD |
594 | amd_pp->ip_funcs = &pp_ip_funcs; |
595 | amd_pp->pp_funcs = &pp_dpm_funcs; | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | int amd_powerplay_fini(void *handle) | |
601 | { | |
ac885b3a JZ |
602 | amd_pp_instance_fini(handle); |
603 | ||
1f7371b2 AD |
604 | return 0; |
605 | } | |
7fb72a1f RZ |
606 | |
607 | /* export this function to DAL */ | |
608 | ||
609 | int amd_powerplay_display_configuration_change(void *handle, const void *input) | |
610 | { | |
611 | struct pp_hwmgr *hwmgr; | |
612 | const struct amd_pp_display_configuration *display_config = input; | |
613 | ||
614 | if (handle == NULL) | |
615 | return -EINVAL; | |
616 | ||
617 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
618 | ||
619 | phm_store_dal_configuration_data(hwmgr, display_config); | |
620 | return 0; | |
621 | } | |
c4dd206b VP |
622 | |
623 | int amd_powerplay_get_display_power_level(void *handle, void *output) | |
624 | { | |
625 | struct pp_hwmgr *hwmgr; | |
626 | ||
627 | if (handle == NULL || output == NULL) | |
628 | return -EINVAL; | |
629 | ||
630 | hwmgr = ((struct pp_instance *)handle)->hwmgr; | |
631 | ||
632 | return phm_get_dal_power_level(hwmgr, | |
633 | (struct pp_dal_clock_info *)output); | |
634 | } |