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drm/amd/powerplay: add multimedia power gating support for Fiji.
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / fiji_hwmgr.c
CommitLineData
aabcb7c1
EH		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include "linux/delay.h"
27
28#include "hwmgr.h"
29#include "fiji_smumgr.h"
30#include "atombios.h"
31#include "hardwaremanager.h"
32#include "ppatomctrl.h"
33#include "atombios.h"
34#include "cgs_common.h"
35#include "fiji_dyn_defaults.h"
36#include "fiji_powertune.h"
37#include "smu73.h"
38#include "smu/smu_7_1_3_d.h"
39#include "smu/smu_7_1_3_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44#include "dce/dce_10_0_d.h"
45#include "dce/dce_10_0_sh_mask.h"
46#include "pppcielanes.h"
47#include "fiji_hwmgr.h"
48#include "tonga_processpptables.h"
49#include "tonga_pptable.h"
50#include "pp_debug.h"
51#include "pp_acpi.h"
16881da6 52#include "amd_pcie_helpers.h"
aabcb7c1 53
91c4c981
EH		 54#include "fiji_clockpowergating.h"
55
aabcb7c1
EH		 56#define VOLTAGE_SCALE 4
57#define SMC_RAM_END 0x40000
58#define VDDC_VDDCI_DELTA 300
59
60#define MC_SEQ_MISC0_GDDR5_SHIFT 28
61#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
62#define MC_SEQ_MISC0_GDDR5_VALUE 5
63
64#define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */
65#define MC_CG_ARB_FREQ_F1 0x0b
66#define MC_CG_ARB_FREQ_F2 0x0c
67#define MC_CG_ARB_FREQ_F3 0x0d
68
69/* From smc_reg.h */
70#define SMC_CG_IND_START 0xc0030000
71#define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */
72
73#define VOLTAGE_SCALE 4
74#define VOLTAGE_VID_OFFSET_SCALE1 625
75#define VOLTAGE_VID_OFFSET_SCALE2 100
76
77#define VDDC_VDDCI_DELTA 300
78
79#define ixSWRST_COMMAND_1 0x1400103
80#define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000
81
82/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
83enum DPM_EVENT_SRC {
84 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
85 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
86 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
87 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
88 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
89};
90
91enum DISPLAY_GAP {
92 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
93 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
94 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. */
95 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
96};
97
98/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
99 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
100 */
101uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
102 {600, 1050, 6, 1} };
103
104/* [FF, SS] type, [] 4 voltage ranges, and
105 * [Floor Freq, Boundary Freq, VID min , VID max]
106 */
107uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
108{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
109 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
110
111/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
112 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
113 */
114uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
115 {0, 2, 4, 5, 6, 5} };
116
117const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
118
119struct fiji_power_state *cast_phw_fiji_power_state(
120 struct pp_hw_power_state *hw_ps)
121{
122 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
123 "Invalid Powerstate Type!",
124 return NULL;);
125
126 return (struct fiji_power_state *)hw_ps;
127}
128
129const struct fiji_power_state *cast_const_phw_fiji_power_state(
130 const struct pp_hw_power_state *hw_ps)
131{
132 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
133 "Invalid Powerstate Type!",
134 return NULL;);
135
136 return (const struct fiji_power_state *)hw_ps;
137}
138
139static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
140{
141 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
142 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
143 ? true : false;
144}
145
146static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
147{
148 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
149 struct fiji_ulv_parm *ulv = &data->ulv;
150
151 ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
152 data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
153 data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
154 data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
155 data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
156 data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
157 data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
158 data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
159 data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
160
161 data->static_screen_threshold_unit =
162 PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
163 data->static_screen_threshold =
164 PPFIJI_STATICSCREENTHRESHOLD_DFLT;
165
166 /* Unset ABM cap as it moved to DAL.
167 * Add PHM_PlatformCaps_NonABMSupportInPPLib
168 * for re-direct ABM related request to DAL
169 */
170 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
171 PHM_PlatformCaps_ABM);
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_NonABMSupportInPPLib);
174
175 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
176 PHM_PlatformCaps_DynamicACTiming);
177
178 fiji_initialize_power_tune_defaults(hwmgr);
179
180 data->mclk_stutter_mode_threshold = 60000;
181 data->pcie_gen_performance.max = PP_PCIEGen1;
182 data->pcie_gen_performance.min = PP_PCIEGen3;
183 data->pcie_gen_power_saving.max = PP_PCIEGen1;
184 data->pcie_gen_power_saving.min = PP_PCIEGen3;
185 data->pcie_lane_performance.max = 0;
186 data->pcie_lane_performance.min = 16;
187 data->pcie_lane_power_saving.max = 0;
188 data->pcie_lane_power_saving.min = 16;
189
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 PHM_PlatformCaps_DynamicUVDState);
192}
193
194static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
195 phm_ppt_v1_voltage_lookup_table *lookup_table,
196 uint16_t virtual_voltage_id, int32_t *sclk)
197{
198 uint8_t entryId;
199 uint8_t voltageId;
200 struct phm_ppt_v1_information *table_info =
201 (struct phm_ppt_v1_information *)(hwmgr->pptable);
202
203 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
204
205 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
206 for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
207 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
208 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
209 break;
210 }
211
212 PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
213 "Can't find requested voltage id in vdd_dep_on_sclk table!",
214 return -EINVAL;
215 );
216
217 *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
218
219 return 0;
220}
221
222/**
223* Get Leakage VDDC based on leakage ID.
224*
225* @param hwmgr the address of the powerplay hardware manager.
226* @return always 0
227*/
228static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
229{
230 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
231 uint16_t vv_id;
232 uint16_t vddc = 0;
233 uint16_t evv_default = 1150;
234 uint16_t i, j;
235 uint32_t sclk = 0;
236 struct phm_ppt_v1_information *table_info =
237 (struct phm_ppt_v1_information *)hwmgr->pptable;
238 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
239 table_info->vdd_dep_on_sclk;
240 int result;
241
242 for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
243 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
244 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
245 table_info->vddc_lookup_table, vv_id, &sclk)) {
246 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
247 PHM_PlatformCaps_ClockStretcher)) {
248 for (j = 1; j < sclk_table->count; j++) {
249 if (sclk_table->entries[j].clk == sclk &&
250 sclk_table->entries[j].cks_enable == 0) {
251 sclk += 5000;
252 break;
253 }
254 }
255 }
256
257 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
258 PHM_PlatformCaps_EnableDriverEVV))
259 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
260 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
261 else
262 result = -EINVAL;
263
264 if (result)
265 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
266 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
267
268 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
269 PP_ASSERT_WITH_CODE((vddc < 2000),
270 "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
271
272 if (result)
273 /* 1.15V is the default safe value for Fiji */
274 vddc = evv_default;
275
276 /* the voltage should not be zero nor equal to leakage ID */
277 if (vddc != 0 && vddc != vv_id) {
278 data->vddc_leakage.actual_voltage
279 [data->vddc_leakage.count] = vddc;
280 data->vddc_leakage.leakage_id
281 [data->vddc_leakage.count] = vv_id;
282 data->vddc_leakage.count++;
283 }
284 }
285 }
286 return 0;
287}
288
289/**
290 * Change virtual leakage voltage to actual value.
291 *
292 * @param hwmgr the address of the powerplay hardware manager.
293 * @param pointer to changing voltage
294 * @param pointer to leakage table
295 */
296static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
297 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
298{
299 uint32_t index;
300
301 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
302 for (index = 0; index < leakage_table->count; index++) {
303 /* if this voltage matches a leakage voltage ID */
304 /* patch with actual leakage voltage */
305 if (leakage_table->leakage_id[index] == *voltage) {
306 *voltage = leakage_table->actual_voltage[index];
307 break;
308 }
309 }
310
311 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
312 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
313}
314
315/**
316* Patch voltage lookup table by EVV leakages.
317*
318* @param hwmgr the address of the powerplay hardware manager.
319* @param pointer to voltage lookup table
320* @param pointer to leakage table
321* @return always 0
322*/
323static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
324 phm_ppt_v1_voltage_lookup_table *lookup_table,
325 struct fiji_leakage_voltage *leakage_table)
326{
327 uint32_t i;
328
329 for (i = 0; i < lookup_table->count; i++)
330 fiji_patch_with_vdd_leakage(hwmgr,
331 &lookup_table->entries[i].us_vdd, leakage_table);
332
333 return 0;
334}
335
336static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
337 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
338 uint16_t *vddc)
339{
340 struct phm_ppt_v1_information *table_info =
341 (struct phm_ppt_v1_information *)(hwmgr->pptable);
342 fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
343 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
344 table_info->max_clock_voltage_on_dc.vddc;
345 return 0;
346}
347
348static int fiji_patch_voltage_dependency_tables_with_lookup_table(
349 struct pp_hwmgr *hwmgr)
350{
351 uint8_t entryId;
352 uint8_t voltageId;
353 struct phm_ppt_v1_information *table_info =
354 (struct phm_ppt_v1_information *)(hwmgr->pptable);
355
356 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
357 table_info->vdd_dep_on_sclk;
358 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
359 table_info->vdd_dep_on_mclk;
360 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
361 table_info->mm_dep_table;
362
363 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
364 voltageId = sclk_table->entries[entryId].vddInd;
365 sclk_table->entries[entryId].vddc =
366 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
367 }
368
369 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
370 voltageId = mclk_table->entries[entryId].vddInd;
371 mclk_table->entries[entryId].vddc =
372 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
373 }
374
375 for (entryId = 0; entryId < mm_table->count; ++entryId) {
376 voltageId = mm_table->entries[entryId].vddcInd;
377 mm_table->entries[entryId].vddc =
378 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
379 }
380
381 return 0;
382
383}
384
385static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
386{
387 /* Need to determine if we need calculated voltage. */
388 return 0;
389}
390
391static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
392{
393 /* Need to determine if we need calculated voltage from mm table. */
394 return 0;
395}
396
397static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
398 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
399{
400 uint32_t table_size, i, j;
401 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
402 table_size = lookup_table->count;
403
404 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
405 "Lookup table is empty", return -EINVAL);
406
407 /* Sorting voltages */
408 for (i = 0; i < table_size - 1; i++) {
409 for (j = i + 1; j > 0; j--) {
410 if (lookup_table->entries[j].us_vdd <
411 lookup_table->entries[j - 1].us_vdd) {
412 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
413 lookup_table->entries[j - 1] = lookup_table->entries[j];
414 lookup_table->entries[j] = tmp_voltage_lookup_record;
415 }
416 }
417 }
418
419 return 0;
420}
421
422static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
423{
424 int result = 0;
425 int tmp_result;
426 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
427 struct phm_ppt_v1_information *table_info =
428 (struct phm_ppt_v1_information *)(hwmgr->pptable);
429
430 tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
431 table_info->vddc_lookup_table, &(data->vddc_leakage));
432 if (tmp_result)
433 result = tmp_result;
434
435 tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
436 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
437 if (tmp_result)
438 result = tmp_result;
439
440 tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
441 if (tmp_result)
442 result = tmp_result;
443
444 tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
445 if (tmp_result)
446 result = tmp_result;
447
448 tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
449 if (tmp_result)
450 result = tmp_result;
451
452 tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
453 if(tmp_result)
454 result = tmp_result;
455
456 return result;
457}
458
459static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
460{
461 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
462 struct phm_ppt_v1_information *table_info =
463 (struct phm_ppt_v1_information *)(hwmgr->pptable);
464
465 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
466 table_info->vdd_dep_on_sclk;
467 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
468 table_info->vdd_dep_on_mclk;
469
470 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
471 "VDD dependency on SCLK table is missing. \
472 This table is mandatory", return -EINVAL);
473 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
474 "VDD dependency on SCLK table has to have is missing. \
475 This table is mandatory", return -EINVAL);
476
477 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
478 "VDD dependency on MCLK table is missing. \
479 This table is mandatory", return -EINVAL);
480 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
481 "VDD dependency on MCLK table has to have is missing. \
482 This table is mandatory", return -EINVAL);
483
484 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
485 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->
486 entries[allowed_sclk_vdd_table->count - 1].vddc;
487
488 table_info->max_clock_voltage_on_ac.sclk =
489 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
490 table_info->max_clock_voltage_on_ac.mclk =
491 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
492 table_info->max_clock_voltage_on_ac.vddc =
493 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
494 table_info->max_clock_voltage_on_ac.vddci =
495 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
496
497 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
498 table_info->max_clock_voltage_on_ac.sclk;
499 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
500 table_info->max_clock_voltage_on_ac.mclk;
501 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
502 table_info->max_clock_voltage_on_ac.vddc;
503 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
504 table_info->max_clock_voltage_on_ac.vddci;
505
506 return 0;
507}
508
509static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
510{
511 uint32_t speedCntl = 0;
512
513 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
514 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
515 ixPCIE_LC_SPEED_CNTL);
516 return((uint16_t)PHM_GET_FIELD(speedCntl,
517 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
518}
519
520static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
521{
522 uint32_t link_width;
523
524 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
525 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
526 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
527
528 PP_ASSERT_WITH_CODE((7 >= link_width),
529 "Invalid PCIe lane width!", return 0);
530
531 return decode_pcie_lane_width(link_width);
532}
533
534/** Patch the Boot State to match VBIOS boot clocks and voltage.
535*
536* @param hwmgr Pointer to the hardware manager.
537* @param pPowerState The address of the PowerState instance being created.
538*
539*/
540static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
541 struct pp_hw_power_state *hw_ps)
542{
543 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
544 struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
545 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
546 uint16_t size;
547 uint8_t frev, crev;
548 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
549
550 /* First retrieve the Boot clocks and VDDC from the firmware info table.
551 * We assume here that fw_info is unchanged if this call fails.
552 */
553 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
554 hwmgr->device, index,
555 &size, &frev, &crev);
556 if (!fw_info)
557 /* During a test, there is no firmware info table. */
558 return 0;
559
560 /* Patch the state. */
561 data->vbios_boot_state.sclk_bootup_value =
562 le32_to_cpu(fw_info->ulDefaultEngineClock);
563 data->vbios_boot_state.mclk_bootup_value =
564 le32_to_cpu(fw_info->ulDefaultMemoryClock);
565 data->vbios_boot_state.mvdd_bootup_value =
566 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
567 data->vbios_boot_state.vddc_bootup_value =
568 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
569 data->vbios_boot_state.vddci_bootup_value =
570 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
571 data->vbios_boot_state.pcie_gen_bootup_value =
572 fiji_get_current_pcie_speed(hwmgr);
573 data->vbios_boot_state.pcie_lane_bootup_value =
574 (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
575
576 /* set boot power state */
577 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
578 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
579 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
580 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
581
582 return 0;
583}
584
585static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
586{
587 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
588 uint32_t i;
589 struct phm_ppt_v1_information *table_info =
590 (struct phm_ppt_v1_information *)(hwmgr->pptable);
591 bool stay_in_boot;
592 int result;
593
594 data->dll_default_on = false;
595 data->sram_end = SMC_RAM_END;
596
597 for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
598 data->activity_target[i] = FIJI_AT_DFLT;
599
600 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
601
602 data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
603 data->mclk_dpm0_activity_target = 0xa;
604
605 data->sclk_dpm_key_disabled = 0;
606 data->mclk_dpm_key_disabled = 0;
607 data->pcie_dpm_key_disabled = 0;
608
609 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
610 PHM_PlatformCaps_UnTabledHardwareInterface);
611 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
612 PHM_PlatformCaps_TablelessHardwareInterface);
613
614 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
615 PHM_PlatformCaps_SclkDeepSleep);
616
617 data->gpio_debug = 0;
618
619 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
620 PHM_PlatformCaps_DynamicPatchPowerState);
621
622 /* need to set voltage control types before EVV patching */
623 data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
624 data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
625 data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
626
627 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
628 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
629 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
630
631 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
632 PHM_PlatformCaps_EnableMVDDControl))
633 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
634 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
635 data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
636
637 if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
638 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
639 PHM_PlatformCaps_EnableMVDDControl);
640
641 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
642 PHM_PlatformCaps_ControlVDDCI)) {
643 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
644 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
645 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
646 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
647 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
648 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
649 }
650
651 if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
652 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
653 PHM_PlatformCaps_ControlVDDCI);
654
655 if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
656 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
657 PHM_PlatformCaps_ClockStretcher);
658
659 fiji_init_dpm_defaults(hwmgr);
660
661 /* Get leakage voltage based on leakage ID. */
662 fiji_get_evv_voltages(hwmgr);
663
664 /* Patch our voltage dependency table with actual leakage voltage
665 * We need to perform leakage translation before it's used by other functions
666 */
667 fiji_complete_dependency_tables(hwmgr);
668
669 /* Parse pptable data read from VBIOS */
670 fiji_set_private_data_based_on_pptable(hwmgr);
671
672 /* ULV Support */
673 data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
674
675 /* Initalize Dynamic State Adjustment Rule Settings */
676 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
677
678 if (!result) {
679 data->uvd_enabled = false;
680 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
681 PHM_PlatformCaps_EnableSMU7ThermalManagement);
682 data->vddc_phase_shed_control = false;
683 }
684
685 stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
686 PHM_PlatformCaps_StayInBootState);
687
688 if (0 == result) {
464cea3e
AD		 689 struct cgs_system_info sys_info = {0};
690
aabcb7c1
EH		 691 data->is_tlu_enabled = 0;
692 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
693 FIJI_MAX_HARDWARE_POWERLEVELS;
694 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
695 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
696
464cea3e
AD		 697 sys_info.size = sizeof(struct cgs_system_info);
698 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
699 result = cgs_query_system_info(hwmgr->device, &sys_info);
700 if (result)
701 data->pcie_gen_cap = 0x30007;
702 else
703 data->pcie_gen_cap = (uint32_t)sys_info.value;
704 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
705 data->pcie_spc_cap = 20;
706 sys_info.size = sizeof(struct cgs_system_info);
707 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
708 result = cgs_query_system_info(hwmgr->device, &sys_info);
709 if (result)
710 data->pcie_lane_cap = 0x2f0000;
711 else
712 data->pcie_lane_cap = (uint32_t)sys_info.value;
aabcb7c1
EH		 713 } else {
714 /* Ignore return value in here, we are cleaning up a mess. */
715 tonga_hwmgr_backend_fini(hwmgr);
716 }
717
718 return 0;
719}
720
721/**
722 * Read clock related registers.
723 *
724 * @param hwmgr the address of the powerplay hardware manager.
725 * @return always 0
726 */
727static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
728{
729 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
730
731 data->clock_registers.vCG_SPLL_FUNC_CNTL =
732 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
733 ixCG_SPLL_FUNC_CNTL);
734 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
735 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
736 ixCG_SPLL_FUNC_CNTL_2);
737 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
738 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
739 ixCG_SPLL_FUNC_CNTL_3);
740 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
741 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
742 ixCG_SPLL_FUNC_CNTL_4);
743 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
744 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
745 ixCG_SPLL_SPREAD_SPECTRUM);
746 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
747 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
748 ixCG_SPLL_SPREAD_SPECTRUM_2);
749
750 return 0;
751}
752
753/**
754 * Find out if memory is GDDR5.
755 *
756 * @param hwmgr the address of the powerplay hardware manager.
757 * @return always 0
758 */
759static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
760{
761 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
762 uint32_t temp;
763
764 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
765
766 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
767 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
768 MC_SEQ_MISC0_GDDR5_SHIFT));
769
770 return 0;
771}
772
773/**
774 * Enables Dynamic Power Management by SMC
775 *
776 * @param hwmgr the address of the powerplay hardware manager.
777 * @return always 0
778 */
779static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
780{
781 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
782 GENERAL_PWRMGT, STATIC_PM_EN, 1);
783
784 return 0;
785}
786
787/**
788 * Initialize PowerGating States for different engines
789 *
790 * @param hwmgr the address of the powerplay hardware manager.
791 * @return always 0
792 */
793static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
794{
795 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
796
797 data->uvd_power_gated = false;
798 data->vce_power_gated = false;
799 data->samu_power_gated = false;
800 data->acp_power_gated = false;
801 data->pg_acp_init = true;
802
803 return 0;
804}
805
806static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
807{
808 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
809 data->low_sclk_interrupt_threshold = 0;
810
811 return 0;
812}
813
814static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
815{
816 int tmp_result, result = 0;
817
818 tmp_result = fiji_read_clock_registers(hwmgr);
819 PP_ASSERT_WITH_CODE((0 == tmp_result),
820 "Failed to read clock registers!", result = tmp_result);
821
822 tmp_result = fiji_get_memory_type(hwmgr);
823 PP_ASSERT_WITH_CODE((0 == tmp_result),
824 "Failed to get memory type!", result = tmp_result);
825
826 tmp_result = fiji_enable_acpi_power_management(hwmgr);
827 PP_ASSERT_WITH_CODE((0 == tmp_result),
828 "Failed to enable ACPI power management!", result = tmp_result);
829
830 tmp_result = fiji_init_power_gate_state(hwmgr);
831 PP_ASSERT_WITH_CODE((0 == tmp_result),
832 "Failed to init power gate state!", result = tmp_result);
833
834 tmp_result = tonga_get_mc_microcode_version(hwmgr);
835 PP_ASSERT_WITH_CODE((0 == tmp_result),
836 "Failed to get MC microcode version!", result = tmp_result);
837
838 tmp_result = fiji_init_sclk_threshold(hwmgr);
839 PP_ASSERT_WITH_CODE((0 == tmp_result),
840 "Failed to init sclk threshold!", result = tmp_result);
841
842 return result;
843}
844
845/**
846* Checks if we want to support voltage control
847*
848* @param hwmgr the address of the powerplay hardware manager.
849*/
850static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
851{
852 const struct fiji_hwmgr *data =
853 (const struct fiji_hwmgr *)(hwmgr->backend);
854
855 return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
856}
857
858/**
859* Enable voltage control
860*
861* @param hwmgr the address of the powerplay hardware manager.
862* @return always 0
863*/
864static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
865{
866 /* enable voltage control */
867 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
868 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
869
870 return 0;
871}
872
873/**
874* Remove repeated voltage values and create table with unique values.
875*
876* @param hwmgr the address of the powerplay hardware manager.
877* @param vol_table the pointer to changing voltage table
878* @return 0 in success
879*/
880
881static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
882 struct pp_atomctrl_voltage_table *vol_table)
883{
884 uint32_t i, j;
885 uint16_t vvalue;
886 bool found = false;
887 struct pp_atomctrl_voltage_table *table;
888
889 PP_ASSERT_WITH_CODE((NULL != vol_table),
890 "Voltage Table empty.", return -EINVAL);
891 table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
892 GFP_KERNEL);
893
894 if (NULL == table)
895 return -EINVAL;
896
897 table->mask_low = vol_table->mask_low;
898 table->phase_delay = vol_table->phase_delay;
899
900 for (i = 0; i < vol_table->count; i++) {
901 vvalue = vol_table->entries[i].value;
902 found = false;
903
904 for (j = 0; j < table->count; j++) {
905 if (vvalue == table->entries[j].value) {
906 found = true;
907 break;
908 }
909 }
910
911 if (!found) {
912 table->entries[table->count].value = vvalue;
913 table->entries[table->count].smio_low =
914 vol_table->entries[i].smio_low;
915 table->count++;
916 }
917 }
918
919 memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
920 kfree(table);
921
922 return 0;
923}
924static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
925 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
926{
927 uint32_t i;
928 int result;
929 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
930 struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
931
932 PP_ASSERT_WITH_CODE((0 != dep_table->count),
933 "Voltage Dependency Table empty.", return -EINVAL);
934
935 vol_table->mask_low = 0;
936 vol_table->phase_delay = 0;
937 vol_table->count = dep_table->count;
938
939 for (i = 0; i < dep_table->count; i++) {
940 vol_table->entries[i].value = dep_table->entries[i].mvdd;
941 vol_table->entries[i].smio_low = 0;
942 }
943
944 result = fiji_trim_voltage_table(hwmgr, vol_table);
945 PP_ASSERT_WITH_CODE((0 == result),
946 "Failed to trim MVDD table.", return result);
947
948 return 0;
949}
950
951static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
952 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
953{
954 uint32_t i;
955 int result;
956 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
957 struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
958
959 PP_ASSERT_WITH_CODE((0 != dep_table->count),
960 "Voltage Dependency Table empty.", return -EINVAL);
961
962 vol_table->mask_low = 0;
963 vol_table->phase_delay = 0;
964 vol_table->count = dep_table->count;
965
966 for (i = 0; i < dep_table->count; i++) {
967 vol_table->entries[i].value = dep_table->entries[i].vddci;
968 vol_table->entries[i].smio_low = 0;
969 }
970
971 result = fiji_trim_voltage_table(hwmgr, vol_table);
972 PP_ASSERT_WITH_CODE((0 == result),
973 "Failed to trim VDDCI table.", return result);
974
975 return 0;
976}
977
978static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
979 phm_ppt_v1_voltage_lookup_table *lookup_table)
980{
981 int i = 0;
982 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
983 struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
984
985 PP_ASSERT_WITH_CODE((0 != lookup_table->count),
986 "Voltage Lookup Table empty.", return -EINVAL);
987
988 vol_table->mask_low = 0;
989 vol_table->phase_delay = 0;
990
991 vol_table->count = lookup_table->count;
992
993 for (i = 0; i < vol_table->count; i++) {
994 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
995 vol_table->entries[i].smio_low = 0;
996 }
997
998 return 0;
999}
1000
1001/* ---- Voltage Tables ----
1002 * If the voltage table would be bigger than
1003 * what will fit into the state table on
1004 * the SMC keep only the higher entries.
1005 */
1006static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
1007 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
1008{
1009 unsigned int i, diff;
1010
1011 if (vol_table->count <= max_vol_steps)
1012 return;
1013
1014 diff = vol_table->count - max_vol_steps;
1015
1016 for (i = 0; i < max_vol_steps; i++)
1017 vol_table->entries[i] = vol_table->entries[i + diff];
1018
1019 vol_table->count = max_vol_steps;
1020
1021 return;
1022}
1023
1024/**
1025* Create Voltage Tables.
1026*
1027* @param hwmgr the address of the powerplay hardware manager.
1028* @return always 0
1029*/
1030static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1031{
1032 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1033 struct phm_ppt_v1_information *table_info =
1034 (struct phm_ppt_v1_information *)hwmgr->pptable;
1035 int result;
1036
1037 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1038 result = atomctrl_get_voltage_table_v3(hwmgr,
1039 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
1040 &(data->mvdd_voltage_table));
1041 PP_ASSERT_WITH_CODE((0 == result),
1042 "Failed to retrieve MVDD table.",
1043 return result);
1044 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1045 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1046 table_info->vdd_dep_on_mclk);
1047 PP_ASSERT_WITH_CODE((0 == result),
1048 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1049 return result;);
1050 }
1051
1052 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1053 result = atomctrl_get_voltage_table_v3(hwmgr,
1054 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1055 &(data->vddci_voltage_table));
1056 PP_ASSERT_WITH_CODE((0 == result),
1057 "Failed to retrieve VDDCI table.",
1058 return result);
1059 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1060 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1061 table_info->vdd_dep_on_mclk);
1062 PP_ASSERT_WITH_CODE((0 == result),
1063 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1064 return result);
1065 }
1066
1067 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1068 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1069 table_info->vddc_lookup_table);
1070 PP_ASSERT_WITH_CODE((0 == result),
1071 "Failed to retrieve SVI2 VDDC table from lookup table.",
1072 return result);
1073 }
1074
1075 PP_ASSERT_WITH_CODE(
1076 (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1077 "Too many voltage values for VDDC. Trimming to fit state table.",
1078 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1079 SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1080
1081 PP_ASSERT_WITH_CODE(
1082 (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1083 "Too many voltage values for VDDCI. Trimming to fit state table.",
1084 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1085 SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1086
1087 PP_ASSERT_WITH_CODE(
1088 (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1089 "Too many voltage values for MVDD. Trimming to fit state table.",
1090 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1091 SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1092
1093 return 0;
1094}
1095
1096static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1097{
1098 /* Program additional LP registers
1099 * that are no longer programmed by VBIOS
1100 */
1101 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1102 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1103 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1104 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1105 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1106 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1107 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1108 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1109 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1110 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1111 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1112 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1113 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1114 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1115
1116 return 0;
1117}
1118
1119/**
1120* Programs static screed detection parameters
1121*
1122* @param hwmgr the address of the powerplay hardware manager.
1123* @return always 0
1124*/
1125static int fiji_program_static_screen_threshold_parameters(
1126 struct pp_hwmgr *hwmgr)
1127{
1128 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1129
1130 /* Set static screen threshold unit */
1131 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1132 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1133 data->static_screen_threshold_unit);
1134 /* Set static screen threshold */
1135 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1136 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1137 data->static_screen_threshold);
1138
1139 return 0;
1140}
1141
1142/**
1143* Setup display gap for glitch free memory clock switching.
1144*
1145* @param hwmgr the address of the powerplay hardware manager.
1146* @return always 0
1147*/
1148static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1149{
1150 uint32_t displayGap =
1151 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1152 ixCG_DISPLAY_GAP_CNTL);
1153
1154 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1155 DISP_GAP, DISPLAY_GAP_IGNORE);
1156
1157 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1158 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1159
1160 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1161 ixCG_DISPLAY_GAP_CNTL, displayGap);
1162
1163 return 0;
1164}
1165
1166/**
1167* Programs activity state transition voting clients
1168*
1169* @param hwmgr the address of the powerplay hardware manager.
1170* @return always 0
1171*/
1172static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1173{
1174 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1175
1176 /* Clear reset for voting clients before enabling DPM */
1177 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1178 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1179 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1180 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1181
1182 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1183 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1184 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1185 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1186 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1187 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1188 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1189 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1190 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1191 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1193 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1194 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1195 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1196 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1197 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1198
1199 return 0;
1200}
1201
1202/**
1203* Get the location of various tables inside the FW image.
1204*
1205* @param hwmgr the address of the powerplay hardware manager.
1206* @return always 0
1207*/
1208static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1209{
1210 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1211 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1212 uint32_t tmp;
1213 int result;
1214 bool error = false;
1215
1216 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1217 SMU7_FIRMWARE_HEADER_LOCATION +
1218 offsetof(SMU73_Firmware_Header, DpmTable),
1219 &tmp, data->sram_end);
1220
1221 if (0 == result)
1222 data->dpm_table_start = tmp;
1223
1224 error |= (0 != result);
1225
1226 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1227 SMU7_FIRMWARE_HEADER_LOCATION +
1228 offsetof(SMU73_Firmware_Header, SoftRegisters),
1229 &tmp, data->sram_end);
1230
1231 if (!result) {
1232 data->soft_regs_start = tmp;
1233 smu_data->soft_regs_start = tmp;
1234 }
1235
1236 error |= (0 != result);
1237
1238 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1239 SMU7_FIRMWARE_HEADER_LOCATION +
1240 offsetof(SMU73_Firmware_Header, mcRegisterTable),
1241 &tmp, data->sram_end);
1242
1243 if (!result)
1244 data->mc_reg_table_start = tmp;
1245
1246 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1247 SMU7_FIRMWARE_HEADER_LOCATION +
1248 offsetof(SMU73_Firmware_Header, FanTable),
1249 &tmp, data->sram_end);
1250
1251 if (!result)
1252 data->fan_table_start = tmp;
1253
1254 error |= (0 != result);
1255
1256 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1257 SMU7_FIRMWARE_HEADER_LOCATION +
1258 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1259 &tmp, data->sram_end);
1260
1261 if (!result)
1262 data->arb_table_start = tmp;
1263
1264 error |= (0 != result);
1265
1266 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1267 SMU7_FIRMWARE_HEADER_LOCATION +
1268 offsetof(SMU73_Firmware_Header, Version),
1269 &tmp, data->sram_end);
1270
1271 if (!result)
1272 hwmgr->microcode_version_info.SMC = tmp;
1273
1274 error |= (0 != result);
1275
1276 return error ? -1 : 0;
1277}
1278
1279/* Copy one arb setting to another and then switch the active set.
1280 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1281 */
1282static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1283 uint32_t arb_src, uint32_t arb_dest)
1284{
1285 uint32_t mc_arb_dram_timing;
1286 uint32_t mc_arb_dram_timing2;
1287 uint32_t burst_time;
1288 uint32_t mc_cg_config;
1289
1290 switch (arb_src) {
1291 case MC_CG_ARB_FREQ_F0:
1292 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1293 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1294 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1295 break;
1296 case MC_CG_ARB_FREQ_F1:
1297 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1298 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1299 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1300 break;
1301 default:
1302 return -EINVAL;
1303 }
1304
1305 switch (arb_dest) {
1306 case MC_CG_ARB_FREQ_F0:
1307 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1308 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1309 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1310 break;
1311 case MC_CG_ARB_FREQ_F1:
1312 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1313 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1314 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1315 break;
1316 default:
1317 return -EINVAL;
1318 }
1319
1320 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1321 mc_cg_config |= 0x0000000F;
1322 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1323 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1324
1325 return 0;
1326}
1327
1328/**
1329* Initial switch from ARB F0->F1
1330*
1331* @param hwmgr the address of the powerplay hardware manager.
1332* @return always 0
1333* This function is to be called from the SetPowerState table.
1334*/
1335static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1336{
1337 return fiji_copy_and_switch_arb_sets(hwmgr,
1338 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1339}
1340
1341static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1342 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1343{
1344 int i;
1345 PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1346 "Fatal error, can not set up single DPM table entries "
1347 "to exceed max number!",);
1348
1349 dpm_table->count = count;
1350 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1351 dpm_table->dpm_levels[i].enabled = false;
1352
1353 return 0;
1354}
1355
1356static void fiji_setup_pcie_table_entry(
1357 struct fiji_single_dpm_table *dpm_table,
1358 uint32_t index, uint32_t pcie_gen,
1359 uint32_t pcie_lanes)
1360{
1361 dpm_table->dpm_levels[index].value = pcie_gen;
1362 dpm_table->dpm_levels[index].param1 = pcie_lanes;
1363 dpm_table->dpm_levels[index].enabled = 1;
1364}
1365
1366static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1367{
1368 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1369 struct phm_ppt_v1_information *table_info =
1370 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1371 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1372 uint32_t i, max_entry;
1373
1374 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1375 data->use_pcie_power_saving_levels), "No pcie performance levels!",
1376 return -EINVAL);
1377
1378 if (data->use_pcie_performance_levels &&
1379 !data->use_pcie_power_saving_levels) {
1380 data->pcie_gen_power_saving = data->pcie_gen_performance;
1381 data->pcie_lane_power_saving = data->pcie_lane_performance;
1382 } else if (!data->use_pcie_performance_levels &&
1383 data->use_pcie_power_saving_levels) {
1384 data->pcie_gen_performance = data->pcie_gen_power_saving;
1385 data->pcie_lane_performance = data->pcie_lane_power_saving;
1386 }
1387
1388 fiji_reset_single_dpm_table(hwmgr,
1389 &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1390
1391 if (pcie_table != NULL) {
1392 /* max_entry is used to make sure we reserve one PCIE level
1393 * for boot level (fix for A+A PSPP issue).
1394 * If PCIE table from PPTable have ULV entry + 8 entries,
1395 * then ignore the last entry.*/
1396 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1397 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1398 for (i = 1; i < max_entry; i++) {
1399 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1400 get_pcie_gen_support(data->pcie_gen_cap,
1401 pcie_table->entries[i].gen_speed),
1402 get_pcie_lane_support(data->pcie_lane_cap,
1403 pcie_table->entries[i].lane_width));
1404 }
1405 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1406 } else {
1407 /* Hardcode Pcie Table */
1408 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1409 get_pcie_gen_support(data->pcie_gen_cap,
1410 PP_Min_PCIEGen),
1411 get_pcie_lane_support(data->pcie_lane_cap,
1412 PP_Max_PCIELane));
1413 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1414 get_pcie_gen_support(data->pcie_gen_cap,
1415 PP_Min_PCIEGen),
1416 get_pcie_lane_support(data->pcie_lane_cap,
1417 PP_Max_PCIELane));
1418 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1419 get_pcie_gen_support(data->pcie_gen_cap,
1420 PP_Max_PCIEGen),
1421 get_pcie_lane_support(data->pcie_lane_cap,
1422 PP_Max_PCIELane));
1423 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1424 get_pcie_gen_support(data->pcie_gen_cap,
1425 PP_Max_PCIEGen),
1426 get_pcie_lane_support(data->pcie_lane_cap,
1427 PP_Max_PCIELane));
1428 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1429 get_pcie_gen_support(data->pcie_gen_cap,
1430 PP_Max_PCIEGen),
1431 get_pcie_lane_support(data->pcie_lane_cap,
1432 PP_Max_PCIELane));
1433 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1434 get_pcie_gen_support(data->pcie_gen_cap,
1435 PP_Max_PCIEGen),
1436 get_pcie_lane_support(data->pcie_lane_cap,
1437 PP_Max_PCIELane));
1438
1439 data->dpm_table.pcie_speed_table.count = 6;
1440 }
1441 /* Populate last level for boot PCIE level, but do not increment count. */
1442 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1443 data->dpm_table.pcie_speed_table.count,
1444 get_pcie_gen_support(data->pcie_gen_cap,
1445 PP_Min_PCIEGen),
1446 get_pcie_lane_support(data->pcie_lane_cap,
1447 PP_Max_PCIELane));
1448
1449 return 0;
1450}
1451
1452/*
1453 * This function is to initalize all DPM state tables
1454 * for SMU7 based on the dependency table.
1455 * Dynamic state patching function will then trim these
1456 * state tables to the allowed range based
1457 * on the power policy or external client requests,
1458 * such as UVD request, etc.
1459 */
1460static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1461{
1462 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1463 struct phm_ppt_v1_information *table_info =
1464 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1465 uint32_t i;
1466
1467 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1468 table_info->vdd_dep_on_sclk;
1469 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1470 table_info->vdd_dep_on_mclk;
1471
1472 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1473 "SCLK dependency table is missing. This table is mandatory",
1474 return -EINVAL);
1475 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1476 "SCLK dependency table has to have is missing. "
1477 "This table is mandatory",
1478 return -EINVAL);
1479
1480 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1481 "MCLK dependency table is missing. This table is mandatory",
1482 return -EINVAL);
1483 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1484 "MCLK dependency table has to have is missing. "
1485 "This table is mandatory",
1486 return -EINVAL);
1487
1488 /* clear the state table to reset everything to default */
1489 fiji_reset_single_dpm_table(hwmgr,
1490 &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1491 fiji_reset_single_dpm_table(hwmgr,
1492 &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1493
1494 /* Initialize Sclk DPM table based on allow Sclk values */
1495 data->dpm_table.sclk_table.count = 0;
1496 for (i = 0; i < dep_sclk_table->count; i++) {
1497 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1498 [data->dpm_table.sclk_table.count - 1].value !=
1499 dep_sclk_table->entries[i].clk) {
1500 data->dpm_table.sclk_table.dpm_levels
1501 [data->dpm_table.sclk_table.count].value =
1502 dep_sclk_table->entries[i].clk;
1503 data->dpm_table.sclk_table.dpm_levels
1504 [data->dpm_table.sclk_table.count].enabled =
1505 (i == 0) ? true : false;
1506 data->dpm_table.sclk_table.count++;
1507 }
1508 }
1509
1510 /* Initialize Mclk DPM table based on allow Mclk values */
1511 data->dpm_table.mclk_table.count = 0;
1512 for (i=0; i<dep_mclk_table->count; i++) {
1513 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1514 [data->dpm_table.mclk_table.count - 1].value !=
1515 dep_mclk_table->entries[i].clk) {
1516 data->dpm_table.mclk_table.dpm_levels
1517 [data->dpm_table.mclk_table.count].value =
1518 dep_mclk_table->entries[i].clk;
1519 data->dpm_table.mclk_table.dpm_levels
1520 [data->dpm_table.mclk_table.count].enabled =
1521 (i == 0) ? true : false;
1522 data->dpm_table.mclk_table.count++;
1523 }
1524 }
1525
1526 /* setup PCIE gen speed levels */
1527 fiji_setup_default_pcie_table(hwmgr);
1528
1529 /* save a copy of the default DPM table */
1530 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1531 sizeof(struct fiji_dpm_table));
1532
1533 return 0;
1534}
1535
1536/**
1537 * @brief PhwFiji_GetVoltageOrder
1538 * Returns index of requested voltage record in lookup(table)
1539 * @param lookup_table - lookup list to search in
1540 * @param voltage - voltage to look for
1541 * @return 0 on success
1542 */
1543uint8_t fiji_get_voltage_index(
1544 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1545{
1546 uint8_t count = (uint8_t) (lookup_table->count);
1547 uint8_t i;
1548
1549 PP_ASSERT_WITH_CODE((NULL != lookup_table),
1550 "Lookup Table empty.", return 0);
1551 PP_ASSERT_WITH_CODE((0 != count),
1552 "Lookup Table empty.", return 0);
1553
1554 for (i = 0; i < lookup_table->count; i++) {
1555 /* find first voltage equal or bigger than requested */
1556 if (lookup_table->entries[i].us_vdd >= voltage)
1557 return i;
1558 }
1559 /* voltage is bigger than max voltage in the table */
1560 return i - 1;
1561}
1562
1563/**
1564* Preparation of vddc and vddgfx CAC tables for SMC.
1565*
1566* @param hwmgr the address of the hardware manager
1567* @param table the SMC DPM table structure to be populated
1568* @return always 0
1569*/
1570static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1571 struct SMU73_Discrete_DpmTable *table)
1572{
1573 uint32_t count;
1574 uint8_t index;
1575 int result = 0;
1576 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1577 struct phm_ppt_v1_information *table_info =
1578 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1579 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1580 table_info->vddc_lookup_table;
1581 /* tables is already swapped, so in order to use the value from it,
1582 * we need to swap it back.
1583 * We are populating vddc CAC data to BapmVddc table
1584 * in split and merged mode
1585 */
1586 for( count = 0; count<lookup_table->count; count++) {
1587 index = fiji_get_voltage_index(lookup_table,
1588 data->vddc_voltage_table.entries[count].value);
1589 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1590 (lookup_table->entries[index].us_cac_low *
1591 VOLTAGE_SCALE)) / 25);
1592 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1593 (lookup_table->entries[index].us_cac_high *
1594 VOLTAGE_SCALE)) / 25);
1595 }
1596
1597 return result;
1598}
1599
1600/**
1601* Preparation of voltage tables for SMC.
1602*
1603* @param hwmgr the address of the hardware manager
1604* @param table the SMC DPM table structure to be populated
1605* @return always 0
1606*/
1607
1608int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1609 struct SMU73_Discrete_DpmTable *table)
1610{
1611 int result;
1612
1613 result = fiji_populate_cac_table(hwmgr, table);
1614 PP_ASSERT_WITH_CODE(0 == result,
1615 "can not populate CAC voltage tables to SMC",
1616 return -EINVAL);
1617
1618 return 0;
1619}
1620
1621static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1622 struct SMU73_Discrete_Ulv *state)
1623{
1624 int result = 0;
1625 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1626 struct phm_ppt_v1_information *table_info =
1627 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1628
1629 state->CcPwrDynRm = 0;
1630 state->CcPwrDynRm1 = 0;
1631
1632 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1633 state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1634 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1635
1636 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1637
1638 if (!result) {
1639 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1640 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1641 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1642 }
1643 return result;
1644}
1645
1646static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1647 struct SMU73_Discrete_DpmTable *table)
1648{
1649 return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1650}
1651
1652static int32_t fiji_get_dpm_level_enable_mask_value(
1653 struct fiji_single_dpm_table* dpm_table)
1654{
1655 int32_t i;
1656 int32_t mask = 0;
1657
1658 for (i = dpm_table->count; i > 0; i--) {
1659 mask = mask << 1;
1660 if (dpm_table->dpm_levels[i - 1].enabled)
1661 mask |= 0x1;
1662 else
1663 mask &= 0xFFFFFFFE;
1664 }
1665 return mask;
1666}
1667
1668static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1669 struct SMU73_Discrete_DpmTable *table)
1670{
1671 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1672 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1673 int i;
1674
1675 /* Index (dpm_table->pcie_speed_table.count)
1676 * is reserved for PCIE boot level. */
1677 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1678 table->LinkLevel[i].PcieGenSpeed =
1679 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1680 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1681 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1682 table->LinkLevel[i].EnabledForActivity = 1;
1683 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1684 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1685 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1686 }
1687
1688 data->smc_state_table.LinkLevelCount =
1689 (uint8_t)dpm_table->pcie_speed_table.count;
1690 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1691 fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1692
1693 return 0;
1694}
1695
1696/**
1697* Calculates the SCLK dividers using the provided engine clock
1698*
1699* @param hwmgr the address of the hardware manager
1700* @param clock the engine clock to use to populate the structure
1701* @param sclk the SMC SCLK structure to be populated
1702*/
1703static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1704 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1705{
1706 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1707 struct pp_atomctrl_clock_dividers_vi dividers;
1708 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1709 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1710 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1711 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1712 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1713 uint32_t ref_clock;
1714 uint32_t ref_divider;
1715 uint32_t fbdiv;
1716 int result;
1717
1718 /* get the engine clock dividers for this clock value */
1719 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
1720
1721 PP_ASSERT_WITH_CODE(result == 0,
1722 "Error retrieving Engine Clock dividers from VBIOS.",
1723 return result);
1724
1725 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1726 ref_clock = atomctrl_get_reference_clock(hwmgr);
1727 ref_divider = 1 + dividers.uc_pll_ref_div;
1728
1729 /* low 14 bits is fraction and high 12 bits is divider */
1730 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1731
1732 /* SPLL_FUNC_CNTL setup */
1733 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1734 SPLL_REF_DIV, dividers.uc_pll_ref_div);
1735 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1736 SPLL_PDIV_A, dividers.uc_pll_post_div);
1737
1738 /* SPLL_FUNC_CNTL_3 setup*/
1739 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1740 SPLL_FB_DIV, fbdiv);
1741
1742 /* set to use fractional accumulation*/
1743 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1744 SPLL_DITHEN, 1);
1745
1746 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1747 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1748 struct pp_atomctrl_internal_ss_info ssInfo;
1749
1750 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1751 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1752 vco_freq, &ssInfo)) {
1753 /*
1754 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1755 * ss_info.speed_spectrum_rate -- in unit of khz
1756 *
1757 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1758 */
1759 uint32_t clk_s = ref_clock * 5 /
1760 (ref_divider * ssInfo.speed_spectrum_rate);
1761 /* clkv = 2 * D * fbdiv / NS */
1762 uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1763 fbdiv / (clk_s * 10000);
1764
1765 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1766 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1767 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1768 CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1769 cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1770 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1771 }
1772 }
1773
1774 sclk->SclkFrequency = clock;
1775 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
1776 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
1777 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
1778 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
1779 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1780
1781 return 0;
1782}
1783
1784static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1785{
1786 uint32_t i;
1787 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1788 struct pp_atomctrl_voltage_table *vddci_table =
1789 &(data->vddci_voltage_table);
1790
1791 for (i = 0; i < vddci_table->count; i++) {
1792 if (vddci_table->entries[i].value >= vddci)
1793 return vddci_table->entries[i].value;
1794 }
1795
1796 PP_ASSERT_WITH_CODE(false,
1797 "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1798 return vddci_table->entries[i].value);
1799}
1800
1801static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1802 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1803 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1804{
1805 uint32_t i;
1806 uint16_t vddci;
1807 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1808
1809 *voltage = *mvdd = 0;
1810
1811 /* clock - voltage dependency table is empty table */
1812 if (dep_table->count == 0)
1813 return -EINVAL;
1814
1815 for (i = 0; i < dep_table->count; i++) {
1816 /* find first sclk bigger than request */
1817 if (dep_table->entries[i].clk >= clock) {
1818 *voltage |= (dep_table->entries[i].vddc *
1819 VOLTAGE_SCALE) << VDDC_SHIFT;
1820 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1821 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1822 VOLTAGE_SCALE) << VDDCI_SHIFT;
1823 else if (dep_table->entries[i].vddci)
1824 *voltage |= (dep_table->entries[i].vddci *
1825 VOLTAGE_SCALE) << VDDCI_SHIFT;
1826 else {
1827 vddci = fiji_find_closest_vddci(hwmgr,
1828 (dep_table->entries[i].vddc -
1829 (uint16_t)data->vddc_vddci_delta));
1830 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1831 }
1832
1833 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1834 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1835 VOLTAGE_SCALE;
1836 else if (dep_table->entries[i].mvdd)
1837 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1838 VOLTAGE_SCALE;
1839
1840 *voltage |= 1 << PHASES_SHIFT;
1841 return 0;
1842 }
1843 }
1844
1845 /* sclk is bigger than max sclk in the dependence table */
1846 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1847
1848 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1849 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1850 VOLTAGE_SCALE) << VDDCI_SHIFT;
1851 else if (dep_table->entries[i-1].vddci) {
1852 vddci = fiji_find_closest_vddci(hwmgr,
1853 (dep_table->entries[i].vddc -
1854 (uint16_t)data->vddc_vddci_delta));
1855 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1856 }
1857
1858 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1859 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1860 else if (dep_table->entries[i].mvdd)
1861 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1862
1863 return 0;
1864}
1865/**
1866* Populates single SMC SCLK structure using the provided engine clock
1867*
1868* @param hwmgr the address of the hardware manager
1869* @param clock the engine clock to use to populate the structure
1870* @param sclk the SMC SCLK structure to be populated
1871*/
1872
1873static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1874 uint32_t clock, uint16_t sclk_al_threshold,
1875 struct SMU73_Discrete_GraphicsLevel *level)
1876{
1877 int result;
1878 /* PP_Clocks minClocks; */
1879 uint32_t threshold, mvdd;
1880 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1881 struct phm_ppt_v1_information *table_info =
1882 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1883
1884 result = fiji_calculate_sclk_params(hwmgr, clock, level);
1885
1886 /* populate graphics levels */
1887 result = fiji_get_dependency_volt_by_clk(hwmgr,
1888 table_info->vdd_dep_on_sclk, clock,
1889 &level->MinVoltage, &mvdd);
1890 PP_ASSERT_WITH_CODE((0 == result),
1891 "can not find VDDC voltage value for "
1892 "VDDC engine clock dependency table",
1893 return result);
1894
1895 level->SclkFrequency = clock;
1896 level->ActivityLevel = sclk_al_threshold;
1897 level->CcPwrDynRm = 0;
1898 level->CcPwrDynRm1 = 0;
1899 level->EnabledForActivity = 0;
1900 level->EnabledForThrottle = 1;
1901 level->UpHyst = 10;
1902 level->DownHyst = 0;
1903 level->VoltageDownHyst = 0;
1904 level->PowerThrottle = 0;
1905
1906 threshold = clock * data->fast_watermark_threshold / 100;
1907
1908 /*
1909 * TODO: get minimum clocks from dal configaration
1910 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1911 */
1912 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1913
1914 /* get level->DeepSleepDivId
1915 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1916 {
1917 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1918 } */
1919
1920 /* Default to slow, highest DPM level will be
1921 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1922 */
1923 level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1924
1925 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1926 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1927 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1928 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1929 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1930 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1931 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1932 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1933 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1934
1935 return 0;
1936}
1937/**
1938* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1939*
1940* @param hwmgr the address of the hardware manager
1941*/
1942static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1943{
1944 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1945 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1946 struct phm_ppt_v1_information *table_info =
1947 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1948 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1949 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1950 int result = 0;
1951 uint32_t array = data->dpm_table_start +
1952 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1953 uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1954 SMU73_MAX_LEVELS_GRAPHICS;
1955 struct SMU73_Discrete_GraphicsLevel *levels =
1956 data->smc_state_table.GraphicsLevel;
1957 uint32_t i, max_entry;
1958 uint8_t hightest_pcie_level_enabled = 0,
1959 lowest_pcie_level_enabled = 0,
1960 mid_pcie_level_enabled = 0,
1961 count = 0;
1962
1963 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1964 result = fiji_populate_single_graphic_level(hwmgr,
1965 dpm_table->sclk_table.dpm_levels[i].value,
1966 (uint16_t)data->activity_target[i],
1967 &levels[i]);
1968 if (result)
1969 return result;
1970
1971 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1972 if (i > 1)
1973 levels[i].DeepSleepDivId = 0;
1974 }
1975
1976 /* Only enable level 0 for now.*/
1977 levels[0].EnabledForActivity = 1;
1978
1979 /* set highest level watermark to high */
1980 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1981 PPSMC_DISPLAY_WATERMARK_HIGH;
1982
1983 data->smc_state_table.GraphicsDpmLevelCount =
1984 (uint8_t)dpm_table->sclk_table.count;
1985 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1986 fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1987
1988 if (pcie_table != NULL) {
1989 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1990 "There must be 1 or more PCIE levels defined in PPTable.",
1991 return -EINVAL);
1992 max_entry = pcie_entry_cnt - 1;
1993 for (i = 0; i < dpm_table->sclk_table.count; i++)
1994 levels[i].pcieDpmLevel =
1995 (uint8_t) ((i < max_entry)? i : max_entry);
1996 } else {
1997 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1998 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1999 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
2000 hightest_pcie_level_enabled++;
2001
2002 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2003 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2004 (1 << lowest_pcie_level_enabled)) == 0 ))
2005 lowest_pcie_level_enabled++;
2006
2007 while ((count < hightest_pcie_level_enabled) &&
2008 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2009 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
2010 count++;
2011
2012 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
2013 hightest_pcie_level_enabled?
2014 (lowest_pcie_level_enabled + 1 + count) :
2015 hightest_pcie_level_enabled;
2016
2017 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2018 for(i = 2; i < dpm_table->sclk_table.count; i++)
2019 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2020
2021 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2022 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2023
2024 /* set pcieDpmLevel to mid_pcie_level_enabled */
2025 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2026 }
2027 /* level count will send to smc once at init smc table and never change */
2028 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2029 (uint32_t)array_size, data->sram_end);
2030
2031 return result;
2032}
2033
2034/**
2035 * MCLK Frequency Ratio
2036 * SEQ_CG_RESP Bit[31:24] - 0x0
2037 * Bit[27:24] \96 DDR3 Frequency ratio
2038 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
2039 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
2040 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
2041 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
2042 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
2043 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
2044 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
2045 * 400 < 0x7 <= 450MHz, 800 < 0xF
2046 */
2047static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2048{
2049 if (mem_clock <= 10000) return 0x0;
2050 if (mem_clock <= 15000) return 0x1;
2051 if (mem_clock <= 20000) return 0x2;
2052 if (mem_clock <= 25000) return 0x3;
2053 if (mem_clock <= 30000) return 0x4;
2054 if (mem_clock <= 35000) return 0x5;
2055 if (mem_clock <= 40000) return 0x6;
2056 if (mem_clock <= 45000) return 0x7;
2057 if (mem_clock <= 50000) return 0x8;
2058 if (mem_clock <= 55000) return 0x9;
2059 if (mem_clock <= 60000) return 0xa;
2060 if (mem_clock <= 65000) return 0xb;
2061 if (mem_clock <= 70000) return 0xc;
2062 if (mem_clock <= 75000) return 0xd;
2063 if (mem_clock <= 80000) return 0xe;
2064 /* mem_clock > 800MHz */
2065 return 0xf;
2066}
2067
2068/**
2069* Populates the SMC MCLK structure using the provided memory clock
2070*
2071* @param hwmgr the address of the hardware manager
2072* @param clock the memory clock to use to populate the structure
2073* @param sclk the SMC SCLK structure to be populated
2074*/
2075static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2076 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2077{
2078 struct pp_atomctrl_memory_clock_param mem_param;
2079 int result;
2080
2081 result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2082 PP_ASSERT_WITH_CODE((0 == result),
2083 "Failed to get Memory PLL Dividers.",);
2084
2085 /* Save the result data to outpupt memory level structure */
2086 mclk->MclkFrequency = clock;
2087 mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
2088 mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
2089
2090 return result;
2091}
2092
2093static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2094 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2095{
2096 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2097 struct phm_ppt_v1_information *table_info =
2098 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2099 int result = 0;
2100
2101 if (table_info->vdd_dep_on_mclk) {
2102 result = fiji_get_dependency_volt_by_clk(hwmgr,
2103 table_info->vdd_dep_on_mclk, clock,
2104 &mem_level->MinVoltage, &mem_level->MinMvdd);
2105 PP_ASSERT_WITH_CODE((0 == result),
2106 "can not find MinVddc voltage value from memory "
2107 "VDDC voltage dependency table", return result);
2108 }
2109
2110 mem_level->EnabledForThrottle = 1;
2111 mem_level->EnabledForActivity = 0;
2112 mem_level->UpHyst = 0;
2113 mem_level->DownHyst = 100;
2114 mem_level->VoltageDownHyst = 0;
2115 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2116 mem_level->StutterEnable = false;
2117
2118 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2119
2120 /* enable stutter mode if all the follow condition applied
2121 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2122 * &(data->DisplayTiming.numExistingDisplays));
2123 */
2124 data->display_timing.num_existing_displays = 1;
2125
2126 if ((data->mclk_stutter_mode_threshold) &&
2127 (clock <= data->mclk_stutter_mode_threshold) &&
2128 (!data->is_uvd_enabled) &&
2129 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2130 STUTTER_ENABLE) & 0x1))
2131 mem_level->StutterEnable = true;
2132
2133 result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2134 if (!result) {
2135 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2136 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2137 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2138 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2139 }
2140 return result;
2141}
2142
2143/**
2144* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2145*
2146* @param hwmgr the address of the hardware manager
2147*/
2148static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2149{
2150 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2151 struct fiji_dpm_table *dpm_table = &data->dpm_table;
2152 int result;
2153 /* populate MCLK dpm table to SMU7 */
2154 uint32_t array = data->dpm_table_start +
2155 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2156 uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2157 SMU73_MAX_LEVELS_MEMORY;
2158 struct SMU73_Discrete_MemoryLevel *levels =
2159 data->smc_state_table.MemoryLevel;
2160 uint32_t i;
2161
2162 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2163 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2164 "can not populate memory level as memory clock is zero",
2165 return -EINVAL);
2166 result = fiji_populate_single_memory_level(hwmgr,
2167 dpm_table->mclk_table.dpm_levels[i].value,
2168 &levels[i]);
2169 if (result)
2170 return result;
2171 }
2172
2173 /* Only enable level 0 for now. */
2174 levels[0].EnabledForActivity = 1;
2175
2176 /* in order to prevent MC activity from stutter mode to push DPM up.
2177 * the UVD change complements this by putting the MCLK in
2178 * a higher state by default such that we are not effected by
2179 * up threshold or and MCLK DPM latency.
2180 */
2181 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2182 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2183
2184 data->smc_state_table.MemoryDpmLevelCount =
2185 (uint8_t)dpm_table->mclk_table.count;
2186 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2187 fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2188 /* set highest level watermark to high */
2189 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2190 PPSMC_DISPLAY_WATERMARK_HIGH;
2191
2192 /* level count will send to smc once at init smc table and never change */
2193 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2194 (uint32_t)array_size, data->sram_end);
2195
2196 return result;
2197}
2198
2199/**
2200* Populates the SMC MVDD structure using the provided memory clock.
2201*
2202* @param hwmgr the address of the hardware manager
2203* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2204* @param voltage the SMC VOLTAGE structure to be populated
2205*/
2206int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2207 uint32_t mclk, SMIO_Pattern *smio_pat)
2208{
2209 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2210 struct phm_ppt_v1_information *table_info =
2211 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2212 uint32_t i = 0;
2213
2214 if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2215 /* find mvdd value which clock is more than request */
2216 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2217 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2218 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2219 break;
2220 }
2221 }
2222 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2223 "MVDD Voltage is outside the supported range.",
2224 return -EINVAL);
2225 } else
2226 return -EINVAL;
2227
2228 return 0;
2229}
2230
2231static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2232 SMU73_Discrete_DpmTable *table)
2233{
2234 int result = 0;
2235 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2236 struct phm_ppt_v1_information *table_info =
2237 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2238 struct pp_atomctrl_clock_dividers_vi dividers;
2239 SMIO_Pattern vol_level;
2240 uint32_t mvdd;
2241 uint16_t us_mvdd;
2242 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2243 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2244
2245 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2246
2247 if (!data->sclk_dpm_key_disabled) {
2248 /* Get MinVoltage and Frequency from DPM0,
2249 * already converted to SMC_UL */
2250 table->ACPILevel.SclkFrequency =
2251 data->dpm_table.sclk_table.dpm_levels[0].value;
2252 result = fiji_get_dependency_volt_by_clk(hwmgr,
2253 table_info->vdd_dep_on_sclk,
2254 table->ACPILevel.SclkFrequency,
2255 &table->ACPILevel.MinVoltage, &mvdd);
2256 PP_ASSERT_WITH_CODE((0 == result),
2257 "Cannot find ACPI VDDC voltage value "
2258 "in Clock Dependency Table",);
2259 } else {
2260 table->ACPILevel.SclkFrequency =
2261 data->vbios_boot_state.sclk_bootup_value;
2262 table->ACPILevel.MinVoltage =
2263 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2264 }
2265
2266 /* get the engine clock dividers for this clock value */
2267 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2268 table->ACPILevel.SclkFrequency, &dividers);
2269 PP_ASSERT_WITH_CODE(result == 0,
2270 "Error retrieving Engine Clock dividers from VBIOS.",
2271 return result);
2272
2273 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2274 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2275 table->ACPILevel.DeepSleepDivId = 0;
2276
2277 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2278 SPLL_PWRON, 0);
2279 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2280 SPLL_RESET, 1);
2281 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2282 SCLK_MUX_SEL, 4);
2283
2284 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2285 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2286 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2287 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2288 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2289 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2290 table->ACPILevel.CcPwrDynRm = 0;
2291 table->ACPILevel.CcPwrDynRm1 = 0;
2292
2293 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2294 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2295 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2296 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2297 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2298 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2299 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2300 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2301 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2302 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2303 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2304
2305 if (!data->mclk_dpm_key_disabled) {
2306 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2307 table->MemoryACPILevel.MclkFrequency =
2308 data->dpm_table.mclk_table.dpm_levels[0].value;
2309 result = fiji_get_dependency_volt_by_clk(hwmgr,
2310 table_info->vdd_dep_on_mclk,
2311 table->MemoryACPILevel.MclkFrequency,
2312 &table->MemoryACPILevel.MinVoltage, &mvdd);
2313 PP_ASSERT_WITH_CODE((0 == result),
2314 "Cannot find ACPI VDDCI voltage value "
2315 "in Clock Dependency Table",);
2316 } else {
2317 table->MemoryACPILevel.MclkFrequency =
2318 data->vbios_boot_state.mclk_bootup_value;
2319 table->MemoryACPILevel.MinVoltage =
2320 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2321 }
2322
2323 us_mvdd = 0;
2324 if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2325 (data->mclk_dpm_key_disabled))
2326 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2327 else {
2328 if (!fiji_populate_mvdd_value(hwmgr,
2329 data->dpm_table.mclk_table.dpm_levels[0].value,
2330 &vol_level))
2331 us_mvdd = vol_level.Voltage;
2332 }
2333
2334 table->MemoryACPILevel.MinMvdd =
2335 PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2336
2337 table->MemoryACPILevel.EnabledForThrottle = 0;
2338 table->MemoryACPILevel.EnabledForActivity = 0;
2339 table->MemoryACPILevel.UpHyst = 0;
2340 table->MemoryACPILevel.DownHyst = 100;
2341 table->MemoryACPILevel.VoltageDownHyst = 0;
2342 table->MemoryACPILevel.ActivityLevel =
2343 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2344
2345 table->MemoryACPILevel.StutterEnable = false;
2346 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2347 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2348
2349 return result;
2350}
2351
2352static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2353 SMU73_Discrete_DpmTable *table)
2354{
2355 int result = -EINVAL;
2356 uint8_t count;
2357 struct pp_atomctrl_clock_dividers_vi dividers;
2358 struct phm_ppt_v1_information *table_info =
2359 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2360 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2361 table_info->mm_dep_table;
2362 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2363
2364 table->VceLevelCount = (uint8_t)(mm_table->count);
2365 table->VceBootLevel = 0;
2366
2367 for(count = 0; count < table->VceLevelCount; count++) {
2368 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2369 table->VceLevel[count].MinVoltage |=
2370 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2371 table->VceLevel[count].MinVoltage |=
2372 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2373 VOLTAGE_SCALE) << VDDCI_SHIFT;
2374 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2375
2376 /*retrieve divider value for VBIOS */
2377 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2378 table->VceLevel[count].Frequency, &dividers);
2379 PP_ASSERT_WITH_CODE((0 == result),
2380 "can not find divide id for VCE engine clock",
2381 return result);
2382
2383 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2384
2385 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2386 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2387 }
2388 return result;
2389}
2390
2391static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2392 SMU73_Discrete_DpmTable *table)
2393{
2394 int result = -EINVAL;
2395 uint8_t count;
2396 struct pp_atomctrl_clock_dividers_vi dividers;
2397 struct phm_ppt_v1_information *table_info =
2398 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2399 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2400 table_info->mm_dep_table;
2401 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2402
2403 table->AcpLevelCount = (uint8_t)(mm_table->count);
2404 table->AcpBootLevel = 0;
2405
2406 for (count = 0; count < table->AcpLevelCount; count++) {
2407 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2408 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2409 VOLTAGE_SCALE) << VDDC_SHIFT;
2410 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2411 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2412 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2413
2414 /* retrieve divider value for VBIOS */
2415 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2416 table->AcpLevel[count].Frequency, &dividers);
2417 PP_ASSERT_WITH_CODE((0 == result),
2418 "can not find divide id for engine clock", return result);
2419
2420 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2421
2422 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2423 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2424 }
2425 return result;
2426}
2427
2428static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2429 SMU73_Discrete_DpmTable *table)
2430{
2431 int result = -EINVAL;
2432 uint8_t count;
2433 struct pp_atomctrl_clock_dividers_vi dividers;
2434 struct phm_ppt_v1_information *table_info =
2435 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2436 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2437 table_info->mm_dep_table;
2438 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2439
2440 table->SamuBootLevel = 0;
2441 table->SamuLevelCount = (uint8_t)(mm_table->count);
2442
2443 for (count = 0; count < table->SamuLevelCount; count++) {
2444 /* not sure whether we need evclk or not */
2445 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2446 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2447 VOLTAGE_SCALE) << VDDC_SHIFT;
2448 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2449 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2450 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2451
2452 /* retrieve divider value for VBIOS */
2453 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2454 table->SamuLevel[count].Frequency, &dividers);
2455 PP_ASSERT_WITH_CODE((0 == result),
2456 "can not find divide id for samu clock", return result);
2457
2458 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2459
2460 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2461 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2462 }
2463 return result;
2464}
2465
2466static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2467 int32_t eng_clock, int32_t mem_clock,
2468 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2469{
2470 uint32_t dram_timing;
2471 uint32_t dram_timing2;
2472 uint32_t burstTime;
2473 ULONG state, trrds, trrdl;
2474 int result;
2475
2476 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2477 eng_clock, mem_clock);
2478 PP_ASSERT_WITH_CODE(result == 0,
2479 "Error calling VBIOS to set DRAM_TIMING.", return result);
2480
2481 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2482 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2483 burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2484
2485 state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2486 trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2487 trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2488
2489 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
2490 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2491 arb_regs->McArbBurstTime = (uint8_t)burstTime;
2492 arb_regs->TRRDS = (uint8_t)trrds;
2493 arb_regs->TRRDL = (uint8_t)trrdl;
2494
2495 return 0;
2496}
2497
2498static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2499{
2500 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2501 struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2502 uint32_t i, j;
2503 int result = 0;
2504
2505 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2506 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2507 result = fiji_populate_memory_timing_parameters(hwmgr,
2508 data->dpm_table.sclk_table.dpm_levels[i].value,
2509 data->dpm_table.mclk_table.dpm_levels[j].value,
2510 &arb_regs.entries[i][j]);
2511 if (result)
2512 break;
2513 }
2514 }
2515
2516 if (!result)
2517 result = fiji_copy_bytes_to_smc(
2518 hwmgr->smumgr,
2519 data->arb_table_start,
2520 (uint8_t *)&arb_regs,
2521 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2522 data->sram_end);
2523 return result;
2524}
2525
2526static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2527 struct SMU73_Discrete_DpmTable *table)
2528{
2529 int result = -EINVAL;
2530 uint8_t count;
2531 struct pp_atomctrl_clock_dividers_vi dividers;
2532 struct phm_ppt_v1_information *table_info =
2533 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2534 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2535 table_info->mm_dep_table;
2536 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2537
2538 table->UvdLevelCount = (uint8_t)(mm_table->count);
2539 table->UvdBootLevel = 0;
2540
2541 for (count = 0; count < table->UvdLevelCount; count++) {
2542 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2543 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2544 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2545 VOLTAGE_SCALE) << VDDC_SHIFT;
2546 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2547 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2548 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2549
2550 /* retrieve divider value for VBIOS */
2551 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2552 table->UvdLevel[count].VclkFrequency, &dividers);
2553 PP_ASSERT_WITH_CODE((0 == result),
2554 "can not find divide id for Vclk clock", return result);
2555
2556 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2557
2558 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2559 table->UvdLevel[count].DclkFrequency, &dividers);
2560 PP_ASSERT_WITH_CODE((0 == result),
2561 "can not find divide id for Dclk clock", return result);
2562
2563 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2564
2565 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2566 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2567 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2568
2569 }
2570 return result;
2571}
2572
2573static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2574 uint32_t value, uint32_t *boot_level)
2575{
2576 int result = -EINVAL;
2577 uint32_t i;
2578
2579 for (i = 0; i < table->count; i++) {
2580 if (value == table->dpm_levels[i].value) {
2581 *boot_level = i;
2582 result = 0;
2583 }
2584 }
2585 return result;
2586}
2587
2588static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2589 struct SMU73_Discrete_DpmTable *table)
2590{
2591 int result = 0;
2592 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2593
2594 table->GraphicsBootLevel = 0;
2595 table->MemoryBootLevel = 0;
2596
2597 /* find boot level from dpm table */
2598 result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2599 data->vbios_boot_state.sclk_bootup_value,
2600 (uint32_t *)&(table->GraphicsBootLevel));
2601
2602 result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2603 data->vbios_boot_state.mclk_bootup_value,
2604 (uint32_t *)&(table->MemoryBootLevel));
2605
2606 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
2607 VOLTAGE_SCALE;
2608 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2609 VOLTAGE_SCALE;
2610 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
2611 VOLTAGE_SCALE;
2612
2613 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2614 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2615 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2616
2617 return 0;
2618}
2619
2620static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2621{
2622 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2623 struct phm_ppt_v1_information *table_info =
2624 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2625 uint8_t count, level;
2626
2627 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2628 for (level = 0; level < count; level++) {
2629 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2630 data->vbios_boot_state.sclk_bootup_value) {
2631 data->smc_state_table.GraphicsBootLevel = level;
2632 break;
2633 }
2634 }
2635
2636 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2637 for (level = 0; level < count; level++) {
2638 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2639 data->vbios_boot_state.mclk_bootup_value) {
2640 data->smc_state_table.MemoryBootLevel = level;
2641 break;
2642 }
2643 }
2644
2645 return 0;
2646}
2647
2648static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2649{
2650 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2651 volt_with_cks, value;
2652 uint16_t clock_freq_u16;
2653 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2654 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2655 volt_offset = 0;
2656 struct phm_ppt_v1_information *table_info =
2657 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2658 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2659 table_info->vdd_dep_on_sclk;
2660
2661 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2662
2663 /* Read SMU_Eefuse to read and calculate RO and determine
2664 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2665 */
2666 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2667 ixSMU_EFUSE_0 + (146 * 4));
2668 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2669 ixSMU_EFUSE_0 + (148 * 4));
2670 efuse &= 0xFF000000;
2671 efuse = efuse >> 24;
2672 efuse2 &= 0xF;
2673
2674 if (efuse2 == 1)
2675 ro = (2300 - 1350) * efuse / 255 + 1350;
2676 else
2677 ro = (2500 - 1000) * efuse / 255 + 1000;
2678
2679 if (ro >= 1660)
2680 type = 0;
2681 else
2682 type = 1;
2683
2684 /* Populate Stretch amount */
2685 data->smc_state_table.ClockStretcherAmount = stretch_amount;
2686
2687 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2688 for (i = 0; i < sclk_table->count; i++) {
2689 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2690 sclk_table->entries[i].cks_enable << i;
2691 volt_without_cks = (uint32_t)((14041 *
2692 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2693 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2694 volt_with_cks = (uint32_t)((13946 *
2695 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2696 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2697 if (volt_without_cks >= volt_with_cks)
2698 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2699 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2700 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2701 }
2702
2703 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2704 STRETCH_ENABLE, 0x0);
2705 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2706 masterReset, 0x1);
2707 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2708 staticEnable, 0x1);
2709 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2710 masterReset, 0x0);
2711
2712 /* Populate CKS Lookup Table */
2713 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2714 stretch_amount2 = 0;
2715 else if (stretch_amount == 3 || stretch_amount == 4)
2716 stretch_amount2 = 1;
2717 else {
2718 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2719 PHM_PlatformCaps_ClockStretcher);
2720 PP_ASSERT_WITH_CODE(false,
2721 "Stretch Amount in PPTable not supported\n",
2722 return -EINVAL);
2723 }
2724
2725 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2726 ixPWR_CKS_CNTL);
2727 value &= 0xFFC2FF87;
2728 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2729 fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2730 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2731 fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2732 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2733 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2734 SclkFrequency) / 100);
2735 if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2736 clock_freq_u16 &&
2737 fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2738 clock_freq_u16) {
2739 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2740 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2741 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2742 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2743 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2744 value |= (fiji_clock_stretch_amount_conversion
2745 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2746 [stretch_amount]) << 3;
2747 }
2748 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2749 CKS_LOOKUPTableEntry[0].minFreq);
2750 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2751 CKS_LOOKUPTableEntry[0].maxFreq);
2752 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2753 fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2754 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2755 (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2756
2757 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2758 ixPWR_CKS_CNTL, value);
2759
2760 /* Populate DDT Lookup Table */
2761 for (i = 0; i < 4; i++) {
2762 /* Assign the minimum and maximum VID stored
2763 * in the last row of Clock Stretcher Voltage Table.
2764 */
2765 data->smc_state_table.ClockStretcherDataTable.
2766 ClockStretcherDataTableEntry[i].minVID =
2767 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2768 data->smc_state_table.ClockStretcherDataTable.
2769 ClockStretcherDataTableEntry[i].maxVID =
2770 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2771 /* Loop through each SCLK and check the frequency
2772 * to see if it lies within the frequency for clock stretcher.
2773 */
2774 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2775 cks_setting = 0;
2776 clock_freq = PP_SMC_TO_HOST_UL(
2777 data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2778 /* Check the allowed frequency against the sclk level[j].
2779 * Sclk's endianness has already been converted,
2780 * and it's in 10Khz unit,
2781 * as opposed to Data table, which is in Mhz unit.
2782 */
2783 if (clock_freq >=
2784 (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2785 cks_setting |= 0x2;
2786 if (clock_freq <
2787 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2788 cks_setting |= 0x1;
2789 }
2790 data->smc_state_table.ClockStretcherDataTable.
2791 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2792 }
2793 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2794 ClockStretcherDataTable.
2795 ClockStretcherDataTableEntry[i].setting);
2796 }
2797
2798 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2799 value &= 0xFFFFFFFE;
2800 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2801
2802 return 0;
2803}
2804
2805/**
2806* Populates the SMC VRConfig field in DPM table.
2807*
2808* @param hwmgr the address of the hardware manager
2809* @param table the SMC DPM table structure to be populated
2810* @return always 0
2811*/
2812static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2813 struct SMU73_Discrete_DpmTable *table)
2814{
2815 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2816 uint16_t config;
2817
2818 config = VR_MERGED_WITH_VDDC;
2819 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2820
2821 /* Set Vddc Voltage Controller */
2822 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2823 config = VR_SVI2_PLANE_1;
2824 table->VRConfig |= config;
2825 } else {
2826 PP_ASSERT_WITH_CODE(false,
2827 "VDDC should be on SVI2 control in merged mode!",);
2828 }
2829 /* Set Vddci Voltage Controller */
2830 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2831 config = VR_SVI2_PLANE_2; /* only in merged mode */
2832 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2833 } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2834 config = VR_SMIO_PATTERN_1;
2835 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2836 } else {
2837 config = VR_STATIC_VOLTAGE;
2838 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2839 }
2840 /* Set Mvdd Voltage Controller */
2841 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2842 config = VR_SVI2_PLANE_2;
2843 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2844 } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2845 config = VR_SMIO_PATTERN_2;
2846 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2847 } else {
2848 config = VR_STATIC_VOLTAGE;
2849 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2850 }
2851
2852 return 0;
2853}
2854
2855/**
2856* Initializes the SMC table and uploads it
2857*
2858* @param hwmgr the address of the powerplay hardware manager.
2859* @param pInput the pointer to input data (PowerState)
2860* @return always 0
2861*/
2862static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2863{
2864 int result;
2865 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2866 struct phm_ppt_v1_information *table_info =
2867 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2868 struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2869 const struct fiji_ulv_parm *ulv = &(data->ulv);
2870 uint8_t i;
2871 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2872
2873 result = fiji_setup_default_dpm_tables(hwmgr);
2874 PP_ASSERT_WITH_CODE(0 == result,
2875 "Failed to setup default DPM tables!", return result);
2876
2877 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2878 fiji_populate_smc_voltage_tables(hwmgr, table);
2879
2880 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2881 PHM_PlatformCaps_AutomaticDCTransition))
2882 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2883
2884 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2885 PHM_PlatformCaps_StepVddc))
2886 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2887
2888 if (data->is_memory_gddr5)
2889 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2890
2891 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2892 result = fiji_populate_ulv_state(hwmgr, table);
2893 PP_ASSERT_WITH_CODE(0 == result,
2894 "Failed to initialize ULV state!", return result);
2895 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2896 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2897 }
2898
2899 result = fiji_populate_smc_link_level(hwmgr, table);
2900 PP_ASSERT_WITH_CODE(0 == result,
2901 "Failed to initialize Link Level!", return result);
2902
2903 result = fiji_populate_all_graphic_levels(hwmgr);
2904 PP_ASSERT_WITH_CODE(0 == result,
2905 "Failed to initialize Graphics Level!", return result);
2906
2907 result = fiji_populate_all_memory_levels(hwmgr);
2908 PP_ASSERT_WITH_CODE(0 == result,
2909 "Failed to initialize Memory Level!", return result);
2910
2911 result = fiji_populate_smc_acpi_level(hwmgr, table);
2912 PP_ASSERT_WITH_CODE(0 == result,
2913 "Failed to initialize ACPI Level!", return result);
2914
2915 result = fiji_populate_smc_vce_level(hwmgr, table);
2916 PP_ASSERT_WITH_CODE(0 == result,
2917 "Failed to initialize VCE Level!", return result);
2918
2919 result = fiji_populate_smc_acp_level(hwmgr, table);
2920 PP_ASSERT_WITH_CODE(0 == result,
2921 "Failed to initialize ACP Level!", return result);
2922
2923 result = fiji_populate_smc_samu_level(hwmgr, table);
2924 PP_ASSERT_WITH_CODE(0 == result,
2925 "Failed to initialize SAMU Level!", return result);
2926
2927 /* Since only the initial state is completely set up at this point
2928 * (the other states are just copies of the boot state) we only
2929 * need to populate the ARB settings for the initial state.
2930 */
2931 result = fiji_program_memory_timing_parameters(hwmgr);
2932 PP_ASSERT_WITH_CODE(0 == result,
2933 "Failed to Write ARB settings for the initial state.", return result);
2934
2935 result = fiji_populate_smc_uvd_level(hwmgr, table);
2936 PP_ASSERT_WITH_CODE(0 == result,
2937 "Failed to initialize UVD Level!", return result);
2938
2939 result = fiji_populate_smc_boot_level(hwmgr, table);
2940 PP_ASSERT_WITH_CODE(0 == result,
2941 "Failed to initialize Boot Level!", return result);
2942
2943 result = fiji_populate_smc_initailial_state(hwmgr);
2944 PP_ASSERT_WITH_CODE(0 == result,
2945 "Failed to initialize Boot State!", return result);
2946
2947 result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2948 PP_ASSERT_WITH_CODE(0 == result,
2949 "Failed to populate BAPM Parameters!", return result);
2950
2951 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2952 PHM_PlatformCaps_ClockStretcher)) {
2953 result = fiji_populate_clock_stretcher_data_table(hwmgr);
2954 PP_ASSERT_WITH_CODE(0 == result,
2955 "Failed to populate Clock Stretcher Data Table!",
2956 return result);
2957 }
2958
2959 table->GraphicsVoltageChangeEnable = 1;
2960 table->GraphicsThermThrottleEnable = 1;
2961 table->GraphicsInterval = 1;
2962 table->VoltageInterval = 1;
2963 table->ThermalInterval = 1;
2964 table->TemperatureLimitHigh =
2965 table_info->cac_dtp_table->usTargetOperatingTemp *
2966 FIJI_Q88_FORMAT_CONVERSION_UNIT;
2967 table->TemperatureLimitLow =
2968 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2969 FIJI_Q88_FORMAT_CONVERSION_UNIT;
2970 table->MemoryVoltageChangeEnable = 1;
2971 table->MemoryInterval = 1;
2972 table->VoltageResponseTime = 0;
2973 table->PhaseResponseTime = 0;
2974 table->MemoryThermThrottleEnable = 1;
2975 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
2976 table->PCIeGenInterval = 1;
2977
2978 result = fiji_populate_vr_config(hwmgr, table);
2979 PP_ASSERT_WITH_CODE(0 == result,
2980 "Failed to populate VRConfig setting!", return result);
2981
2982 table->ThermGpio = 17;
2983 table->SclkStepSize = 0x4000;
2984
2985 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2986 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2987 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2988 PHM_PlatformCaps_RegulatorHot);
2989 } else {
2990 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
2991 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2992 PHM_PlatformCaps_RegulatorHot);
2993 }
2994
2995 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2996 &gpio_pin)) {
2997 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2998 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2999 PHM_PlatformCaps_AutomaticDCTransition);
3000 } else {
3001 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
3002 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3003 PHM_PlatformCaps_AutomaticDCTransition);
3004 }
3005
3006 /* Thermal Output GPIO */
3007 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
3008 &gpio_pin)) {
3009 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3010 PHM_PlatformCaps_ThermalOutGPIO);
3011
3012 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
3013
3014 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3015 * since VBIOS will program this register to set 'inactive state',
3016 * driver can then determine 'active state' from this and
3017 * program SMU with correct polarity
3018 */
3019 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3020 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3021 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3022
3023 /* if required, combine VRHot/PCC with thermal out GPIO */
3024 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3025 PHM_PlatformCaps_RegulatorHot) &&
3026 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3027 PHM_PlatformCaps_CombinePCCWithThermalSignal))
3028 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3029 } else {
3030 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3031 PHM_PlatformCaps_ThermalOutGPIO);
3032 table->ThermOutGpio = 17;
3033 table->ThermOutPolarity = 1;
3034 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3035 }
3036
3037 for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3038 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3039
3040 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3041 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3042 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3043 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3044 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3045 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3046 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3047 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3048 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3049
3050 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3051 result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3052 data->dpm_table_start +
3053 offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3054 (uint8_t *)&(table->SystemFlags),
3055 sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3056 data->sram_end);
3057 PP_ASSERT_WITH_CODE(0 == result,
3058 "Failed to upload dpm data to SMC memory!", return result);
3059
3060 return 0;
3061}
3062
3063/**
3064* Initialize the ARB DRAM timing table's index field.
3065*
3066* @param hwmgr the address of the powerplay hardware manager.
3067* @return always 0
3068*/
3069static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3070{
3071 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3072 uint32_t tmp;
3073 int result;
3074
3075 /* This is a read-modify-write on the first byte of the ARB table.
3076 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3077 * is the field 'current'.
3078 * This solution is ugly, but we never write the whole table only
3079 * individual fields in it.
3080 * In reality this field should not be in that structure
3081 * but in a soft register.
3082 */
3083 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3084 data->arb_table_start, &tmp, data->sram_end);
3085
3086 if (result)
3087 return result;
3088
3089 tmp &= 0x00FFFFFF;
3090 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3091
3092 return fiji_write_smc_sram_dword(hwmgr->smumgr,
3093 data->arb_table_start, tmp, data->sram_end);
3094}
3095
3096static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3097{
3098 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3099 PHM_PlatformCaps_RegulatorHot))
3100 return smum_send_msg_to_smc(hwmgr->smumgr,
3101 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3102
3103 return 0;
3104}
3105
3106static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3107{
3108 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3109 SCLK_PWRMGT_OFF, 0);
3110 return 0;
3111}
3112
3113static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3114{
3115 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3116 struct fiji_ulv_parm *ulv = &(data->ulv);
3117
3118 if (ulv->ulv_supported)
3119 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3120
3121 return 0;
3122}
3123
3124static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3125{
3126 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3127 PHM_PlatformCaps_SclkDeepSleep)) {
3128 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3129 PP_ASSERT_WITH_CODE(false,
3130 "Attempt to enable Master Deep Sleep switch failed!",
3131 return -1);
3132 } else {
3133 if (smum_send_msg_to_smc(hwmgr->smumgr,
3134 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3135 PP_ASSERT_WITH_CODE(false,
3136 "Attempt to disable Master Deep Sleep switch failed!",
3137 return -1);
3138 }
3139 }
3140
3141 return 0;
3142}
3143
3144static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3145{
3146 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3147 uint32_t val, val0, val2;
3148 uint32_t i, cpl_cntl, cpl_threshold, mc_threshold;
3149
3150 /* enable SCLK dpm */
3151 if(!data->sclk_dpm_key_disabled)
3152 PP_ASSERT_WITH_CODE(
3153 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3154 "Failed to enable SCLK DPM during DPM Start Function!",
3155 return -1);
3156
3157 /* enable MCLK dpm */
3158 if(0 == data->mclk_dpm_key_disabled) {
3159 cpl_threshold = 0;
3160 mc_threshold = 0;
3161
3162 /* Read per MCD tile (0 - 7) */
3163 for (i = 0; i < 8; i++) {
3164 PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3165 val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3166 if (0xf0000000 != val) {
3167 /* count number of MCQ that has channel(s) enabled */
3168 cpl_threshold++;
3169 /* only harvest 3 or full 4 supported */
3170 mc_threshold = val ? 3 : 4;
3171 }
3172 }
3173 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3174 "Number of MCQ is zero!", return -EINVAL;);
3175
3176 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3177 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3178 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3179 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3180 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3181 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3182 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3183 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3184 ixLCAC_MC0_CNTL, mc_threshold);
3185 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3186 ixLCAC_MC1_CNTL, mc_threshold);
3187 if (8 == cpl_threshold) {
3188 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3189 ixLCAC_MC2_CNTL, mc_threshold);
3190 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3191 ixLCAC_MC3_CNTL, mc_threshold);
3192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3193 ixLCAC_MC4_CNTL, mc_threshold);
3194 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3195 ixLCAC_MC5_CNTL, mc_threshold);
3196 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3197 ixLCAC_MC6_CNTL, mc_threshold);
3198 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3199 ixLCAC_MC7_CNTL, mc_threshold);
3200 }
3201 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3202 ixLCAC_CPL_CNTL, cpl_cntl);
3203
3204 udelay(5);
3205
3206 mc_threshold = mc_threshold |
3207 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3208 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3209 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3210 ixLCAC_MC0_CNTL, mc_threshold);
3211 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3212 ixLCAC_MC1_CNTL, mc_threshold);
3213 if (8 == cpl_threshold) {
3214 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3215 ixLCAC_MC2_CNTL, mc_threshold);
3216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3217 ixLCAC_MC3_CNTL, mc_threshold);
3218 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3219 ixLCAC_MC4_CNTL, mc_threshold);
3220 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3221 ixLCAC_MC5_CNTL, mc_threshold);
3222 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3223 ixLCAC_MC6_CNTL, mc_threshold);
3224 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3225 ixLCAC_MC7_CNTL, mc_threshold);
3226 }
3227 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3228 ixLCAC_CPL_CNTL, cpl_cntl);
3229
3230 /* Program CAC_EN per MCD (0-7) Tile */
3231 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3232 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3233 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3234 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3235 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3236 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3237 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3238 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3239 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3240 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3241
3242 for (i = 0; i < 8; i++) {
3243 /* Enable MCD i Tile read & write */
3244 val2 = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3245 (1 << i));
3246 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3247 /* Enbale CAC_ON MCD i Tile */
3248 val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3249 val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3250 cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3251 }
3252 /* Set MC_CONFIG_MCD back to its default setting val0 */
3253 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3254
3255 PP_ASSERT_WITH_CODE(
3256 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3257 PPSMC_MSG_MCLKDPM_Enable)),
3258 "Failed to enable MCLK DPM during DPM Start Function!",
3259 return -1);
3260 }
3261 return 0;
3262}
3263
3264static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3265{
3266 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3267
3268 /*enable general power management */
3269 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3270 GLOBAL_PWRMGT_EN, 1);
3271 /* enable sclk deep sleep */
3272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3273 DYNAMIC_PM_EN, 1);
3274 /* prepare for PCIE DPM */
3275 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3276 data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3277 VoltageChangeTimeout), 0x1000);
3278 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3279 SWRST_COMMAND_1, RESETLC, 0x0);
3280
3281 PP_ASSERT_WITH_CODE(
3282 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3283 PPSMC_MSG_Voltage_Cntl_Enable)),
3284 "Failed to enable voltage DPM during DPM Start Function!",
3285 return -1);
3286
3287 if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3288 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3289 return -1;
3290 }
3291
3292 /* enable PCIE dpm */
3293 if(!data->pcie_dpm_key_disabled) {
3294 PP_ASSERT_WITH_CODE(
3295 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3296 PPSMC_MSG_PCIeDPM_Enable)),
3297 "Failed to enable pcie DPM during DPM Start Function!",
3298 return -1);
3299 }
3300
3301 return 0;
3302}
3303
3304static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3305 uint32_t sources)
3306{
3307 bool protection;
3308 enum DPM_EVENT_SRC src;
3309
3310 switch (sources) {
3311 default:
3312 printk(KERN_ERR "Unknown throttling event sources.");
3313 /* fall through */
3314 case 0:
3315 protection = false;
3316 /* src is unused */
3317 break;
3318 case (1 << PHM_AutoThrottleSource_Thermal):
3319 protection = true;
3320 src = DPM_EVENT_SRC_DIGITAL;
3321 break;
3322 case (1 << PHM_AutoThrottleSource_External):
3323 protection = true;
3324 src = DPM_EVENT_SRC_EXTERNAL;
3325 break;
3326 case (1 << PHM_AutoThrottleSource_External) |
3327 (1 << PHM_AutoThrottleSource_Thermal):
3328 protection = true;
3329 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3330 break;
3331 }
3332 /* Order matters - don't enable thermal protection for the wrong source. */
3333 if (protection) {
3334 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3335 DPM_EVENT_SRC, src);
3336 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3337 THERMAL_PROTECTION_DIS,
3338 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3339 PHM_PlatformCaps_ThermalController));
3340 } else
3341 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3342 THERMAL_PROTECTION_DIS, 1);
3343}
3344
3345static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3346 PHM_AutoThrottleSource source)
3347{
3348 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3349
3350 if (!(data->active_auto_throttle_sources & (1 << source))) {
3351 data->active_auto_throttle_sources |= 1 << source;
3352 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3353 }
3354 return 0;
3355}
3356
3357static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3358{
3359 return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3360}
3361
3362static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3363{
3364 int tmp_result, result = 0;
3365
3366 tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3367 PP_ASSERT_WITH_CODE(result == 0,
3368 "DPM is already running right now, no need to enable DPM!",
3369 return 0);
3370
3371 if (fiji_voltage_control(hwmgr)) {
3372 tmp_result = fiji_enable_voltage_control(hwmgr);
3373 PP_ASSERT_WITH_CODE(tmp_result == 0,
3374 "Failed to enable voltage control!",
3375 result = tmp_result);
3376 }
3377
3378 if (fiji_voltage_control(hwmgr)) {
3379 tmp_result = fiji_construct_voltage_tables(hwmgr);
3380 PP_ASSERT_WITH_CODE((0 == tmp_result),
3381 "Failed to contruct voltage tables!",
3382 result = tmp_result);
3383 }
3384
3385 tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3386 PP_ASSERT_WITH_CODE((0 == tmp_result),
3387 "Failed to initialize MC reg table!", result = tmp_result);
3388
3389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3390 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3391 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3392 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3393
3394 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3395 PHM_PlatformCaps_ThermalController))
3396 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3397 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3398
3399 tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3400 PP_ASSERT_WITH_CODE((0 == tmp_result),
3401 "Failed to program static screen threshold parameters!",
3402 result = tmp_result);
3403
3404 tmp_result = fiji_enable_display_gap(hwmgr);
3405 PP_ASSERT_WITH_CODE((0 == tmp_result),
3406 "Failed to enable display gap!", result = tmp_result);
3407
3408 tmp_result = fiji_program_voting_clients(hwmgr);
3409 PP_ASSERT_WITH_CODE((0 == tmp_result),
3410 "Failed to program voting clients!", result = tmp_result);
3411
3412 tmp_result = fiji_process_firmware_header(hwmgr);
3413 PP_ASSERT_WITH_CODE((0 == tmp_result),
3414 "Failed to process firmware header!", result = tmp_result);
3415
3416 tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3417 PP_ASSERT_WITH_CODE((0 == tmp_result),
3418 "Failed to initialize switch from ArbF0 to F1!",
3419 result = tmp_result);
3420
3421 tmp_result = fiji_init_smc_table(hwmgr);
3422 PP_ASSERT_WITH_CODE((0 == tmp_result),
3423 "Failed to initialize SMC table!", result = tmp_result);
3424
3425 tmp_result = fiji_init_arb_table_index(hwmgr);
3426 PP_ASSERT_WITH_CODE((0 == tmp_result),
3427 "Failed to initialize ARB table index!", result = tmp_result);
3428
3429 tmp_result = fiji_populate_pm_fuses(hwmgr);
3430 PP_ASSERT_WITH_CODE((0 == tmp_result),
3431 "Failed to populate PM fuses!", result = tmp_result);
3432
3433 tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3434 PP_ASSERT_WITH_CODE((0 == tmp_result),
3435 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3436
3437 tmp_result = fiji_enable_sclk_control(hwmgr);
3438 PP_ASSERT_WITH_CODE((0 == tmp_result),
3439 "Failed to enable SCLK control!", result = tmp_result);
3440
3441 tmp_result = fiji_enable_ulv(hwmgr);
3442 PP_ASSERT_WITH_CODE((0 == tmp_result),
3443 "Failed to enable ULV!", result = tmp_result);
3444
3445 tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3446 PP_ASSERT_WITH_CODE((0 == tmp_result),
3447 "Failed to enable deep sleep master switch!", result = tmp_result);
3448
3449 tmp_result = fiji_start_dpm(hwmgr);
3450 PP_ASSERT_WITH_CODE((0 == tmp_result),
3451 "Failed to start DPM!", result = tmp_result);
3452
3453 tmp_result = fiji_enable_smc_cac(hwmgr);
3454 PP_ASSERT_WITH_CODE((0 == tmp_result),
3455 "Failed to enable SMC CAC!", result = tmp_result);
3456
3457 tmp_result = fiji_enable_power_containment(hwmgr);
3458 PP_ASSERT_WITH_CODE((0 == tmp_result),
3459 "Failed to enable power containment!", result = tmp_result);
3460
3461 tmp_result = fiji_power_control_set_level(hwmgr);
3462 PP_ASSERT_WITH_CODE((0 == tmp_result),
3463 "Failed to power control set level!", result = tmp_result);
3464
3465 tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3466 PP_ASSERT_WITH_CODE((0 == tmp_result),
3467 "Failed to enable thermal auto throttle!", result = tmp_result);
3468
3469 return result;
3470}
3471
3472static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3473{
3474 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3475 uint32_t level, tmp;
3476
3477 if (!data->sclk_dpm_key_disabled) {
3478 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3479 level = 0;
3480 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3481 while (tmp >>= 1)
3482 level++;
3483 if (level)
3484 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3485 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3486 (1 << level));
3487 }
3488 }
3489
3490 if (!data->mclk_dpm_key_disabled) {
3491 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3492 level = 0;
3493 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3494 while (tmp >>= 1)
3495 level++;
3496 if (level)
3497 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3498 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3499 (1 << level));
3500 }
3501 }
3502
3503 if (!data->pcie_dpm_key_disabled) {
3504 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3505 level = 0;
3506 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3507 while (tmp >>= 1)
3508 level++;
3509 if (level)
3510 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3511 PPSMC_MSG_PCIeDPM_ForceLevel,
3512 (1 << level));
3513 }
3514 }
3515 return 0;
3516}
3517
3518static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
3519{
3520 struct phm_ppt_v1_information *table_info =
3521 (struct phm_ppt_v1_information *)hwmgr->pptable;
3522 struct phm_clock_voltage_dependency_table *table =
3523 table_info->vddc_dep_on_dal_pwrl;
3524 struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
3525 enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
3526 uint32_t req_vddc = 0, req_volt, i;
3527
3528 if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
3529 dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
3530 return;
3531
3532 for (i= 0; i < table->count; i++) {
3533 if (dal_power_level == table->entries[i].clk) {
3534 req_vddc = table->entries[i].v;
3535 break;
3536 }
3537 }
3538
3539 vddc_table = table_info->vdd_dep_on_sclk;
3540 for (i= 0; i < vddc_table->count; i++) {
3541 if (req_vddc <= vddc_table->entries[i].vddc) {
3542 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
3543 << VDDC_SHIFT;
3544 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3545 PPSMC_MSG_VddC_Request, req_volt);
3546 return;
3547 }
3548 }
3549 printk(KERN_ERR "DAL requested level can not"
3550 " found a available voltage in VDDC DPM Table \n");
3551}
3552
3553static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3554{
3555 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3556
3557 fiji_apply_dal_min_voltage_request(hwmgr);
3558
3559 if (!data->sclk_dpm_key_disabled) {
3560 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3561 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3562 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3563 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3564 }
3565 return 0;
3566}
3567
3568static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3569{
3570 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3571
3572 if (!fiji_is_dpm_running(hwmgr))
3573 return -EINVAL;
3574
3575 if (!data->pcie_dpm_key_disabled) {
3576 smum_send_msg_to_smc(hwmgr->smumgr,
3577 PPSMC_MSG_PCIeDPM_UnForceLevel);
3578 }
3579
3580 return fiji_upload_dpmlevel_enable_mask(hwmgr);
3581}
3582
3583static uint32_t fiji_get_lowest_enabled_level(
3584 struct pp_hwmgr *hwmgr, uint32_t mask)
3585{
3586 uint32_t level = 0;
3587
3588 while(0 == (mask & (1 << level)))
3589 level++;
3590
3591 return level;
3592}
3593
3594static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3595{
3596 struct fiji_hwmgr *data =
3597 (struct fiji_hwmgr *)(hwmgr->backend);
74c577b0 3598 uint32_t level;
aabcb7c1 3599
aabcb7c1
EH		 3600 if (!data->sclk_dpm_key_disabled)
3601 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3602 level = fiji_get_lowest_enabled_level(hwmgr,
74c577b0 3603 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
aabcb7c1 3604 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
74c577b0
AD		 3605 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3606 (1 << level));
3607
3608 }
3609
3610 if (!data->mclk_dpm_key_disabled) {
3611 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3612 level = fiji_get_lowest_enabled_level(hwmgr,
3613 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3614 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3615 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3616 (1 << level));
3617 }
3618 }
aabcb7c1 3619
74c577b0
AD		 3620 if (!data->pcie_dpm_key_disabled) {
3621 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3622 level = fiji_get_lowest_enabled_level(hwmgr,
3623 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3624 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3625 PPSMC_MSG_PCIeDPM_ForceLevel,
3626 (1 << level));
3627 }
aabcb7c1 3628 }
74c577b0 3629
aabcb7c1
EH		 3630 return 0;
3631
3632}
3633static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3634 enum amd_dpm_forced_level level)
3635{
3636 int ret = 0;
3637
3638 switch (level) {
3639 case AMD_DPM_FORCED_LEVEL_HIGH:
3640 ret = fiji_force_dpm_highest(hwmgr);
3641 if (ret)
3642 return ret;
3643 break;
3644 case AMD_DPM_FORCED_LEVEL_LOW:
3645 ret = fiji_force_dpm_lowest(hwmgr);
3646 if (ret)
3647 return ret;
3648 break;
3649 case AMD_DPM_FORCED_LEVEL_AUTO:
3650 ret = fiji_unforce_dpm_levels(hwmgr);
3651 if (ret)
3652 return ret;
3653 break;
3654 default:
3655 break;
3656 }
3657
3658 hwmgr->dpm_level = level;
3659
3660 return ret;
3661}
3662
3663static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3664{
3665 return sizeof(struct fiji_power_state);
3666}
3667
3668static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3669 void *state, struct pp_power_state *power_state,
3670 void *pp_table, uint32_t classification_flag)
3671{
3672 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3673 struct fiji_power_state *fiji_power_state =
3674 (struct fiji_power_state *)(&(power_state->hardware));
3675 struct fiji_performance_level *performance_level;
3676 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3677 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3678 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3679 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3680 (ATOM_Tonga_SCLK_Dependency_Table *)
3681 (((unsigned long)powerplay_table) +
3682 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3683 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3684 (ATOM_Tonga_MCLK_Dependency_Table *)
3685 (((unsigned long)powerplay_table) +
3686 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3687
3688 /* The following fields are not initialized here: id orderedList allStatesList */
3689 power_state->classification.ui_label =
3690 (le16_to_cpu(state_entry->usClassification) &
3691 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3692 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3693 power_state->classification.flags = classification_flag;
3694 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3695
3696 power_state->classification.temporary_state = false;
3697 power_state->classification.to_be_deleted = false;
3698
3699 power_state->validation.disallowOnDC =
3700 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3701 ATOM_Tonga_DISALLOW_ON_DC));
3702
3703 power_state->pcie.lanes = 0;
3704
3705 power_state->display.disableFrameModulation = false;
3706 power_state->display.limitRefreshrate = false;
3707 power_state->display.enableVariBright =
3708 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3709 ATOM_Tonga_ENABLE_VARIBRIGHT));
3710
3711 power_state->validation.supportedPowerLevels = 0;
3712 power_state->uvd_clocks.VCLK = 0;
3713 power_state->uvd_clocks.DCLK = 0;
3714 power_state->temperatures.min = 0;
3715 power_state->temperatures.max = 0;
3716
3717 performance_level = &(fiji_power_state->performance_levels
3718 [fiji_power_state->performance_level_count++]);
3719
3720 PP_ASSERT_WITH_CODE(
3721 (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3722 "Performance levels exceeds SMC limit!",
3723 return -1);
3724
3725 PP_ASSERT_WITH_CODE(
3726 (fiji_power_state->performance_level_count <=
3727 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3728 "Performance levels exceeds Driver limit!",
3729 return -1);
3730
3731 /* Performance levels are arranged from low to high. */
3732 performance_level->memory_clock = mclk_dep_table->entries
3733 [state_entry->ucMemoryClockIndexLow].ulMclk;
3734 performance_level->engine_clock = sclk_dep_table->entries
3735 [state_entry->ucEngineClockIndexLow].ulSclk;
3736 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3737 state_entry->ucPCIEGenLow);
3738 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3739 state_entry->ucPCIELaneHigh);
3740
3741 performance_level = &(fiji_power_state->performance_levels
3742 [fiji_power_state->performance_level_count++]);
3743 performance_level->memory_clock = mclk_dep_table->entries
3744 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3745 performance_level->engine_clock = sclk_dep_table->entries
3746 [state_entry->ucEngineClockIndexHigh].ulSclk;
3747 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3748 state_entry->ucPCIEGenHigh);
3749 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3750 state_entry->ucPCIELaneHigh);
3751
3752 return 0;
3753}
3754
3755static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3756 unsigned long entry_index, struct pp_power_state *state)
3757{
3758 int result;
3759 struct fiji_power_state *ps;
3760 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3761 struct phm_ppt_v1_information *table_info =
3762 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3763 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3764 table_info->vdd_dep_on_mclk;
3765
3766 state->hardware.magic = PHM_VIslands_Magic;
3767
3768 ps = (struct fiji_power_state *)(&state->hardware);
3769
3770 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3771 fiji_get_pp_table_entry_callback_func);
3772
3773 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3774 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3775 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3776 */
3777 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3778 if (dep_mclk_table->entries[0].clk !=
3779 data->vbios_boot_state.mclk_bootup_value)
3780 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3781 "does not match VBIOS boot MCLK level");
3782 if (dep_mclk_table->entries[0].vddci !=
3783 data->vbios_boot_state.vddci_bootup_value)
3784 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3785 "does not match VBIOS boot VDDCI level");
3786 }
3787
3788 /* set DC compatible flag if this state supports DC */
3789 if (!state->validation.disallowOnDC)
3790 ps->dc_compatible = true;
3791
3792 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3793 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3794
3795 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3796 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3797
3798 if (!result) {
3799 uint32_t i;
3800
3801 switch (state->classification.ui_label) {
3802 case PP_StateUILabel_Performance:
3803 data->use_pcie_performance_levels = true;
3804
3805 for (i = 0; i < ps->performance_level_count; i++) {
3806 if (data->pcie_gen_performance.max <
3807 ps->performance_levels[i].pcie_gen)
3808 data->pcie_gen_performance.max =
3809 ps->performance_levels[i].pcie_gen;
3810
3811 if (data->pcie_gen_performance.min >
3812 ps->performance_levels[i].pcie_gen)
3813 data->pcie_gen_performance.min =
3814 ps->performance_levels[i].pcie_gen;
3815
3816 if (data->pcie_lane_performance.max <
3817 ps->performance_levels[i].pcie_lane)
3818 data->pcie_lane_performance.max =
3819 ps->performance_levels[i].pcie_lane;
3820
3821 if (data->pcie_lane_performance.min >
3822 ps->performance_levels[i].pcie_lane)
3823 data->pcie_lane_performance.min =
3824 ps->performance_levels[i].pcie_lane;
3825 }
3826 break;
3827 case PP_StateUILabel_Battery:
3828 data->use_pcie_power_saving_levels = true;
3829
3830 for (i = 0; i < ps->performance_level_count; i++) {
3831 if (data->pcie_gen_power_saving.max <
3832 ps->performance_levels[i].pcie_gen)
3833 data->pcie_gen_power_saving.max =
3834 ps->performance_levels[i].pcie_gen;
3835
3836 if (data->pcie_gen_power_saving.min >
3837 ps->performance_levels[i].pcie_gen)
3838 data->pcie_gen_power_saving.min =
3839 ps->performance_levels[i].pcie_gen;
3840
3841 if (data->pcie_lane_power_saving.max <
3842 ps->performance_levels[i].pcie_lane)
3843 data->pcie_lane_power_saving.max =
3844 ps->performance_levels[i].pcie_lane;
3845
3846 if (data->pcie_lane_power_saving.min >
3847 ps->performance_levels[i].pcie_lane)
3848 data->pcie_lane_power_saving.min =
3849 ps->performance_levels[i].pcie_lane;
3850 }
3851 break;
3852 default:
3853 break;
3854 }
3855 }
3856 return 0;
3857}
3858
3859static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3860 struct pp_power_state *request_ps,
3861 const struct pp_power_state *current_ps)
3862{
3863 struct fiji_power_state *fiji_ps =
3864 cast_phw_fiji_power_state(&request_ps->hardware);
3865 uint32_t sclk;
3866 uint32_t mclk;
3867 struct PP_Clocks minimum_clocks = {0};
3868 bool disable_mclk_switching;
3869 bool disable_mclk_switching_for_frame_lock;
3870 struct cgs_display_info info = {0};
3871 const struct phm_clock_and_voltage_limits *max_limits;
3872 uint32_t i;
3873 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3874 struct phm_ppt_v1_information *table_info =
3875 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3876 int32_t count;
3877 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3878
3879 data->battery_state = (PP_StateUILabel_Battery ==
3880 request_ps->classification.ui_label);
3881
3882 PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3883 "VI should always have 2 performance levels",);
3884
3885 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3886 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3887 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3888
3889 /* Cap clock DPM tables at DC MAX if it is in DC. */
3890 if (PP_PowerSource_DC == hwmgr->power_source) {
3891 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3892 if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3893 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3894 if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3895 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3896 }
3897 }
3898
3899 fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3900 fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3901
3902 fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3903
3904 cgs_get_active_displays_info(hwmgr->device, &info);
3905
3906 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3907
3908 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3909
3910 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3911 PHM_PlatformCaps_StablePState)) {
3912 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3913 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3914
3915 for (count = table_info->vdd_dep_on_sclk->count - 1;
3916 count >= 0; count--) {
3917 if (stable_pstate_sclk >=
3918 table_info->vdd_dep_on_sclk->entries[count].clk) {
3919 stable_pstate_sclk =
3920 table_info->vdd_dep_on_sclk->entries[count].clk;
3921 break;
3922 }
3923 }
3924
3925 if (count < 0)
3926 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3927
3928 stable_pstate_mclk = max_limits->mclk;
3929
3930 minimum_clocks.engineClock = stable_pstate_sclk;
3931 minimum_clocks.memoryClock = stable_pstate_mclk;
3932 }
3933
3934 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3935 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3936
3937 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3938 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3939
3940 fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3941
3942 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3943 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3944 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3945 "Overdrive sclk exceeds limit",
3946 hwmgr->gfx_arbiter.sclk_over_drive =
3947 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3948
3949 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3950 fiji_ps->performance_levels[1].engine_clock =
3951 hwmgr->gfx_arbiter.sclk_over_drive;
3952 }
3953
3954 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3955 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3956 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3957 "Overdrive mclk exceeds limit",
3958 hwmgr->gfx_arbiter.mclk_over_drive =
3959 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3960
3961 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3962 fiji_ps->performance_levels[1].memory_clock =
3963 hwmgr->gfx_arbiter.mclk_over_drive;
3964 }
3965
3966 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3967 hwmgr->platform_descriptor.platformCaps,
3968 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3969
3970 disable_mclk_switching = (1 < info.display_count) ||
3971 disable_mclk_switching_for_frame_lock;
3972
3973 sclk = fiji_ps->performance_levels[0].engine_clock;
3974 mclk = fiji_ps->performance_levels[0].memory_clock;
3975
3976 if (disable_mclk_switching)
3977 mclk = fiji_ps->performance_levels
3978 [fiji_ps->performance_level_count - 1].memory_clock;
3979
3980 if (sclk < minimum_clocks.engineClock)
3981 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3982 max_limits->sclk : minimum_clocks.engineClock;
3983
3984 if (mclk < minimum_clocks.memoryClock)
3985 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3986 max_limits->mclk : minimum_clocks.memoryClock;
3987
3988 fiji_ps->performance_levels[0].engine_clock = sclk;
3989 fiji_ps->performance_levels[0].memory_clock = mclk;
3990
3991 fiji_ps->performance_levels[1].engine_clock =
3992 (fiji_ps->performance_levels[1].engine_clock >=
3993 fiji_ps->performance_levels[0].engine_clock) ?
3994 fiji_ps->performance_levels[1].engine_clock :
3995 fiji_ps->performance_levels[0].engine_clock;
3996
3997 if (disable_mclk_switching) {
3998 if (mclk < fiji_ps->performance_levels[1].memory_clock)
3999 mclk = fiji_ps->performance_levels[1].memory_clock;
4000
4001 fiji_ps->performance_levels[0].memory_clock = mclk;
4002 fiji_ps->performance_levels[1].memory_clock = mclk;
4003 } else {
4004 if (fiji_ps->performance_levels[1].memory_clock <
4005 fiji_ps->performance_levels[0].memory_clock)
4006 fiji_ps->performance_levels[1].memory_clock =
4007 fiji_ps->performance_levels[0].memory_clock;
4008 }
4009
4010 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4011 PHM_PlatformCaps_StablePState)) {
4012 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4013 fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4014 fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4015 fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4016 fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4017 }
4018 }
4019
4020 return 0;
4021}
4022
4023static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4024{
4025 const struct phm_set_power_state_input *states =
4026 (const struct phm_set_power_state_input *)input;
4027 const struct fiji_power_state *fiji_ps =
4028 cast_const_phw_fiji_power_state(states->pnew_state);
4029 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4030 struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4031 uint32_t sclk = fiji_ps->performance_levels
4032 [fiji_ps->performance_level_count - 1].engine_clock;
4033 struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4034 uint32_t mclk = fiji_ps->performance_levels
4035 [fiji_ps->performance_level_count - 1].memory_clock;
4036 struct PP_Clocks min_clocks = {0};
4037 uint32_t i;
4038 struct cgs_display_info info = {0};
4039
4040 data->need_update_smu7_dpm_table = 0;
4041
4042 for (i = 0; i < sclk_table->count; i++) {
4043 if (sclk == sclk_table->dpm_levels[i].value)
4044 break;
4045 }
4046
4047 if (i >= sclk_table->count)
4048 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4049 else {
4050 /* TODO: Check SCLK in DAL's minimum clocks
4051 * in case DeepSleep divider update is required.
4052 */
4053 if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
4054 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4055 }
4056
4057 for (i = 0; i < mclk_table->count; i++) {
4058 if (mclk == mclk_table->dpm_levels[i].value)
4059 break;
4060 }
4061
4062 if (i >= mclk_table->count)
4063 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4064
4065 cgs_get_active_displays_info(hwmgr->device, &info);
4066
4067 if (data->display_timing.num_existing_displays != info.display_count)
4068 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4069
4070 return 0;
4071}
4072
4073static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4074 const struct fiji_power_state *fiji_ps)
4075{
4076 uint32_t i;
4077 uint32_t sclk, max_sclk = 0;
4078 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4079 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4080
4081 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4082 sclk = fiji_ps->performance_levels[i].engine_clock;
4083 if (max_sclk < sclk)
4084 max_sclk = sclk;
4085 }
4086
4087 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4088 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4089 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4090 dpm_table->pcie_speed_table.dpm_levels
4091 [dpm_table->pcie_speed_table.count - 1].value :
4092 dpm_table->pcie_speed_table.dpm_levels[i].value);
4093 }
4094
4095 return 0;
4096}
4097
4098static int fiji_request_link_speed_change_before_state_change(
4099 struct pp_hwmgr *hwmgr, const void *input)
4100{
4101 const struct phm_set_power_state_input *states =
4102 (const struct phm_set_power_state_input *)input;
4103 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4104 const struct fiji_power_state *fiji_nps =
4105 cast_const_phw_fiji_power_state(states->pnew_state);
4106 const struct fiji_power_state *fiji_cps =
4107 cast_const_phw_fiji_power_state(states->pcurrent_state);
4108
4109 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4110 uint16_t current_link_speed;
4111
4112 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4113 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4114 else
4115 current_link_speed = data->force_pcie_gen;
4116
4117 data->force_pcie_gen = PP_PCIEGenInvalid;
4118 data->pspp_notify_required = false;
4119 if (target_link_speed > current_link_speed) {
4120 switch(target_link_speed) {
4121 case PP_PCIEGen3:
4122 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4123 break;
4124 data->force_pcie_gen = PP_PCIEGen2;
4125 if (current_link_speed == PP_PCIEGen2)
4126 break;
4127 case PP_PCIEGen2:
4128 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4129 break;
4130 default:
4131 data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4132 break;
4133 }
4134 } else {
4135 if (target_link_speed < current_link_speed)
4136 data->pspp_notify_required = true;
4137 }
4138
4139 return 0;
4140}
4141
4142static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4143{
4144 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4145
4146 if (0 == data->need_update_smu7_dpm_table)
4147 return 0;
4148
4149 if ((0 == data->sclk_dpm_key_disabled) &&
4150 (data->need_update_smu7_dpm_table &
4151 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4152 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4153 "Trying to freeze SCLK DPM when DPM is disabled",);
4154 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4155 PPSMC_MSG_SCLKDPM_FreezeLevel),
4156 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4157 return -1);
4158 }
4159
4160 if ((0 == data->mclk_dpm_key_disabled) &&
4161 (data->need_update_smu7_dpm_table &
4162 DPMTABLE_OD_UPDATE_MCLK)) {
4163 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4164 "Trying to freeze MCLK DPM when DPM is disabled",);
4165 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4166 PPSMC_MSG_MCLKDPM_FreezeLevel),
4167 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4168 return -1);
4169 }
4170
4171 return 0;
4172}
4173
4174static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4175 struct pp_hwmgr *hwmgr, const void *input)
4176{
4177 int result = 0;
4178 const struct phm_set_power_state_input *states =
4179 (const struct phm_set_power_state_input *)input;
4180 const struct fiji_power_state *fiji_ps =
4181 cast_const_phw_fiji_power_state(states->pnew_state);
4182 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4183 uint32_t sclk = fiji_ps->performance_levels
4184 [fiji_ps->performance_level_count - 1].engine_clock;
4185 uint32_t mclk = fiji_ps->performance_levels
4186 [fiji_ps->performance_level_count - 1].memory_clock;
4187 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4188
4189 struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4190 uint32_t dpm_count, clock_percent;
4191 uint32_t i;
4192
4193 if (0 == data->need_update_smu7_dpm_table)
4194 return 0;
4195
4196 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4197 dpm_table->sclk_table.dpm_levels
4198 [dpm_table->sclk_table.count - 1].value = sclk;
4199
4200 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4201 PHM_PlatformCaps_OD6PlusinACSupport) ||
4202 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4203 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4204 /* Need to do calculation based on the golden DPM table
4205 * as the Heatmap GPU Clock axis is also based on the default values
4206 */
4207 PP_ASSERT_WITH_CODE(
4208 (golden_dpm_table->sclk_table.dpm_levels
4209 [golden_dpm_table->sclk_table.count - 1].value != 0),
4210 "Divide by 0!",
4211 return -1);
4212 dpm_count = dpm_table->sclk_table.count < 2 ?
4213 0 : dpm_table->sclk_table.count - 2;
4214 for (i = dpm_count; i > 1; i--) {
4215 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4216 [golden_dpm_table->sclk_table.count-1].value) {
4217 clock_percent =
4218 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4219 [golden_dpm_table->sclk_table.count-1].value) * 100) /
4220 golden_dpm_table->sclk_table.dpm_levels
4221 [golden_dpm_table->sclk_table.count-1].value;
4222
4223 dpm_table->sclk_table.dpm_levels[i].value =
4224 golden_dpm_table->sclk_table.dpm_levels[i].value +
4225 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4226 clock_percent)/100;
4227
4228 } else if (golden_dpm_table->sclk_table.dpm_levels
4229 [dpm_table->sclk_table.count-1].value > sclk) {
4230 clock_percent =
4231 ((golden_dpm_table->sclk_table.dpm_levels
4232 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4233 100) /
4234 golden_dpm_table->sclk_table.dpm_levels
4235 [golden_dpm_table->sclk_table.count-1].value;
4236
4237 dpm_table->sclk_table.dpm_levels[i].value =
4238 golden_dpm_table->sclk_table.dpm_levels[i].value -
4239 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4240 clock_percent) / 100;
4241 } else
4242 dpm_table->sclk_table.dpm_levels[i].value =
4243 golden_dpm_table->sclk_table.dpm_levels[i].value;
4244 }
4245 }
4246 }
4247
4248 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4249 dpm_table->mclk_table.dpm_levels
4250 [dpm_table->mclk_table.count - 1].value = mclk;
4251
4252 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4253 PHM_PlatformCaps_OD6PlusinACSupport) ||
4254 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4255 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4256
4257 PP_ASSERT_WITH_CODE(
4258 (golden_dpm_table->mclk_table.dpm_levels
4259 [golden_dpm_table->mclk_table.count-1].value != 0),
4260 "Divide by 0!",
4261 return -1);
4262 dpm_count = dpm_table->mclk_table.count < 2 ?
4263 0 : dpm_table->mclk_table.count - 2;
4264 for (i = dpm_count; i > 1; i--) {
4265 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4266 [golden_dpm_table->mclk_table.count-1].value) {
4267 clock_percent = ((mclk -
4268 golden_dpm_table->mclk_table.dpm_levels
4269 [golden_dpm_table->mclk_table.count-1].value) * 100) /
4270 golden_dpm_table->mclk_table.dpm_levels
4271 [golden_dpm_table->mclk_table.count-1].value;
4272
4273 dpm_table->mclk_table.dpm_levels[i].value =
4274 golden_dpm_table->mclk_table.dpm_levels[i].value +
4275 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4276 clock_percent) / 100;
4277
4278 } else if (golden_dpm_table->mclk_table.dpm_levels
4279 [dpm_table->mclk_table.count-1].value > mclk) {
4280 clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4281 [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4282 golden_dpm_table->mclk_table.dpm_levels
4283 [golden_dpm_table->mclk_table.count-1].value;
4284
4285 dpm_table->mclk_table.dpm_levels[i].value =
4286 golden_dpm_table->mclk_table.dpm_levels[i].value -
4287 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4288 clock_percent) / 100;
4289 } else
4290 dpm_table->mclk_table.dpm_levels[i].value =
4291 golden_dpm_table->mclk_table.dpm_levels[i].value;
4292 }
4293 }
4294 }
4295
4296 if (data->need_update_smu7_dpm_table &
4297 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4298 result = fiji_populate_all_memory_levels(hwmgr);
4299 PP_ASSERT_WITH_CODE((0 == result),
4300 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4301 return result);
4302 }
4303
4304 if (data->need_update_smu7_dpm_table &
4305 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4306 /*populate MCLK dpm table to SMU7 */
4307 result = fiji_populate_all_memory_levels(hwmgr);
4308 PP_ASSERT_WITH_CODE((0 == result),
4309 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4310 return result);
4311 }
4312
4313 return result;
4314}
4315
4316static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4317 struct fiji_single_dpm_table * dpm_table,
4318 uint32_t low_limit, uint32_t high_limit)
4319{
4320 uint32_t i;
4321
4322 for (i = 0; i < dpm_table->count; i++) {
4323 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4324 (dpm_table->dpm_levels[i].value > high_limit))
4325 dpm_table->dpm_levels[i].enabled = false;
4326 else
4327 dpm_table->dpm_levels[i].enabled = true;
4328 }
4329 return 0;
4330}
4331
4332static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4333 const struct fiji_power_state *fiji_ps)
4334{
4335 int result = 0;
4336 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4337 uint32_t high_limit_count;
4338
4339 PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4340 "power state did not have any performance level",
4341 return -1);
4342
4343 high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4344
4345 fiji_trim_single_dpm_states(hwmgr,
4346 &(data->dpm_table.sclk_table),
4347 fiji_ps->performance_levels[0].engine_clock,
4348 fiji_ps->performance_levels[high_limit_count].engine_clock);
4349
4350 fiji_trim_single_dpm_states(hwmgr,
4351 &(data->dpm_table.mclk_table),
4352 fiji_ps->performance_levels[0].memory_clock,
4353 fiji_ps->performance_levels[high_limit_count].memory_clock);
4354
4355 return result;
4356}
4357
4358static int fiji_generate_dpm_level_enable_mask(
4359 struct pp_hwmgr *hwmgr, const void *input)
4360{
4361 int result;
4362 const struct phm_set_power_state_input *states =
4363 (const struct phm_set_power_state_input *)input;
4364 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4365 const struct fiji_power_state *fiji_ps =
4366 cast_const_phw_fiji_power_state(states->pnew_state);
4367
4368 result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4369 if (result)
4370 return result;
4371
4372 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4373 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4374 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4375 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4376 data->last_mclk_dpm_enable_mask =
4377 data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4378
4379 if (data->uvd_enabled) {
4380 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4381 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4382 }
4383
4384 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4385 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4386
4387 return 0;
4388}
4389
91c4c981
EH		 4390int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4391{
4392 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4393 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
4394 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
4395}
4396
4397int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
aabcb7c1
EH		 4398{
4399 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4400 PPSMC_MSG_VCEDPM_Enable :
4401 PPSMC_MSG_VCEDPM_Disable);
4402}
4403
91c4c981
EH		 4404int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4405{
4406 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4407 PPSMC_MSG_SAMUDPM_Enable :
4408 PPSMC_MSG_SAMUDPM_Disable);
4409}
4410
4411int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
4412{
4413 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4414 PPSMC_MSG_ACPDPM_Enable :
4415 PPSMC_MSG_ACPDPM_Disable);
4416}
4417
4418int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4419{
4420 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4421 uint32_t mm_boot_level_offset, mm_boot_level_value;
4422 struct phm_ppt_v1_information *table_info =
4423 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4424
4425 if (!bgate) {
4426 data->smc_state_table.UvdBootLevel = 0;
4427 if (table_info->mm_dep_table->count > 0)
4428 data->smc_state_table.UvdBootLevel =
4429 (uint8_t) (table_info->mm_dep_table->count - 1);
4430 mm_boot_level_offset = data->dpm_table_start +
4431 offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
4432 mm_boot_level_offset /= 4;
4433 mm_boot_level_offset *= 4;
4434 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4435 CGS_IND_REG__SMC, mm_boot_level_offset);
4436 mm_boot_level_value &= 0x00FFFFFF;
4437 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4438 cgs_write_ind_register(hwmgr->device,
4439 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4440
4441 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4442 PHM_PlatformCaps_UVDDPM) ||
4443 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4444 PHM_PlatformCaps_StablePState))
4445 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4446 PPSMC_MSG_UVDDPM_SetEnabledMask,
4447 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4448 }
4449
4450 return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
4451}
4452
4453int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
aabcb7c1
EH		 4454{
4455 const struct phm_set_power_state_input *states =
4456 (const struct phm_set_power_state_input *)input;
4457 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4458 const struct fiji_power_state *fiji_nps =
4459 cast_const_phw_fiji_power_state(states->pnew_state);
4460 const struct fiji_power_state *fiji_cps =
4461 cast_const_phw_fiji_power_state(states->pcurrent_state);
4462
4463 uint32_t mm_boot_level_offset, mm_boot_level_value;
4464 struct phm_ppt_v1_information *table_info =
4465 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4466
4467 if (fiji_nps->vce_clks.evclk >0 &&
4468 (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4469 data->smc_state_table.VceBootLevel =
4470 (uint8_t) (table_info->mm_dep_table->count - 1);
4471
4472 mm_boot_level_offset = data->dpm_table_start +
4473 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4474 mm_boot_level_offset /= 4;
4475 mm_boot_level_offset *= 4;
4476 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4477 CGS_IND_REG__SMC, mm_boot_level_offset);
4478 mm_boot_level_value &= 0xFF00FFFF;
4479 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4480 cgs_write_ind_register(hwmgr->device,
4481 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4482
4483 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4484 PHM_PlatformCaps_StablePState)) {
4485 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4486 PPSMC_MSG_VCEDPM_SetEnabledMask,
4487 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4488
4489 fiji_enable_disable_vce_dpm(hwmgr, true);
4490 } else if (fiji_nps->vce_clks.evclk == 0 &&
4491 fiji_cps != NULL &&
4492 fiji_cps->vce_clks.evclk > 0)
4493 fiji_enable_disable_vce_dpm(hwmgr, false);
4494 }
4495
4496 return 0;
4497}
4498
91c4c981
EH		 4499int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4500{
4501 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4502 uint32_t mm_boot_level_offset, mm_boot_level_value;
4503 struct phm_ppt_v1_information *table_info =
4504 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4505
4506 if (!bgate) {
4507 data->smc_state_table.SamuBootLevel =
4508 (uint8_t) (table_info->mm_dep_table->count - 1);
4509 mm_boot_level_offset = data->dpm_table_start +
4510 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
4511 mm_boot_level_offset /= 4;
4512 mm_boot_level_offset *= 4;
4513 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4514 CGS_IND_REG__SMC, mm_boot_level_offset);
4515 mm_boot_level_value &= 0xFFFFFF00;
4516 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4517 cgs_write_ind_register(hwmgr->device,
4518 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4519
4520 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4521 PHM_PlatformCaps_StablePState))
4522 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4523 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4524 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4525 }
4526
4527 return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
4528}
4529
4530int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4531{
4532 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4533 uint32_t mm_boot_level_offset, mm_boot_level_value;
4534 struct phm_ppt_v1_information *table_info =
4535 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4536
4537 if (!bgate) {
4538 data->smc_state_table.AcpBootLevel =
4539 (uint8_t) (table_info->mm_dep_table->count - 1);
4540 mm_boot_level_offset = data->dpm_table_start +
4541 offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
4542 mm_boot_level_offset /= 4;
4543 mm_boot_level_offset *= 4;
4544 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4545 CGS_IND_REG__SMC, mm_boot_level_offset);
4546 mm_boot_level_value &= 0xFFFF00FF;
4547 mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
4548 cgs_write_ind_register(hwmgr->device,
4549 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4550
4551 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4552 PHM_PlatformCaps_StablePState))
4553 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4554 PPSMC_MSG_ACPDPM_SetEnabledMask,
4555 (uint32_t)(1 << data->smc_state_table.AcpBootLevel));
4556 }
4557
4558 return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
4559}
4560
aabcb7c1
EH		 4561static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4562{
4563 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4564
4565 int result = 0;
4566 uint32_t low_sclk_interrupt_threshold = 0;
4567
4568 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4569 PHM_PlatformCaps_SclkThrottleLowNotification)
4570 && (hwmgr->gfx_arbiter.sclk_threshold !=
4571 data->low_sclk_interrupt_threshold)) {
4572 data->low_sclk_interrupt_threshold =
4573 hwmgr->gfx_arbiter.sclk_threshold;
4574 low_sclk_interrupt_threshold =
4575 data->low_sclk_interrupt_threshold;
4576
4577 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4578
4579 result = fiji_copy_bytes_to_smc(
4580 hwmgr->smumgr,
4581 data->dpm_table_start +
4582 offsetof(SMU73_Discrete_DpmTable,
4583 LowSclkInterruptThreshold),
4584 (uint8_t *)&low_sclk_interrupt_threshold,
4585 sizeof(uint32_t),
4586 data->sram_end);
4587 }
4588
4589 return result;
4590}
4591
4592static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4593{
4594 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4595
4596 if (data->need_update_smu7_dpm_table &
4597 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4598 return fiji_program_memory_timing_parameters(hwmgr);
4599
4600 return 0;
4601}
4602
4603static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4604{
4605 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4606
4607 if (0 == data->need_update_smu7_dpm_table)
4608 return 0;
4609
4610 if ((0 == data->sclk_dpm_key_disabled) &&
4611 (data->need_update_smu7_dpm_table &
4612 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4613
4614 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4615 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4616 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4617 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4618 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4619 return -1);
4620 }
4621
4622 if ((0 == data->mclk_dpm_key_disabled) &&
4623 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4624
4625 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4626 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4627 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4628 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4629 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4630 return -1);
4631 }
4632
4633 data->need_update_smu7_dpm_table = 0;
4634
4635 return 0;
4636}
4637
4638/* Look up the voltaged based on DAL's requested level.
4639 * and then send the requested VDDC voltage to SMC
4640 */
4641static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4642{
4643 return;
4644}
4645
4646int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4647{
4648 int result;
4649 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4650
4651 /* Apply minimum voltage based on DAL's request level */
4652 fiji_apply_dal_minimum_voltage_request(hwmgr);
4653
4654 if (0 == data->sclk_dpm_key_disabled) {
4655 /* Checking if DPM is running. If we discover hang because of this,
4656 * we should skip this message.
4657 */
4658 if (!fiji_is_dpm_running(hwmgr))
4659 printk(KERN_ERR "[ powerplay ] "
4660 "Trying to set Enable Mask when DPM is disabled \n");
4661
4662 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4663 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4664 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4665 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4666 PP_ASSERT_WITH_CODE((0 == result),
4667 "Set Sclk Dpm enable Mask failed", return -1);
4668 }
4669 }
4670
4671 if (0 == data->mclk_dpm_key_disabled) {
4672 /* Checking if DPM is running. If we discover hang because of this,
4673 * we should skip this message.
4674 */
4675 if (!fiji_is_dpm_running(hwmgr))
4676 printk(KERN_ERR "[ powerplay ]"
4677 " Trying to set Enable Mask when DPM is disabled \n");
4678
4679 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4680 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4681 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4682 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4683 PP_ASSERT_WITH_CODE((0 == result),
4684 "Set Mclk Dpm enable Mask failed", return -1);
4685 }
4686 }
4687
4688 return 0;
4689}
4690
4691static int fiji_notify_link_speed_change_after_state_change(
4692 struct pp_hwmgr *hwmgr, const void *input)
4693{
4694 const struct phm_set_power_state_input *states =
4695 (const struct phm_set_power_state_input *)input;
4696 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4697 const struct fiji_power_state *fiji_ps =
4698 cast_const_phw_fiji_power_state(states->pnew_state);
4699 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4700 uint8_t request;
4701
4702 if (data->pspp_notify_required) {
4703 if (target_link_speed == PP_PCIEGen3)
4704 request = PCIE_PERF_REQ_GEN3;
4705 else if (target_link_speed == PP_PCIEGen2)
4706 request = PCIE_PERF_REQ_GEN2;
4707 else
4708 request = PCIE_PERF_REQ_GEN1;
4709
4710 if(request == PCIE_PERF_REQ_GEN1 &&
4711 fiji_get_current_pcie_speed(hwmgr) > 0)
4712 return 0;
4713
4714 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4715 if (PP_PCIEGen2 == target_link_speed)
4716 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4717 else
4718 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4719 }
4720 }
4721
4722 return 0;
4723}
4724
4725static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4726 const void *input)
4727{
4728 int tmp_result, result = 0;
4729
4730 tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4731 PP_ASSERT_WITH_CODE((0 == tmp_result),
4732 "Failed to find DPM states clocks in DPM table!",
4733 result = tmp_result);
4734
4735 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4736 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4737 tmp_result =
4738 fiji_request_link_speed_change_before_state_change(hwmgr, input);
4739 PP_ASSERT_WITH_CODE((0 == tmp_result),
4740 "Failed to request link speed change before state change!",
4741 result = tmp_result);
4742 }
4743
4744 tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4745 PP_ASSERT_WITH_CODE((0 == tmp_result),
4746 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4747
4748 tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4749 PP_ASSERT_WITH_CODE((0 == tmp_result),
4750 "Failed to populate and upload SCLK MCLK DPM levels!",
4751 result = tmp_result);
4752
4753 tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4754 PP_ASSERT_WITH_CODE((0 == tmp_result),
4755 "Failed to generate DPM level enabled mask!",
4756 result = tmp_result);
4757
4758 tmp_result = fiji_update_vce_dpm(hwmgr, input);
4759 PP_ASSERT_WITH_CODE((0 == tmp_result),
4760 "Failed to update VCE DPM!",
4761 result = tmp_result);
4762
4763 tmp_result = fiji_update_sclk_threshold(hwmgr);
4764 PP_ASSERT_WITH_CODE((0 == tmp_result),
4765 "Failed to update SCLK threshold!",
4766 result = tmp_result);
4767
4768 tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4769 PP_ASSERT_WITH_CODE((0 == tmp_result),
4770 "Failed to program memory timing parameters!",
4771 result = tmp_result);
4772
4773 tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4774 PP_ASSERT_WITH_CODE((0 == tmp_result),
4775 "Failed to unfreeze SCLK MCLK DPM!",
4776 result = tmp_result);
4777
4778 tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4779 PP_ASSERT_WITH_CODE((0 == tmp_result),
4780 "Failed to upload DPM level enabled mask!",
4781 result = tmp_result);
4782
4783 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4784 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4785 tmp_result =
4786 fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4787 PP_ASSERT_WITH_CODE((0 == tmp_result),
4788 "Failed to notify link speed change after state change!",
4789 result = tmp_result);
4790 }
4791
4792 return result;
4793}
4794
4795static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4796{
4797 struct pp_power_state *ps;
4798 struct fiji_power_state *fiji_ps;
4799
4800 if (hwmgr == NULL)
4801 return -EINVAL;
4802
4803 ps = hwmgr->request_ps;
4804
4805 if (ps == NULL)
4806 return -EINVAL;
4807
4808 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4809
4810 if (low)
4811 return fiji_ps->performance_levels[0].engine_clock;
4812 else
4813 return fiji_ps->performance_levels
4814 [fiji_ps->performance_level_count-1].engine_clock;
4815}
4816
4817static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4818{
4819 struct pp_power_state *ps;
4820 struct fiji_power_state *fiji_ps;
4821
4822 if (hwmgr == NULL)
4823 return -EINVAL;
4824
4825 ps = hwmgr->request_ps;
4826
4827 if (ps == NULL)
4828 return -EINVAL;
4829
4830 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4831
4832 if (low)
4833 return fiji_ps->performance_levels[0].memory_clock;
4834 else
4835 return fiji_ps->performance_levels
4836 [fiji_ps->performance_level_count-1].memory_clock;
4837}
4838
4839static void fiji_print_current_perforce_level(
4840 struct pp_hwmgr *hwmgr, struct seq_file *m)
4841{
4842 uint32_t sclk, mclk;
4843
4844 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4845
4846 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4847
4848 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4849
4850 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4851 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4852 mclk / 100, sclk / 100);
4853}
4854
4855static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
4856 .backend_init = &fiji_hwmgr_backend_init,
4857 .backend_fini = &tonga_hwmgr_backend_fini,
4858 .asic_setup = &fiji_setup_asic_task,
4859 .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
4860 .force_dpm_level = &fiji_dpm_force_dpm_level,
4861 .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
4862 .get_power_state_size = &fiji_get_power_state_size,
4863 .get_pp_table_entry = &fiji_get_pp_table_entry,
4864 .patch_boot_state = &fiji_patch_boot_state,
4865 .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
4866 .power_state_set = &fiji_set_power_state_tasks,
4867 .get_sclk = &fiji_dpm_get_sclk,
4868 .get_mclk = &fiji_dpm_get_mclk,
4869 .print_current_perforce_level = &fiji_print_current_perforce_level,
91c4c981
EH		 4870 .powergate_uvd = &fiji_phm_powergate_uvd,
4871 .powergate_vce = &fiji_phm_powergate_vce,
4872 .disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
aabcb7c1
EH		 4873};
4874
4875int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
4876{
4877 struct fiji_hwmgr *data;
4878 int ret = 0;
4879
4880 data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
4881 if (data == NULL)
4882 return -ENOMEM;
4883
4884 hwmgr->backend = data;
4885 hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
4886 hwmgr->pptable_func = &tonga_pptable_funcs;
4887 return ret;
4888}
Linux kernel - Deliverables
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