[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hardwaremanager.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/errno.h>
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "power_state.h"
#include "pp_acpi.h"
#include "amd_acpi.h"
#include "amd_powerplay.h"

#define PHM_FUNC_CHECK(hw) \
	do {							\
		if ((hw) == NULL || (hw)->hwmgr_func == NULL)	\
			return -EINVAL;				\
	} while (0)

void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);

	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
}

bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
{
	return hwmgr->block_hw_access;
}

int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
{
	hwmgr->block_hw_access = block;
	return 0;
}

int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->asic_setup)
			return hwmgr->hwmgr_func->asic_setup(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_power_down_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_off_asic)
			return hwmgr->hwmgr_func->power_off_asic(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		    const struct pp_hw_power_state *pnew_power_state)
{
	struct phm_set_power_state_input states;

	PHM_FUNC_CHECK(hwmgr);

	states.pcurrent_state = pcurrent_state;
	states.pnew_state = pnew_power_state;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_state_set)
			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	}

	return 0;
}

int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
			return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr,
				&(hwmgr->enable_dynamic_state_management),
				NULL, NULL);
	}
	return 0;
}

int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

	return 0;
}

int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
		return hwmgr->hwmgr_func->apply_state_adjust_rules(
									hwmgr,
								 adjusted_ps,
								 current_ps);
	return 0;
}

int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	return 0;
}

int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	return 0;
}

int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_vce != NULL)
		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	return 0;
}

int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	}
	return 0;
}

int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->display_config_changed)
			hwmgr->hwmgr_func->display_config_changed(hwmgr);
	} else
		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
	return 0;
}

int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface))
		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);

	return 0;
}

int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
}

int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
}

/**
* Initializes the thermal controller subsystem.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pTemperatureRange the address of the structure holding the temperature range.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
*/
int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
{
	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
}


bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
}


int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_states_equal == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
}

int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		    const struct amd_pp_display_configuration *display_config)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
		return -EINVAL;

	hwmgr->display_config = *display_config;
	/* to do pass other display configuration in furture */

	if (hwmgr->hwmgr_func->store_cc6_data)
		hwmgr->hwmgr_func->store_cc6_data(hwmgr,
				display_config->cpu_pstate_separation_time,
				display_config->cpu_cc6_disable,
				display_config->cpu_pstate_disable,
				display_config->nb_pstate_switch_disable);

	return 0;
}

int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_dal_clock_info *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
}

int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);

	return 0;
}
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/errno.h>
	24	#include "hwmgr.h"
	25	#include "hardwaremanager.h"
28a18bab	26	#include "power_state.h"
3bace359 JZ	27	#include "pp_acpi.h"
3bace359 JZ	28	#include "amd_acpi.h"
7fb72a1f	29	#include "amd_powerplay.h"
3bace359	30
88b8dcbe RZ	31	#define PHM_FUNC_CHECK(hw) \
	32	do { \
	33	if ((hw) == NULL \|\| (hw)->hwmgr_func == NULL) \
	34	return -EINVAL; \
	35	} while (0)
	36
3bace359 JZ	37	void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
	38	{
	39	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	40	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	41	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	42	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	43	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	44	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	45	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	46	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	47	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	48	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
	49
	50	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	51	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	52	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
	53
	54	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	55
	56	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	57	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
	58
	59	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
	60
	61	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
	62	acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
	63	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	64	}
	65
28a18bab RZ	66	bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
	67	{
	68	return hwmgr->block_hw_access;
	69	}
	70
	71	int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
	72	{
	73	hwmgr->block_hw_access = block;
	74	return 0;
	75	}
	76
3bace359 JZ	77	int phm_setup_asic(struct pp_hwmgr *hwmgr)
3bace359 JZ	78	{
88b8dcbe RZ	79	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	80
3bace359 JZ	81	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	82	PHM_PlatformCaps_TablelessHardwareInterface)) {
	83	if (NULL != hwmgr->hwmgr_func->asic_setup)
	84	return hwmgr->hwmgr_func->asic_setup(hwmgr);
	85	} else {
28a18bab	86	return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
3bace359 JZ	87	NULL, NULL);
	88	}
	89
	90	return 0;
	91	}
	92
e1d32e60 RZ	93	int phm_power_down_asic(struct pp_hwmgr *hwmgr)
	94	{
	95	PHM_FUNC_CHECK(hwmgr);
	96
	97	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	98	PHM_PlatformCaps_TablelessHardwareInterface)) {
	99	if (NULL != hwmgr->hwmgr_func->power_off_asic)
	100	return hwmgr->hwmgr_func->power_off_asic(hwmgr);
	101	} else {
	102	return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
	103	NULL, NULL);
	104	}
	105
	106	return 0;
	107	}
	108
28a18bab RZ	109	int phm_set_power_state(struct pp_hwmgr *hwmgr,
	110	const struct pp_hw_power_state *pcurrent_state,
	111	const struct pp_hw_power_state *pnew_power_state)
	112	{
	113	struct phm_set_power_state_input states;
	114
88b8dcbe RZ	115	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	116
28a18bab RZ	117	states.pcurrent_state = pcurrent_state;
	118	states.pnew_state = pnew_power_state;
	119
	120	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	121	PHM_PlatformCaps_TablelessHardwareInterface)) {
	122	if (NULL != hwmgr->hwmgr_func->power_state_set)
	123	return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	124	} else {
	125	return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	126	}
	127
	128	return 0;
	129	}
	130
3bace359 JZ	131	int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
3bace359 JZ	132	{
88b8dcbe RZ	133	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	134
3bace359 JZ	135	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	136	PHM_PlatformCaps_TablelessHardwareInterface)) {
	137	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
	138	return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	139	} else {
28a18bab	140	return phm_dispatch_table(hwmgr,
3bace359 JZ	141	&(hwmgr->enable_dynamic_state_management),
	142	NULL, NULL);
	143	}
	144	return 0;
	145	}
28a18bab RZ	146
	147	int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
	148	{
88b8dcbe RZ	149	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	150
28a18bab RZ	151	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
	152	return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
	153
	154	return 0;
	155	}
	156
	157	int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
	158	struct pp_power_state *adjusted_ps,
	159	const struct pp_power_state *current_ps)
	160	{
88b8dcbe RZ	161	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	162
28a18bab RZ	163	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
	164	return hwmgr->hwmgr_func->apply_state_adjust_rules(
	165	hwmgr,
	166	adjusted_ps,
	167	current_ps);
	168	return 0;
	169	}
	170
	171	int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
	172	{
88b8dcbe RZ	173	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	174
28a18bab RZ	175	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
	176	return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	177	return 0;
	178	}
	179
	180	int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
	181	{
88b8dcbe RZ	182	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	183
28a18bab RZ	184	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
	185	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	186	return 0;
	187	}
	188
	189	int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
	190	{
88b8dcbe RZ	191	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	192
28a18bab RZ	193	if (hwmgr->hwmgr_func->powergate_vce != NULL)
	194	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	195	return 0;
	196	}
	197
	198	int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
	199	{
88b8dcbe RZ	200	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	201
28a18bab RZ	202	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	203	PHM_PlatformCaps_TablelessHardwareInterface)) {
	204	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
	205	return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	206	} else {
	207	return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	208	}
	209	return 0;
	210	}
6f3bf747 RZ	211
	212	int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
	213	{
88b8dcbe	214	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	215
	216	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	217	PHM_PlatformCaps_TablelessHardwareInterface)) {
	218	if (NULL != hwmgr->hwmgr_func->display_config_changed)
	219	hwmgr->hwmgr_func->display_config_changed(hwmgr);
	220	} else
	221	return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
73afe621	222	return 0;
6f3bf747 RZ	223	}
	224
	225	int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
	226	{
88b8dcbe	227	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	228
	229	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	230	PHM_PlatformCaps_TablelessHardwareInterface))
eafbbd98	231	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
6f3bf747 RZ	232	hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
6f3bf747 RZ	233
73afe621	234	return 0;
6f3bf747	235	}
fba4eef5 RZ	236
	237	int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
	238	{
88b8dcbe RZ	239	PHM_FUNC_CHECK(hwmgr);
	240
	241	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
fba4eef5 RZ	242	return -EINVAL;
	243
	244	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
	245	}
	246
	247	int phm_register_thermal_interrupt(struct pp_hwmgr hwmgr, const void info)
	248	{
88b8dcbe RZ	249	PHM_FUNC_CHECK(hwmgr);
	250
	251	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
fba4eef5 RZ	252	return -EINVAL;
	253
	254	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
	255	}
	256
	257	/**
	258	* Initializes the thermal controller subsystem.
	259	*
	260	* @param pHwMgr the address of the powerplay hardware manager.
	261	* @param pTemperatureRange the address of the structure holding the temperature range.
	262	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
	263	*/
	264	int phm_start_thermal_controller(struct pp_hwmgr hwmgr, struct PP_TemperatureRange temperature_range)
	265	{
fba4eef5 RZ	266	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
fba4eef5 RZ	267	}
09b4c872 RZ	268
	269
	270	bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
	271	{
88b8dcbe RZ	272	PHM_FUNC_CHECK(hwmgr);
	273
	274	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
09b4c872 RZ	275	return -EINVAL;
	276
	277	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
	278	}
	279
	280
	281	int phm_check_states_equal(struct pp_hwmgr *hwmgr,
	282	const struct pp_hw_power_state *pstate1,
	283	const struct pp_hw_power_state *pstate2,
	284	bool *equal)
	285	{
88b8dcbe RZ	286	PHM_FUNC_CHECK(hwmgr);
	287
	288	if (hwmgr->hwmgr_func->check_states_equal == NULL)
09b4c872 RZ	289	return -EINVAL;
	290
	291	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
	292	}
7fb72a1f RZ	293
	294	int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
	295	const struct amd_pp_display_configuration *display_config)
	296	{
88b8dcbe	297	PHM_FUNC_CHECK(hwmgr);
14f63411	298
88b8dcbe	299	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
7fb72a1f RZ	300	return -EINVAL;
7fb72a1f RZ	301
14f63411	302	hwmgr->display_config = *display_config;
7fb72a1f	303	/* to do pass other display configuration in furture */
7fb72a1f	304
14f63411 EY	305	if (hwmgr->hwmgr_func->store_cc6_data)
	306	hwmgr->hwmgr_func->store_cc6_data(hwmgr,
	307	display_config->cpu_pstate_separation_time,
	308	display_config->cpu_cc6_disable,
	309	display_config->cpu_pstate_disable,
	310	display_config->nb_pstate_switch_disable);
	311
	312	return 0;
7fb72a1f	313	}
73afe621	314
c4dd206b	315	int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
88b8dcbe	316	struct amd_pp_dal_clock_info *info)
c4dd206b	317	{
88b8dcbe RZ	318	PHM_FUNC_CHECK(hwmgr);
	319
	320	if (info == NULL \|\| hwmgr->hwmgr_func->get_dal_power_level == NULL)
c4dd206b VP	321	return -EINVAL;
c4dd206b VP	322
1c9a9082	323	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
c4dd206b VP	324	}
c4dd206b VP	325
73afe621 RZ	326	int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
73afe621 RZ	327	{
88b8dcbe RZ	328	PHM_FUNC_CHECK(hwmgr);
	329
	330	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
73afe621 RZ	331	return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
	332
	333	return 0;
	334	}