[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hardwaremanager.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/errno.h>
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "power_state.h"
#include "pp_acpi.h"
#include "amd_acpi.h"
#include "pp_debug.h"

#define PHM_FUNC_CHECK(hw) \
	do {							\
		if ((hw) == NULL || (hw)->hwmgr_func == NULL)	\
			return -EINVAL;				\
	} while (0)

void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);

	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
}

bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
{
	return hwmgr->block_hw_access;
}

int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
{
	hwmgr->block_hw_access = block;
	return 0;
}

int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->asic_setup)
			return hwmgr->hwmgr_func->asic_setup(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_power_down_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_off_asic)
			return hwmgr->hwmgr_func->power_off_asic(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		    const struct pp_hw_power_state *pnew_power_state)
{
	struct phm_set_power_state_input states;

	PHM_FUNC_CHECK(hwmgr);

	states.pcurrent_state = pcurrent_state;
	states.pnew_state = pnew_power_state;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_state_set)
			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	}

	return 0;
}

int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	int ret = 1;
	bool enabled;
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
			ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	} else {
		ret = phm_dispatch_table(hwmgr,
				&(hwmgr->enable_dynamic_state_management),
				NULL, NULL);
	}

	enabled = ret == 0 ? true : false;

	cgs_notify_dpm_enabled(hwmgr->device, enabled);

	return ret;
}

int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	int ret = -1;
	bool enabled;

	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (hwmgr->hwmgr_func->dynamic_state_management_disable)
			ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
	} else {
		ret = phm_dispatch_table(hwmgr,
				&(hwmgr->disable_dynamic_state_management),
				NULL, NULL);
	}

	enabled = ret == 0 ? false : true;

	cgs_notify_dpm_enabled(hwmgr->device, enabled);

	return ret;
}

int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

	return 0;
}

int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
		return hwmgr->hwmgr_func->apply_state_adjust_rules(
									hwmgr,
								 adjusted_ps,
								 current_ps);
	return 0;
}

int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	return 0;
}

int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	return 0;
}

int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_vce != NULL)
		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	return 0;
}

int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	}
	return 0;
}

int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->display_config_changed)
			hwmgr->hwmgr_func->display_config_changed(hwmgr);
	} else
		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
	return 0;
}

int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface))
		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);

	return 0;
}

int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
}

int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
}

/**
* Initializes the thermal controller subsystem.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pTemperatureRange the address of the structure holding the temperature range.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
*/
int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
{
	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
}


bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
}


int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_states_equal == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
}

int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		    const struct amd_pp_display_configuration *display_config)
{
	PHM_FUNC_CHECK(hwmgr);

	if (display_config == NULL)
		return -EINVAL;

	hwmgr->display_config = *display_config;

	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
		return -EINVAL;

	/* TODO: pass other display configuration in the future */

	if (hwmgr->hwmgr_func->store_cc6_data)
		hwmgr->hwmgr_func->store_cc6_data(hwmgr,
				display_config->cpu_pstate_separation_time,
				display_config->cpu_cc6_disable,
				display_config->cpu_pstate_disable,
				display_config->nb_pstate_switch_disable);

	return 0;
}

int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_simple_clock_info *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
		return -EINVAL;
	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
}

int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);

	return 0;
}


int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
				PHM_PerformanceLevelDesignation designation, uint32_t index,
				PHM_PerformanceLevel *level)
{
	PHM_FUNC_CHECK(hwmgr);
	if (hwmgr->hwmgr_func->get_performance_level == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);


}


/**
* Gets Clock Info.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pPowerState the address of the Power State structure.
* @param    pClockInfo the address of PP_ClockInfo structure where the result will be returned.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
*/
int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
			PHM_PerformanceLevelDesignation designation)
{
	int result;
	PHM_PerformanceLevel performance_level;

	PHM_FUNC_CHECK(hwmgr);

	PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
	PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);

	result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);

	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);


	pclock_info->min_mem_clk = performance_level.memory_clock;
	pclock_info->min_eng_clk = performance_level.coreClock;
	pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;


	result = phm_get_performance_level(hwmgr, state, designation,
					(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);

	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);

	pclock_info->max_mem_clk = performance_level.memory_clock;
	pclock_info->max_eng_clk = performance_level.coreClock;
	pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;

	return 0;
}

int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);

}

int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);

}

int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
}
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/errno.h>
	24	#include "hwmgr.h"
	25	#include "hardwaremanager.h"
28a18bab	26	#include "power_state.h"
3bace359 JZ	27	#include "pp_acpi.h"
3bace359 JZ	28	#include "amd_acpi.h"
e273b041	29	#include "pp_debug.h"
3bace359	30
88b8dcbe RZ	31	#define PHM_FUNC_CHECK(hw) \
	32	do { \
	33	if ((hw) == NULL \|\| (hw)->hwmgr_func == NULL) \
	34	return -EINVAL; \
	35	} while (0)
	36
3bace359 JZ	37	void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
	38	{
	39	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	40	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	41	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	42	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	43	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	44	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	45	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	46	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	47	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	48	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
	49
	50	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	51	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	52	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
	53
	54	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	55
	56	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	57	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
	58
	59	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
	60
91628231 RZ	61	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
	62	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
	63
3bace359 JZ	64	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
	65	acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
	66	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	67	}
	68
28a18bab RZ	69	bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
	70	{
	71	return hwmgr->block_hw_access;
	72	}
	73
	74	int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
	75	{
	76	hwmgr->block_hw_access = block;
	77	return 0;
	78	}
	79
3bace359 JZ	80	int phm_setup_asic(struct pp_hwmgr *hwmgr)
3bace359 JZ	81	{
88b8dcbe RZ	82	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	83
3bace359 JZ	84	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	85	PHM_PlatformCaps_TablelessHardwareInterface)) {
	86	if (NULL != hwmgr->hwmgr_func->asic_setup)
	87	return hwmgr->hwmgr_func->asic_setup(hwmgr);
	88	} else {
28a18bab	89	return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
3bace359 JZ	90	NULL, NULL);
	91	}
	92
	93	return 0;
	94	}
	95
e1d32e60 RZ	96	int phm_power_down_asic(struct pp_hwmgr *hwmgr)
	97	{
	98	PHM_FUNC_CHECK(hwmgr);
	99
	100	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	101	PHM_PlatformCaps_TablelessHardwareInterface)) {
	102	if (NULL != hwmgr->hwmgr_func->power_off_asic)
	103	return hwmgr->hwmgr_func->power_off_asic(hwmgr);
	104	} else {
	105	return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
	106	NULL, NULL);
	107	}
	108
	109	return 0;
	110	}
	111
28a18bab RZ	112	int phm_set_power_state(struct pp_hwmgr *hwmgr,
	113	const struct pp_hw_power_state *pcurrent_state,
	114	const struct pp_hw_power_state *pnew_power_state)
	115	{
	116	struct phm_set_power_state_input states;
	117
88b8dcbe RZ	118	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	119
28a18bab RZ	120	states.pcurrent_state = pcurrent_state;
	121	states.pnew_state = pnew_power_state;
	122
	123	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	124	PHM_PlatformCaps_TablelessHardwareInterface)) {
	125	if (NULL != hwmgr->hwmgr_func->power_state_set)
	126	return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	127	} else {
	128	return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	129	}
	130
	131	return 0;
	132	}
	133
3bace359 JZ	134	int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
3bace359 JZ	135	{
4cd05a74 RZ	136	int ret = 1;
4cd05a74 RZ	137	bool enabled;
88b8dcbe RZ	138	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	139
3bace359 JZ	140	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	141	PHM_PlatformCaps_TablelessHardwareInterface)) {
	142	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
4cd05a74	143	ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
3bace359	144	} else {
4cd05a74	145	ret = phm_dispatch_table(hwmgr,
3bace359 JZ	146	&(hwmgr->enable_dynamic_state_management),
	147	NULL, NULL);
	148	}
4cd05a74 RZ	149
	150	enabled = ret == 0 ? true : false;
	151
	152	cgs_notify_dpm_enabled(hwmgr->device, enabled);
	153
80597521 EH	154	return ret;
	155	}
	156
	157	int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
	158	{
	159	int ret = -1;
	160	bool enabled;
	161
	162	PHM_FUNC_CHECK(hwmgr);
	163
	164	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	165	PHM_PlatformCaps_TablelessHardwareInterface)) {
	166	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
	167	ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
	168	} else {
	169	ret = phm_dispatch_table(hwmgr,
	170	&(hwmgr->disable_dynamic_state_management),
	171	NULL, NULL);
	172	}
	173
	174	enabled = ret == 0 ? false : true;
	175
	176	cgs_notify_dpm_enabled(hwmgr->device, enabled);
	177
4cd05a74	178	return ret;
3bace359	179	}
28a18bab RZ	180
	181	int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
	182	{
88b8dcbe RZ	183	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	184
28a18bab RZ	185	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
	186	return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
	187
	188	return 0;
	189	}
	190
	191	int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
	192	struct pp_power_state *adjusted_ps,
	193	const struct pp_power_state *current_ps)
	194	{
88b8dcbe RZ	195	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	196
28a18bab RZ	197	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
	198	return hwmgr->hwmgr_func->apply_state_adjust_rules(
	199	hwmgr,
	200	adjusted_ps,
	201	current_ps);
	202	return 0;
	203	}
	204
	205	int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
	206	{
88b8dcbe RZ	207	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	208
28a18bab RZ	209	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
	210	return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	211	return 0;
	212	}
	213
	214	int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
	215	{
88b8dcbe RZ	216	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	217
28a18bab RZ	218	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
	219	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	220	return 0;
	221	}
	222
	223	int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
	224	{
88b8dcbe RZ	225	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	226
28a18bab RZ	227	if (hwmgr->hwmgr_func->powergate_vce != NULL)
	228	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	229	return 0;
	230	}
	231
	232	int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
	233	{
88b8dcbe RZ	234	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	235
28a18bab RZ	236	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	237	PHM_PlatformCaps_TablelessHardwareInterface)) {
	238	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
	239	return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	240	} else {
	241	return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	242	}
	243	return 0;
	244	}
6f3bf747 RZ	245
	246	int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
	247	{
88b8dcbe	248	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	249
	250	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	251	PHM_PlatformCaps_TablelessHardwareInterface)) {
	252	if (NULL != hwmgr->hwmgr_func->display_config_changed)
	253	hwmgr->hwmgr_func->display_config_changed(hwmgr);
	254	} else
	255	return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
73afe621	256	return 0;
6f3bf747 RZ	257	}
	258
	259	int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
	260	{
88b8dcbe	261	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	262
	263	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	264	PHM_PlatformCaps_TablelessHardwareInterface))
eafbbd98	265	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
6f3bf747 RZ	266	hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
6f3bf747 RZ	267
73afe621	268	return 0;
6f3bf747	269	}
fba4eef5 RZ	270
	271	int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
	272	{
88b8dcbe RZ	273	PHM_FUNC_CHECK(hwmgr);
	274
	275	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
fba4eef5 RZ	276	return -EINVAL;
	277
	278	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
	279	}
	280
	281	int phm_register_thermal_interrupt(struct pp_hwmgr hwmgr, const void info)
	282	{
88b8dcbe RZ	283	PHM_FUNC_CHECK(hwmgr);
	284
	285	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
fba4eef5 RZ	286	return -EINVAL;
	287
	288	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
	289	}
	290
	291	/**
	292	* Initializes the thermal controller subsystem.
	293	*
	294	* @param pHwMgr the address of the powerplay hardware manager.
	295	* @param pTemperatureRange the address of the structure holding the temperature range.
	296	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
	297	*/
	298	int phm_start_thermal_controller(struct pp_hwmgr hwmgr, struct PP_TemperatureRange temperature_range)
	299	{
fba4eef5 RZ	300	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
fba4eef5 RZ	301	}
09b4c872 RZ	302
	303
	304	bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
	305	{
88b8dcbe RZ	306	PHM_FUNC_CHECK(hwmgr);
	307
	308	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
09b4c872 RZ	309	return -EINVAL;
	310
	311	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
	312	}
	313
	314
	315	int phm_check_states_equal(struct pp_hwmgr *hwmgr,
	316	const struct pp_hw_power_state *pstate1,
	317	const struct pp_hw_power_state *pstate2,
	318	bool *equal)
	319	{
88b8dcbe RZ	320	PHM_FUNC_CHECK(hwmgr);
	321
	322	if (hwmgr->hwmgr_func->check_states_equal == NULL)
09b4c872 RZ	323	return -EINVAL;
	324
	325	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
	326	}
7fb72a1f RZ	327
	328	int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
	329	const struct amd_pp_display_configuration *display_config)
	330	{
88b8dcbe	331	PHM_FUNC_CHECK(hwmgr);
14f63411	332
1d7b84d1	333	if (display_config == NULL)
7fb72a1f RZ	334	return -EINVAL;
7fb72a1f RZ	335
14f63411	336	hwmgr->display_config = *display_config;
1d7b84d1 RZ	337
	338	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
	339	return -EINVAL;
	340
023efca2	341	/* TODO: pass other display configuration in the future */
7fb72a1f	342
14f63411 EY	343	if (hwmgr->hwmgr_func->store_cc6_data)
	344	hwmgr->hwmgr_func->store_cc6_data(hwmgr,
	345	display_config->cpu_pstate_separation_time,
	346	display_config->cpu_cc6_disable,
	347	display_config->cpu_pstate_disable,
	348	display_config->nb_pstate_switch_disable);
	349
	350	return 0;
7fb72a1f	351	}
73afe621	352
c4dd206b	353	int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
47329134	354	struct amd_pp_simple_clock_info *info)
c4dd206b	355	{
88b8dcbe RZ	356	PHM_FUNC_CHECK(hwmgr);
	357
	358	if (info == NULL \|\| hwmgr->hwmgr_func->get_dal_power_level == NULL)
c4dd206b	359	return -EINVAL;
1c9a9082	360	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
c4dd206b VP	361	}
c4dd206b VP	362
73afe621 RZ	363	int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
73afe621 RZ	364	{
88b8dcbe RZ	365	PHM_FUNC_CHECK(hwmgr);
	366
	367	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
73afe621 RZ	368	return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
	369
	370	return 0;
	371	}
e273b041 RZ	372
	373
	374	int phm_get_performance_level(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state,
	375	PHM_PerformanceLevelDesignation designation, uint32_t index,
	376	PHM_PerformanceLevel *level)
	377	{
	378	PHM_FUNC_CHECK(hwmgr);
	379	if (hwmgr->hwmgr_func->get_performance_level == NULL)
	380	return -EINVAL;
	381
	382	return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
	383
	384
	385	}
	386
	387
	388	/**
	389	* Gets Clock Info.
	390	*
	391	* @param pHwMgr the address of the powerplay hardware manager.
	392	* @param pPowerState the address of the Power State structure.
	393	* @param pClockInfo the address of PP_ClockInfo structure where the result will be returned.
	394	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
	395	*/
	396	int phm_get_clock_info(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state, struct pp_clock_info *pclock_info,
	397	PHM_PerformanceLevelDesignation designation)
	398	{
	399	int result;
	400	PHM_PerformanceLevel performance_level;
	401
	402	PHM_FUNC_CHECK(hwmgr);
	403
	404	PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
	405	PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
	406
	407	result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
	408
	409	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
	410
	411
	412	pclock_info->min_mem_clk = performance_level.memory_clock;
	413	pclock_info->min_eng_clk = performance_level.coreClock;
	414	pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
	415
	416
	417	result = phm_get_performance_level(hwmgr, state, designation,
	418	(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
	419
	420	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
	421
	422	pclock_info->max_mem_clk = performance_level.memory_clock;
	423	pclock_info->max_eng_clk = performance_level.coreClock;
	424	pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
	425
	426	return 0;
	427	}
	428
	429	int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state, struct pp_clock_info *clock_info)
	430	{
	431	PHM_FUNC_CHECK(hwmgr);
	432
	433	if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
	434	return -EINVAL;
	435
436	return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
437
438	}
439
440	int phm_get_clock_by_type(struct pp_hwmgr hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks clocks)
441	{
442	PHM_FUNC_CHECK(hwmgr);
443
444	if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
445	return -EINVAL;
446
447	return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
448
449	}
450
451	int phm_get_max_high_clocks(struct pp_hwmgr hwmgr, struct amd_pp_simple_clock_info clocks)
452	{
453	PHM_FUNC_CHECK(hwmgr);
454
455	if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
456	return -EINVAL;
457
458	return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
459	}