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c82baa28 | 1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/module.h> | |
24 | #include <linux/slab.h> | |
c82baa28 | 25 | #include "linux/delay.h" |
26 | #include "pp_acpi.h" | |
27 | #include "hwmgr.h" | |
28 | #include <atombios.h> | |
29 | #include "tonga_hwmgr.h" | |
30 | #include "pptable.h" | |
31 | #include "processpptables.h" | |
32 | #include "tonga_processpptables.h" | |
33 | #include "tonga_pptable.h" | |
34 | #include "pp_debug.h" | |
35 | #include "tonga_ppsmc.h" | |
36 | #include "cgs_common.h" | |
37 | #include "pppcielanes.h" | |
38 | #include "tonga_dyn_defaults.h" | |
39 | #include "smumgr.h" | |
40 | #include "tonga_smumgr.h" | |
0859ed3d | 41 | #include "tonga_clockpowergating.h" |
1e4854e9 | 42 | #include "tonga_thermal.h" |
c82baa28 | 43 | |
44 | #include "smu/smu_7_1_2_d.h" | |
45 | #include "smu/smu_7_1_2_sh_mask.h" | |
46 | ||
47 | #include "gmc/gmc_8_1_d.h" | |
48 | #include "gmc/gmc_8_1_sh_mask.h" | |
49 | ||
50 | #include "bif/bif_5_0_d.h" | |
51 | #include "bif/bif_5_0_sh_mask.h" | |
52 | ||
7e8d1fbd AD |
53 | #include "dce/dce_10_0_d.h" |
54 | #include "dce/dce_10_0_sh_mask.h" | |
55 | ||
1e4854e9 RZ |
56 | #include "cgs_linux.h" |
57 | #include "eventmgr.h" | |
16881da6 | 58 | #include "amd_pcie_helpers.h" |
1e4854e9 | 59 | |
c82baa28 | 60 | #define MC_CG_ARB_FREQ_F0 0x0a |
61 | #define MC_CG_ARB_FREQ_F1 0x0b | |
62 | #define MC_CG_ARB_FREQ_F2 0x0c | |
63 | #define MC_CG_ARB_FREQ_F3 0x0d | |
64 | ||
65 | #define MC_CG_SEQ_DRAMCONF_S0 0x05 | |
66 | #define MC_CG_SEQ_DRAMCONF_S1 0x06 | |
67 | #define MC_CG_SEQ_YCLK_SUSPEND 0x04 | |
68 | #define MC_CG_SEQ_YCLK_RESUME 0x0a | |
69 | ||
70 | #define PCIE_BUS_CLK 10000 | |
71 | #define TCLK (PCIE_BUS_CLK / 10) | |
72 | ||
73 | #define SMC_RAM_END 0x40000 | |
74 | #define SMC_CG_IND_START 0xc0030000 | |
75 | #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/ | |
76 | ||
77 | #define VOLTAGE_SCALE 4 | |
78 | #define VOLTAGE_VID_OFFSET_SCALE1 625 | |
79 | #define VOLTAGE_VID_OFFSET_SCALE2 100 | |
80 | ||
81 | #define VDDC_VDDCI_DELTA 200 | |
82 | #define VDDC_VDDGFX_DELTA 300 | |
83 | ||
84 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | |
85 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | |
86 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | |
87 | ||
88 | typedef uint32_t PECI_RegistryValue; | |
89 | ||
90 | /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ | |
f498d9ed | 91 | static const uint16_t PP_ClockStretcherLookupTable[2][4] = { |
c82baa28 | 92 | {600, 1050, 3, 0}, |
93 | {600, 1050, 6, 1} }; | |
94 | ||
95 | /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ | |
f498d9ed | 96 | static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = { |
c82baa28 | 97 | { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, |
98 | { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; | |
99 | ||
100 | /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ | |
f498d9ed | 101 | static const uint8_t PP_ClockStretchAmountConversion[2][6] = { |
c82baa28 | 102 | {0, 1, 3, 2, 4, 5}, |
103 | {0, 2, 4, 5, 6, 5} }; | |
104 | ||
105 | /* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ | |
106 | enum DPM_EVENT_SRC { | |
107 | DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */ | |
108 | DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */ | |
109 | DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */ | |
110 | DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */ | |
111 | DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */ | |
112 | }; | |
113 | typedef enum DPM_EVENT_SRC DPM_EVENT_SRC; | |
114 | ||
f498d9ed | 115 | static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); |
c82baa28 | 116 | |
117 | struct tonga_power_state *cast_phw_tonga_power_state( | |
118 | struct pp_hw_power_state *hw_ps) | |
119 | { | |
c15c8d70 RZ |
120 | if (hw_ps == NULL) |
121 | return NULL; | |
122 | ||
c82baa28 | 123 | PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), |
124 | "Invalid Powerstate Type!", | |
c15c8d70 | 125 | return NULL); |
c82baa28 | 126 | |
127 | return (struct tonga_power_state *)hw_ps; | |
128 | } | |
129 | ||
130 | const struct tonga_power_state *cast_const_phw_tonga_power_state( | |
131 | const struct pp_hw_power_state *hw_ps) | |
132 | { | |
c15c8d70 RZ |
133 | if (hw_ps == NULL) |
134 | return NULL; | |
135 | ||
c82baa28 | 136 | PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), |
137 | "Invalid Powerstate Type!", | |
c15c8d70 | 138 | return NULL); |
c82baa28 | 139 | |
140 | return (const struct tonga_power_state *)hw_ps; | |
141 | } | |
142 | ||
143 | int tonga_add_voltage(struct pp_hwmgr *hwmgr, | |
144 | phm_ppt_v1_voltage_lookup_table *look_up_table, | |
145 | phm_ppt_v1_voltage_lookup_record *record) | |
146 | { | |
147 | uint32_t i; | |
148 | PP_ASSERT_WITH_CODE((NULL != look_up_table), | |
149 | "Lookup Table empty.", return -1;); | |
150 | PP_ASSERT_WITH_CODE((0 != look_up_table->count), | |
151 | "Lookup Table empty.", return -1;); | |
152 | PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count), | |
153 | "Lookup Table is full.", return -1;); | |
154 | ||
155 | /* This is to avoid entering duplicate calculated records. */ | |
156 | for (i = 0; i < look_up_table->count; i++) { | |
157 | if (look_up_table->entries[i].us_vdd == record->us_vdd) { | |
158 | if (look_up_table->entries[i].us_calculated == 1) | |
159 | return 0; | |
160 | else | |
161 | break; | |
162 | } | |
163 | } | |
164 | ||
165 | look_up_table->entries[i].us_calculated = 1; | |
166 | look_up_table->entries[i].us_vdd = record->us_vdd; | |
167 | look_up_table->entries[i].us_cac_low = record->us_cac_low; | |
168 | look_up_table->entries[i].us_cac_mid = record->us_cac_mid; | |
169 | look_up_table->entries[i].us_cac_high = record->us_cac_high; | |
170 | /* Only increment the count when we're appending, not replacing duplicate entry. */ | |
171 | if (i == look_up_table->count) | |
172 | look_up_table->count++; | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
bbb207f3 RZ |
177 | int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) |
178 | { | |
179 | PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; | |
180 | ||
181 | return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; | |
182 | } | |
183 | ||
c82baa28 | 184 | uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, |
185 | uint32_t voltage) | |
186 | { | |
187 | uint8_t count = (uint8_t) (voltage_table->count); | |
188 | uint8_t i = 0; | |
189 | ||
190 | PP_ASSERT_WITH_CODE((NULL != voltage_table), | |
191 | "Voltage Table empty.", return 0;); | |
192 | PP_ASSERT_WITH_CODE((0 != count), | |
193 | "Voltage Table empty.", return 0;); | |
194 | ||
195 | for (i = 0; i < count; i++) { | |
196 | /* find first voltage bigger than requested */ | |
197 | if (voltage_table->entries[i].value >= voltage) | |
198 | return i; | |
199 | } | |
200 | ||
201 | /* voltage is bigger than max voltage in the table */ | |
202 | return i - 1; | |
203 | } | |
204 | ||
205 | /** | |
206 | * @brief PhwTonga_GetVoltageOrder | |
207 | * Returns index of requested voltage record in lookup(table) | |
208 | * @param hwmgr - pointer to hardware manager | |
209 | * @param lookupTable - lookup list to search in | |
210 | * @param voltage - voltage to look for | |
211 | * @return 0 on success | |
212 | */ | |
213 | uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table, | |
214 | uint16_t voltage) | |
215 | { | |
216 | uint8_t count = (uint8_t) (look_up_table->count); | |
217 | uint8_t i; | |
218 | ||
219 | PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;); | |
220 | PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;); | |
221 | ||
222 | for (i = 0; i < count; i++) { | |
223 | /* find first voltage equal or bigger than requested */ | |
224 | if (look_up_table->entries[i].us_vdd >= voltage) | |
225 | return i; | |
226 | } | |
227 | ||
228 | /* voltage is bigger than max voltage in the table */ | |
229 | return i-1; | |
230 | } | |
231 | ||
232 | bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) | |
233 | { | |
234 | /* | |
235 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM | |
236 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, | |
237 | * whereas voltage control is a fundemental change that will not be disabled | |
238 | */ | |
239 | ||
240 | return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
241 | FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0); | |
242 | } | |
243 | ||
244 | /** | |
245 | * Re-generate the DPM level mask value | |
246 | * @param hwmgr the address of the hardware manager | |
247 | */ | |
248 | static uint32_t tonga_get_dpm_level_enable_mask_value( | |
249 | struct tonga_single_dpm_table * dpm_table) | |
250 | { | |
251 | uint32_t i; | |
252 | uint32_t mask_value = 0; | |
253 | ||
254 | for (i = dpm_table->count; i > 0; i--) { | |
255 | mask_value = mask_value << 1; | |
256 | ||
257 | if (dpm_table->dpm_levels[i-1].enabled) | |
258 | mask_value |= 0x1; | |
259 | else | |
260 | mask_value &= 0xFFFFFFFE; | |
261 | } | |
262 | return mask_value; | |
263 | } | |
264 | ||
265 | /** | |
266 | * Retrieve DPM default values from registry (if available) | |
267 | * | |
268 | * @param hwmgr the address of the powerplay hardware manager. | |
269 | */ | |
270 | void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) | |
271 | { | |
272 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
273 | phw_tonga_ulv_parm *ulv = &(data->ulv); | |
274 | uint32_t tmp; | |
275 | ||
276 | ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT; | |
277 | data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0; | |
278 | data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1; | |
279 | data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2; | |
280 | data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3; | |
281 | data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4; | |
282 | data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5; | |
283 | data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6; | |
284 | data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7; | |
285 | ||
286 | data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT; | |
287 | data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT; | |
288 | ||
289 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
290 | PHM_PlatformCaps_ABM); | |
291 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
292 | PHM_PlatformCaps_NonABMSupportInPPLib); | |
293 | ||
294 | tmp = 0; | |
295 | if (tmp == 0) | |
296 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
297 | PHM_PlatformCaps_DynamicACTiming); | |
298 | ||
299 | tmp = 0; | |
300 | if (0 != tmp) | |
301 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
302 | PHM_PlatformCaps_DisableMemoryTransition); | |
303 | ||
2a702ccd RZ |
304 | tonga_initialize_power_tune_defaults(hwmgr); |
305 | ||
c82baa28 | 306 | data->mclk_strobe_mode_threshold = 40000; |
307 | data->mclk_stutter_mode_threshold = 30000; | |
308 | data->mclk_edc_enable_threshold = 40000; | |
309 | data->mclk_edc_wr_enable_threshold = 40000; | |
310 | ||
311 | tmp = 0; | |
312 | if (tmp != 0) | |
313 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
314 | PHM_PlatformCaps_DisableMCLS); | |
315 | ||
316 | data->pcie_gen_performance.max = PP_PCIEGen1; | |
317 | data->pcie_gen_performance.min = PP_PCIEGen3; | |
318 | data->pcie_gen_power_saving.max = PP_PCIEGen1; | |
319 | data->pcie_gen_power_saving.min = PP_PCIEGen3; | |
320 | ||
321 | data->pcie_lane_performance.max = 0; | |
322 | data->pcie_lane_performance.min = 16; | |
323 | data->pcie_lane_power_saving.max = 0; | |
324 | data->pcie_lane_power_saving.min = 16; | |
325 | ||
326 | tmp = 0; | |
327 | ||
328 | if (tmp) | |
329 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
330 | PHM_PlatformCaps_SclkThrottleLowNotification); | |
331 | ||
332 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
333 | PHM_PlatformCaps_DynamicUVDState); | |
334 | ||
335 | } | |
336 | ||
337 | int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) | |
338 | { | |
339 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
340 | ||
341 | int result = 0; | |
342 | uint32_t low_sclk_interrupt_threshold = 0; | |
343 | ||
344 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
345 | PHM_PlatformCaps_SclkThrottleLowNotification) | |
346 | && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) { | |
347 | data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold; | |
348 | low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold; | |
349 | ||
350 | CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); | |
351 | ||
352 | result = tonga_copy_bytes_to_smc( | |
353 | hwmgr->smumgr, | |
354 | data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, | |
355 | LowSclkInterruptThreshold), | |
356 | (uint8_t *)&low_sclk_interrupt_threshold, | |
357 | sizeof(uint32_t), | |
358 | data->sram_end | |
359 | ); | |
360 | } | |
361 | ||
362 | return result; | |
363 | } | |
364 | ||
365 | /** | |
366 | * Find SCLK value that is associated with specified virtual_voltage_Id. | |
367 | * | |
368 | * @param hwmgr the address of the powerplay hardware manager. | |
369 | * @param virtual_voltage_Id voltageId to look for. | |
370 | * @param sclk output value . | |
371 | * @return always 0 if success and 2 if association not found | |
372 | */ | |
373 | static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, | |
374 | phm_ppt_v1_voltage_lookup_table *lookup_table, | |
375 | uint16_t virtual_voltage_id, uint32_t *sclk) | |
376 | { | |
377 | uint8_t entryId; | |
378 | uint8_t voltageId; | |
379 | struct phm_ppt_v1_information *pptable_info = | |
380 | (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
381 | ||
382 | PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1); | |
383 | ||
384 | /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ | |
385 | for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) { | |
386 | voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd; | |
387 | if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id) | |
388 | break; | |
389 | } | |
390 | ||
391 | PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count, | |
392 | "Can't find requested voltage id in vdd_dep_on_sclk table!", | |
393 | return -1; | |
394 | ); | |
395 | ||
396 | *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk; | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | /** | |
402 | * Get Leakage VDDC based on leakage ID. | |
403 | * | |
404 | * @param hwmgr the address of the powerplay hardware manager. | |
405 | * @return 2 if vddgfx returned is greater than 2V or if BIOS | |
406 | */ | |
407 | int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) | |
408 | { | |
409 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
410 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
411 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; | |
412 | uint16_t virtual_voltage_id; | |
413 | uint16_t vddc = 0; | |
414 | uint16_t vddgfx = 0; | |
415 | uint16_t i, j; | |
416 | uint32_t sclk = 0; | |
417 | ||
418 | /* retrieve voltage for leakage ID (0xff01 + i) */ | |
419 | for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) { | |
420 | virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; | |
421 | ||
422 | /* in split mode we should have only vddgfx EVV leakages */ | |
423 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { | |
424 | if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, | |
425 | pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) { | |
426 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
427 | PHM_PlatformCaps_ClockStretcher)) { | |
428 | for (j = 1; j < sclk_table->count; j++) { | |
429 | if (sclk_table->entries[j].clk == sclk && | |
430 | sclk_table->entries[j].cks_enable == 0) { | |
431 | sclk += 5000; | |
432 | break; | |
433 | } | |
434 | } | |
435 | } | |
ac0cc350 MK |
436 | if (0 == atomctrl_get_voltage_evv_on_sclk |
437 | (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, | |
438 | virtual_voltage_id, &vddgfx)) { | |
439 | /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ | |
440 | PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1); | |
441 | ||
442 | /* the voltage should not be zero nor equal to leakage ID */ | |
443 | if (vddgfx != 0 && vddgfx != virtual_voltage_id) { | |
444 | data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; | |
445 | data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id; | |
446 | data->vddcgfx_leakage.count++; | |
447 | } | |
448 | } else { | |
449 | printk("Error retrieving EVV voltage value!\n"); | |
c82baa28 | 450 | } |
451 | } | |
452 | } else { | |
453 | /* in merged mode we have only vddc EVV leakages */ | |
454 | if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, | |
455 | pptable_info->vddc_lookup_table, | |
456 | virtual_voltage_id, &sclk)) { | |
ac0cc350 MK |
457 | if (0 == atomctrl_get_voltage_evv_on_sclk |
458 | (hwmgr, VOLTAGE_TYPE_VDDC, sclk, | |
459 | virtual_voltage_id, &vddc)) { | |
460 | /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ | |
461 | PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1); | |
462 | ||
463 | /* the voltage should not be zero nor equal to leakage ID */ | |
464 | if (vddc != 0 && vddc != virtual_voltage_id) { | |
465 | data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; | |
466 | data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; | |
467 | data->vddc_leakage.count++; | |
468 | } | |
469 | } else { | |
470 | printk("Error retrieving EVV voltage value!\n"); | |
c82baa28 | 471 | } |
472 | } | |
473 | } | |
474 | } | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
480 | { | |
481 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
482 | ||
483 | /* enable SCLK dpm */ | |
484 | if (0 == data->sclk_dpm_key_disabled) { | |
485 | PP_ASSERT_WITH_CODE( | |
486 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
487 | PPSMC_MSG_DPM_Enable)), | |
488 | "Failed to enable SCLK DPM during DPM Start Function!", | |
489 | return -1); | |
490 | } | |
491 | ||
492 | /* enable MCLK dpm */ | |
493 | if (0 == data->mclk_dpm_key_disabled) { | |
494 | PP_ASSERT_WITH_CODE( | |
495 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
496 | PPSMC_MSG_MCLKDPM_Enable)), | |
497 | "Failed to enable MCLK DPM during DPM Start Function!", | |
498 | return -1); | |
499 | ||
500 | PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); | |
501 | ||
502 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
503 | ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */ | |
504 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
505 | ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */ | |
506 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
507 | ixLCAC_CPL_CNTL, 0x100005);/*Read */ | |
508 | ||
509 | udelay(10); | |
510 | ||
511 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
512 | ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */ | |
513 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
514 | ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */ | |
515 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
516 | ixLCAC_CPL_CNTL, 0x500005);/* write */ | |
517 | ||
518 | } | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | int tonga_start_dpm(struct pp_hwmgr *hwmgr) | |
524 | { | |
525 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
526 | ||
527 | /* enable general power management */ | |
528 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1); | |
529 | /* enable sclk deep sleep */ | |
530 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1); | |
531 | ||
532 | /* prepare for PCIE DPM */ | |
533 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + | |
534 | offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000); | |
535 | ||
536 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); | |
537 | ||
538 | PP_ASSERT_WITH_CODE( | |
539 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
540 | PPSMC_MSG_Voltage_Cntl_Enable)), | |
541 | "Failed to enable voltage DPM during DPM Start Function!", | |
542 | return -1); | |
543 | ||
544 | if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) { | |
545 | PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1); | |
546 | } | |
547 | ||
548 | /* enable PCIE dpm */ | |
549 | if (0 == data->pcie_dpm_key_disabled) { | |
550 | PP_ASSERT_WITH_CODE( | |
551 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
552 | PPSMC_MSG_PCIeDPM_Enable)), | |
553 | "Failed to enable pcie DPM during DPM Start Function!", | |
554 | return -1 | |
555 | ); | |
556 | } | |
557 | ||
558 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
559 | PHM_PlatformCaps_Falcon_QuickTransition)) { | |
560 | smum_send_msg_to_smc(hwmgr->smumgr, | |
561 | PPSMC_MSG_EnableACDCGPIOInterrupt); | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
568 | { | |
569 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
570 | ||
571 | /* disable SCLK dpm */ | |
572 | if (0 == data->sclk_dpm_key_disabled) { | |
573 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
574 | PP_ASSERT_WITH_CODE( | |
4ba27f9b | 575 | !tonga_is_dpm_running(hwmgr), |
c82baa28 | 576 | "Trying to Disable SCLK DPM when DPM is disabled", |
577 | return -1 | |
578 | ); | |
579 | ||
580 | PP_ASSERT_WITH_CODE( | |
581 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
582 | PPSMC_MSG_DPM_Disable)), | |
583 | "Failed to disable SCLK DPM during DPM stop Function!", | |
584 | return -1); | |
585 | } | |
586 | ||
587 | /* disable MCLK dpm */ | |
588 | if (0 == data->mclk_dpm_key_disabled) { | |
589 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ | |
590 | PP_ASSERT_WITH_CODE( | |
4ba27f9b | 591 | !tonga_is_dpm_running(hwmgr), |
c82baa28 | 592 | "Trying to Disable MCLK DPM when DPM is disabled", |
593 | return -1 | |
594 | ); | |
595 | ||
596 | PP_ASSERT_WITH_CODE( | |
597 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
598 | PPSMC_MSG_MCLKDPM_Disable)), | |
599 | "Failed to Disable MCLK DPM during DPM stop Function!", | |
600 | return -1); | |
601 | } | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | int tonga_stop_dpm(struct pp_hwmgr *hwmgr) | |
607 | { | |
608 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
609 | ||
610 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0); | |
611 | /* disable sclk deep sleep*/ | |
612 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0); | |
613 | ||
614 | /* disable PCIE dpm */ | |
615 | if (0 == data->pcie_dpm_key_disabled) { | |
616 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
617 | PP_ASSERT_WITH_CODE( | |
4ba27f9b | 618 | !tonga_is_dpm_running(hwmgr), |
c82baa28 | 619 | "Trying to Disable PCIE DPM when DPM is disabled", |
620 | return -1 | |
621 | ); | |
622 | PP_ASSERT_WITH_CODE( | |
623 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
624 | PPSMC_MSG_PCIeDPM_Disable)), | |
625 | "Failed to disable pcie DPM during DPM stop Function!", | |
626 | return -1); | |
627 | } | |
628 | ||
629 | if (0 != tonga_disable_sclk_mclk_dpm(hwmgr)) | |
630 | PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1); | |
631 | ||
632 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
633 | PP_ASSERT_WITH_CODE( | |
4ba27f9b | 634 | !tonga_is_dpm_running(hwmgr), |
c82baa28 | 635 | "Trying to Disable Voltage CNTL when DPM is disabled", |
636 | return -1 | |
637 | ); | |
638 | ||
639 | PP_ASSERT_WITH_CODE( | |
640 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
641 | PPSMC_MSG_Voltage_Cntl_Disable)), | |
642 | "Failed to disable voltage DPM during DPM stop Function!", | |
643 | return -1); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr) | |
649 | { | |
650 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | /** | |
656 | * Send a message to the SMC and return a parameter | |
657 | * | |
658 | * @param hwmgr: the address of the powerplay hardware manager. | |
659 | * @param msg: the message to send. | |
660 | * @param parameter: pointer to the received parameter | |
661 | * @return The response that came from the SMC. | |
662 | */ | |
663 | PPSMC_Result tonga_send_msg_to_smc_return_parameter( | |
664 | struct pp_hwmgr *hwmgr, | |
665 | PPSMC_Msg msg, | |
666 | uint32_t *parameter) | |
667 | { | |
668 | int result; | |
669 | ||
670 | result = smum_send_msg_to_smc(hwmgr->smumgr, msg); | |
671 | ||
672 | if ((0 == result) && parameter) { | |
673 | *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
674 | } | |
675 | ||
676 | return result; | |
677 | } | |
678 | ||
679 | /** | |
680 | * force DPM power State | |
681 | * | |
682 | * @param hwmgr: the address of the powerplay hardware manager. | |
683 | * @param n : DPM level | |
684 | * @return The response that came from the SMC. | |
685 | */ | |
686 | int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) | |
687 | { | |
688 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
689 | uint32_t level_mask = 1 << n; | |
690 | ||
691 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ | |
4ba27f9b EC |
692 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
693 | "Trying to force SCLK when DPM is disabled", | |
694 | return -1;); | |
c82baa28 | 695 | if (0 == data->sclk_dpm_key_disabled) |
696 | return (0 == smum_send_msg_to_smc_with_parameter( | |
697 | hwmgr->smumgr, | |
698 | (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask), | |
699 | level_mask) ? 0 : 1); | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | /** | |
705 | * force DPM power State | |
706 | * | |
707 | * @param hwmgr: the address of the powerplay hardware manager. | |
708 | * @param n : DPM level | |
709 | * @return The response that came from the SMC. | |
710 | */ | |
711 | int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) | |
712 | { | |
713 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
714 | uint32_t level_mask = 1 << n; | |
715 | ||
716 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ | |
4ba27f9b EC |
717 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
718 | "Trying to Force MCLK when DPM is disabled", | |
719 | return -1;); | |
c82baa28 | 720 | if (0 == data->mclk_dpm_key_disabled) |
721 | return (0 == smum_send_msg_to_smc_with_parameter( | |
722 | hwmgr->smumgr, | |
723 | (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask), | |
724 | level_mask) ? 0 : 1); | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | /** | |
730 | * force DPM power State | |
731 | * | |
732 | * @param hwmgr: the address of the powerplay hardware manager. | |
733 | * @param n : DPM level | |
734 | * @return The response that came from the SMC. | |
735 | */ | |
736 | int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) | |
737 | { | |
738 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
739 | ||
740 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
4ba27f9b EC |
741 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
742 | "Trying to Force PCIE level when DPM is disabled", | |
743 | return -1;); | |
c82baa28 | 744 | if (0 == data->pcie_dpm_key_disabled) |
745 | return (0 == smum_send_msg_to_smc_with_parameter( | |
746 | hwmgr->smumgr, | |
747 | (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel), | |
748 | n) ? 0 : 1); | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | /** | |
754 | * Set the initial state by calling SMC to switch to this state directly | |
755 | * | |
756 | * @param hwmgr the address of the powerplay hardware manager. | |
757 | * @return always 0 | |
758 | */ | |
759 | int tonga_set_boot_state(struct pp_hwmgr *hwmgr) | |
760 | { | |
761 | /* | |
762 | * SMC only stores one state that SW will ask to switch too, | |
763 | * so we switch the the just uploaded one | |
764 | */ | |
765 | return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1; | |
766 | } | |
767 | ||
768 | /** | |
769 | * Get the location of various tables inside the FW image. | |
770 | * | |
771 | * @param hwmgr the address of the powerplay hardware manager. | |
772 | * @return always 0 | |
773 | */ | |
774 | int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) | |
775 | { | |
776 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
777 | struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend); | |
778 | ||
779 | uint32_t tmp; | |
780 | int result; | |
ed5121a3 | 781 | bool error = false; |
c82baa28 | 782 | |
783 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
784 | SMU72_FIRMWARE_HEADER_LOCATION + | |
785 | offsetof(SMU72_Firmware_Header, DpmTable), | |
786 | &tmp, data->sram_end); | |
787 | ||
788 | if (0 == result) { | |
789 | data->dpm_table_start = tmp; | |
790 | } | |
791 | ||
792 | error |= (0 != result); | |
793 | ||
794 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
795 | SMU72_FIRMWARE_HEADER_LOCATION + | |
796 | offsetof(SMU72_Firmware_Header, SoftRegisters), | |
797 | &tmp, data->sram_end); | |
798 | ||
799 | if (0 == result) { | |
800 | data->soft_regs_start = tmp; | |
801 | tonga_smu->ulSoftRegsStart = tmp; | |
802 | } | |
803 | ||
804 | error |= (0 != result); | |
805 | ||
806 | ||
807 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
808 | SMU72_FIRMWARE_HEADER_LOCATION + | |
809 | offsetof(SMU72_Firmware_Header, mcRegisterTable), | |
810 | &tmp, data->sram_end); | |
811 | ||
812 | if (0 == result) { | |
813 | data->mc_reg_table_start = tmp; | |
814 | } | |
815 | ||
816 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
817 | SMU72_FIRMWARE_HEADER_LOCATION + | |
818 | offsetof(SMU72_Firmware_Header, FanTable), | |
819 | &tmp, data->sram_end); | |
820 | ||
821 | if (0 == result) { | |
822 | data->fan_table_start = tmp; | |
823 | } | |
824 | ||
825 | error |= (0 != result); | |
826 | ||
827 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
828 | SMU72_FIRMWARE_HEADER_LOCATION + | |
829 | offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), | |
830 | &tmp, data->sram_end); | |
831 | ||
832 | if (0 == result) { | |
833 | data->arb_table_start = tmp; | |
834 | } | |
835 | ||
836 | error |= (0 != result); | |
837 | ||
838 | ||
839 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
840 | SMU72_FIRMWARE_HEADER_LOCATION + | |
841 | offsetof(SMU72_Firmware_Header, Version), | |
842 | &tmp, data->sram_end); | |
843 | ||
844 | if (0 == result) { | |
845 | hwmgr->microcode_version_info.SMC = tmp; | |
846 | } | |
847 | ||
848 | error |= (0 != result); | |
849 | ||
850 | return error ? 1 : 0; | |
851 | } | |
852 | ||
853 | /** | |
854 | * Read clock related registers. | |
855 | * | |
856 | * @param hwmgr the address of the powerplay hardware manager. | |
857 | * @return always 0 | |
858 | */ | |
859 | int tonga_read_clock_registers(struct pp_hwmgr *hwmgr) | |
860 | { | |
861 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
862 | ||
863 | data->clock_registers.vCG_SPLL_FUNC_CNTL = | |
864 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); | |
865 | data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = | |
866 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); | |
867 | data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = | |
868 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); | |
869 | data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = | |
870 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); | |
871 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = | |
872 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); | |
873 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = | |
874 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); | |
875 | data->clock_registers.vDLL_CNTL = | |
876 | cgs_read_register(hwmgr->device, mmDLL_CNTL); | |
877 | data->clock_registers.vMCLK_PWRMGT_CNTL = | |
878 | cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); | |
879 | data->clock_registers.vMPLL_AD_FUNC_CNTL = | |
880 | cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); | |
881 | data->clock_registers.vMPLL_DQ_FUNC_CNTL = | |
882 | cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); | |
883 | data->clock_registers.vMPLL_FUNC_CNTL = | |
884 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); | |
885 | data->clock_registers.vMPLL_FUNC_CNTL_1 = | |
886 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); | |
887 | data->clock_registers.vMPLL_FUNC_CNTL_2 = | |
888 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); | |
889 | data->clock_registers.vMPLL_SS1 = | |
890 | cgs_read_register(hwmgr->device, mmMPLL_SS1); | |
891 | data->clock_registers.vMPLL_SS2 = | |
892 | cgs_read_register(hwmgr->device, mmMPLL_SS2); | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
897 | /** | |
898 | * Find out if memory is GDDR5. | |
899 | * | |
900 | * @param hwmgr the address of the powerplay hardware manager. | |
901 | * @return always 0 | |
902 | */ | |
903 | int tonga_get_memory_type(struct pp_hwmgr *hwmgr) | |
904 | { | |
905 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
906 | uint32_t temp; | |
907 | ||
908 | temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); | |
909 | ||
910 | data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE == | |
911 | ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> | |
912 | MC_SEQ_MISC0_GDDR5_SHIFT)); | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | /** | |
918 | * Enables Dynamic Power Management by SMC | |
919 | * | |
920 | * @param hwmgr the address of the powerplay hardware manager. | |
921 | * @return always 0 | |
922 | */ | |
923 | int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr) | |
924 | { | |
925 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
930 | /** | |
931 | * Initialize PowerGating States for different engines | |
932 | * | |
933 | * @param hwmgr the address of the powerplay hardware manager. | |
934 | * @return always 0 | |
935 | */ | |
936 | int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr) | |
937 | { | |
938 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
939 | ||
ed5121a3 EC |
940 | data->uvd_power_gated = false; |
941 | data->vce_power_gated = false; | |
942 | data->samu_power_gated = false; | |
943 | data->acp_power_gated = false; | |
944 | data->pg_acp_init = true; | |
c82baa28 | 945 | |
946 | return 0; | |
947 | } | |
948 | ||
949 | /** | |
950 | * Checks if DPM is enabled | |
951 | * | |
952 | * @param hwmgr the address of the powerplay hardware manager. | |
953 | * @return always 0 | |
954 | */ | |
955 | int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr) | |
956 | { | |
957 | /* | |
958 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM | |
959 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, | |
960 | * whereas voltage control is a fundemental change that will not be disabled | |
961 | */ | |
4ba27f9b | 962 | return (!tonga_is_dpm_running(hwmgr) ? 0 : 1); |
c82baa28 | 963 | } |
964 | ||
965 | /** | |
966 | * Checks if DPM is stopped | |
967 | * | |
968 | * @param hwmgr the address of the powerplay hardware manager. | |
969 | * @return always 0 | |
970 | */ | |
971 | int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr) | |
972 | { | |
973 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
974 | ||
4ba27f9b | 975 | if (tonga_is_dpm_running(hwmgr)) { |
c82baa28 | 976 | /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */ |
977 | if (!data->dpm_table_start) { | |
978 | return 1; | |
979 | } | |
980 | } | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | /** | |
986 | * Remove repeated voltage values and create table with unique values. | |
987 | * | |
988 | * @param hwmgr the address of the powerplay hardware manager. | |
989 | * @param voltage_table the pointer to changing voltage table | |
990 | * @return 1 in success | |
991 | */ | |
992 | ||
993 | static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr, | |
994 | pp_atomctrl_voltage_table *voltage_table) | |
995 | { | |
996 | uint32_t table_size, i, j; | |
997 | uint16_t vvalue; | |
ed5121a3 | 998 | bool bVoltageFound = false; |
c82baa28 | 999 | pp_atomctrl_voltage_table *table; |
1000 | ||
1001 | PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;); | |
1002 | table_size = sizeof(pp_atomctrl_voltage_table); | |
1003 | table = kzalloc(table_size, GFP_KERNEL); | |
1004 | ||
1005 | if (NULL == table) | |
1006 | return -ENOMEM; | |
1007 | ||
1008 | memset(table, 0x00, table_size); | |
1009 | table->mask_low = voltage_table->mask_low; | |
1010 | table->phase_delay = voltage_table->phase_delay; | |
1011 | ||
1012 | for (i = 0; i < voltage_table->count; i++) { | |
1013 | vvalue = voltage_table->entries[i].value; | |
ed5121a3 | 1014 | bVoltageFound = false; |
c82baa28 | 1015 | |
1016 | for (j = 0; j < table->count; j++) { | |
1017 | if (vvalue == table->entries[j].value) { | |
ed5121a3 | 1018 | bVoltageFound = true; |
c82baa28 | 1019 | break; |
1020 | } | |
1021 | } | |
1022 | ||
1023 | if (!bVoltageFound) { | |
1024 | table->entries[table->count].value = vvalue; | |
1025 | table->entries[table->count].smio_low = | |
1026 | voltage_table->entries[i].smio_low; | |
1027 | table->count++; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table)); | |
1032 | ||
1033 | kfree(table); | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | static int tonga_get_svi2_vdd_ci_voltage_table( | |
1039 | struct pp_hwmgr *hwmgr, | |
1040 | phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table) | |
1041 | { | |
1042 | uint32_t i; | |
1043 | int result; | |
1044 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1045 | pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table); | |
1046 | ||
1047 | PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count), | |
1048 | "Voltage Dependency Table empty.", return -1;); | |
1049 | ||
1050 | vddci_voltage_table->mask_low = 0; | |
1051 | vddci_voltage_table->phase_delay = 0; | |
1052 | vddci_voltage_table->count = voltage_dependency_table->count; | |
1053 | ||
1054 | for (i = 0; i < voltage_dependency_table->count; i++) { | |
1055 | vddci_voltage_table->entries[i].value = | |
1056 | voltage_dependency_table->entries[i].vddci; | |
1057 | vddci_voltage_table->entries[i].smio_low = 0; | |
1058 | } | |
1059 | ||
1060 | result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table); | |
1061 | PP_ASSERT_WITH_CODE((0 == result), | |
1062 | "Failed to trim VDDCI table.", return result;); | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | ||
1068 | ||
1069 | static int tonga_get_svi2_vdd_voltage_table( | |
1070 | struct pp_hwmgr *hwmgr, | |
1071 | phm_ppt_v1_voltage_lookup_table *look_up_table, | |
1072 | pp_atomctrl_voltage_table *voltage_table) | |
1073 | { | |
1074 | uint8_t i = 0; | |
1075 | ||
1076 | PP_ASSERT_WITH_CODE((0 != look_up_table->count), | |
1077 | "Voltage Lookup Table empty.", return -1;); | |
1078 | ||
1079 | voltage_table->mask_low = 0; | |
1080 | voltage_table->phase_delay = 0; | |
1081 | ||
1082 | voltage_table->count = look_up_table->count; | |
1083 | ||
1084 | for (i = 0; i < voltage_table->count; i++) { | |
1085 | voltage_table->entries[i].value = look_up_table->entries[i].us_vdd; | |
1086 | voltage_table->entries[i].smio_low = 0; | |
1087 | } | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | /* | |
1093 | * -------------------------------------------------------- Voltage Tables -------------------------------------------------------------------------- | |
1094 | * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries. | |
1095 | */ | |
1096 | ||
1097 | static void tonga_trim_voltage_table_to_fit_state_table( | |
1098 | struct pp_hwmgr *hwmgr, | |
1099 | uint32_t max_voltage_steps, | |
1100 | pp_atomctrl_voltage_table *voltage_table) | |
1101 | { | |
1102 | unsigned int i, diff; | |
1103 | ||
1104 | if (voltage_table->count <= max_voltage_steps) { | |
1105 | return; | |
1106 | } | |
1107 | ||
1108 | diff = voltage_table->count - max_voltage_steps; | |
1109 | ||
1110 | for (i = 0; i < max_voltage_steps; i++) { | |
1111 | voltage_table->entries[i] = voltage_table->entries[i + diff]; | |
1112 | } | |
1113 | ||
1114 | voltage_table->count = max_voltage_steps; | |
1115 | ||
1116 | return; | |
1117 | } | |
1118 | ||
1119 | /** | |
1120 | * Create Voltage Tables. | |
1121 | * | |
1122 | * @param hwmgr the address of the powerplay hardware manager. | |
1123 | * @return always 0 | |
1124 | */ | |
1125 | int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr) | |
1126 | { | |
1127 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1128 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1129 | int result; | |
1130 | ||
1131 | /* MVDD has only GPIO voltage control */ | |
1132 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { | |
1133 | result = atomctrl_get_voltage_table_v3(hwmgr, | |
1134 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table)); | |
1135 | PP_ASSERT_WITH_CODE((0 == result), | |
1136 | "Failed to retrieve MVDD table.", return result;); | |
1137 | } | |
1138 | ||
1139 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { | |
1140 | /* GPIO voltage */ | |
1141 | result = atomctrl_get_voltage_table_v3(hwmgr, | |
1142 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table)); | |
1143 | PP_ASSERT_WITH_CODE((0 == result), | |
1144 | "Failed to retrieve VDDCI table.", return result;); | |
1145 | } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { | |
1146 | /* SVI2 voltage */ | |
1147 | result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr, | |
1148 | pptable_info->vdd_dep_on_mclk); | |
1149 | PP_ASSERT_WITH_CODE((0 == result), | |
1150 | "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;); | |
1151 | } | |
1152 | ||
1153 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { | |
1154 | /* VDDGFX has only SVI2 voltage control */ | |
1155 | result = tonga_get_svi2_vdd_voltage_table(hwmgr, | |
1156 | pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table)); | |
1157 | PP_ASSERT_WITH_CODE((0 == result), | |
1158 | "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); | |
1159 | } | |
1160 | ||
1161 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { | |
1162 | /* VDDC has only SVI2 voltage control */ | |
1163 | result = tonga_get_svi2_vdd_voltage_table(hwmgr, | |
1164 | pptable_info->vddc_lookup_table, &(data->vddc_voltage_table)); | |
1165 | PP_ASSERT_WITH_CODE((0 == result), | |
1166 | "Failed to retrieve SVI2 VDDC table from lookup table.", return result;); | |
1167 | } | |
1168 | ||
1169 | PP_ASSERT_WITH_CODE( | |
1170 | (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)), | |
1171 | "Too many voltage values for VDDC. Trimming to fit state table.", | |
1172 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, | |
1173 | SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)); | |
1174 | ); | |
1175 | ||
1176 | PP_ASSERT_WITH_CODE( | |
1177 | (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)), | |
1178 | "Too many voltage values for VDDGFX. Trimming to fit state table.", | |
1179 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, | |
1180 | SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table)); | |
1181 | ); | |
1182 | ||
1183 | PP_ASSERT_WITH_CODE( | |
1184 | (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)), | |
1185 | "Too many voltage values for VDDCI. Trimming to fit state table.", | |
1186 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, | |
1187 | SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)); | |
1188 | ); | |
1189 | ||
1190 | PP_ASSERT_WITH_CODE( | |
1191 | (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)), | |
1192 | "Too many voltage values for MVDD. Trimming to fit state table.", | |
1193 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, | |
1194 | SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)); | |
1195 | ); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | /** | |
1201 | * Vddc table preparation for SMC. | |
1202 | * | |
1203 | * @param hwmgr the address of the hardware manager | |
1204 | * @param table the SMC DPM table structure to be populated | |
1205 | * @return always 0 | |
1206 | */ | |
1207 | static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, | |
1208 | SMU72_Discrete_DpmTable *table) | |
1209 | { | |
1210 | unsigned int count; | |
1211 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1212 | ||
1213 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { | |
1214 | table->VddcLevelCount = data->vddc_voltage_table.count; | |
1215 | for (count = 0; count < table->VddcLevelCount; count++) { | |
1216 | table->VddcTable[count] = | |
1217 | PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE); | |
1218 | } | |
1219 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); | |
1220 | } | |
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | /** | |
1225 | * VddGfx table preparation for SMC. | |
1226 | * | |
1227 | * @param hwmgr the address of the hardware manager | |
1228 | * @param table the SMC DPM table structure to be populated | |
1229 | * @return always 0 | |
1230 | */ | |
1231 | static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr, | |
1232 | SMU72_Discrete_DpmTable *table) | |
1233 | { | |
1234 | unsigned int count; | |
1235 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1236 | ||
1237 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { | |
1238 | table->VddGfxLevelCount = data->vddgfx_voltage_table.count; | |
1239 | for (count = 0; count < data->vddgfx_voltage_table.count; count++) { | |
1240 | table->VddGfxTable[count] = | |
1241 | PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE); | |
1242 | } | |
1243 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount); | |
1244 | } | |
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | /** | |
1249 | * Vddci table preparation for SMC. | |
1250 | * | |
1251 | * @param *hwmgr The address of the hardware manager. | |
1252 | * @param *table The SMC DPM table structure to be populated. | |
1253 | * @return 0 | |
1254 | */ | |
1255 | static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, | |
1256 | SMU72_Discrete_DpmTable *table) | |
1257 | { | |
1258 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1259 | uint32_t count; | |
1260 | ||
1261 | table->VddciLevelCount = data->vddci_voltage_table.count; | |
1262 | for (count = 0; count < table->VddciLevelCount; count++) { | |
1263 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { | |
1264 | table->VddciTable[count] = | |
1265 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); | |
1266 | } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { | |
1267 | table->SmioTable1.Pattern[count].Voltage = | |
1268 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); | |
1269 | /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */ | |
1270 | table->SmioTable1.Pattern[count].Smio = | |
1271 | (uint8_t) count; | |
1272 | table->Smio[count] |= | |
1273 | data->vddci_voltage_table.entries[count].smio_low; | |
1274 | table->VddciTable[count] = | |
1275 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); | |
1276 | } | |
1277 | } | |
1278 | ||
1279 | table->SmioMask1 = data->vddci_voltage_table.mask_low; | |
1280 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | /** | |
1286 | * Mvdd table preparation for SMC. | |
1287 | * | |
1288 | * @param *hwmgr The address of the hardware manager. | |
1289 | * @param *table The SMC DPM table structure to be populated. | |
1290 | * @return 0 | |
1291 | */ | |
1292 | static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, | |
1293 | SMU72_Discrete_DpmTable *table) | |
1294 | { | |
1295 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1296 | uint32_t count; | |
1297 | ||
1298 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { | |
1299 | table->MvddLevelCount = data->mvdd_voltage_table.count; | |
1300 | for (count = 0; count < table->MvddLevelCount; count++) { | |
1301 | table->SmioTable2.Pattern[count].Voltage = | |
1302 | PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); | |
1303 | /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ | |
1304 | table->SmioTable2.Pattern[count].Smio = | |
1305 | (uint8_t) count; | |
1306 | table->Smio[count] |= | |
1307 | data->mvdd_voltage_table.entries[count].smio_low; | |
1308 | } | |
1dfefee8 | 1309 | table->SmioMask2 = data->mvdd_voltage_table.mask_low; |
c82baa28 | 1310 | |
1311 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); | |
1312 | } | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | /** | |
1318 | * Convert a voltage value in mv unit to VID number required by SMU firmware | |
1319 | */ | |
1320 | static uint8_t convert_to_vid(uint16_t vddc) | |
1321 | { | |
1322 | return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); | |
1323 | } | |
1324 | ||
1325 | ||
1326 | /** | |
1327 | * Preparation of vddc and vddgfx CAC tables for SMC. | |
1328 | * | |
1329 | * @param hwmgr the address of the hardware manager | |
1330 | * @param table the SMC DPM table structure to be populated | |
1331 | * @return always 0 | |
1332 | */ | |
1333 | static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, | |
1334 | SMU72_Discrete_DpmTable *table) | |
1335 | { | |
1336 | uint32_t count; | |
1337 | uint8_t index; | |
c82baa28 | 1338 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
1339 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1340 | struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table; | |
1341 | struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table; | |
1342 | ||
1343 | /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */ | |
1344 | uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount); | |
1345 | uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount); | |
1346 | ||
1347 | for (count = 0; count < vddcLevelCount; count++) { | |
1348 | /* We are populating vddc CAC data to BapmVddc table in split and merged mode */ | |
1349 | index = tonga_get_voltage_index(vddc_lookup_table, | |
1350 | data->vddc_voltage_table.entries[count].value); | |
1351 | table->BapmVddcVidLoSidd[count] = | |
1352 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); | |
1353 | table->BapmVddcVidHiSidd[count] = | |
1354 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); | |
1355 | table->BapmVddcVidHiSidd2[count] = | |
1356 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); | |
1357 | } | |
1358 | ||
1359 | if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) { | |
1360 | /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */ | |
1361 | for (count = 0; count < vddgfxLevelCount; count++) { | |
1362 | index = tonga_get_voltage_index(vddgfx_lookup_table, | |
1363 | data->vddgfx_voltage_table.entries[count].value); | |
1364 | table->BapmVddGfxVidLoSidd[count] = | |
1365 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low); | |
1366 | table->BapmVddGfxVidHiSidd[count] = | |
1367 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid); | |
1368 | table->BapmVddGfxVidHiSidd2[count] = | |
1369 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high); | |
1370 | } | |
1371 | } else { | |
1372 | for (count = 0; count < vddcLevelCount; count++) { | |
1373 | index = tonga_get_voltage_index(vddc_lookup_table, | |
1374 | data->vddc_voltage_table.entries[count].value); | |
1375 | table->BapmVddGfxVidLoSidd[count] = | |
1376 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); | |
1377 | table->BapmVddGfxVidHiSidd[count] = | |
1378 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); | |
1379 | table->BapmVddGfxVidHiSidd2[count] = | |
1380 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); | |
1381 | } | |
1382 | } | |
1383 | ||
538f1ef3 | 1384 | return 0; |
c82baa28 | 1385 | } |
1386 | ||
1387 | ||
1388 | /** | |
1389 | * Preparation of voltage tables for SMC. | |
1390 | * | |
1391 | * @param hwmgr the address of the hardware manager | |
1392 | * @param table the SMC DPM table structure to be populated | |
1393 | * @return always 0 | |
1394 | */ | |
1395 | ||
1396 | int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, | |
1397 | SMU72_Discrete_DpmTable *table) | |
1398 | { | |
1399 | int result; | |
1400 | ||
1401 | result = tonga_populate_smc_vddc_table(hwmgr, table); | |
1402 | PP_ASSERT_WITH_CODE(0 == result, | |
1403 | "can not populate VDDC voltage table to SMC", return -1); | |
1404 | ||
1405 | result = tonga_populate_smc_vdd_ci_table(hwmgr, table); | |
1406 | PP_ASSERT_WITH_CODE(0 == result, | |
1407 | "can not populate VDDCI voltage table to SMC", return -1); | |
1408 | ||
1409 | result = tonga_populate_smc_vdd_gfx_table(hwmgr, table); | |
1410 | PP_ASSERT_WITH_CODE(0 == result, | |
1411 | "can not populate VDDGFX voltage table to SMC", return -1); | |
1412 | ||
1413 | result = tonga_populate_smc_mvdd_table(hwmgr, table); | |
1414 | PP_ASSERT_WITH_CODE(0 == result, | |
1415 | "can not populate MVDD voltage table to SMC", return -1); | |
1416 | ||
1417 | result = tonga_populate_cac_tables(hwmgr, table); | |
1418 | PP_ASSERT_WITH_CODE(0 == result, | |
1419 | "can not populate CAC voltage tables to SMC", return -1); | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | /** | |
1425 | * Populates the SMC VRConfig field in DPM table. | |
1426 | * | |
1427 | * @param hwmgr the address of the hardware manager | |
1428 | * @param table the SMC DPM table structure to be populated | |
1429 | * @return always 0 | |
1430 | */ | |
1431 | static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, | |
1432 | SMU72_Discrete_DpmTable *table) | |
1433 | { | |
1434 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1435 | uint16_t config; | |
1436 | ||
1437 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { | |
1438 | /* Splitted mode */ | |
1439 | config = VR_SVI2_PLANE_1; | |
1440 | table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); | |
1441 | ||
1442 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { | |
1443 | config = VR_SVI2_PLANE_2; | |
1444 | table->VRConfig |= config; | |
1445 | } else { | |
1446 | printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n"); | |
1447 | } | |
1448 | } else { | |
1449 | /* Merged mode */ | |
1450 | config = VR_MERGED_WITH_VDDC; | |
1451 | table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); | |
1452 | ||
1453 | /* Set Vddc Voltage Controller */ | |
1454 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { | |
1455 | config = VR_SVI2_PLANE_1; | |
1456 | table->VRConfig |= config; | |
1457 | } else { | |
1458 | printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n"); | |
1459 | } | |
1460 | } | |
1461 | ||
1462 | /* Set Vddci Voltage Controller */ | |
1463 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { | |
1464 | config = VR_SVI2_PLANE_2; /* only in merged mode */ | |
1465 | table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); | |
1466 | } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { | |
1467 | config = VR_SMIO_PATTERN_1; | |
1468 | table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); | |
1469 | } | |
1470 | ||
1471 | /* Set Mvdd Voltage Controller */ | |
1472 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { | |
1473 | config = VR_SMIO_PATTERN_2; | |
1474 | table->VRConfig |= (config<<VRCONF_MVDD_SHIFT); | |
1475 | } | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, | |
1481 | phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table, | |
1482 | uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) | |
1483 | { | |
1484 | uint32_t i = 0; | |
1485 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1486 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1487 | ||
1488 | /* clock - voltage dependency table is empty table */ | |
1489 | if (allowed_clock_voltage_table->count == 0) | |
1490 | return -1; | |
1491 | ||
1492 | for (i = 0; i < allowed_clock_voltage_table->count; i++) { | |
1493 | /* find first sclk bigger than request */ | |
1494 | if (allowed_clock_voltage_table->entries[i].clk >= clock) { | |
1495 | voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, | |
1496 | allowed_clock_voltage_table->entries[i].vddgfx); | |
1497 | ||
1498 | voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table, | |
1499 | allowed_clock_voltage_table->entries[i].vddc); | |
1500 | ||
1501 | if (allowed_clock_voltage_table->entries[i].vddci) { | |
1502 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, | |
1503 | allowed_clock_voltage_table->entries[i].vddci); | |
1504 | } else { | |
1505 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, | |
1506 | allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta); | |
1507 | } | |
1508 | ||
1509 | if (allowed_clock_voltage_table->entries[i].mvdd) { | |
1510 | *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd; | |
1511 | } | |
1512 | ||
1513 | voltage->Phases = 1; | |
1514 | return 0; | |
1515 | } | |
1516 | } | |
1517 | ||
1518 | /* sclk is bigger than max sclk in the dependence table */ | |
1519 | voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, | |
1520 | allowed_clock_voltage_table->entries[i-1].vddgfx); | |
1521 | voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table, | |
1522 | allowed_clock_voltage_table->entries[i-1].vddc); | |
1523 | ||
1524 | if (allowed_clock_voltage_table->entries[i-1].vddci) { | |
1525 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, | |
1526 | allowed_clock_voltage_table->entries[i-1].vddci); | |
1527 | } | |
1528 | if (allowed_clock_voltage_table->entries[i-1].mvdd) { | |
1529 | *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd; | |
1530 | } | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | /** | |
1536 | * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value | |
1537 | * | |
1538 | * @param hwmgr the address of the powerplay hardware manager. | |
1539 | * @return always 0 | |
1540 | */ | |
1541 | int tonga_reset_to_default(struct pp_hwmgr *hwmgr) | |
1542 | { | |
1543 | return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1; | |
1544 | } | |
1545 | ||
1546 | int tonga_populate_memory_timing_parameters( | |
1547 | struct pp_hwmgr *hwmgr, | |
1548 | uint32_t engine_clock, | |
1549 | uint32_t memory_clock, | |
1550 | struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs | |
1551 | ) | |
1552 | { | |
1553 | uint32_t dramTiming; | |
1554 | uint32_t dramTiming2; | |
1555 | uint32_t burstTime; | |
1556 | int result; | |
1557 | ||
1558 | result = atomctrl_set_engine_dram_timings_rv770(hwmgr, | |
1559 | engine_clock, memory_clock); | |
1560 | ||
1561 | PP_ASSERT_WITH_CODE(result == 0, | |
1562 | "Error calling VBIOS to set DRAM_TIMING.", return result); | |
1563 | ||
1564 | dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); | |
1565 | dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); | |
1566 | burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); | |
1567 | ||
1568 | arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); | |
1569 | arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); | |
1570 | arb_regs->McArbBurstTime = (uint8_t)burstTime; | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | /** | |
1576 | * Setup parameters for the MC ARB. | |
1577 | * | |
1578 | * @param hwmgr the address of the powerplay hardware manager. | |
1579 | * @return always 0 | |
1580 | * This function is to be called from the SetPowerState table. | |
1581 | */ | |
1582 | int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) | |
1583 | { | |
1584 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1585 | int result = 0; | |
1586 | SMU72_Discrete_MCArbDramTimingTable arb_regs; | |
1587 | uint32_t i, j; | |
1588 | ||
1589 | memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); | |
1590 | ||
1591 | for (i = 0; i < data->dpm_table.sclk_table.count; i++) { | |
1592 | for (j = 0; j < data->dpm_table.mclk_table.count; j++) { | |
1593 | result = tonga_populate_memory_timing_parameters | |
1594 | (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, | |
1595 | data->dpm_table.mclk_table.dpm_levels[j].value, | |
1596 | &arb_regs.entries[i][j]); | |
1597 | ||
1598 | if (0 != result) { | |
1599 | break; | |
1600 | } | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | if (0 == result) { | |
1605 | result = tonga_copy_bytes_to_smc( | |
1606 | hwmgr->smumgr, | |
1607 | data->arb_table_start, | |
1608 | (uint8_t *)&arb_regs, | |
1609 | sizeof(SMU72_Discrete_MCArbDramTimingTable), | |
1610 | data->sram_end | |
1611 | ); | |
1612 | } | |
1613 | ||
1614 | return result; | |
1615 | } | |
1616 | ||
1617 | static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table) | |
1618 | { | |
1619 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1620 | struct tonga_dpm_table *dpm_table = &data->dpm_table; | |
1621 | uint32_t i; | |
1622 | ||
1623 | /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ | |
1624 | for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { | |
1625 | table->LinkLevel[i].PcieGenSpeed = | |
1626 | (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; | |
1627 | table->LinkLevel[i].PcieLaneCount = | |
1628 | (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); | |
1629 | table->LinkLevel[i].EnabledForActivity = | |
1630 | 1; | |
1631 | table->LinkLevel[i].SPC = | |
1632 | (uint8_t)(data->pcie_spc_cap & 0xff); | |
1633 | table->LinkLevel[i].DownThreshold = | |
1634 | PP_HOST_TO_SMC_UL(5); | |
1635 | table->LinkLevel[i].UpThreshold = | |
1636 | PP_HOST_TO_SMC_UL(30); | |
1637 | } | |
1638 | ||
1639 | data->smc_state_table.LinkLevelCount = | |
1640 | (uint8_t)dpm_table->pcie_speed_table.count; | |
1641 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = | |
1642 | tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); | |
1643 | ||
1644 | return 0; | |
1645 | } | |
1646 | ||
0104aa21 AD |
1647 | static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, |
1648 | SMU72_Discrete_DpmTable *table) | |
1649 | { | |
1650 | int result = 0; | |
1651 | ||
1652 | uint8_t count; | |
1653 | pp_atomctrl_clock_dividers_vi dividers; | |
1654 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1655 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1656 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; | |
1657 | ||
1658 | table->UvdLevelCount = (uint8_t) (mm_table->count); | |
1659 | table->UvdBootLevel = 0; | |
1660 | ||
1661 | for (count = 0; count < table->UvdLevelCount; count++) { | |
1662 | table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; | |
1663 | table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; | |
1664 | table->UvdLevel[count].MinVoltage.Vddc = | |
1665 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, | |
1666 | mm_table->entries[count].vddc); | |
1667 | table->UvdLevel[count].MinVoltage.VddGfx = | |
1668 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? | |
1669 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, | |
1670 | mm_table->entries[count].vddgfx) : 0; | |
1671 | table->UvdLevel[count].MinVoltage.Vddci = | |
1672 | tonga_get_voltage_id(&data->vddci_voltage_table, | |
1673 | mm_table->entries[count].vddc - data->vddc_vddci_delta); | |
1674 | table->UvdLevel[count].MinVoltage.Phases = 1; | |
1675 | ||
1676 | /* retrieve divider value for VBIOS */ | |
1677 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, | |
1678 | table->UvdLevel[count].VclkFrequency, ÷rs); | |
1679 | PP_ASSERT_WITH_CODE((0 == result), | |
1680 | "can not find divide id for Vclk clock", return result); | |
1681 | ||
1682 | table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; | |
1683 | ||
1684 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, | |
1685 | table->UvdLevel[count].DclkFrequency, ÷rs); | |
1686 | PP_ASSERT_WITH_CODE((0 == result), | |
1687 | "can not find divide id for Dclk clock", return result); | |
1688 | ||
1689 | table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; | |
1690 | ||
1691 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); | |
1692 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); | |
1693 | //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage); | |
c15c8d70 | 1694 | } |
0104aa21 | 1695 | |
c15c8d70 | 1696 | return result; |
0104aa21 AD |
1697 | |
1698 | } | |
c82baa28 | 1699 | |
1700 | static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr, | |
1701 | SMU72_Discrete_DpmTable *table) | |
1702 | { | |
1703 | int result = 0; | |
1704 | ||
1705 | uint8_t count; | |
1706 | pp_atomctrl_clock_dividers_vi dividers; | |
1707 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1708 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1709 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; | |
1710 | ||
1711 | table->VceLevelCount = (uint8_t) (mm_table->count); | |
1712 | table->VceBootLevel = 0; | |
1713 | ||
1714 | for (count = 0; count < table->VceLevelCount; count++) { | |
1715 | table->VceLevel[count].Frequency = | |
1716 | mm_table->entries[count].eclk; | |
1717 | table->VceLevel[count].MinVoltage.Vddc = | |
1718 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, | |
1719 | mm_table->entries[count].vddc); | |
1720 | table->VceLevel[count].MinVoltage.VddGfx = | |
1721 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? | |
1722 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, | |
1723 | mm_table->entries[count].vddgfx) : 0; | |
1724 | table->VceLevel[count].MinVoltage.Vddci = | |
1725 | tonga_get_voltage_id(&data->vddci_voltage_table, | |
1726 | mm_table->entries[count].vddc - data->vddc_vddci_delta); | |
1727 | table->VceLevel[count].MinVoltage.Phases = 1; | |
1728 | ||
1729 | /* retrieve divider value for VBIOS */ | |
1730 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, | |
1731 | table->VceLevel[count].Frequency, ÷rs); | |
1732 | PP_ASSERT_WITH_CODE((0 == result), | |
1733 | "can not find divide id for VCE engine clock", return result); | |
1734 | ||
c15c8d70 | 1735 | table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
c82baa28 | 1736 | |
1737 | CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); | |
1738 | } | |
1739 | ||
1740 | return result; | |
1741 | } | |
1742 | ||
1743 | static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr, | |
1744 | SMU72_Discrete_DpmTable *table) | |
1745 | { | |
1746 | int result = 0; | |
1747 | uint8_t count; | |
1748 | pp_atomctrl_clock_dividers_vi dividers; | |
1749 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1750 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1751 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; | |
1752 | ||
1753 | table->AcpLevelCount = (uint8_t) (mm_table->count); | |
1754 | table->AcpBootLevel = 0; | |
1755 | ||
1756 | for (count = 0; count < table->AcpLevelCount; count++) { | |
1757 | table->AcpLevel[count].Frequency = | |
1758 | pptable_info->mm_dep_table->entries[count].aclk; | |
1759 | table->AcpLevel[count].MinVoltage.Vddc = | |
1760 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, | |
1761 | mm_table->entries[count].vddc); | |
1762 | table->AcpLevel[count].MinVoltage.VddGfx = | |
1763 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? | |
1764 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, | |
1765 | mm_table->entries[count].vddgfx) : 0; | |
1766 | table->AcpLevel[count].MinVoltage.Vddci = | |
1767 | tonga_get_voltage_id(&data->vddci_voltage_table, | |
1768 | mm_table->entries[count].vddc - data->vddc_vddci_delta); | |
1769 | table->AcpLevel[count].MinVoltage.Phases = 1; | |
1770 | ||
1771 | /* retrieve divider value for VBIOS */ | |
1772 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, | |
1773 | table->AcpLevel[count].Frequency, ÷rs); | |
1774 | PP_ASSERT_WITH_CODE((0 == result), | |
1775 | "can not find divide id for engine clock", return result); | |
1776 | ||
1777 | table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; | |
1778 | ||
1779 | CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); | |
1780 | } | |
1781 | ||
1782 | return result; | |
1783 | } | |
1784 | ||
1785 | static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr, | |
1786 | SMU72_Discrete_DpmTable *table) | |
1787 | { | |
1788 | int result = 0; | |
1789 | uint8_t count; | |
1790 | pp_atomctrl_clock_dividers_vi dividers; | |
1791 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1792 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
1793 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; | |
1794 | ||
1795 | table->SamuBootLevel = 0; | |
1796 | table->SamuLevelCount = (uint8_t) (mm_table->count); | |
1797 | ||
1798 | for (count = 0; count < table->SamuLevelCount; count++) { | |
1799 | /* not sure whether we need evclk or not */ | |
1800 | table->SamuLevel[count].Frequency = | |
1801 | pptable_info->mm_dep_table->entries[count].samclock; | |
1802 | table->SamuLevel[count].MinVoltage.Vddc = | |
1803 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, | |
1804 | mm_table->entries[count].vddc); | |
1805 | table->SamuLevel[count].MinVoltage.VddGfx = | |
1806 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? | |
1807 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, | |
1808 | mm_table->entries[count].vddgfx) : 0; | |
1809 | table->SamuLevel[count].MinVoltage.Vddci = | |
1810 | tonga_get_voltage_id(&data->vddci_voltage_table, | |
1811 | mm_table->entries[count].vddc - data->vddc_vddci_delta); | |
1812 | table->SamuLevel[count].MinVoltage.Phases = 1; | |
1813 | ||
1814 | /* retrieve divider value for VBIOS */ | |
1815 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, | |
1816 | table->SamuLevel[count].Frequency, ÷rs); | |
1817 | PP_ASSERT_WITH_CODE((0 == result), | |
1818 | "can not find divide id for samu clock", return result); | |
1819 | ||
c15c8d70 | 1820 | table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
c82baa28 | 1821 | |
1822 | CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); | |
1823 | } | |
1824 | ||
1825 | return result; | |
1826 | } | |
1827 | ||
1828 | /** | |
1829 | * Populates the SMC MCLK structure using the provided memory clock | |
1830 | * | |
1831 | * @param hwmgr the address of the hardware manager | |
1832 | * @param memory_clock the memory clock to use to populate the structure | |
1833 | * @param sclk the SMC SCLK structure to be populated | |
1834 | */ | |
1835 | static int tonga_calculate_mclk_params( | |
1836 | struct pp_hwmgr *hwmgr, | |
1837 | uint32_t memory_clock, | |
1838 | SMU72_Discrete_MemoryLevel *mclk, | |
1839 | bool strobe_mode, | |
1840 | bool dllStateOn | |
1841 | ) | |
1842 | { | |
1843 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
1844 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; | |
1845 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; | |
1846 | uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; | |
1847 | uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; | |
1848 | uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; | |
1849 | uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; | |
1850 | uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; | |
1851 | uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; | |
1852 | uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; | |
1853 | ||
1854 | pp_atomctrl_memory_clock_param mpll_param; | |
1855 | int result; | |
1856 | ||
1857 | result = atomctrl_get_memory_pll_dividers_si(hwmgr, | |
1858 | memory_clock, &mpll_param, strobe_mode); | |
1859 | PP_ASSERT_WITH_CODE(0 == result, | |
1860 | "Error retrieving Memory Clock Parameters from VBIOS.", return result); | |
1861 | ||
1862 | /* MPLL_FUNC_CNTL setup*/ | |
c15c8d70 | 1863 | mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); |
c82baa28 | 1864 | |
1865 | /* MPLL_FUNC_CNTL_1 setup*/ | |
1866 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1867 | MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); | |
1868 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1869 | MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); | |
1870 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1871 | MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); | |
1872 | ||
1873 | /* MPLL_AD_FUNC_CNTL setup*/ | |
1874 | mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, | |
1875 | MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); | |
1876 | ||
1877 | if (data->is_memory_GDDR5) { | |
1878 | /* MPLL_DQ_FUNC_CNTL setup*/ | |
1879 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, | |
1880 | MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); | |
1881 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, | |
1882 | MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); | |
1883 | } | |
1884 | ||
1885 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
1886 | PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { | |
1887 | /* | |
1888 | ************************************ | |
1889 | Fref = Reference Frequency | |
1890 | NF = Feedback divider ratio | |
1891 | NR = Reference divider ratio | |
1892 | Fnom = Nominal VCO output frequency = Fref * NF / NR | |
1893 | Fs = Spreading Rate | |
1894 | D = Percentage down-spread / 2 | |
1895 | Fint = Reference input frequency to PFD = Fref / NR | |
1896 | NS = Spreading rate divider ratio = int(Fint / (2 * Fs)) | |
1897 | CLKS = NS - 1 = ISS_STEP_NUM[11:0] | |
1898 | NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2) | |
1899 | CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] | |
1900 | ************************************* | |
1901 | */ | |
1902 | pp_atomctrl_internal_ss_info ss_info; | |
1903 | uint32_t freq_nom; | |
1904 | uint32_t tmp; | |
1905 | uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); | |
1906 | ||
1907 | /* for GDDR5 for all modes and DDR3 */ | |
1908 | if (1 == mpll_param.qdr) | |
1909 | freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); | |
1910 | else | |
1911 | freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); | |
1912 | ||
1913 | /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ | |
1914 | tmp = (freq_nom / reference_clock); | |
1915 | tmp = tmp * tmp; | |
1916 | ||
1917 | if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { | |
1918 | /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */ | |
1919 | /* ss.Info.speed_spectrum_rate -- in unit of khz */ | |
1920 | /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */ | |
1921 | /* = reference_clock * 5 / speed_spectrum_rate */ | |
1922 | uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; | |
1923 | ||
1924 | /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */ | |
1925 | /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */ | |
1926 | uint32_t clkv = | |
1927 | (uint32_t)((((131 * ss_info.speed_spectrum_percentage * | |
1928 | ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); | |
1929 | ||
1930 | mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); | |
1931 | mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); | |
1932 | } | |
1933 | } | |
1934 | ||
1935 | /* MCLK_PWRMGT_CNTL setup */ | |
1936 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1937 | MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); | |
1938 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1939 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); | |
1940 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1941 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); | |
1942 | ||
1943 | ||
1944 | /* Save the result data to outpupt memory level structure */ | |
1945 | mclk->MclkFrequency = memory_clock; | |
1946 | mclk->MpllFuncCntl = mpll_func_cntl; | |
1947 | mclk->MpllFuncCntl_1 = mpll_func_cntl_1; | |
1948 | mclk->MpllFuncCntl_2 = mpll_func_cntl_2; | |
1949 | mclk->MpllAdFuncCntl = mpll_ad_func_cntl; | |
1950 | mclk->MpllDqFuncCntl = mpll_dq_func_cntl; | |
1951 | mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; | |
1952 | mclk->DllCntl = dll_cntl; | |
1953 | mclk->MpllSs1 = mpll_ss1; | |
1954 | mclk->MpllSs2 = mpll_ss2; | |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, | |
1960 | bool strobe_mode) | |
1961 | { | |
1962 | uint8_t mc_para_index; | |
1963 | ||
1964 | if (strobe_mode) { | |
1965 | if (memory_clock < 12500) { | |
1966 | mc_para_index = 0x00; | |
1967 | } else if (memory_clock > 47500) { | |
1968 | mc_para_index = 0x0f; | |
1969 | } else { | |
1970 | mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); | |
1971 | } | |
1972 | } else { | |
1973 | if (memory_clock < 65000) { | |
1974 | mc_para_index = 0x00; | |
1975 | } else if (memory_clock > 135000) { | |
1976 | mc_para_index = 0x0f; | |
1977 | } else { | |
1978 | mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); | |
1979 | } | |
1980 | } | |
1981 | ||
1982 | return mc_para_index; | |
1983 | } | |
1984 | ||
1985 | static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) | |
1986 | { | |
1987 | uint8_t mc_para_index; | |
1988 | ||
1989 | if (memory_clock < 10000) { | |
1990 | mc_para_index = 0; | |
1991 | } else if (memory_clock >= 80000) { | |
1992 | mc_para_index = 0x0f; | |
1993 | } else { | |
1994 | mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); | |
1995 | } | |
1996 | ||
1997 | return mc_para_index; | |
1998 | } | |
1999 | ||
2000 | static int tonga_populate_single_memory_level( | |
2001 | struct pp_hwmgr *hwmgr, | |
2002 | uint32_t memory_clock, | |
2003 | SMU72_Discrete_MemoryLevel *memory_level | |
2004 | ) | |
2005 | { | |
2006 | uint32_t minMvdd = 0; | |
2007 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2008 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2009 | int result = 0; | |
2010 | bool dllStateOn; | |
2011 | struct cgs_display_info info = {0}; | |
2012 | ||
2013 | ||
2014 | if (NULL != pptable_info->vdd_dep_on_mclk) { | |
2015 | result = tonga_get_dependecy_volt_by_clk(hwmgr, | |
2016 | pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd); | |
2017 | PP_ASSERT_WITH_CODE((0 == result), | |
2018 | "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); | |
2019 | } | |
2020 | ||
2021 | if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) { | |
2022 | memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value; | |
2023 | } else { | |
2024 | memory_level->MinMvdd = minMvdd; | |
2025 | } | |
2026 | memory_level->EnabledForThrottle = 1; | |
2027 | memory_level->EnabledForActivity = 0; | |
2028 | memory_level->UpHyst = 0; | |
2029 | memory_level->DownHyst = 100; | |
2030 | memory_level->VoltageDownHyst = 0; | |
2031 | ||
2032 | /* Indicates maximum activity level for this performance level.*/ | |
2033 | memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target; | |
2034 | memory_level->StutterEnable = 0; | |
2035 | memory_level->StrobeEnable = 0; | |
2036 | memory_level->EdcReadEnable = 0; | |
2037 | memory_level->EdcWriteEnable = 0; | |
2038 | memory_level->RttEnable = 0; | |
2039 | ||
2040 | /* default set to low watermark. Highest level will be set to high later.*/ | |
2041 | memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
2042 | ||
2043 | cgs_get_active_displays_info(hwmgr->device, &info); | |
2044 | data->display_timing.num_existing_displays = info.display_count; | |
2045 | ||
2046 | if ((data->mclk_stutter_mode_threshold != 0) && | |
7e8d1fbd | 2047 | (memory_clock <= data->mclk_stutter_mode_threshold) && |
4ba27f9b | 2048 | (!data->is_uvd_enabled) |
7e8d1fbd AD |
2049 | && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) |
2050 | && (data->display_timing.num_existing_displays <= 2) | |
2051 | && (data->display_timing.num_existing_displays != 0)) | |
c82baa28 | 2052 | memory_level->StutterEnable = 1; |
2053 | ||
2054 | /* decide strobe mode*/ | |
2055 | memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) && | |
2056 | (memory_clock <= data->mclk_strobe_mode_threshold); | |
2057 | ||
2058 | /* decide EDC mode and memory clock ratio*/ | |
2059 | if (data->is_memory_GDDR5) { | |
2060 | memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock, | |
2061 | memory_level->StrobeEnable); | |
2062 | ||
2063 | if ((data->mclk_edc_enable_threshold != 0) && | |
2064 | (memory_clock > data->mclk_edc_enable_threshold)) { | |
2065 | memory_level->EdcReadEnable = 1; | |
2066 | } | |
2067 | ||
2068 | if ((data->mclk_edc_wr_enable_threshold != 0) && | |
2069 | (memory_clock > data->mclk_edc_wr_enable_threshold)) { | |
2070 | memory_level->EdcWriteEnable = 1; | |
2071 | } | |
2072 | ||
2073 | if (memory_level->StrobeEnable) { | |
2074 | if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >= | |
2075 | ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) { | |
2076 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; | |
2077 | } else { | |
2078 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; | |
2079 | } | |
2080 | ||
2081 | } else { | |
2082 | dllStateOn = data->dll_defaule_on; | |
2083 | } | |
2084 | } else { | |
2085 | memory_level->StrobeRatio = | |
2086 | tonga_get_ddr3_mclk_frequency_ratio(memory_clock); | |
2087 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; | |
2088 | } | |
2089 | ||
2090 | result = tonga_calculate_mclk_params(hwmgr, | |
2091 | memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn); | |
2092 | ||
2093 | if (0 == result) { | |
2094 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd); | |
2095 | /* MCLK frequency in units of 10KHz*/ | |
2096 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); | |
2097 | /* Indicates maximum activity level for this performance level.*/ | |
2098 | CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); | |
2099 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); | |
2100 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); | |
2101 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); | |
2102 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); | |
2103 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); | |
2104 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); | |
2105 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); | |
2106 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); | |
2107 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); | |
2108 | } | |
2109 | ||
2110 | return result; | |
2111 | } | |
2112 | ||
2113 | /** | |
2114 | * Populates the SMC MVDD structure using the provided memory clock. | |
2115 | * | |
2116 | * @param hwmgr the address of the hardware manager | |
2117 | * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. | |
2118 | * @param voltage the SMC VOLTAGE structure to be populated | |
2119 | */ | |
2120 | int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern) | |
2121 | { | |
2122 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2123 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2124 | uint32_t i = 0; | |
2125 | ||
2126 | if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) { | |
2127 | /* find mvdd value which clock is more than request */ | |
2128 | for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) { | |
2129 | if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) { | |
2130 | /* Always round to higher voltage. */ | |
2131 | smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value; | |
2132 | break; | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count, | |
2137 | "MVDD Voltage is outside the supported range.", return -1); | |
2138 | ||
2139 | } else { | |
2140 | return -1; | |
2141 | } | |
2142 | ||
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | ||
2147 | static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr, | |
2148 | SMU72_Discrete_DpmTable *table) | |
2149 | { | |
2150 | int result = 0; | |
2151 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2152 | pp_atomctrl_clock_dividers_vi dividers; | |
2153 | SMIO_Pattern voltage_level; | |
2154 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; | |
2155 | uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; | |
2156 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; | |
2157 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; | |
2158 | ||
2159 | /* The ACPI state should not do DPM on DC (or ever).*/ | |
2160 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; | |
2161 | ||
2162 | table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage; | |
2163 | ||
2164 | /* assign zero for now*/ | |
2165 | table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); | |
2166 | ||
2167 | /* get the engine clock dividers for this clock value*/ | |
2168 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, | |
2169 | table->ACPILevel.SclkFrequency, ÷rs); | |
2170 | ||
2171 | PP_ASSERT_WITH_CODE(result == 0, | |
2172 | "Error retrieving Engine Clock dividers from VBIOS.", return result); | |
2173 | ||
2174 | /* divider ID for required SCLK*/ | |
2175 | table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; | |
2176 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
2177 | table->ACPILevel.DeepSleepDivId = 0; | |
2178 | ||
2179 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2180 | CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); | |
2181 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2182 | CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); | |
2183 | spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, | |
2184 | CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); | |
2185 | ||
2186 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; | |
2187 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; | |
2188 | table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; | |
2189 | table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; | |
2190 | table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; | |
2191 | table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; | |
2192 | table->ACPILevel.CcPwrDynRm = 0; | |
2193 | table->ACPILevel.CcPwrDynRm1 = 0; | |
2194 | ||
2195 | ||
2196 | /* For various features to be enabled/disabled while this level is active.*/ | |
2197 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); | |
2198 | /* SCLK frequency in units of 10KHz*/ | |
2199 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); | |
2200 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); | |
2201 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); | |
2202 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); | |
2203 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); | |
2204 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); | |
2205 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); | |
2206 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); | |
2207 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); | |
2208 | ||
2209 | /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ | |
2210 | table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage; | |
2211 | ||
2212 | /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/ | |
2213 | ||
2214 | if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level)) | |
2215 | table->MemoryACPILevel.MinMvdd = | |
2216 | PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); | |
2217 | else | |
2218 | table->MemoryACPILevel.MinMvdd = 0; | |
2219 | ||
2220 | /* Force reset on DLL*/ | |
2221 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2222 | MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); | |
2223 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2224 | MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); | |
2225 | ||
2226 | /* Disable DLL in ACPIState*/ | |
2227 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2228 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); | |
2229 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
2230 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); | |
2231 | ||
2232 | /* Enable DLL bypass signal*/ | |
2233 | dll_cntl = PHM_SET_FIELD(dll_cntl, | |
2234 | DLL_CNTL, MRDCK0_BYPASS, 0); | |
2235 | dll_cntl = PHM_SET_FIELD(dll_cntl, | |
2236 | DLL_CNTL, MRDCK1_BYPASS, 0); | |
2237 | ||
2238 | table->MemoryACPILevel.DllCntl = | |
2239 | PP_HOST_TO_SMC_UL(dll_cntl); | |
2240 | table->MemoryACPILevel.MclkPwrmgtCntl = | |
2241 | PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); | |
2242 | table->MemoryACPILevel.MpllAdFuncCntl = | |
2243 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); | |
2244 | table->MemoryACPILevel.MpllDqFuncCntl = | |
2245 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); | |
2246 | table->MemoryACPILevel.MpllFuncCntl = | |
2247 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); | |
2248 | table->MemoryACPILevel.MpllFuncCntl_1 = | |
2249 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); | |
2250 | table->MemoryACPILevel.MpllFuncCntl_2 = | |
2251 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); | |
2252 | table->MemoryACPILevel.MpllSs1 = | |
2253 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); | |
2254 | table->MemoryACPILevel.MpllSs2 = | |
2255 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); | |
2256 | ||
2257 | table->MemoryACPILevel.EnabledForThrottle = 0; | |
2258 | table->MemoryACPILevel.EnabledForActivity = 0; | |
2259 | table->MemoryACPILevel.UpHyst = 0; | |
2260 | table->MemoryACPILevel.DownHyst = 100; | |
2261 | table->MemoryACPILevel.VoltageDownHyst = 0; | |
2262 | /* Indicates maximum activity level for this performance level.*/ | |
2263 | table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); | |
2264 | ||
2265 | table->MemoryACPILevel.StutterEnable = 0; | |
2266 | table->MemoryACPILevel.StrobeEnable = 0; | |
2267 | table->MemoryACPILevel.EdcReadEnable = 0; | |
2268 | table->MemoryACPILevel.EdcWriteEnable = 0; | |
2269 | table->MemoryACPILevel.RttEnable = 0; | |
2270 | ||
2271 | return result; | |
2272 | } | |
2273 | ||
2274 | static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level) | |
2275 | { | |
2276 | int result = 0; | |
2277 | uint32_t i; | |
2278 | ||
2279 | for (i = 0; i < table->count; i++) { | |
2280 | if (value == table->dpm_levels[i].value) { | |
2281 | *boot_level = i; | |
2282 | result = 0; | |
2283 | } | |
2284 | } | |
2285 | return result; | |
2286 | } | |
2287 | ||
2288 | static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, | |
2289 | SMU72_Discrete_DpmTable *table) | |
2290 | { | |
2291 | int result = 0; | |
2292 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2293 | ||
2294 | table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */ | |
2295 | table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */ | |
2296 | ||
2297 | /* find boot level from dpm table*/ | |
2298 | result = tonga_find_boot_level(&(data->dpm_table.sclk_table), | |
2299 | data->vbios_boot_state.sclk_bootup_value, | |
2300 | (uint32_t *)&(data->smc_state_table.GraphicsBootLevel)); | |
2301 | ||
2302 | if (0 != result) { | |
2303 | data->smc_state_table.GraphicsBootLevel = 0; | |
2304 | printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ | |
2305 | in dependency table. Using Graphics DPM level 0!"); | |
2306 | result = 0; | |
2307 | } | |
2308 | ||
2309 | result = tonga_find_boot_level(&(data->dpm_table.mclk_table), | |
2310 | data->vbios_boot_state.mclk_bootup_value, | |
2311 | (uint32_t *)&(data->smc_state_table.MemoryBootLevel)); | |
2312 | ||
2313 | if (0 != result) { | |
2314 | data->smc_state_table.MemoryBootLevel = 0; | |
2315 | printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ | |
2316 | in dependency table. Using Memory DPM level 0!"); | |
2317 | result = 0; | |
2318 | } | |
2319 | ||
2320 | table->BootVoltage.Vddc = | |
2321 | tonga_get_voltage_id(&(data->vddc_voltage_table), | |
2322 | data->vbios_boot_state.vddc_bootup_value); | |
2323 | table->BootVoltage.VddGfx = | |
2324 | tonga_get_voltage_id(&(data->vddgfx_voltage_table), | |
2325 | data->vbios_boot_state.vddgfx_bootup_value); | |
2326 | table->BootVoltage.Vddci = | |
2327 | tonga_get_voltage_id(&(data->vddci_voltage_table), | |
2328 | data->vbios_boot_state.vddci_bootup_value); | |
2329 | table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; | |
2330 | ||
2331 | CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); | |
2332 | ||
2333 | return result; | |
2334 | } | |
2335 | ||
2336 | ||
2337 | /** | |
2338 | * Calculates the SCLK dividers using the provided engine clock | |
2339 | * | |
2340 | * @param hwmgr the address of the hardware manager | |
2341 | * @param engine_clock the engine clock to use to populate the structure | |
2342 | * @param sclk the SMC SCLK structure to be populated | |
2343 | */ | |
2344 | int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, | |
2345 | uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) | |
2346 | { | |
2347 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2348 | pp_atomctrl_clock_dividers_vi dividers; | |
2349 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; | |
2350 | uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; | |
2351 | uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; | |
2352 | uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; | |
2353 | uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; | |
2354 | uint32_t reference_clock; | |
2355 | uint32_t reference_divider; | |
2356 | uint32_t fbdiv; | |
2357 | int result; | |
2358 | ||
2359 | /* get the engine clock dividers for this clock value*/ | |
2360 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); | |
2361 | ||
2362 | PP_ASSERT_WITH_CODE(result == 0, | |
2363 | "Error retrieving Engine Clock dividers from VBIOS.", return result); | |
2364 | ||
2365 | /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/ | |
2366 | reference_clock = atomctrl_get_reference_clock(hwmgr); | |
2367 | ||
2368 | reference_divider = 1 + dividers.uc_pll_ref_div; | |
2369 | ||
2370 | /* low 14 bits is fraction and high 12 bits is divider*/ | |
2371 | fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; | |
2372 | ||
2373 | /* SPLL_FUNC_CNTL setup*/ | |
2374 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2375 | CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); | |
2376 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
2377 | CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); | |
2378 | ||
2379 | /* SPLL_FUNC_CNTL_3 setup*/ | |
2380 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, | |
2381 | CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); | |
2382 | ||
2383 | /* set to use fractional accumulation*/ | |
2384 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, | |
2385 | CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); | |
2386 | ||
2387 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2388 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { | |
2389 | pp_atomctrl_internal_ss_info ss_info; | |
2390 | ||
2391 | uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; | |
2392 | if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { | |
2393 | /* | |
2394 | * ss_info.speed_spectrum_percentage -- in unit of 0.01% | |
2395 | * ss_info.speed_spectrum_rate -- in unit of khz | |
2396 | */ | |
2397 | /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */ | |
2398 | uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); | |
2399 | ||
2400 | /* clkv = 2 * D * fbdiv / NS */ | |
2401 | uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); | |
2402 | ||
2403 | cg_spll_spread_spectrum = | |
2404 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS); | |
2405 | cg_spll_spread_spectrum = | |
2406 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); | |
2407 | cg_spll_spread_spectrum_2 = | |
2408 | PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV); | |
2409 | } | |
2410 | } | |
2411 | ||
2412 | sclk->SclkFrequency = engine_clock; | |
2413 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; | |
2414 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; | |
2415 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; | |
2416 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; | |
2417 | sclk->SclkDid = (uint8_t)dividers.pll_post_divider; | |
2418 | ||
2419 | return 0; | |
2420 | } | |
2421 | ||
438498a8 NW |
2422 | static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock, |
2423 | uint32_t min_engine_clock_in_sr) | |
a4333b4c EH |
2424 | { |
2425 | uint32_t i, temp; | |
9887e425 | 2426 | uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK); |
a4333b4c EH |
2427 | |
2428 | PP_ASSERT_WITH_CODE((engine_clock >= min), | |
2429 | "Engine clock can't satisfy stutter requirement!", return 0); | |
2430 | ||
2431 | for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) { | |
354ef928 | 2432 | temp = engine_clock >> i; |
a4333b4c EH |
2433 | |
2434 | if(temp >= min || i == 0) | |
2435 | break; | |
2436 | } | |
2437 | return (uint8_t)i; | |
2438 | } | |
2439 | ||
c82baa28 | 2440 | /** |
2441 | * Populates single SMC SCLK structure using the provided engine clock | |
2442 | * | |
2443 | * @param hwmgr the address of the hardware manager | |
2444 | * @param engine_clock the engine clock to use to populate the structure | |
2445 | * @param sclk the SMC SCLK structure to be populated | |
2446 | */ | |
2447 | static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level) | |
2448 | { | |
2449 | int result; | |
2450 | uint32_t threshold; | |
2451 | uint32_t mvdd; | |
2452 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2453 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2454 | ||
2455 | result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); | |
2456 | ||
2457 | ||
2458 | /* populate graphics levels*/ | |
2459 | result = tonga_get_dependecy_volt_by_clk(hwmgr, | |
2460 | pptable_info->vdd_dep_on_sclk, engine_clock, | |
2461 | &graphic_level->MinVoltage, &mvdd); | |
2462 | PP_ASSERT_WITH_CODE((0 == result), | |
2463 | "can not find VDDC voltage value for VDDC \ | |
2464 | engine clock dependency table", return result); | |
2465 | ||
2466 | /* SCLK frequency in units of 10KHz*/ | |
2467 | graphic_level->SclkFrequency = engine_clock; | |
2468 | ||
2469 | /* Indicates maximum activity level for this performance level. 50% for now*/ | |
2470 | graphic_level->ActivityLevel = sclk_activity_level_threshold; | |
2471 | ||
2472 | graphic_level->CcPwrDynRm = 0; | |
2473 | graphic_level->CcPwrDynRm1 = 0; | |
2474 | /* this level can be used if activity is high enough.*/ | |
2475 | graphic_level->EnabledForActivity = 0; | |
2476 | /* this level can be used for throttling.*/ | |
2477 | graphic_level->EnabledForThrottle = 1; | |
2478 | graphic_level->UpHyst = 0; | |
2479 | graphic_level->DownHyst = 0; | |
2480 | graphic_level->VoltageDownHyst = 0; | |
2481 | graphic_level->PowerThrottle = 0; | |
2482 | ||
2a702ccd | 2483 | threshold = engine_clock * data->fast_watermark_threshold / 100; |
c82baa28 | 2484 | /* |
2485 | *get the DAL clock. do it in funture. | |
2486 | PECI_GetMinClockSettings(hwmgr->peci, &minClocks); | |
2487 | data->display_timing.min_clock_insr = minClocks.engineClockInSR; | |
c82baa28 | 2488 | */ |
a4333b4c EH |
2489 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
2490 | PHM_PlatformCaps_SclkDeepSleep)) | |
2491 | graphic_level->DeepSleepDivId = | |
438498a8 | 2492 | tonga_get_sleep_divider_id_from_clock(engine_clock, |
a4333b4c | 2493 | data->display_timing.min_clock_insr); |
c82baa28 | 2494 | |
2495 | /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ | |
2496 | graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
2497 | ||
2498 | if (0 == result) { | |
2499 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/ | |
2500 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/ | |
2501 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); | |
2502 | CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); | |
2503 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); | |
2504 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); | |
2505 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); | |
2506 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); | |
2507 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); | |
2508 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); | |
2509 | } | |
2510 | ||
2511 | return result; | |
2512 | } | |
2513 | ||
2514 | /** | |
2515 | * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states | |
2516 | * | |
2517 | * @param hwmgr the address of the hardware manager | |
2518 | */ | |
2519 | static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) | |
2520 | { | |
2521 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2522 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2523 | struct tonga_dpm_table *dpm_table = &data->dpm_table; | |
2524 | phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; | |
2525 | uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; | |
2526 | int result = 0; | |
2527 | uint32_t level_array_adress = data->dpm_table_start + | |
2528 | offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); | |
2529 | uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) * | |
2530 | SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/ | |
2531 | SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; | |
2532 | uint32_t i, maxEntry; | |
2533 | uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0; | |
2534 | PECI_RegistryValue reg_value; | |
2535 | memset(levels, 0x00, level_array_size); | |
2536 | ||
2537 | for (i = 0; i < dpm_table->sclk_table.count; i++) { | |
2538 | result = tonga_populate_single_graphic_level(hwmgr, | |
2539 | dpm_table->sclk_table.dpm_levels[i].value, | |
2540 | (uint16_t)data->activity_target[i], | |
2541 | &(data->smc_state_table.GraphicsLevel[i])); | |
2542 | ||
2543 | if (0 != result) | |
2544 | return result; | |
2545 | ||
2546 | /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ | |
2547 | if (i > 1) | |
2548 | data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; | |
2549 | ||
2550 | if (0 == i) { | |
2551 | reg_value = 0; | |
2552 | if (reg_value != 0) | |
2553 | data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value; | |
2554 | } | |
2555 | ||
2556 | if (1 == i) { | |
2557 | reg_value = 0; | |
2558 | if (reg_value != 0) | |
2559 | data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value; | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | /* Only enable level 0 for now. */ | |
2564 | data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; | |
2565 | ||
2566 | /* set highest level watermark to high */ | |
2567 | if (dpm_table->sclk_table.count > 1) | |
2568 | data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = | |
2569 | PPSMC_DISPLAY_WATERMARK_HIGH; | |
2570 | ||
2571 | data->smc_state_table.GraphicsDpmLevelCount = | |
2572 | (uint8_t)dpm_table->sclk_table.count; | |
2573 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = | |
2574 | tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); | |
2575 | ||
2576 | if (pcie_table != NULL) { | |
2577 | PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), | |
2578 | "There must be 1 or more PCIE levels defined in PPTable.", return -1); | |
2579 | maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/ | |
2580 | for (i = 0; i < dpm_table->sclk_table.count; i++) { | |
2581 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = | |
2582 | (uint8_t) ((i < maxEntry) ? i : maxEntry); | |
2583 | } | |
2584 | } else { | |
2585 | if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) | |
2586 | printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!"); | |
2587 | ||
2588 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && | |
2589 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
2590 | (1<<(highest_pcie_level_enabled+1))) != 0)) { | |
2591 | highest_pcie_level_enabled++; | |
2592 | } | |
2593 | ||
2594 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && | |
2595 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
2596 | (1<<lowest_pcie_level_enabled)) == 0)) { | |
2597 | lowest_pcie_level_enabled++; | |
2598 | } | |
2599 | ||
2600 | while ((count < highest_pcie_level_enabled) && | |
2601 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
2602 | (1<<(lowest_pcie_level_enabled+1+count))) == 0)) { | |
2603 | count++; | |
2604 | } | |
2605 | mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ? | |
2606 | (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled; | |
2607 | ||
2608 | ||
2609 | /* set pcieDpmLevel to highest_pcie_level_enabled*/ | |
2610 | for (i = 2; i < dpm_table->sclk_table.count; i++) { | |
2611 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; | |
2612 | } | |
2613 | ||
2614 | /* set pcieDpmLevel to lowest_pcie_level_enabled*/ | |
2615 | data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; | |
2616 | ||
2617 | /* set pcieDpmLevel to mid_pcie_level_enabled*/ | |
2618 | data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; | |
2619 | } | |
2620 | /* level count will send to smc once at init smc table and never change*/ | |
2621 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); | |
2622 | ||
2623 | if (0 != result) | |
2624 | return result; | |
2625 | ||
2626 | return 0; | |
2627 | } | |
2628 | ||
2629 | /** | |
2630 | * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states | |
2631 | * | |
2632 | * @param hwmgr the address of the hardware manager | |
2633 | */ | |
2634 | ||
2635 | static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) | |
2636 | { | |
2637 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2638 | struct tonga_dpm_table *dpm_table = &data->dpm_table; | |
2639 | int result; | |
2640 | /* populate MCLK dpm table to SMU7 */ | |
2641 | uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel); | |
2642 | uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY; | |
2643 | SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel; | |
2644 | uint32_t i; | |
2645 | ||
2646 | memset(levels, 0x00, level_array_size); | |
2647 | ||
2648 | for (i = 0; i < dpm_table->mclk_table.count; i++) { | |
2649 | PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), | |
2650 | "can not populate memory level as memory clock is zero", return -1); | |
2651 | result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, | |
2652 | &(data->smc_state_table.MemoryLevel[i])); | |
2653 | if (0 != result) { | |
2654 | return result; | |
2655 | } | |
2656 | } | |
2657 | ||
2658 | /* Only enable level 0 for now.*/ | |
2659 | data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; | |
2660 | ||
2661 | /* | |
2662 | * in order to prevent MC activity from stutter mode to push DPM up. | |
2663 | * the UVD change complements this by putting the MCLK in a higher state | |
2664 | * by default such that we are not effected by up threshold or and MCLK DPM latency. | |
2665 | */ | |
2666 | data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; | |
2667 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel); | |
2668 | ||
2669 | data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; | |
2670 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); | |
2671 | /* set highest level watermark to high*/ | |
2672 | data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; | |
2673 | ||
2674 | /* level count will send to smc once at init smc table and never change*/ | |
2675 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, | |
2676 | level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); | |
2677 | ||
2678 | if (0 != result) { | |
2679 | return result; | |
2680 | } | |
2681 | ||
2682 | return 0; | |
2683 | } | |
2684 | ||
2685 | struct TONGA_DLL_SPEED_SETTING { | |
2686 | uint16_t Min; /* Minimum Data Rate*/ | |
2687 | uint16_t Max; /* Maximum Data Rate*/ | |
edf600da | 2688 | uint32_t dll_speed; /* The desired DLL_SPEED setting*/ |
c82baa28 | 2689 | }; |
2690 | ||
2691 | static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) | |
2692 | { | |
2693 | return 0; | |
2694 | } | |
2695 | ||
2696 | /* ---------------------------------------- ULV related functions ----------------------------------------------------*/ | |
2697 | ||
2698 | ||
2699 | static int tonga_reset_single_dpm_table( | |
2700 | struct pp_hwmgr *hwmgr, | |
2701 | struct tonga_single_dpm_table *dpm_table, | |
2702 | uint32_t count) | |
2703 | { | |
2704 | uint32_t i; | |
2705 | if (!(count <= MAX_REGULAR_DPM_NUMBER)) | |
2706 | printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \ | |
2707 | table entries to exceed max number! \n"); | |
2708 | ||
2709 | dpm_table->count = count; | |
2710 | for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) { | |
ed5121a3 | 2711 | dpm_table->dpm_levels[i].enabled = false; |
c82baa28 | 2712 | } |
2713 | ||
2714 | return 0; | |
2715 | } | |
2716 | ||
2717 | static void tonga_setup_pcie_table_entry( | |
2718 | struct tonga_single_dpm_table *dpm_table, | |
2719 | uint32_t index, uint32_t pcie_gen, | |
2720 | uint32_t pcie_lanes) | |
2721 | { | |
2722 | dpm_table->dpm_levels[index].value = pcie_gen; | |
2723 | dpm_table->dpm_levels[index].param1 = pcie_lanes; | |
ed5121a3 | 2724 | dpm_table->dpm_levels[index].enabled = true; |
c82baa28 | 2725 | } |
2726 | ||
c82baa28 | 2727 | static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr) |
2728 | { | |
2729 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2730 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2731 | phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; | |
2732 | uint32_t i, maxEntry; | |
2733 | ||
2734 | if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) { | |
2735 | data->pcie_gen_power_saving = data->pcie_gen_performance; | |
2736 | data->pcie_lane_power_saving = data->pcie_lane_performance; | |
2737 | } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) { | |
2738 | data->pcie_gen_performance = data->pcie_gen_power_saving; | |
2739 | data->pcie_lane_performance = data->pcie_lane_power_saving; | |
2740 | } | |
2741 | ||
2742 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK); | |
2743 | ||
2744 | if (pcie_table != NULL) { | |
2745 | /* | |
2746 | * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue). | |
2747 | * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry. | |
2748 | */ | |
2749 | maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ? | |
2750 | SMU72_MAX_LEVELS_LINK : pcie_table->count; | |
2751 | for (i = 1; i < maxEntry; i++) { | |
2752 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1, | |
2753 | get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed), | |
2754 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2755 | } | |
2756 | data->dpm_table.pcie_speed_table.count = maxEntry - 1; | |
2757 | } else { | |
2758 | /* Hardcode Pcie Table */ | |
2759 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, | |
2760 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), | |
2761 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2762 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, | |
2763 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), | |
2764 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2765 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, | |
2766 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
2767 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2768 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, | |
2769 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
2770 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2771 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, | |
2772 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
2773 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2774 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, | |
2775 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), | |
2776 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2777 | data->dpm_table.pcie_speed_table.count = 6; | |
2778 | } | |
2779 | /* Populate last level for boot PCIE level, but do not increment count. */ | |
2780 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, | |
2781 | data->dpm_table.pcie_speed_table.count, | |
2782 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), | |
2783 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); | |
2784 | ||
2785 | return 0; | |
2786 | ||
2787 | } | |
2788 | ||
2789 | /* | |
2790 | * This function is to initalize all DPM state tables for SMU7 based on the dependency table. | |
2791 | * Dynamic state patching function will then trim these state tables to the allowed range based | |
2792 | * on the power policy or external client requests, such as UVD request, etc. | |
2793 | */ | |
2794 | static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) | |
2795 | { | |
2796 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2797 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2798 | uint32_t i; | |
2799 | ||
2800 | phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table = | |
2801 | pptable_info->vdd_dep_on_sclk; | |
2802 | phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table = | |
2803 | pptable_info->vdd_dep_on_mclk; | |
2804 | ||
2805 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, | |
2806 | "SCLK dependency table is missing. This table is mandatory", return -1); | |
2807 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, | |
2808 | "SCLK dependency table has to have is missing. This table is mandatory", return -1); | |
2809 | ||
2810 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, | |
2811 | "MCLK dependency table is missing. This table is mandatory", return -1); | |
2812 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, | |
2813 | "VMCLK dependency table has to have is missing. This table is mandatory", return -1); | |
2814 | ||
2815 | /* clear the state table to reset everything to default */ | |
2816 | memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); | |
2817 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS); | |
2818 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY); | |
2819 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */ | |
2820 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/ | |
2821 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/ | |
2822 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/ | |
2823 | ||
2824 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, | |
2825 | "SCLK dependency table is missing. This table is mandatory", return -1); | |
2826 | /* Initialize Sclk DPM table based on allow Sclk values*/ | |
2827 | data->dpm_table.sclk_table.count = 0; | |
2828 | ||
2829 | for (i = 0; i < allowed_vdd_sclk_table->count; i++) { | |
2830 | if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != | |
2831 | allowed_vdd_sclk_table->entries[i].clk) { | |
2832 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = | |
2833 | allowed_vdd_sclk_table->entries[i].clk; | |
ed5121a3 | 2834 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = true; /*(i==0) ? 1 : 0; to do */ |
c82baa28 | 2835 | data->dpm_table.sclk_table.count++; |
2836 | } | |
2837 | } | |
2838 | ||
2839 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, | |
2840 | "MCLK dependency table is missing. This table is mandatory", return -1); | |
2841 | /* Initialize Mclk DPM table based on allow Mclk values */ | |
2842 | data->dpm_table.mclk_table.count = 0; | |
2843 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { | |
2844 | if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != | |
2845 | allowed_vdd_mclk_table->entries[i].clk) { | |
2846 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = | |
2847 | allowed_vdd_mclk_table->entries[i].clk; | |
ed5121a3 | 2848 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = true; /*(i==0) ? 1 : 0; */ |
c82baa28 | 2849 | data->dpm_table.mclk_table.count++; |
2850 | } | |
2851 | } | |
2852 | ||
c82baa28 | 2853 | /* setup PCIE gen speed levels*/ |
2854 | tonga_setup_default_pcie_tables(hwmgr); | |
2855 | ||
2856 | /* save a copy of the default DPM table*/ | |
2857 | memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table)); | |
2858 | ||
2859 | return 0; | |
2860 | } | |
2861 | ||
2862 | int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr, | |
2863 | const struct tonga_power_state *bootState) | |
2864 | { | |
2865 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2866 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2867 | uint8_t count, level; | |
2868 | ||
2869 | count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count); | |
2870 | for (level = 0; level < count; level++) { | |
2871 | if (pptable_info->vdd_dep_on_sclk->entries[level].clk >= | |
2872 | bootState->performance_levels[0].engine_clock) { | |
2873 | data->smc_state_table.GraphicsBootLevel = level; | |
2874 | break; | |
2875 | } | |
2876 | } | |
2877 | ||
2878 | count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count); | |
2879 | for (level = 0; level < count; level++) { | |
2880 | if (pptable_info->vdd_dep_on_mclk->entries[level].clk >= | |
2881 | bootState->performance_levels[0].memory_clock) { | |
2882 | data->smc_state_table.MemoryBootLevel = level; | |
2883 | break; | |
2884 | } | |
2885 | } | |
2886 | ||
2887 | return 0; | |
2888 | } | |
2889 | ||
2890 | /** | |
2891 | * Initializes the SMC table and uploads it | |
2892 | * | |
2893 | * @param hwmgr the address of the powerplay hardware manager. | |
2894 | * @param pInput the pointer to input data (PowerState) | |
2895 | * @return always 0 | |
2896 | */ | |
2897 | int tonga_init_smc_table(struct pp_hwmgr *hwmgr) | |
2898 | { | |
2899 | int result; | |
2900 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
2901 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
2902 | SMU72_Discrete_DpmTable *table = &(data->smc_state_table); | |
2903 | const phw_tonga_ulv_parm *ulv = &(data->ulv); | |
2904 | uint8_t i; | |
2905 | PECI_RegistryValue reg_value; | |
2906 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; | |
2907 | ||
2908 | result = tonga_setup_default_dpm_tables(hwmgr); | |
2909 | PP_ASSERT_WITH_CODE(0 == result, | |
2910 | "Failed to setup default DPM tables!", return result;); | |
2911 | memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table)); | |
2912 | if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) { | |
2913 | tonga_populate_smc_voltage_tables(hwmgr, table); | |
2914 | } | |
2915 | ||
2916 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2917 | PHM_PlatformCaps_AutomaticDCTransition)) { | |
2918 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; | |
2919 | } | |
2920 | ||
2921 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2922 | PHM_PlatformCaps_StepVddc)) { | |
2923 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; | |
2924 | } | |
2925 | ||
2926 | if (data->is_memory_GDDR5) { | |
2927 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; | |
2928 | } | |
2929 | ||
2930 | i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN); | |
2931 | ||
2932 | if (i == 1 || i == 0) { | |
2933 | table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL; | |
2934 | } | |
2935 | ||
2936 | if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) { | |
2937 | PP_ASSERT_WITH_CODE(0 == result, | |
2938 | "Failed to initialize ULV state!", return result;); | |
2939 | ||
2940 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
2941 | ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter); | |
2942 | } | |
2943 | ||
2944 | result = tonga_populate_smc_link_level(hwmgr, table); | |
2945 | PP_ASSERT_WITH_CODE(0 == result, | |
2946 | "Failed to initialize Link Level!", return result;); | |
2947 | ||
2948 | result = tonga_populate_all_graphic_levels(hwmgr); | |
2949 | PP_ASSERT_WITH_CODE(0 == result, | |
2950 | "Failed to initialize Graphics Level!", return result;); | |
2951 | ||
2952 | result = tonga_populate_all_memory_levels(hwmgr); | |
2953 | PP_ASSERT_WITH_CODE(0 == result, | |
2954 | "Failed to initialize Memory Level!", return result;); | |
2955 | ||
2956 | result = tonga_populate_smv_acpi_level(hwmgr, table); | |
2957 | PP_ASSERT_WITH_CODE(0 == result, | |
2958 | "Failed to initialize ACPI Level!", return result;); | |
2959 | ||
2960 | result = tonga_populate_smc_vce_level(hwmgr, table); | |
2961 | PP_ASSERT_WITH_CODE(0 == result, | |
2962 | "Failed to initialize VCE Level!", return result;); | |
2963 | ||
2964 | result = tonga_populate_smc_acp_level(hwmgr, table); | |
2965 | PP_ASSERT_WITH_CODE(0 == result, | |
2966 | "Failed to initialize ACP Level!", return result;); | |
2967 | ||
2968 | result = tonga_populate_smc_samu_level(hwmgr, table); | |
2969 | PP_ASSERT_WITH_CODE(0 == result, | |
2970 | "Failed to initialize SAMU Level!", return result;); | |
2971 | ||
2972 | /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */ | |
2973 | /* need to populate the ARB settings for the initial state. */ | |
2974 | result = tonga_program_memory_timing_parameters(hwmgr); | |
2975 | PP_ASSERT_WITH_CODE(0 == result, | |
2976 | "Failed to Write ARB settings for the initial state.", return result;); | |
2977 | ||
0104aa21 AD |
2978 | result = tonga_populate_smc_uvd_level(hwmgr, table); |
2979 | PP_ASSERT_WITH_CODE(0 == result, | |
2980 | "Failed to initialize UVD Level!", return result;); | |
2981 | ||
c82baa28 | 2982 | result = tonga_populate_smc_boot_level(hwmgr, table); |
2983 | PP_ASSERT_WITH_CODE(0 == result, | |
2984 | "Failed to initialize Boot Level!", return result;); | |
2985 | ||
2a702ccd RZ |
2986 | result = tonga_populate_bapm_parameters_in_dpm_table(hwmgr); |
2987 | PP_ASSERT_WITH_CODE(result == 0, | |
2988 | "Failed to populate BAPM Parameters!", return result); | |
2989 | ||
c82baa28 | 2990 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
2991 | PHM_PlatformCaps_ClockStretcher)) { | |
2992 | result = tonga_populate_clock_stretcher_data_table(hwmgr); | |
2993 | PP_ASSERT_WITH_CODE(0 == result, | |
2994 | "Failed to populate Clock Stretcher Data Table!", return result;); | |
2995 | } | |
2996 | table->GraphicsVoltageChangeEnable = 1; | |
2997 | table->GraphicsThermThrottleEnable = 1; | |
2998 | table->GraphicsInterval = 1; | |
2999 | table->VoltageInterval = 1; | |
3000 | table->ThermalInterval = 1; | |
3001 | table->TemperatureLimitHigh = | |
3002 | pptable_info->cac_dtp_table->usTargetOperatingTemp * | |
3003 | TONGA_Q88_FORMAT_CONVERSION_UNIT; | |
3004 | table->TemperatureLimitLow = | |
3005 | (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) * | |
3006 | TONGA_Q88_FORMAT_CONVERSION_UNIT; | |
3007 | table->MemoryVoltageChangeEnable = 1; | |
3008 | table->MemoryInterval = 1; | |
3009 | table->VoltageResponseTime = 0; | |
3010 | table->PhaseResponseTime = 0; | |
3011 | table->MemoryThermThrottleEnable = 1; | |
3012 | ||
3013 | /* | |
3014 | * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had) | |
3015 | * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again | |
3016 | * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay | |
3017 | * To avoid it, we set PCIeBootLinkLevel to highest dpm level | |
3018 | */ | |
3019 | PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), | |
3020 | "There must be 1 or more PCIE levels defined in PPTable.", | |
3021 | return -1); | |
3022 | ||
3023 | table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); | |
3024 | ||
3025 | table->PCIeGenInterval = 1; | |
3026 | ||
3027 | result = tonga_populate_vr_config(hwmgr, table); | |
3028 | PP_ASSERT_WITH_CODE(0 == result, | |
3029 | "Failed to populate VRConfig setting!", return result); | |
3030 | ||
3031 | table->ThermGpio = 17; | |
3032 | table->SclkStepSize = 0x4000; | |
3033 | ||
3034 | reg_value = 0; | |
3035 | if ((0 == reg_value) && | |
e013c91c RZ |
3036 | (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, |
3037 | &gpio_pin_assignment))) { | |
c82baa28 | 3038 | table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
3039 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3040 | PHM_PlatformCaps_RegulatorHot); | |
3041 | } else { | |
3042 | table->VRHotGpio = TONGA_UNUSED_GPIO_PIN; | |
3043 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3044 | PHM_PlatformCaps_RegulatorHot); | |
3045 | } | |
3046 | ||
3047 | /* ACDC Switch GPIO */ | |
3048 | reg_value = 0; | |
3049 | if ((0 == reg_value) && | |
e013c91c RZ |
3050 | (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, |
3051 | &gpio_pin_assignment))) { | |
c82baa28 | 3052 | table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
3053 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3054 | PHM_PlatformCaps_AutomaticDCTransition); | |
3055 | } else { | |
3056 | table->AcDcGpio = TONGA_UNUSED_GPIO_PIN; | |
3057 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3058 | PHM_PlatformCaps_AutomaticDCTransition); | |
3059 | } | |
3060 | ||
3061 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3062 | PHM_PlatformCaps_Falcon_QuickTransition); | |
3063 | ||
3064 | reg_value = 0; | |
3065 | if (1 == reg_value) { | |
3066 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3067 | PHM_PlatformCaps_AutomaticDCTransition); | |
3068 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3069 | PHM_PlatformCaps_Falcon_QuickTransition); | |
3070 | } | |
3071 | ||
3072 | reg_value = 0; | |
e013c91c | 3073 | if ((0 == reg_value) && (atomctrl_get_pp_assign_pin(hwmgr, |
c82baa28 | 3074 | THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) { |
3075 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
3076 | PHM_PlatformCaps_ThermalOutGPIO); | |
3077 | ||
3078 | table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; | |
3079 | ||
3080 | table->ThermOutPolarity = | |
3081 | (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & | |
3082 | (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0; | |
3083 | ||
3084 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; | |
3085 | ||
3086 | /* if required, combine VRHot/PCC with thermal out GPIO*/ | |
3087 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
3088 | PHM_PlatformCaps_RegulatorHot) && | |
3089 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
3090 | PHM_PlatformCaps_CombinePCCWithThermalSignal)){ | |
3091 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; | |
3092 | } | |
3093 | } else { | |
3094 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
3095 | PHM_PlatformCaps_ThermalOutGPIO); | |
3096 | ||
3097 | table->ThermOutGpio = 17; | |
3098 | table->ThermOutPolarity = 1; | |
3099 | table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; | |
3100 | } | |
3101 | ||
3102 | for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) { | |
3103 | table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); | |
3104 | } | |
3105 | CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); | |
3106 | CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); | |
3107 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); | |
3108 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); | |
3109 | CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); | |
3110 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); | |
3111 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); | |
3112 | CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); | |
3113 | CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); | |
3114 | ||
3115 | /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ | |
3116 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start + | |
3117 | offsetof(SMU72_Discrete_DpmTable, SystemFlags), | |
3118 | (uint8_t *)&(table->SystemFlags), | |
3119 | sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController), | |
3120 | data->sram_end); | |
3121 | ||
3122 | PP_ASSERT_WITH_CODE(0 == result, | |
3123 | "Failed to upload dpm data to SMC memory!", return result;); | |
3124 | ||
3125 | return result; | |
3126 | } | |
3127 | ||
3128 | /* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/ | |
3129 | static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr) | |
3130 | { | |
3131 | return; | |
3132 | } | |
3133 | ||
3134 | int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) | |
3135 | { | |
3136 | PPSMC_Result result; | |
3137 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3138 | ||
3139 | /* Apply minimum voltage based on DAL's request level */ | |
3140 | tonga_apply_dal_minimum_voltage_request(hwmgr); | |
3141 | ||
3142 | if (0 == data->sclk_dpm_key_disabled) { | |
3143 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
4ba27f9b | 3144 | if (tonga_is_dpm_running(hwmgr)) |
c82baa28 | 3145 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); |
3146 | ||
3147 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { | |
3148 | result = smum_send_msg_to_smc_with_parameter( | |
3149 | hwmgr->smumgr, | |
3150 | (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask, | |
3151 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); | |
3152 | PP_ASSERT_WITH_CODE((0 == result), | |
3153 | "Set Sclk Dpm enable Mask failed", return -1); | |
3154 | } | |
3155 | } | |
3156 | ||
3157 | if (0 == data->mclk_dpm_key_disabled) { | |
3158 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ | |
4ba27f9b | 3159 | if (tonga_is_dpm_running(hwmgr)) |
c82baa28 | 3160 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); |
3161 | ||
3162 | if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) { | |
3163 | result = smum_send_msg_to_smc_with_parameter( | |
3164 | hwmgr->smumgr, | |
3165 | (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask, | |
3166 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); | |
3167 | PP_ASSERT_WITH_CODE((0 == result), | |
3168 | "Set Mclk Dpm enable Mask failed", return -1); | |
3169 | } | |
3170 | } | |
3171 | ||
3172 | return 0; | |
3173 | } | |
3174 | ||
3175 | ||
3176 | int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr) | |
3177 | { | |
3178 | uint32_t level, tmp; | |
3179 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3180 | ||
3181 | if (0 == data->pcie_dpm_key_disabled) { | |
3182 | /* PCIE */ | |
3183 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { | |
3184 | level = 0; | |
3185 | tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; | |
3186 | while (tmp >>= 1) | |
3187 | level++ ; | |
3188 | ||
3189 | if (0 != level) { | |
3190 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)), | |
3191 | "force highest pcie dpm state failed!", return -1); | |
3192 | } | |
3193 | } | |
3194 | } | |
3195 | ||
3196 | if (0 == data->sclk_dpm_key_disabled) { | |
3197 | /* SCLK */ | |
3198 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) { | |
3199 | level = 0; | |
3200 | tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; | |
3201 | while (tmp >>= 1) | |
3202 | level++ ; | |
3203 | ||
3204 | if (0 != level) { | |
3205 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)), | |
3206 | "force highest sclk dpm state failed!", return -1); | |
3207 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, | |
3208 | CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level) | |
3209 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ | |
3210 | Curr_Sclk_Index does not match the level \n"); | |
3211 | ||
3212 | } | |
3213 | } | |
3214 | } | |
3215 | ||
3216 | if (0 == data->mclk_dpm_key_disabled) { | |
3217 | /* MCLK */ | |
3218 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { | |
3219 | level = 0; | |
3220 | tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; | |
3221 | while (tmp >>= 1) | |
3222 | level++ ; | |
3223 | ||
3224 | if (0 != level) { | |
3225 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)), | |
3226 | "force highest mclk dpm state failed!", return -1); | |
3227 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
3228 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level) | |
3229 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ | |
9fe1837d | 3230 | Curr_Mclk_Index does not match the level \n"); |
c82baa28 | 3231 | } |
3232 | } | |
3233 | } | |
3234 | ||
3235 | return 0; | |
3236 | } | |
3237 | ||
3238 | /** | |
3239 | * Find the MC microcode version and store it in the HwMgr struct | |
3240 | * | |
3241 | * @param hwmgr the address of the powerplay hardware manager. | |
3242 | * @return always 0 | |
3243 | */ | |
3244 | int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr) | |
3245 | { | |
3246 | cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); | |
3247 | ||
3248 | hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); | |
3249 | ||
3250 | return 0; | |
3251 | } | |
3252 | ||
3253 | /** | |
3254 | * Initialize Dynamic State Adjustment Rule Settings | |
3255 | * | |
3256 | * @param hwmgr the address of the powerplay hardware manager. | |
3257 | */ | |
3258 | int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr) | |
3259 | { | |
3260 | uint32_t table_size; | |
3261 | struct phm_clock_voltage_dependency_table *table_clk_vlt; | |
3262 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3263 | ||
3264 | hwmgr->dyn_state.mclk_sclk_ratio = 4; | |
3265 | hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */ | |
3266 | hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */ | |
3267 | ||
3268 | /* initialize vddc_dep_on_dal_pwrl table */ | |
3269 | table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record); | |
5969a8c7 | 3270 | table_clk_vlt = kzalloc(table_size, GFP_KERNEL); |
c82baa28 | 3271 | |
3272 | if (NULL == table_clk_vlt) { | |
3273 | printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n"); | |
3274 | return -ENOMEM; | |
3275 | } else { | |
3276 | table_clk_vlt->count = 4; | |
3277 | table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; | |
3278 | table_clk_vlt->entries[0].v = 0; | |
3279 | table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; | |
3280 | table_clk_vlt->entries[1].v = 720; | |
3281 | table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; | |
3282 | table_clk_vlt->entries[2].v = 810; | |
3283 | table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; | |
3284 | table_clk_vlt->entries[3].v = 900; | |
3285 | pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt; | |
3286 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; | |
3287 | } | |
3288 | ||
3289 | return 0; | |
3290 | } | |
3291 | ||
3292 | static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr) | |
3293 | { | |
3294 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3295 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3296 | ||
3297 | phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = | |
3298 | pptable_info->vdd_dep_on_sclk; | |
3299 | phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = | |
3300 | pptable_info->vdd_dep_on_mclk; | |
3301 | ||
3302 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, | |
edf600da | 3303 | "VDD dependency on SCLK table is missing. \ |
c82baa28 | 3304 | This table is mandatory", return -1); |
3305 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, | |
edf600da | 3306 | "VDD dependency on SCLK table has to have is missing. \ |
c82baa28 | 3307 | This table is mandatory", return -1); |
3308 | ||
3309 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, | |
edf600da | 3310 | "VDD dependency on MCLK table is missing. \ |
c82baa28 | 3311 | This table is mandatory", return -1); |
3312 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, | |
3313 | "VDD dependency on MCLK table has to have is missing. \ | |
3314 | This table is mandatory", return -1); | |
3315 | ||
3316 | data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc; | |
3317 | data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; | |
3318 | ||
3319 | pptable_info->max_clock_voltage_on_ac.sclk = | |
3320 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; | |
3321 | pptable_info->max_clock_voltage_on_ac.mclk = | |
3322 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; | |
3323 | pptable_info->max_clock_voltage_on_ac.vddc = | |
3324 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; | |
3325 | pptable_info->max_clock_voltage_on_ac.vddci = | |
3326 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; | |
3327 | ||
3328 | hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = | |
3329 | pptable_info->max_clock_voltage_on_ac.sclk; | |
3330 | hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = | |
3331 | pptable_info->max_clock_voltage_on_ac.mclk; | |
3332 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = | |
3333 | pptable_info->max_clock_voltage_on_ac.vddc; | |
3334 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = | |
3335 | pptable_info->max_clock_voltage_on_ac.vddci; | |
3336 | ||
3337 | return 0; | |
3338 | } | |
3339 | ||
3340 | int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr) | |
3341 | { | |
3342 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3343 | int result = 1; | |
3344 | ||
4ba27f9b EC |
3345 | PP_ASSERT_WITH_CODE (!tonga_is_dpm_running(hwmgr), |
3346 | "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.", | |
3347 | return result); | |
c82baa28 | 3348 | |
3349 | if (0 == data->pcie_dpm_key_disabled) { | |
3350 | PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( | |
3351 | hwmgr->smumgr, | |
3352 | PPSMC_MSG_PCIeDPM_UnForceLevel)), | |
3353 | "unforce pcie level failed!", | |
3354 | return -1); | |
3355 | } | |
3356 | ||
3357 | result = tonga_upload_dpm_level_enable_mask(hwmgr); | |
3358 | ||
3359 | return result; | |
3360 | } | |
3361 | ||
3362 | static uint32_t tonga_get_lowest_enable_level( | |
3363 | struct pp_hwmgr *hwmgr, uint32_t level_mask) | |
3364 | { | |
3365 | uint32_t level = 0; | |
3366 | ||
3367 | while (0 == (level_mask & (1 << level))) | |
3368 | level++; | |
3369 | ||
3370 | return level; | |
3371 | } | |
3372 | ||
3373 | static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr) | |
3374 | { | |
9fe1837d | 3375 | uint32_t level; |
c82baa28 | 3376 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
3377 | ||
9fe1837d AD |
3378 | if (0 == data->pcie_dpm_key_disabled) { |
3379 | /* PCIE */ | |
3380 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { | |
3381 | level = tonga_get_lowest_enable_level(hwmgr, | |
3382 | data->dpm_level_enable_mask.pcie_dpm_enable_mask); | |
3383 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)), | |
3384 | "force lowest pcie dpm state failed!", return -1); | |
3385 | } | |
3386 | } | |
3387 | ||
3388 | if (0 == data->sclk_dpm_key_disabled) { | |
3389 | /* SCLK */ | |
3390 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { | |
3391 | level = tonga_get_lowest_enable_level(hwmgr, | |
3392 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); | |
c82baa28 | 3393 | |
9fe1837d AD |
3394 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)), |
3395 | "force sclk dpm state failed!", return -1); | |
c82baa28 | 3396 | |
9fe1837d AD |
3397 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, |
3398 | CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level) | |
3399 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ | |
c82baa28 | 3400 | Curr_Sclk_Index does not match the level \n"); |
9fe1837d AD |
3401 | } |
3402 | } | |
3403 | ||
3404 | if (0 == data->mclk_dpm_key_disabled) { | |
3405 | /* MCLK */ | |
3406 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { | |
3407 | level = tonga_get_lowest_enable_level(hwmgr, | |
3408 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); | |
3409 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)), | |
3410 | "force lowest mclk dpm state failed!", return -1); | |
3411 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
3412 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level) | |
3413 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ | |
3414 | Curr_Mclk_Index does not match the level \n"); | |
3415 | } | |
c82baa28 | 3416 | } |
3417 | ||
3418 | return 0; | |
3419 | } | |
3420 | ||
3421 | static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr) | |
3422 | { | |
3423 | uint8_t entryId; | |
3424 | uint8_t voltageId; | |
3425 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3426 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3427 | ||
3428 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; | |
3429 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; | |
3430 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; | |
3431 | ||
3432 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { | |
3433 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { | |
3434 | voltageId = sclk_table->entries[entryId].vddInd; | |
3435 | sclk_table->entries[entryId].vddgfx = | |
3436 | pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd; | |
3437 | } | |
3438 | } else { | |
3439 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { | |
3440 | voltageId = sclk_table->entries[entryId].vddInd; | |
3441 | sclk_table->entries[entryId].vddc = | |
3442 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; | |
3443 | } | |
3444 | } | |
3445 | ||
3446 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { | |
3447 | voltageId = mclk_table->entries[entryId].vddInd; | |
3448 | mclk_table->entries[entryId].vddc = | |
3449 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; | |
3450 | } | |
3451 | ||
3452 | for (entryId = 0; entryId < mm_table->count; ++entryId) { | |
3453 | voltageId = mm_table->entries[entryId].vddcInd; | |
3454 | mm_table->entries[entryId].vddc = | |
3455 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; | |
3456 | } | |
3457 | ||
3458 | return 0; | |
3459 | ||
3460 | } | |
3461 | ||
3462 | static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) | |
3463 | { | |
3464 | uint8_t entryId; | |
3465 | phm_ppt_v1_voltage_lookup_record v_record; | |
3466 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3467 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3468 | ||
3469 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; | |
3470 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; | |
3471 | ||
3472 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { | |
3473 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { | |
3474 | if (sclk_table->entries[entryId].vdd_offset & (1 << 15)) | |
3475 | v_record.us_vdd = sclk_table->entries[entryId].vddgfx + | |
3476 | sclk_table->entries[entryId].vdd_offset - 0xFFFF; | |
3477 | else | |
3478 | v_record.us_vdd = sclk_table->entries[entryId].vddgfx + | |
3479 | sclk_table->entries[entryId].vdd_offset; | |
3480 | ||
3481 | sclk_table->entries[entryId].vddc = | |
3482 | v_record.us_cac_low = v_record.us_cac_mid = | |
3483 | v_record.us_cac_high = v_record.us_vdd; | |
3484 | ||
3485 | tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); | |
3486 | } | |
3487 | ||
3488 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { | |
3489 | if (mclk_table->entries[entryId].vdd_offset & (1 << 15)) | |
3490 | v_record.us_vdd = mclk_table->entries[entryId].vddc + | |
3491 | mclk_table->entries[entryId].vdd_offset - 0xFFFF; | |
3492 | else | |
3493 | v_record.us_vdd = mclk_table->entries[entryId].vddc + | |
3494 | mclk_table->entries[entryId].vdd_offset; | |
3495 | ||
3496 | mclk_table->entries[entryId].vddgfx = v_record.us_cac_low = | |
3497 | v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; | |
3498 | tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); | |
3499 | } | |
3500 | } | |
3501 | ||
3502 | return 0; | |
3503 | ||
3504 | } | |
3505 | ||
3506 | static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) | |
3507 | { | |
3508 | uint32_t entryId; | |
3509 | phm_ppt_v1_voltage_lookup_record v_record; | |
3510 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3511 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3512 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; | |
3513 | ||
3514 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { | |
3515 | for (entryId = 0; entryId < mm_table->count; entryId++) { | |
3516 | if (mm_table->entries[entryId].vddgfx_offset & (1 << 15)) | |
3517 | v_record.us_vdd = mm_table->entries[entryId].vddc + | |
3518 | mm_table->entries[entryId].vddgfx_offset - 0xFFFF; | |
3519 | else | |
3520 | v_record.us_vdd = mm_table->entries[entryId].vddc + | |
3521 | mm_table->entries[entryId].vddgfx_offset; | |
3522 | ||
3523 | /* Add the calculated VDDGFX to the VDDGFX lookup table */ | |
3524 | mm_table->entries[entryId].vddgfx = v_record.us_cac_low = | |
3525 | v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; | |
3526 | tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); | |
3527 | } | |
3528 | } | |
3529 | return 0; | |
3530 | } | |
3531 | ||
3532 | ||
3533 | /** | |
3534 | * Change virtual leakage voltage to actual value. | |
3535 | * | |
3536 | * @param hwmgr the address of the powerplay hardware manager. | |
3537 | * @param pointer to changing voltage | |
3538 | * @param pointer to leakage table | |
3539 | */ | |
3540 | static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, | |
3541 | uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable) | |
3542 | { | |
3543 | uint32_t leakage_index; | |
3544 | ||
3545 | /* search for leakage voltage ID 0xff01 ~ 0xff08 */ | |
3546 | for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) { | |
3547 | /* if this voltage matches a leakage voltage ID */ | |
3548 | /* patch with actual leakage voltage */ | |
3549 | if (pLeakageTable->leakage_id[leakage_index] == *voltage) { | |
3550 | *voltage = pLeakageTable->actual_voltage[leakage_index]; | |
3551 | break; | |
3552 | } | |
3553 | } | |
3554 | ||
3555 | if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) | |
3556 | printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n"); | |
3557 | } | |
3558 | ||
3559 | /** | |
3560 | * Patch voltage lookup table by EVV leakages. | |
3561 | * | |
3562 | * @param hwmgr the address of the powerplay hardware manager. | |
3563 | * @param pointer to voltage lookup table | |
3564 | * @param pointer to leakage table | |
3565 | * @return always 0 | |
3566 | */ | |
3567 | static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, | |
3568 | phm_ppt_v1_voltage_lookup_table *lookup_table, | |
3569 | phw_tonga_leakage_voltage *pLeakageTable) | |
3570 | { | |
3571 | uint32_t i; | |
3572 | ||
3573 | for (i = 0; i < lookup_table->count; i++) { | |
3574 | tonga_patch_with_vdd_leakage(hwmgr, | |
3575 | &lookup_table->entries[i].us_vdd, pLeakageTable); | |
3576 | } | |
3577 | ||
3578 | return 0; | |
3579 | } | |
3580 | ||
3581 | static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr, | |
3582 | phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc) | |
3583 | { | |
3584 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3585 | ||
3586 | tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable); | |
3587 | hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = | |
3588 | pptable_info->max_clock_voltage_on_dc.vddc; | |
3589 | ||
3590 | return 0; | |
3591 | } | |
3592 | ||
3593 | static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage( | |
3594 | struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable, | |
3595 | uint16_t *Vddgfx) | |
3596 | { | |
3597 | tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable); | |
3598 | return 0; | |
3599 | } | |
3600 | ||
3601 | int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr, | |
3602 | phm_ppt_v1_voltage_lookup_table *lookup_table) | |
3603 | { | |
3604 | uint32_t table_size, i, j; | |
3605 | phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; | |
3606 | table_size = lookup_table->count; | |
3607 | ||
3608 | PP_ASSERT_WITH_CODE(0 != lookup_table->count, | |
3609 | "Lookup table is empty", return -1); | |
3610 | ||
3611 | /* Sorting voltages */ | |
3612 | for (i = 0; i < table_size - 1; i++) { | |
3613 | for (j = i + 1; j > 0; j--) { | |
3614 | if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) { | |
3615 | tmp_voltage_lookup_record = lookup_table->entries[j-1]; | |
3616 | lookup_table->entries[j-1] = lookup_table->entries[j]; | |
3617 | lookup_table->entries[j] = tmp_voltage_lookup_record; | |
3618 | } | |
3619 | } | |
3620 | } | |
3621 | ||
3622 | return 0; | |
3623 | } | |
3624 | ||
3625 | static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr) | |
3626 | { | |
3627 | int result = 0; | |
3628 | int tmp_result; | |
3629 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
3630 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
3631 | ||
3632 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { | |
3633 | tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr, | |
3634 | pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); | |
3635 | if (tmp_result != 0) | |
3636 | result = tmp_result; | |
3637 | ||
3638 | tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr, | |
3639 | &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx); | |
3640 | if (tmp_result != 0) | |
3641 | result = tmp_result; | |
3642 | } else { | |
3643 | tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr, | |
3644 | pptable_info->vddc_lookup_table, &(data->vddc_leakage)); | |
3645 | if (tmp_result != 0) | |
3646 | result = tmp_result; | |
3647 | ||
3648 | tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr, | |
3649 | &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc); | |
3650 | if (tmp_result != 0) | |
3651 | result = tmp_result; | |
3652 | } | |
3653 | ||
3654 | tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr); | |
3655 | if (tmp_result != 0) | |
3656 | result = tmp_result; | |
3657 | ||
3658 | tmp_result = tonga_calc_voltage_dependency_tables(hwmgr); | |
3659 | if (tmp_result != 0) | |
3660 | result = tmp_result; | |
3661 | ||
3662 | tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr); | |
3663 | if (tmp_result != 0) | |
3664 | result = tmp_result; | |
3665 | ||
3666 | tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table); | |
3667 | if (tmp_result != 0) | |
3668 | result = tmp_result; | |
3669 | ||
3670 | tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table); | |
3671 | if (tmp_result != 0) | |
3672 | result = tmp_result; | |
3673 | ||
3674 | return result; | |
3675 | } | |
3676 | ||
3677 | int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr) | |
3678 | { | |
3679 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3680 | data->low_sclk_interrupt_threshold = 0; | |
3681 | ||
3682 | return 0; | |
3683 | } | |
3684 | ||
3685 | int tonga_setup_asic_task(struct pp_hwmgr *hwmgr) | |
3686 | { | |
3687 | int tmp_result, result = 0; | |
3688 | ||
3689 | tmp_result = tonga_read_clock_registers(hwmgr); | |
3690 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3691 | "Failed to read clock registers!", result = tmp_result); | |
3692 | ||
3693 | tmp_result = tonga_get_memory_type(hwmgr); | |
3694 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3695 | "Failed to get memory type!", result = tmp_result); | |
3696 | ||
3697 | tmp_result = tonga_enable_acpi_power_management(hwmgr); | |
3698 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3699 | "Failed to enable ACPI power management!", result = tmp_result); | |
3700 | ||
3701 | tmp_result = tonga_init_power_gate_state(hwmgr); | |
3702 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3703 | "Failed to init power gate state!", result = tmp_result); | |
3704 | ||
3705 | tmp_result = tonga_get_mc_microcode_version(hwmgr); | |
3706 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3707 | "Failed to get MC microcode version!", result = tmp_result); | |
3708 | ||
3709 | tmp_result = tonga_init_sclk_threshold(hwmgr); | |
3710 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
3711 | "Failed to init sclk threshold!", result = tmp_result); | |
3712 | ||
3713 | return result; | |
3714 | } | |
3715 | ||
3716 | /** | |
3717 | * Enable voltage control | |
3718 | * | |
3719 | * @param hwmgr the address of the powerplay hardware manager. | |
3720 | * @return always 0 | |
3721 | */ | |
3722 | int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr) | |
3723 | { | |
3724 | /* enable voltage control */ | |
3725 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); | |
3726 | ||
3727 | return 0; | |
3728 | } | |
3729 | ||
3730 | /** | |
3731 | * Checks if we want to support voltage control | |
3732 | * | |
3733 | * @param hwmgr the address of the powerplay hardware manager. | |
3734 | */ | |
3735 | bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr) | |
3736 | { | |
3737 | const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
3738 | ||
3739 | return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control); | |
3740 | } | |
3741 | ||
3742 | /*---------------------------MC----------------------------*/ | |
3743 | ||
3744 | uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr) | |
3745 | { | |
3746 | return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); | |
3747 | } | |
3748 | ||
3749 | bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) | |
3750 | { | |
ed5121a3 | 3751 | bool result = true; |
c82baa28 | 3752 | |
3753 | switch (inReg) { | |
3754 | case mmMC_SEQ_RAS_TIMING: | |
3755 | *outReg = mmMC_SEQ_RAS_TIMING_LP; | |
3756 | break; | |
3757 | ||
3758 | case mmMC_SEQ_DLL_STBY: | |
3759 | *outReg = mmMC_SEQ_DLL_STBY_LP; | |
3760 | break; | |
3761 | ||
3762 | case mmMC_SEQ_G5PDX_CMD0: | |
3763 | *outReg = mmMC_SEQ_G5PDX_CMD0_LP; | |
3764 | break; | |
3765 | ||
3766 | case mmMC_SEQ_G5PDX_CMD1: | |
3767 | *outReg = mmMC_SEQ_G5PDX_CMD1_LP; | |
3768 | break; | |
3769 | ||
3770 | case mmMC_SEQ_G5PDX_CTRL: | |
3771 | *outReg = mmMC_SEQ_G5PDX_CTRL_LP; | |
3772 | break; | |
3773 | ||
3774 | case mmMC_SEQ_CAS_TIMING: | |
3775 | *outReg = mmMC_SEQ_CAS_TIMING_LP; | |
3776 | break; | |
3777 | ||
3778 | case mmMC_SEQ_MISC_TIMING: | |
3779 | *outReg = mmMC_SEQ_MISC_TIMING_LP; | |
3780 | break; | |
3781 | ||
3782 | case mmMC_SEQ_MISC_TIMING2: | |
3783 | *outReg = mmMC_SEQ_MISC_TIMING2_LP; | |
3784 | break; | |
3785 | ||
3786 | case mmMC_SEQ_PMG_DVS_CMD: | |
3787 | *outReg = mmMC_SEQ_PMG_DVS_CMD_LP; | |
3788 | break; | |
3789 | ||
3790 | case mmMC_SEQ_PMG_DVS_CTL: | |
3791 | *outReg = mmMC_SEQ_PMG_DVS_CTL_LP; | |
3792 | break; | |
3793 | ||
3794 | case mmMC_SEQ_RD_CTL_D0: | |
3795 | *outReg = mmMC_SEQ_RD_CTL_D0_LP; | |
3796 | break; | |
3797 | ||
3798 | case mmMC_SEQ_RD_CTL_D1: | |
3799 | *outReg = mmMC_SEQ_RD_CTL_D1_LP; | |
3800 | break; | |
3801 | ||
3802 | case mmMC_SEQ_WR_CTL_D0: | |
3803 | *outReg = mmMC_SEQ_WR_CTL_D0_LP; | |
3804 | break; | |
3805 | ||
3806 | case mmMC_SEQ_WR_CTL_D1: | |
3807 | *outReg = mmMC_SEQ_WR_CTL_D1_LP; | |
3808 | break; | |
3809 | ||
3810 | case mmMC_PMG_CMD_EMRS: | |
3811 | *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP; | |
3812 | break; | |
3813 | ||
3814 | case mmMC_PMG_CMD_MRS: | |
3815 | *outReg = mmMC_SEQ_PMG_CMD_MRS_LP; | |
3816 | break; | |
3817 | ||
3818 | case mmMC_PMG_CMD_MRS1: | |
3819 | *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP; | |
3820 | break; | |
3821 | ||
3822 | case mmMC_SEQ_PMG_TIMING: | |
3823 | *outReg = mmMC_SEQ_PMG_TIMING_LP; | |
3824 | break; | |
3825 | ||
3826 | case mmMC_PMG_CMD_MRS2: | |
3827 | *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP; | |
3828 | break; | |
3829 | ||
3830 | case mmMC_SEQ_WR_CTL_2: | |
3831 | *outReg = mmMC_SEQ_WR_CTL_2_LP; | |
3832 | break; | |
3833 | ||
3834 | default: | |
ed5121a3 | 3835 | result = false; |
c82baa28 | 3836 | break; |
3837 | } | |
3838 | ||
3839 | return result; | |
3840 | } | |
3841 | ||
3842 | int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table) | |
3843 | { | |
3844 | uint32_t i; | |
3845 | uint16_t address; | |
3846 | ||
3847 | for (i = 0; i < table->last; i++) { | |
3848 | table->mc_reg_address[i].s0 = | |
3849 | tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) | |
3850 | ? address : table->mc_reg_address[i].s1; | |
3851 | } | |
3852 | return 0; | |
3853 | } | |
3854 | ||
3855 | int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table) | |
3856 | { | |
3857 | uint8_t i, j; | |
3858 | ||
3859 | PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
3860 | "Invalid VramInfo table.", return -1); | |
3861 | PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), | |
3862 | "Invalid VramInfo table.", return -1); | |
3863 | ||
3864 | for (i = 0; i < table->last; i++) { | |
3865 | ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; | |
3866 | } | |
3867 | ni_table->last = table->last; | |
3868 | ||
3869 | for (i = 0; i < table->num_entries; i++) { | |
3870 | ni_table->mc_reg_table_entry[i].mclk_max = | |
3871 | table->mc_reg_table_entry[i].mclk_max; | |
3872 | for (j = 0; j < table->last; j++) { | |
3873 | ni_table->mc_reg_table_entry[i].mc_data[j] = | |
3874 | table->mc_reg_table_entry[i].mc_data[j]; | |
3875 | } | |
3876 | } | |
c15c8d70 | 3877 | |
c82baa28 | 3878 | ni_table->num_entries = table->num_entries; |
3879 | ||
3880 | return 0; | |
3881 | } | |
3882 | ||
3883 | /** | |
3884 | * VBIOS omits some information to reduce size, we need to recover them here. | |
3885 | * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. | |
3886 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] | |
3887 | * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0]. | |
3888 | * 3. need to set these data for each clock range | |
3889 | * | |
3890 | * @param hwmgr the address of the powerplay hardware manager. | |
3891 | * @param table the address of MCRegTable | |
3892 | * @return always 0 | |
3893 | */ | |
3894 | int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table) | |
3895 | { | |
3896 | uint8_t i, j, k; | |
3897 | uint32_t temp_reg; | |
3898 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
3899 | ||
3900 | for (i = 0, j = table->last; i < table->last; i++) { | |
3901 | PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
3902 | "Invalid VramInfo table.", return -1); | |
3903 | switch (table->mc_reg_address[i].s1) { | |
3904 | /* | |
3905 | * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. | |
3906 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] | |
3907 | */ | |
3908 | case mmMC_SEQ_MISC1: | |
3909 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); | |
3910 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; | |
3911 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; | |
3912 | for (k = 0; k < table->num_entries; k++) { | |
3913 | table->mc_reg_table_entry[k].mc_data[j] = | |
3914 | ((temp_reg & 0xffff0000)) | | |
3915 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); | |
3916 | } | |
3917 | j++; | |
3918 | PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
3919 | "Invalid VramInfo table.", return -1); | |
3920 | ||
3921 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); | |
3922 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; | |
3923 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; | |
3924 | for (k = 0; k < table->num_entries; k++) { | |
3925 | table->mc_reg_table_entry[k].mc_data[j] = | |
3926 | (temp_reg & 0xffff0000) | | |
3927 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
3928 | ||
3929 | if (!data->is_memory_GDDR5) { | |
3930 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; | |
3931 | } | |
3932 | } | |
3933 | j++; | |
3934 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
3935 | "Invalid VramInfo table.", return -1); | |
3936 | ||
3937 | if (!data->is_memory_GDDR5) { | |
3938 | table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; | |
3939 | table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; | |
3940 | for (k = 0; k < table->num_entries; k++) { | |
3941 | table->mc_reg_table_entry[k].mc_data[j] = | |
3942 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; | |
3943 | } | |
3944 | j++; | |
3945 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
3946 | "Invalid VramInfo table.", return -1); | |
3947 | } | |
3948 | ||
3949 | break; | |
3950 | ||
3951 | case mmMC_SEQ_RESERVE_M: | |
3952 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); | |
3953 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; | |
3954 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; | |
3955 | for (k = 0; k < table->num_entries; k++) { | |
3956 | table->mc_reg_table_entry[k].mc_data[j] = | |
3957 | (temp_reg & 0xffff0000) | | |
3958 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
3959 | } | |
3960 | j++; | |
3961 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
3962 | "Invalid VramInfo table.", return -1); | |
3963 | break; | |
3964 | ||
3965 | default: | |
3966 | break; | |
3967 | } | |
3968 | ||
3969 | } | |
3970 | ||
3971 | table->last = j; | |
3972 | ||
3973 | return 0; | |
3974 | } | |
3975 | ||
3976 | int tonga_set_valid_flag(phw_tonga_mc_reg_table *table) | |
3977 | { | |
3978 | uint8_t i, j; | |
3979 | for (i = 0; i < table->last; i++) { | |
3980 | for (j = 1; j < table->num_entries; j++) { | |
3981 | if (table->mc_reg_table_entry[j-1].mc_data[i] != | |
3982 | table->mc_reg_table_entry[j].mc_data[i]) { | |
3983 | table->validflag |= (1<<i); | |
3984 | break; | |
3985 | } | |
3986 | } | |
3987 | } | |
3988 | ||
3989 | return 0; | |
3990 | } | |
3991 | ||
3992 | int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) | |
3993 | { | |
3994 | int result; | |
3995 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
3996 | pp_atomctrl_mc_reg_table *table; | |
3997 | phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table; | |
3998 | uint8_t module_index = tonga_get_memory_modile_index(hwmgr); | |
3999 | ||
4000 | table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); | |
4001 | ||
4002 | if (NULL == table) | |
c15c8d70 | 4003 | return -ENOMEM; |
c82baa28 | 4004 | |
4005 | /* Program additional LP registers that are no longer programmed by VBIOS */ | |
4006 | cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); | |
4007 | cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); | |
4008 | cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); | |
4009 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); | |
4010 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); | |
4011 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); | |
4012 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); | |
4013 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); | |
4014 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); | |
4015 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); | |
4016 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); | |
4017 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); | |
4018 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); | |
4019 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); | |
4020 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); | |
4021 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); | |
4022 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); | |
4023 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); | |
4024 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); | |
4025 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); | |
4026 | ||
4027 | memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); | |
4028 | ||
4029 | result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); | |
4030 | ||
4031 | if (0 == result) | |
4032 | result = tonga_copy_vbios_smc_reg_table(table, ni_table); | |
4033 | ||
4034 | if (0 == result) { | |
4035 | tonga_set_s0_mc_reg_index(ni_table); | |
4036 | result = tonga_set_mc_special_registers(hwmgr, ni_table); | |
4037 | } | |
4038 | ||
4039 | if (0 == result) | |
4040 | tonga_set_valid_flag(ni_table); | |
4041 | ||
4042 | kfree(table); | |
4043 | return result; | |
4044 | } | |
4045 | ||
4046 | /* | |
4047 | * Copy one arb setting to another and then switch the active set. | |
4048 | * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants. | |
4049 | */ | |
4050 | int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, | |
4051 | uint32_t arbFreqSrc, uint32_t arbFreqDest) | |
4052 | { | |
4053 | uint32_t mc_arb_dram_timing; | |
4054 | uint32_t mc_arb_dram_timing2; | |
4055 | uint32_t burst_time; | |
4056 | uint32_t mc_cg_config; | |
4057 | ||
4058 | switch (arbFreqSrc) { | |
4059 | case MC_CG_ARB_FREQ_F0: | |
4060 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); | |
4061 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); | |
4062 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); | |
4063 | break; | |
4064 | ||
4065 | case MC_CG_ARB_FREQ_F1: | |
4066 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); | |
4067 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); | |
4068 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); | |
4069 | break; | |
4070 | ||
4071 | default: | |
4072 | return -1; | |
4073 | } | |
4074 | ||
4075 | switch (arbFreqDest) { | |
4076 | case MC_CG_ARB_FREQ_F0: | |
4077 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); | |
4078 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); | |
4079 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); | |
4080 | break; | |
4081 | ||
4082 | case MC_CG_ARB_FREQ_F1: | |
4083 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); | |
4084 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); | |
4085 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); | |
4086 | break; | |
4087 | ||
4088 | default: | |
4089 | return -1; | |
4090 | } | |
4091 | ||
4092 | mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); | |
4093 | mc_cg_config |= 0x0000000F; | |
4094 | cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); | |
4095 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest); | |
4096 | ||
4097 | return 0; | |
4098 | } | |
4099 | ||
4100 | /** | |
4101 | * Initial switch from ARB F0->F1 | |
4102 | * | |
4103 | * @param hwmgr the address of the powerplay hardware manager. | |
4104 | * @return always 0 | |
4105 | * This function is to be called from the SetPowerState table. | |
4106 | */ | |
4107 | int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) | |
4108 | { | |
4109 | return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); | |
4110 | } | |
4111 | ||
4112 | /** | |
4113 | * Initialize the ARB DRAM timing table's index field. | |
4114 | * | |
4115 | * @param hwmgr the address of the powerplay hardware manager. | |
4116 | * @return always 0 | |
4117 | */ | |
4118 | int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) | |
4119 | { | |
4120 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4121 | uint32_t tmp; | |
4122 | int result; | |
4123 | ||
4124 | /* | |
4125 | * This is a read-modify-write on the first byte of the ARB table. | |
4126 | * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'. | |
4127 | * This solution is ugly, but we never write the whole table only individual fields in it. | |
4128 | * In reality this field should not be in that structure but in a soft register. | |
4129 | */ | |
4130 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, | |
4131 | data->arb_table_start, &tmp, data->sram_end); | |
4132 | ||
4133 | if (0 != result) | |
4134 | return result; | |
4135 | ||
4136 | tmp &= 0x00FFFFFF; | |
4137 | tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; | |
4138 | ||
4139 | return tonga_write_smc_sram_dword(hwmgr->smumgr, | |
4140 | data->arb_table_start, tmp, data->sram_end); | |
4141 | } | |
4142 | ||
4143 | int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table) | |
4144 | { | |
4145 | const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4146 | ||
4147 | uint32_t i, j; | |
4148 | ||
4149 | for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) { | |
4150 | if (data->tonga_mc_reg_table.validflag & 1<<j) { | |
4151 | PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE, | |
4152 | "Index of mc_reg_table->address[] array out of boundary", return -1); | |
4153 | mc_reg_table->address[i].s0 = | |
4154 | PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0); | |
4155 | mc_reg_table->address[i].s1 = | |
4156 | PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1); | |
4157 | i++; | |
4158 | } | |
4159 | } | |
4160 | ||
4161 | mc_reg_table->last = (uint8_t)i; | |
4162 | ||
4163 | return 0; | |
4164 | } | |
4165 | ||
4166 | /*convert register values from driver to SMC format */ | |
4167 | void tonga_convert_mc_registers( | |
4168 | const phw_tonga_mc_reg_entry * pEntry, | |
4169 | SMU72_Discrete_MCRegisterSet *pData, | |
4170 | uint32_t numEntries, uint32_t validflag) | |
4171 | { | |
4172 | uint32_t i, j; | |
4173 | ||
4174 | for (i = 0, j = 0; j < numEntries; j++) { | |
4175 | if (validflag & 1<<j) { | |
4176 | pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]); | |
4177 | i++; | |
4178 | } | |
4179 | } | |
4180 | } | |
4181 | ||
4182 | /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */ | |
4183 | int tonga_convert_mc_reg_table_entry_to_smc( | |
4184 | struct pp_hwmgr *hwmgr, | |
4185 | const uint32_t memory_clock, | |
4186 | SMU72_Discrete_MCRegisterSet *mc_reg_table_data | |
4187 | ) | |
4188 | { | |
4189 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4190 | uint32_t i = 0; | |
4191 | ||
4192 | for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) { | |
4193 | if (memory_clock <= | |
4194 | data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) { | |
4195 | break; | |
4196 | } | |
4197 | } | |
4198 | ||
4199 | if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0)) | |
4200 | --i; | |
4201 | ||
4202 | tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i], | |
4203 | mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag); | |
4204 | ||
4205 | return 0; | |
4206 | } | |
4207 | ||
4208 | int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, | |
4209 | SMU72_Discrete_MCRegisters *mc_reg_table) | |
4210 | { | |
4211 | int result = 0; | |
4212 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4213 | int res; | |
4214 | uint32_t i; | |
4215 | ||
4216 | for (i = 0; i < data->dpm_table.mclk_table.count; i++) { | |
4217 | res = tonga_convert_mc_reg_table_entry_to_smc( | |
4218 | hwmgr, | |
4219 | data->dpm_table.mclk_table.dpm_levels[i].value, | |
4220 | &mc_reg_table->data[i] | |
4221 | ); | |
4222 | ||
4223 | if (0 != res) | |
4224 | result = res; | |
4225 | } | |
4226 | ||
4227 | return result; | |
4228 | } | |
4229 | ||
4230 | int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) | |
4231 | { | |
4232 | int result; | |
4233 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4234 | ||
4235 | memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters)); | |
4236 | result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table)); | |
4237 | PP_ASSERT_WITH_CODE(0 == result, | |
4238 | "Failed to initialize MCRegTable for the MC register addresses!", return result;); | |
4239 | ||
4240 | result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table); | |
4241 | PP_ASSERT_WITH_CODE(0 == result, | |
4242 | "Failed to initialize MCRegTable for driver state!", return result;); | |
4243 | ||
4244 | return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start, | |
4245 | (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end); | |
4246 | } | |
4247 | ||
4248 | /** | |
4249 | * Programs static screed detection parameters | |
4250 | * | |
4251 | * @param hwmgr the address of the powerplay hardware manager. | |
4252 | * @return always 0 | |
4253 | */ | |
4254 | int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) | |
4255 | { | |
4256 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
4257 | ||
4258 | /* Set static screen threshold unit*/ | |
4259 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, | |
4260 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, | |
4261 | data->static_screen_threshold_unit); | |
4262 | /* Set static screen threshold*/ | |
4263 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, | |
4264 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, | |
4265 | data->static_screen_threshold); | |
4266 | ||
4267 | return 0; | |
4268 | } | |
4269 | ||
4270 | /** | |
4271 | * Setup display gap for glitch free memory clock switching. | |
4272 | * | |
4273 | * @param hwmgr the address of the powerplay hardware manager. | |
4274 | * @return always 0 | |
4275 | */ | |
4276 | int tonga_enable_display_gap(struct pp_hwmgr *hwmgr) | |
4277 | { | |
4278 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, | |
4279 | CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); | |
4280 | ||
4281 | display_gap = PHM_SET_FIELD(display_gap, | |
4282 | CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE); | |
4283 | ||
4284 | display_gap = PHM_SET_FIELD(display_gap, | |
4285 | CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); | |
4286 | ||
4287 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4288 | ixCG_DISPLAY_GAP_CNTL, display_gap); | |
4289 | ||
4290 | return 0; | |
4291 | } | |
4292 | ||
4293 | /** | |
4294 | * Programs activity state transition voting clients | |
4295 | * | |
4296 | * @param hwmgr the address of the powerplay hardware manager. | |
4297 | * @return always 0 | |
4298 | */ | |
4299 | int tonga_program_voting_clients(struct pp_hwmgr *hwmgr) | |
4300 | { | |
4301 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | |
4302 | ||
4303 | /* Clear reset for voting clients before enabling DPM */ | |
4304 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
4305 | SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); | |
4306 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
4307 | SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); | |
4308 | ||
4309 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4310 | ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); | |
4311 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4312 | ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); | |
4313 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4314 | ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); | |
4315 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4316 | ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); | |
4317 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4318 | ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); | |
4319 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4320 | ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); | |
4321 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4322 | ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); | |
4323 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4324 | ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); | |
4325 | ||
4326 | return 0; | |
4327 | } | |
4328 | ||
4329 | ||
4330 | int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr) | |
4331 | { | |
4332 | int tmp_result, result = 0; | |
4333 | ||
4334 | tmp_result = tonga_check_for_dpm_stopped(hwmgr); | |
4335 | ||
4336 | if (cf_tonga_voltage_control(hwmgr)) { | |
4337 | tmp_result = tonga_enable_voltage_control(hwmgr); | |
4338 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4339 | "Failed to enable voltage control!", result = tmp_result); | |
4340 | ||
4341 | tmp_result = tonga_construct_voltage_tables(hwmgr); | |
4342 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4343 | "Failed to contruct voltage tables!", result = tmp_result); | |
4344 | } | |
4345 | ||
4346 | tmp_result = tonga_initialize_mc_reg_table(hwmgr); | |
4347 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4348 | "Failed to initialize MC reg table!", result = tmp_result); | |
4349 | ||
4350 | tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr); | |
4351 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4352 | "Failed to program static screen threshold parameters!", result = tmp_result); | |
4353 | ||
4354 | tmp_result = tonga_enable_display_gap(hwmgr); | |
4355 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4356 | "Failed to enable display gap!", result = tmp_result); | |
4357 | ||
4358 | tmp_result = tonga_program_voting_clients(hwmgr); | |
4359 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4360 | "Failed to program voting clients!", result = tmp_result); | |
4361 | ||
4362 | tmp_result = tonga_process_firmware_header(hwmgr); | |
4363 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4364 | "Failed to process firmware header!", result = tmp_result); | |
4365 | ||
4366 | tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr); | |
4367 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4368 | "Failed to initialize switch from ArbF0 to F1!", result = tmp_result); | |
4369 | ||
4370 | tmp_result = tonga_init_smc_table(hwmgr); | |
4371 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4372 | "Failed to initialize SMC table!", result = tmp_result); | |
4373 | ||
4374 | tmp_result = tonga_init_arb_table_index(hwmgr); | |
4375 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4376 | "Failed to initialize ARB table index!", result = tmp_result); | |
4377 | ||
2a702ccd RZ |
4378 | tmp_result = tonga_populate_pm_fuses(hwmgr); |
4379 | PP_ASSERT_WITH_CODE((tmp_result == 0), | |
4380 | "Failed to populate PM fuses!", result = tmp_result); | |
4381 | ||
c82baa28 | 4382 | tmp_result = tonga_populate_initial_mc_reg_table(hwmgr); |
4383 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4384 | "Failed to populate initialize MC Reg table!", result = tmp_result); | |
4385 | ||
bbb207f3 RZ |
4386 | tmp_result = tonga_notify_smc_display_change(hwmgr, false); |
4387 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4388 | "Failed to notify no display!", result = tmp_result); | |
4389 | ||
c82baa28 | 4390 | /* enable SCLK control */ |
4391 | tmp_result = tonga_enable_sclk_control(hwmgr); | |
4392 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4393 | "Failed to enable SCLK control!", result = tmp_result); | |
4394 | ||
4395 | /* enable DPM */ | |
4396 | tmp_result = tonga_start_dpm(hwmgr); | |
4397 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4398 | "Failed to start DPM!", result = tmp_result); | |
4399 | ||
2a702ccd RZ |
4400 | tmp_result = tonga_enable_smc_cac(hwmgr); |
4401 | PP_ASSERT_WITH_CODE((tmp_result == 0), | |
4402 | "Failed to enable SMC CAC!", result = tmp_result); | |
4403 | ||
4404 | tmp_result = tonga_enable_power_containment(hwmgr); | |
4405 | PP_ASSERT_WITH_CODE((tmp_result == 0), | |
4406 | "Failed to enable power containment!", result = tmp_result); | |
4407 | ||
4408 | tmp_result = tonga_power_control_set_level(hwmgr); | |
4409 | PP_ASSERT_WITH_CODE((tmp_result == 0), | |
4410 | "Failed to power control set level!", result = tmp_result); | |
4411 | ||
c82baa28 | 4412 | return result; |
4413 | } | |
4414 | ||
4415 | int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr) | |
4416 | { | |
4417 | int tmp_result, result = 0; | |
4418 | ||
4419 | tmp_result = tonga_check_for_dpm_running(hwmgr); | |
4420 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4421 | "SMC is still running!", return 0); | |
4422 | ||
4423 | tmp_result = tonga_stop_dpm(hwmgr); | |
4424 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4425 | "Failed to stop DPM!", result = tmp_result); | |
4426 | ||
4427 | tmp_result = tonga_reset_to_default(hwmgr); | |
4428 | PP_ASSERT_WITH_CODE((0 == tmp_result), | |
4429 | "Failed to reset to default!", result = tmp_result); | |
4430 | ||
4431 | return result; | |
4432 | } | |
4433 | ||
4434 | int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr) | |
4435 | { | |
4436 | int result; | |
4437 | ||
4438 | result = tonga_set_boot_state(hwmgr); | |
4439 | if (0 != result) | |
4440 | printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n"); | |
4441 | ||
4442 | return result; | |
4443 | } | |
4444 | ||
4445 | int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) | |
4446 | { | |
92dea67d | 4447 | return phm_hwmgr_backend_fini(hwmgr); |
c82baa28 | 4448 | } |
4449 | ||
4450 | /** | |
4451 | * Initializes the Volcanic Islands Hardware Manager | |
4452 | * | |
4453 | * @param hwmgr the address of the powerplay hardware manager. | |
4454 | * @return 1 if success; otherwise appropriate error code. | |
4455 | */ | |
4456 | int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) | |
4457 | { | |
4458 | int result = 0; | |
4459 | SMU72_Discrete_DpmTable *table = NULL; | |
76ad42c1 | 4460 | tonga_hwmgr *data; |
c82baa28 | 4461 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; |
4462 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
4463 | phw_tonga_ulv_parm *ulv; | |
52b52a87 | 4464 | struct cgs_system_info sys_info = {0}; |
c82baa28 | 4465 | |
4466 | PP_ASSERT_WITH_CODE((NULL != hwmgr), | |
4467 | "Invalid Parameter!", return -1;); | |
4468 | ||
76ad42c1 EH |
4469 | data = kzalloc(sizeof(struct tonga_hwmgr), GFP_KERNEL); |
4470 | if (data == NULL) | |
4471 | return -ENOMEM; | |
4472 | ||
4473 | hwmgr->backend = data; | |
4474 | ||
ed5121a3 | 4475 | data->dll_defaule_on = false; |
c82baa28 | 4476 | data->sram_end = SMC_RAM_END; |
4477 | ||
4478 | data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT; | |
4479 | data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT; | |
4480 | data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT; | |
4481 | data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT; | |
4482 | data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT; | |
4483 | data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT; | |
4484 | data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT; | |
4485 | data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT; | |
4486 | ||
4487 | data->vddc_vddci_delta = VDDC_VDDCI_DELTA; | |
4488 | data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA; | |
4489 | data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT; | |
4490 | ||
4491 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4492 | PHM_PlatformCaps_DisableVoltageIsland); | |
4493 | ||
4494 | data->sclk_dpm_key_disabled = 0; | |
4495 | data->mclk_dpm_key_disabled = 0; | |
4496 | data->pcie_dpm_key_disabled = 0; | |
4497 | data->pcc_monitor_enabled = 0; | |
4498 | ||
4499 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4500 | PHM_PlatformCaps_UnTabledHardwareInterface); | |
4501 | ||
4502 | data->gpio_debug = 0; | |
4503 | data->engine_clock_data = 0; | |
4504 | data->memory_clock_data = 0; | |
4505 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4506 | PHM_PlatformCaps_DynamicPatchPowerState); | |
4507 | ||
4508 | /* need to set voltage control types before EVV patching*/ | |
4509 | data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE; | |
4510 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE; | |
4511 | data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE; | |
4512 | data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE; | |
a2fb4934 | 4513 | data->force_pcie_gen = PP_PCIEGenInvalid; |
c82baa28 | 4514 | |
3ec2cdb8 | 4515 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
c82baa28 | 4516 | VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { |
4517 | data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; | |
4518 | } | |
4519 | ||
4520 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
4521 | PHM_PlatformCaps_ControlVDDGFX)) { | |
3ec2cdb8 | 4522 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
c82baa28 | 4523 | VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { |
4524 | data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; | |
4525 | } | |
4526 | } | |
4527 | ||
4528 | if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) { | |
4529 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
4530 | PHM_PlatformCaps_ControlVDDGFX); | |
4531 | } | |
4532 | ||
4533 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
4534 | PHM_PlatformCaps_EnableMVDDControl)) { | |
3ec2cdb8 | 4535 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
c82baa28 | 4536 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) { |
4537 | data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO; | |
4538 | } | |
4539 | } | |
4540 | ||
4541 | if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) { | |
4542 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
4543 | PHM_PlatformCaps_EnableMVDDControl); | |
4544 | } | |
4545 | ||
4546 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
4547 | PHM_PlatformCaps_ControlVDDCI)) { | |
3ec2cdb8 | 4548 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
c82baa28 | 4549 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) |
4550 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO; | |
3ec2cdb8 | 4551 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
c82baa28 | 4552 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) |
4553 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; | |
4554 | } | |
4555 | ||
4556 | if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control) | |
4557 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
4558 | PHM_PlatformCaps_ControlVDDCI); | |
4559 | ||
4560 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4561 | PHM_PlatformCaps_TablelessHardwareInterface); | |
4562 | ||
4563 | if (pptable_info->cac_dtp_table->usClockStretchAmount != 0) | |
4564 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4565 | PHM_PlatformCaps_ClockStretcher); | |
4566 | ||
4567 | /* Initializes DPM default values*/ | |
4568 | tonga_initialize_dpm_defaults(hwmgr); | |
4569 | ||
4570 | /* Get leakage voltage based on leakage ID.*/ | |
4571 | PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)), | |
4572 | "Get EVV Voltage Failed. Abort Driver loading!", return -1); | |
4573 | ||
4574 | tonga_complete_dependency_tables(hwmgr); | |
4575 | ||
4576 | /* Parse pptable data read from VBIOS*/ | |
4577 | tonga_set_private_var_based_on_pptale(hwmgr); | |
4578 | ||
4579 | /* ULV Support*/ | |
4580 | ulv = &(data->ulv); | |
ed5121a3 | 4581 | ulv->ulv_supported = false; |
c82baa28 | 4582 | |
4583 | /* Initalize Dynamic State Adjustment Rule Settings*/ | |
4584 | result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr); | |
aa22ae4b AD |
4585 | if (result) |
4586 | printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n"); | |
ed5121a3 | 4587 | data->uvd_enabled = false; |
c82baa28 | 4588 | |
4589 | table = &(data->smc_state_table); | |
4590 | ||
4591 | /* | |
4592 | * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, | |
4593 | * Peak Current Control feature is enabled and we should program PCC HW register | |
4594 | */ | |
e013c91c | 4595 | if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { |
c82baa28 | 4596 | uint32_t temp_reg = cgs_read_ind_register(hwmgr->device, |
4597 | CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); | |
4598 | ||
4599 | switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { | |
4600 | case 0: | |
4601 | temp_reg = PHM_SET_FIELD(temp_reg, | |
4602 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); | |
4603 | break; | |
4604 | case 1: | |
4605 | temp_reg = PHM_SET_FIELD(temp_reg, | |
4606 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); | |
4607 | break; | |
4608 | case 2: | |
4609 | temp_reg = PHM_SET_FIELD(temp_reg, | |
4610 | CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); | |
4611 | break; | |
4612 | case 3: | |
4613 | temp_reg = PHM_SET_FIELD(temp_reg, | |
4614 | CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); | |
4615 | break; | |
4616 | case 4: | |
4617 | temp_reg = PHM_SET_FIELD(temp_reg, | |
4618 | CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); | |
4619 | break; | |
4620 | default: | |
4621 | printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \ | |
4622 | Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n"); | |
4623 | break; | |
4624 | } | |
4625 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
4626 | ixCNB_PWRMGT_CNTL, temp_reg); | |
4627 | } | |
4628 | ||
4629 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4630 | PHM_PlatformCaps_EnableSMU7ThermalManagement); | |
4631 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4632 | PHM_PlatformCaps_SMU7); | |
4633 | ||
ed5121a3 | 4634 | data->vddc_phase_shed_control = false; |
c82baa28 | 4635 | |
3d5afb41 AD |
4636 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
4637 | PHM_PlatformCaps_UVDPowerGating); | |
f997e6f2 AD |
4638 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
4639 | PHM_PlatformCaps_VCEPowerGating); | |
52b52a87 AD |
4640 | sys_info.size = sizeof(struct cgs_system_info); |
4641 | sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; | |
4642 | result = cgs_query_system_info(hwmgr->device, &sys_info); | |
4643 | if (!result) { | |
4644 | if (sys_info.value & AMD_PG_SUPPORT_UVD) | |
4645 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4646 | PHM_PlatformCaps_UVDPowerGating); | |
4647 | if (sys_info.value & AMD_PG_SUPPORT_VCE) | |
4648 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | |
4649 | PHM_PlatformCaps_VCEPowerGating); | |
4650 | } | |
834b694c | 4651 | |
c82baa28 | 4652 | if (0 == result) { |
ed5121a3 | 4653 | data->is_tlu_enabled = false; |
c82baa28 | 4654 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = |
4655 | TONGA_MAX_HARDWARE_POWERLEVELS; | |
4656 | hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; | |
4657 | hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; | |
4658 | ||
834b694c AD |
4659 | sys_info.size = sizeof(struct cgs_system_info); |
4660 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; | |
4661 | result = cgs_query_system_info(hwmgr->device, &sys_info); | |
4662 | if (result) | |
d1371f8c | 4663 | data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; |
834b694c AD |
4664 | else |
4665 | data->pcie_gen_cap = (uint32_t)sys_info.value; | |
4666 | if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) | |
4667 | data->pcie_spc_cap = 20; | |
4668 | sys_info.size = sizeof(struct cgs_system_info); | |
4669 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; | |
4670 | result = cgs_query_system_info(hwmgr->device, &sys_info); | |
4671 | if (result) | |
d1371f8c | 4672 | data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; |
834b694c AD |
4673 | else |
4674 | data->pcie_lane_cap = (uint32_t)sys_info.value; | |
c82baa28 | 4675 | } else { |
4676 | /* Ignore return value in here, we are cleaning up a mess. */ | |
4677 | tonga_hwmgr_backend_fini(hwmgr); | |
4678 | } | |
4679 | ||
4680 | return result; | |
4681 | } | |
4682 | ||
4683 | static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr, | |
4684 | enum amd_dpm_forced_level level) | |
4685 | { | |
4686 | int ret = 0; | |
4687 | ||
4688 | switch (level) { | |
4689 | case AMD_DPM_FORCED_LEVEL_HIGH: | |
4690 | ret = tonga_force_dpm_highest(hwmgr); | |
4691 | if (ret) | |
4692 | return ret; | |
4693 | break; | |
4694 | case AMD_DPM_FORCED_LEVEL_LOW: | |
4695 | ret = tonga_force_dpm_lowest(hwmgr); | |
4696 | if (ret) | |
4697 | return ret; | |
4698 | break; | |
4699 | case AMD_DPM_FORCED_LEVEL_AUTO: | |
4700 | ret = tonga_unforce_dpm_levels(hwmgr); | |
4701 | if (ret) | |
4702 | return ret; | |
4703 | break; | |
4704 | default: | |
4705 | break; | |
4706 | } | |
4707 | ||
4708 | hwmgr->dpm_level = level; | |
4709 | return ret; | |
4710 | } | |
4711 | ||
4712 | static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |
4713 | struct pp_power_state *prequest_ps, | |
4714 | const struct pp_power_state *pcurrent_ps) | |
4715 | { | |
4716 | struct tonga_power_state *tonga_ps = | |
4717 | cast_phw_tonga_power_state(&prequest_ps->hardware); | |
4718 | ||
4719 | uint32_t sclk; | |
4720 | uint32_t mclk; | |
4721 | struct PP_Clocks minimum_clocks = {0}; | |
4722 | bool disable_mclk_switching; | |
4723 | bool disable_mclk_switching_for_frame_lock; | |
4724 | struct cgs_display_info info = {0}; | |
4725 | const struct phm_clock_and_voltage_limits *max_limits; | |
4726 | uint32_t i; | |
4727 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4728 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
4729 | ||
4730 | int32_t count; | |
4731 | int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; | |
4732 | ||
4733 | data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); | |
4734 | ||
4735 | PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2, | |
4736 | "VI should always have 2 performance levels", | |
4737 | ); | |
4738 | ||
4739 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? | |
4740 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : | |
4741 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); | |
4742 | ||
4743 | if (PP_PowerSource_DC == hwmgr->power_source) { | |
4744 | for (i = 0; i < tonga_ps->performance_level_count; i++) { | |
4745 | if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk) | |
4746 | tonga_ps->performance_levels[i].memory_clock = max_limits->mclk; | |
4747 | if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk) | |
4748 | tonga_ps->performance_levels[i].engine_clock = max_limits->sclk; | |
4749 | } | |
4750 | } | |
4751 | ||
4752 | tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk; | |
4753 | tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk; | |
4754 | ||
4755 | tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk; | |
4756 | ||
4757 | cgs_get_active_displays_info(hwmgr->device, &info); | |
4758 | ||
4759 | /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ | |
4760 | ||
4761 | /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ | |
4762 | ||
4763 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { | |
4764 | ||
4765 | max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); | |
4766 | stable_pstate_sclk = (max_limits->sclk * 75) / 100; | |
4767 | ||
4768 | for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { | |
4769 | if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) { | |
4770 | stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk; | |
4771 | break; | |
4772 | } | |
4773 | } | |
4774 | ||
4775 | if (count < 0) | |
4776 | stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk; | |
4777 | ||
4778 | stable_pstate_mclk = max_limits->mclk; | |
4779 | ||
4780 | minimum_clocks.engineClock = stable_pstate_sclk; | |
4781 | minimum_clocks.memoryClock = stable_pstate_mclk; | |
4782 | } | |
4783 | ||
4784 | if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) | |
4785 | minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; | |
4786 | ||
4787 | if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) | |
4788 | minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; | |
4789 | ||
4790 | tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; | |
4791 | ||
4792 | if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { | |
4793 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock), | |
4794 | "Overdrive sclk exceeds limit", | |
4795 | hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock); | |
4796 | ||
4797 | if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) | |
4798 | tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive; | |
4799 | } | |
4800 | ||
4801 | if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { | |
4802 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock), | |
4803 | "Overdrive mclk exceeds limit", | |
4804 | hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock); | |
4805 | ||
4806 | if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) | |
4807 | tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive; | |
4808 | } | |
4809 | ||
4810 | disable_mclk_switching_for_frame_lock = phm_cap_enabled( | |
4811 | hwmgr->platform_descriptor.platformCaps, | |
4812 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); | |
4813 | ||
4814 | disable_mclk_switching = (1 < info.display_count) || | |
4815 | disable_mclk_switching_for_frame_lock; | |
4816 | ||
4817 | sclk = tonga_ps->performance_levels[0].engine_clock; | |
4818 | mclk = tonga_ps->performance_levels[0].memory_clock; | |
4819 | ||
4820 | if (disable_mclk_switching) | |
4821 | mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock; | |
4822 | ||
4823 | if (sclk < minimum_clocks.engineClock) | |
4824 | sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock; | |
4825 | ||
4826 | if (mclk < minimum_clocks.memoryClock) | |
4827 | mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock; | |
4828 | ||
4829 | tonga_ps->performance_levels[0].engine_clock = sclk; | |
4830 | tonga_ps->performance_levels[0].memory_clock = mclk; | |
4831 | ||
4832 | tonga_ps->performance_levels[1].engine_clock = | |
4833 | (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ? | |
4834 | tonga_ps->performance_levels[1].engine_clock : | |
4835 | tonga_ps->performance_levels[0].engine_clock; | |
4836 | ||
4837 | if (disable_mclk_switching) { | |
4838 | if (mclk < tonga_ps->performance_levels[1].memory_clock) | |
4839 | mclk = tonga_ps->performance_levels[1].memory_clock; | |
4840 | ||
4841 | tonga_ps->performance_levels[0].memory_clock = mclk; | |
4842 | tonga_ps->performance_levels[1].memory_clock = mclk; | |
4843 | } else { | |
4844 | if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock) | |
4845 | tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock; | |
4846 | } | |
4847 | ||
4848 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { | |
4849 | for (i=0; i < tonga_ps->performance_level_count; i++) { | |
4850 | tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk; | |
4851 | tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk; | |
4852 | tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; | |
4853 | tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; | |
4854 | } | |
4855 | } | |
4856 | ||
4857 | return 0; | |
4858 | } | |
4859 | ||
4860 | int tonga_get_power_state_size(struct pp_hwmgr *hwmgr) | |
4861 | { | |
4862 | return sizeof(struct tonga_power_state); | |
4863 | } | |
4864 | ||
4865 | static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) | |
4866 | { | |
4867 | struct pp_power_state *ps; | |
4868 | struct tonga_power_state *tonga_ps; | |
4869 | ||
4870 | if (hwmgr == NULL) | |
4871 | return -EINVAL; | |
4872 | ||
4873 | ps = hwmgr->request_ps; | |
4874 | ||
4875 | if (ps == NULL) | |
4876 | return -EINVAL; | |
4877 | ||
4878 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); | |
4879 | ||
4880 | if (low) | |
4881 | return tonga_ps->performance_levels[0].memory_clock; | |
4882 | else | |
4883 | return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; | |
4884 | } | |
4885 | ||
4886 | static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) | |
4887 | { | |
4888 | struct pp_power_state *ps; | |
4889 | struct tonga_power_state *tonga_ps; | |
4890 | ||
4891 | if (hwmgr == NULL) | |
4892 | return -EINVAL; | |
4893 | ||
4894 | ps = hwmgr->request_ps; | |
4895 | ||
4896 | if (ps == NULL) | |
4897 | return -EINVAL; | |
4898 | ||
4899 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); | |
4900 | ||
4901 | if (low) | |
4902 | return tonga_ps->performance_levels[0].engine_clock; | |
4903 | else | |
4904 | return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; | |
4905 | } | |
4906 | ||
4907 | static uint16_t tonga_get_current_pcie_speed( | |
4908 | struct pp_hwmgr *hwmgr) | |
4909 | { | |
4910 | uint32_t speed_cntl = 0; | |
4911 | ||
4912 | speed_cntl = cgs_read_ind_register(hwmgr->device, | |
4913 | CGS_IND_REG__PCIE, | |
4914 | ixPCIE_LC_SPEED_CNTL); | |
4915 | return((uint16_t)PHM_GET_FIELD(speed_cntl, | |
4916 | PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); | |
4917 | } | |
4918 | ||
4919 | static int tonga_get_current_pcie_lane_number( | |
4920 | struct pp_hwmgr *hwmgr) | |
4921 | { | |
4922 | uint32_t link_width; | |
4923 | ||
4924 | link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, | |
4925 | CGS_IND_REG__PCIE, | |
4926 | PCIE_LC_LINK_WIDTH_CNTL, | |
4927 | LC_LINK_WIDTH_RD); | |
4928 | ||
4929 | PP_ASSERT_WITH_CODE((7 >= link_width), | |
4930 | "Invalid PCIe lane width!", return 0); | |
4931 | ||
4932 | return decode_pcie_lane_width(link_width); | |
4933 | } | |
4934 | ||
4935 | static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, | |
4936 | struct pp_hw_power_state *hw_ps) | |
4937 | { | |
4938 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4939 | struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps; | |
4940 | ATOM_FIRMWARE_INFO_V2_2 *fw_info; | |
4941 | uint16_t size; | |
4942 | uint8_t frev, crev; | |
4943 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
4944 | ||
4945 | /* First retrieve the Boot clocks and VDDC from the firmware info table. | |
4946 | * We assume here that fw_info is unchanged if this call fails. | |
4947 | */ | |
4948 | fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( | |
4949 | hwmgr->device, index, | |
4950 | &size, &frev, &crev); | |
4951 | if (!fw_info) | |
4952 | /* During a test, there is no firmware info table. */ | |
4953 | return 0; | |
4954 | ||
4955 | /* Patch the state. */ | |
4956 | data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock); | |
4957 | data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock); | |
4958 | data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage); | |
4959 | data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage); | |
4960 | data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage); | |
4961 | data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr); | |
4962 | data->vbios_boot_state.pcie_lane_bootup_value = | |
4963 | (uint16_t)tonga_get_current_pcie_lane_number(hwmgr); | |
4964 | ||
4965 | /* set boot power state */ | |
4966 | ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; | |
4967 | ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; | |
4968 | ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; | |
4969 | ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; | |
4970 | ||
4971 | return 0; | |
4972 | } | |
4973 | ||
4974 | static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, | |
4975 | void *state, struct pp_power_state *power_state, | |
4976 | void *pp_table, uint32_t classification_flag) | |
4977 | { | |
4978 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
4979 | ||
4980 | struct tonga_power_state *tonga_ps = | |
4981 | (struct tonga_power_state *)(&(power_state->hardware)); | |
4982 | ||
4983 | struct tonga_performance_level *performance_level; | |
4984 | ||
4985 | ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; | |
4986 | ||
4987 | ATOM_Tonga_POWERPLAYTABLE *powerplay_table = | |
4988 | (ATOM_Tonga_POWERPLAYTABLE *)pp_table; | |
4989 | ||
4990 | ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = | |
4991 | (ATOM_Tonga_SCLK_Dependency_Table *) | |
c9fe74e6 | 4992 | (((unsigned long)powerplay_table) + |
c82baa28 | 4993 | le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); |
4994 | ||
4995 | ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = | |
4996 | (ATOM_Tonga_MCLK_Dependency_Table *) | |
c9fe74e6 | 4997 | (((unsigned long)powerplay_table) + |
c82baa28 | 4998 | le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); |
4999 | ||
5000 | /* The following fields are not initialized here: id orderedList allStatesList */ | |
5001 | power_state->classification.ui_label = | |
5002 | (le16_to_cpu(state_entry->usClassification) & | |
5003 | ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> | |
5004 | ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; | |
5005 | power_state->classification.flags = classification_flag; | |
5006 | /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ | |
5007 | ||
5008 | power_state->classification.temporary_state = false; | |
5009 | power_state->classification.to_be_deleted = false; | |
5010 | ||
5011 | power_state->validation.disallowOnDC = | |
5012 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC)); | |
5013 | ||
5014 | power_state->pcie.lanes = 0; | |
5015 | ||
5016 | power_state->display.disableFrameModulation = false; | |
5017 | power_state->display.limitRefreshrate = false; | |
5018 | power_state->display.enableVariBright = | |
5019 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT)); | |
5020 | ||
5021 | power_state->validation.supportedPowerLevels = 0; | |
5022 | power_state->uvd_clocks.VCLK = 0; | |
5023 | power_state->uvd_clocks.DCLK = 0; | |
5024 | power_state->temperatures.min = 0; | |
5025 | power_state->temperatures.max = 0; | |
5026 | ||
5027 | performance_level = &(tonga_ps->performance_levels | |
5028 | [tonga_ps->performance_level_count++]); | |
5029 | ||
5030 | PP_ASSERT_WITH_CODE( | |
5031 | (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS), | |
5032 | "Performance levels exceeds SMC limit!", | |
5033 | return -1); | |
5034 | ||
5035 | PP_ASSERT_WITH_CODE( | |
5036 | (tonga_ps->performance_level_count <= | |
5037 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), | |
5038 | "Performance levels exceeds Driver limit!", | |
5039 | return -1); | |
5040 | ||
5041 | /* Performance levels are arranged from low to high. */ | |
5042 | performance_level->memory_clock = | |
5043 | le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk); | |
5044 | ||
5045 | performance_level->engine_clock = | |
5046 | le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk); | |
5047 | ||
5048 | performance_level->pcie_gen = get_pcie_gen_support( | |
5049 | data->pcie_gen_cap, | |
5050 | state_entry->ucPCIEGenLow); | |
5051 | ||
5052 | performance_level->pcie_lane = get_pcie_lane_support( | |
5053 | data->pcie_lane_cap, | |
5054 | state_entry->ucPCIELaneHigh); | |
5055 | ||
5056 | performance_level = | |
5057 | &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]); | |
5058 | ||
5059 | performance_level->memory_clock = | |
5060 | le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk); | |
5061 | ||
5062 | performance_level->engine_clock = | |
5063 | le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk); | |
5064 | ||
5065 | performance_level->pcie_gen = get_pcie_gen_support( | |
5066 | data->pcie_gen_cap, | |
5067 | state_entry->ucPCIEGenHigh); | |
5068 | ||
5069 | performance_level->pcie_lane = get_pcie_lane_support( | |
5070 | data->pcie_lane_cap, | |
5071 | state_entry->ucPCIELaneHigh); | |
5072 | ||
5073 | return 0; | |
5074 | } | |
5075 | ||
5076 | static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr, | |
5077 | unsigned long entry_index, struct pp_power_state *ps) | |
5078 | { | |
5079 | int result; | |
5080 | struct tonga_power_state *tonga_ps; | |
5081 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5082 | ||
5083 | struct phm_ppt_v1_information *table_info = | |
5084 | (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
5085 | ||
5086 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = | |
5087 | table_info->vdd_dep_on_mclk; | |
5088 | ||
5089 | ps->hardware.magic = PhwTonga_Magic; | |
5090 | ||
5091 | tonga_ps = cast_phw_tonga_power_state(&(ps->hardware)); | |
5092 | ||
5093 | result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps, | |
5094 | tonga_get_pp_table_entry_callback_func); | |
5095 | ||
5096 | /* This is the earliest time we have all the dependency table and the VBIOS boot state | |
5097 | * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state | |
5098 | * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state | |
5099 | */ | |
5100 | if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { | |
5101 | if (dep_mclk_table->entries[0].clk != | |
5102 | data->vbios_boot_state.mclk_bootup_value) | |
5103 | printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " | |
5104 | "does not match VBIOS boot MCLK level"); | |
5105 | if (dep_mclk_table->entries[0].vddci != | |
5106 | data->vbios_boot_state.vddci_bootup_value) | |
5107 | printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " | |
5108 | "does not match VBIOS boot VDDCI level"); | |
5109 | } | |
5110 | ||
5111 | /* set DC compatible flag if this state supports DC */ | |
5112 | if (!ps->validation.disallowOnDC) | |
5113 | tonga_ps->dc_compatible = true; | |
5114 | ||
5115 | if (ps->classification.flags & PP_StateClassificationFlag_ACPI) | |
5116 | data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen; | |
5117 | else if (ps->classification.flags & PP_StateClassificationFlag_Boot) { | |
5118 | if (data->bacos.best_match == 0xffff) { | |
5119 | /* For V.I. use boot state as base BACO state */ | |
5120 | data->bacos.best_match = PP_StateClassificationFlag_Boot; | |
5121 | data->bacos.performance_level = tonga_ps->performance_levels[0]; | |
5122 | } | |
5123 | } | |
5124 | ||
5125 | tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK; | |
5126 | tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK; | |
5127 | ||
5128 | if (!result) { | |
5129 | uint32_t i; | |
5130 | ||
5131 | switch (ps->classification.ui_label) { | |
5132 | case PP_StateUILabel_Performance: | |
5133 | data->use_pcie_performance_levels = true; | |
5134 | ||
5135 | for (i = 0; i < tonga_ps->performance_level_count; i++) { | |
5136 | if (data->pcie_gen_performance.max < | |
5137 | tonga_ps->performance_levels[i].pcie_gen) | |
5138 | data->pcie_gen_performance.max = | |
5139 | tonga_ps->performance_levels[i].pcie_gen; | |
5140 | ||
5141 | if (data->pcie_gen_performance.min > | |
5142 | tonga_ps->performance_levels[i].pcie_gen) | |
5143 | data->pcie_gen_performance.min = | |
5144 | tonga_ps->performance_levels[i].pcie_gen; | |
5145 | ||
5146 | if (data->pcie_lane_performance.max < | |
5147 | tonga_ps->performance_levels[i].pcie_lane) | |
5148 | data->pcie_lane_performance.max = | |
5149 | tonga_ps->performance_levels[i].pcie_lane; | |
5150 | ||
5151 | if (data->pcie_lane_performance.min > | |
5152 | tonga_ps->performance_levels[i].pcie_lane) | |
5153 | data->pcie_lane_performance.min = | |
5154 | tonga_ps->performance_levels[i].pcie_lane; | |
5155 | } | |
5156 | break; | |
5157 | case PP_StateUILabel_Battery: | |
5158 | data->use_pcie_power_saving_levels = true; | |
5159 | ||
5160 | for (i = 0; i < tonga_ps->performance_level_count; i++) { | |
5161 | if (data->pcie_gen_power_saving.max < | |
5162 | tonga_ps->performance_levels[i].pcie_gen) | |
5163 | data->pcie_gen_power_saving.max = | |
5164 | tonga_ps->performance_levels[i].pcie_gen; | |
5165 | ||
5166 | if (data->pcie_gen_power_saving.min > | |
5167 | tonga_ps->performance_levels[i].pcie_gen) | |
5168 | data->pcie_gen_power_saving.min = | |
5169 | tonga_ps->performance_levels[i].pcie_gen; | |
5170 | ||
5171 | if (data->pcie_lane_power_saving.max < | |
5172 | tonga_ps->performance_levels[i].pcie_lane) | |
5173 | data->pcie_lane_power_saving.max = | |
5174 | tonga_ps->performance_levels[i].pcie_lane; | |
5175 | ||
5176 | if (data->pcie_lane_power_saving.min > | |
5177 | tonga_ps->performance_levels[i].pcie_lane) | |
5178 | data->pcie_lane_power_saving.min = | |
5179 | tonga_ps->performance_levels[i].pcie_lane; | |
5180 | } | |
5181 | break; | |
5182 | default: | |
5183 | break; | |
5184 | } | |
5185 | } | |
5186 | return 0; | |
5187 | } | |
5188 | ||
5189 | static void | |
5190 | tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) | |
5191 | { | |
ab4f4b14 | 5192 | uint32_t sclk, mclk, activity_percent; |
9c5f8de6 RZ |
5193 | uint32_t offset; |
5194 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
c82baa28 | 5195 | |
5196 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency)); | |
5197 | ||
5198 | sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
5199 | ||
5200 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency)); | |
5201 | ||
5202 | mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
5203 | seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100); | |
9c5f8de6 | 5204 | |
9c5f8de6 | 5205 | offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity); |
ab4f4b14 RZ |
5206 | activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); |
5207 | activity_percent += 0x80; | |
5208 | activity_percent >>= 8; | |
9c5f8de6 | 5209 | |
ab4f4b14 | 5210 | seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent); |
9c5f8de6 | 5211 | |
d27d4941 RZ |
5212 | seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en"); |
5213 | ||
5214 | seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); | |
c82baa28 | 5215 | } |
5216 | ||
5217 | static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) | |
5218 | { | |
5219 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
5220 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); | |
5221 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5222 | struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table); | |
5223 | uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; | |
5224 | struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table); | |
5225 | uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; | |
5226 | struct PP_Clocks min_clocks = {0}; | |
5227 | uint32_t i; | |
5228 | struct cgs_display_info info = {0}; | |
5229 | ||
5230 | data->need_update_smu7_dpm_table = 0; | |
5231 | ||
5232 | for (i = 0; i < psclk_table->count; i++) { | |
5233 | if (sclk == psclk_table->dpm_levels[i].value) | |
5234 | break; | |
5235 | } | |
5236 | ||
5237 | if (i >= psclk_table->count) | |
5238 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; | |
5239 | else { | |
5240 | /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/ | |
5241 | if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR) | |
5242 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; | |
5243 | } | |
5244 | ||
5245 | for (i=0; i < pmclk_table->count; i++) { | |
5246 | if (mclk == pmclk_table->dpm_levels[i].value) | |
5247 | break; | |
5248 | } | |
5249 | ||
5250 | if (i >= pmclk_table->count) | |
5251 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; | |
5252 | ||
5253 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5254 | ||
5255 | if (data->display_timing.num_existing_displays != info.display_count) | |
5256 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; | |
5257 | ||
5258 | return 0; | |
5259 | } | |
5260 | ||
5261 | static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps) | |
5262 | { | |
5263 | uint32_t i; | |
5264 | uint32_t sclk, max_sclk = 0; | |
5265 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5266 | struct tonga_dpm_table *pdpm_table = &data->dpm_table; | |
5267 | ||
5268 | for (i = 0; i < hw_ps->performance_level_count; i++) { | |
5269 | sclk = hw_ps->performance_levels[i].engine_clock; | |
5270 | if (max_sclk < sclk) | |
5271 | max_sclk = sclk; | |
5272 | } | |
5273 | ||
5274 | for (i = 0; i < pdpm_table->sclk_table.count; i++) { | |
5275 | if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk) | |
5276 | return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ? | |
5277 | pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value : | |
5278 | pdpm_table->pcie_speed_table.dpm_levels[i].value); | |
5279 | } | |
5280 | ||
5281 | return 0; | |
5282 | } | |
5283 | ||
5284 | static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input) | |
5285 | { | |
5286 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
5287 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5288 | const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state); | |
5289 | const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state); | |
5290 | ||
5291 | uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps); | |
5292 | uint16_t current_link_speed; | |
5293 | ||
5294 | if (data->force_pcie_gen == PP_PCIEGenInvalid) | |
5295 | current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps); | |
5296 | else | |
5297 | current_link_speed = data->force_pcie_gen; | |
5298 | ||
5299 | data->force_pcie_gen = PP_PCIEGenInvalid; | |
5300 | data->pspp_notify_required = false; | |
5301 | if (target_link_speed > current_link_speed) { | |
5302 | switch(target_link_speed) { | |
5303 | case PP_PCIEGen3: | |
5304 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) | |
5305 | break; | |
5306 | data->force_pcie_gen = PP_PCIEGen2; | |
5307 | if (current_link_speed == PP_PCIEGen2) | |
5308 | break; | |
5309 | case PP_PCIEGen2: | |
5310 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) | |
5311 | break; | |
5312 | default: | |
5313 | data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr); | |
5314 | break; | |
5315 | } | |
5316 | } else { | |
5317 | if (target_link_speed < current_link_speed) | |
5318 | data->pspp_notify_required = true; | |
5319 | } | |
5320 | ||
5321 | return 0; | |
5322 | } | |
5323 | ||
5324 | static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
5325 | { | |
5326 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5327 | ||
5328 | if (0 == data->need_update_smu7_dpm_table) | |
5329 | return 0; | |
5330 | ||
5331 | if ((0 == data->sclk_dpm_key_disabled) && | |
5332 | (data->need_update_smu7_dpm_table & | |
5333 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { | |
4ba27f9b EC |
5334 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
5335 | "Trying to freeze SCLK DPM when DPM is disabled", | |
c82baa28 | 5336 | ); |
5337 | PP_ASSERT_WITH_CODE( | |
5338 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
5339 | PPSMC_MSG_SCLKDPM_FreezeLevel), | |
5340 | "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", | |
5341 | return -1); | |
5342 | } | |
5343 | ||
5344 | if ((0 == data->mclk_dpm_key_disabled) && | |
5345 | (data->need_update_smu7_dpm_table & | |
5346 | DPMTABLE_OD_UPDATE_MCLK)) { | |
4ba27f9b EC |
5347 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
5348 | "Trying to freeze MCLK DPM when DPM is disabled", | |
c82baa28 | 5349 | ); |
5350 | PP_ASSERT_WITH_CODE( | |
5351 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
5352 | PPSMC_MSG_MCLKDPM_FreezeLevel), | |
5353 | "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", | |
5354 | return -1); | |
5355 | } | |
5356 | ||
5357 | return 0; | |
5358 | } | |
5359 | ||
5360 | static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input) | |
5361 | { | |
5362 | int result = 0; | |
5363 | ||
5364 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
5365 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); | |
5366 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5367 | uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; | |
5368 | uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; | |
5369 | struct tonga_dpm_table *pdpm_table = &data->dpm_table; | |
5370 | ||
5371 | struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table; | |
5372 | uint32_t dpm_count, clock_percent; | |
5373 | uint32_t i; | |
5374 | ||
5375 | if (0 == data->need_update_smu7_dpm_table) | |
5376 | return 0; | |
5377 | ||
5378 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { | |
5379 | pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk; | |
5380 | ||
5381 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || | |
5382 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { | |
5383 | /* Need to do calculation based on the golden DPM table | |
5384 | * as the Heatmap GPU Clock axis is also based on the default values | |
5385 | */ | |
5386 | PP_ASSERT_WITH_CODE( | |
5387 | (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0), | |
5388 | "Divide by 0!", | |
5389 | return -1); | |
5390 | dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2; | |
5391 | for (i = dpm_count; i > 1; i--) { | |
5392 | if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) { | |
5393 | clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) / | |
5394 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; | |
5395 | ||
5396 | pdpm_table->sclk_table.dpm_levels[i].value = | |
5397 | pgolden_dpm_table->sclk_table.dpm_levels[i].value + | |
5398 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; | |
5399 | ||
5400 | } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) { | |
5401 | clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) / | |
5402 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; | |
5403 | ||
5404 | pdpm_table->sclk_table.dpm_levels[i].value = | |
5405 | pgolden_dpm_table->sclk_table.dpm_levels[i].value - | |
5406 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; | |
5407 | } else | |
5408 | pdpm_table->sclk_table.dpm_levels[i].value = | |
5409 | pgolden_dpm_table->sclk_table.dpm_levels[i].value; | |
5410 | } | |
5411 | } | |
5412 | } | |
5413 | ||
5414 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { | |
5415 | pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk; | |
5416 | ||
5417 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || | |
5418 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { | |
5419 | ||
5420 | PP_ASSERT_WITH_CODE( | |
5421 | (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0), | |
5422 | "Divide by 0!", | |
5423 | return -1); | |
5424 | dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2; | |
5425 | for (i = dpm_count; i > 1; i--) { | |
5426 | if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) { | |
5427 | clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) / | |
5428 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; | |
5429 | ||
5430 | pdpm_table->mclk_table.dpm_levels[i].value = | |
5431 | pgolden_dpm_table->mclk_table.dpm_levels[i].value + | |
5432 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; | |
5433 | ||
5434 | } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) { | |
5435 | clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) / | |
5436 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; | |
5437 | ||
5438 | pdpm_table->mclk_table.dpm_levels[i].value = | |
5439 | pgolden_dpm_table->mclk_table.dpm_levels[i].value - | |
5440 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; | |
5441 | } else | |
5442 | pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value; | |
5443 | } | |
5444 | } | |
5445 | } | |
5446 | ||
5447 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { | |
e2ed8a13 | 5448 | result = tonga_populate_all_graphic_levels(hwmgr); |
c82baa28 | 5449 | PP_ASSERT_WITH_CODE((0 == result), |
5450 | "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", | |
5451 | return result); | |
5452 | } | |
5453 | ||
5454 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { | |
5455 | /*populate MCLK dpm table to SMU7 */ | |
5456 | result = tonga_populate_all_memory_levels(hwmgr); | |
5457 | PP_ASSERT_WITH_CODE((0 == result), | |
5458 | "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", | |
5459 | return result); | |
5460 | } | |
5461 | ||
5462 | return result; | |
5463 | } | |
5464 | ||
5465 | static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr, | |
5466 | struct tonga_single_dpm_table * pdpm_table, | |
5467 | uint32_t low_limit, uint32_t high_limit) | |
5468 | { | |
5469 | uint32_t i; | |
5470 | ||
5471 | for (i = 0; i < pdpm_table->count; i++) { | |
5472 | if ((pdpm_table->dpm_levels[i].value < low_limit) || | |
5473 | (pdpm_table->dpm_levels[i].value > high_limit)) | |
5474 | pdpm_table->dpm_levels[i].enabled = false; | |
5475 | else | |
5476 | pdpm_table->dpm_levels[i].enabled = true; | |
5477 | } | |
5478 | return 0; | |
5479 | } | |
5480 | ||
5481 | static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state) | |
5482 | { | |
c82baa28 | 5483 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
5484 | uint32_t high_limit_count; | |
5485 | ||
5486 | PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1), | |
5487 | "power state did not have any performance level", | |
5488 | return -1); | |
5489 | ||
5490 | high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1; | |
5491 | ||
5492 | tonga_trim_single_dpm_states(hwmgr, | |
5493 | &(data->dpm_table.sclk_table), | |
5494 | hw_state->performance_levels[0].engine_clock, | |
5495 | hw_state->performance_levels[high_limit_count].engine_clock); | |
5496 | ||
5497 | tonga_trim_single_dpm_states(hwmgr, | |
5498 | &(data->dpm_table.mclk_table), | |
5499 | hw_state->performance_levels[0].memory_clock, | |
5500 | hw_state->performance_levels[high_limit_count].memory_clock); | |
5501 | ||
538f1ef3 | 5502 | return 0; |
c82baa28 | 5503 | } |
5504 | ||
5505 | static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input) | |
5506 | { | |
5507 | int result; | |
5508 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
5509 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5510 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); | |
5511 | ||
c82baa28 | 5512 | result = tonga_trim_dpm_states(hwmgr, tonga_ps); |
5513 | if (0 != result) | |
5514 | return result; | |
5515 | ||
5516 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); | |
5517 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); | |
5518 | data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask; | |
5519 | if (data->uvd_enabled) | |
5520 | data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; | |
5521 | ||
5522 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); | |
5523 | ||
5524 | return 0; | |
5525 | } | |
5526 | ||
0859ed3d | 5527 | int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) |
c82baa28 | 5528 | { |
0859ed3d | 5529 | return smum_send_msg_to_smc(hwmgr->smumgr, enable ? |
c82baa28 | 5530 | (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable : |
5531 | (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable); | |
5532 | } | |
5533 | ||
0859ed3d RZ |
5534 | int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) |
5535 | { | |
5536 | return smum_send_msg_to_smc(hwmgr->smumgr, enable ? | |
5537 | (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable : | |
5538 | (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable); | |
5539 | } | |
5540 | ||
5541 | int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) | |
5542 | { | |
5543 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5544 | uint32_t mm_boot_level_offset, mm_boot_level_value; | |
5545 | struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
5546 | ||
5547 | if (!bgate) { | |
5548 | data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1); | |
5549 | mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); | |
5550 | mm_boot_level_offset /= 4; | |
5551 | mm_boot_level_offset *= 4; | |
5552 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset); | |
5553 | mm_boot_level_value &= 0x00FFFFFF; | |
5554 | mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24; | |
5555 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); | |
5556 | ||
5557 | if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) || | |
5558 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) | |
5559 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
5560 | PPSMC_MSG_UVDDPM_SetEnabledMask, | |
5561 | (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); | |
5562 | } | |
5563 | ||
5564 | return tonga_enable_disable_uvd_dpm(hwmgr, !bgate); | |
5565 | } | |
5566 | ||
5567 | int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) | |
c82baa28 | 5568 | { |
5569 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
5570 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5571 | const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state); | |
5572 | const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state); | |
5573 | ||
5574 | uint32_t mm_boot_level_offset, mm_boot_level_value; | |
5575 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | |
5576 | ||
0859ed3d | 5577 | if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) { |
c82baa28 | 5578 | data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1); |
5579 | ||
5580 | mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel); | |
5581 | mm_boot_level_offset /= 4; | |
5582 | mm_boot_level_offset *= 4; | |
5583 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset); | |
5584 | mm_boot_level_value &= 0xFF00FFFF; | |
5585 | mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; | |
5586 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); | |
5587 | ||
0859ed3d RZ |
5588 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) |
5589 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
5590 | PPSMC_MSG_VCEDPM_SetEnabledMask, | |
5591 | (uint32_t)(1 << data->smc_state_table.VceBootLevel)); | |
c82baa28 | 5592 | |
0859ed3d RZ |
5593 | tonga_enable_disable_vce_dpm(hwmgr, true); |
5594 | } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0) | |
5595 | tonga_enable_disable_vce_dpm(hwmgr, false); | |
c82baa28 | 5596 | |
5597 | return 0; | |
5598 | } | |
5599 | ||
5600 | static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) | |
5601 | { | |
5602 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5603 | ||
5604 | uint32_t address; | |
5605 | int32_t result; | |
5606 | ||
5607 | if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) | |
5608 | return 0; | |
5609 | ||
5610 | ||
5611 | memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters)); | |
5612 | ||
5613 | result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table)); | |
5614 | ||
5615 | if(result != 0) | |
5616 | return result; | |
5617 | ||
5618 | ||
5619 | address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); | |
5620 | ||
5621 | return tonga_copy_bytes_to_smc(hwmgr->smumgr, address, | |
5622 | (uint8_t *)&data->mc_reg_table.data[0], | |
5623 | sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, | |
5624 | data->sram_end); | |
5625 | } | |
5626 | ||
5627 | static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr) | |
5628 | { | |
5629 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5630 | ||
5631 | if (data->need_update_smu7_dpm_table & | |
5632 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) | |
5633 | return tonga_program_memory_timing_parameters(hwmgr); | |
5634 | ||
5635 | return 0; | |
5636 | } | |
5637 | ||
5638 | static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) | |
5639 | { | |
5640 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5641 | ||
5642 | if (0 == data->need_update_smu7_dpm_table) | |
5643 | return 0; | |
5644 | ||
5645 | if ((0 == data->sclk_dpm_key_disabled) && | |
5646 | (data->need_update_smu7_dpm_table & | |
5647 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { | |
5648 | ||
4ba27f9b EC |
5649 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
5650 | "Trying to Unfreeze SCLK DPM when DPM is disabled", | |
c82baa28 | 5651 | ); |
5652 | PP_ASSERT_WITH_CODE( | |
5653 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
5654 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), | |
5655 | "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", | |
5656 | return -1); | |
5657 | } | |
5658 | ||
5659 | if ((0 == data->mclk_dpm_key_disabled) && | |
5660 | (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { | |
5661 | ||
4ba27f9b EC |
5662 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
5663 | "Trying to Unfreeze MCLK DPM when DPM is disabled", | |
c82baa28 | 5664 | ); |
5665 | PP_ASSERT_WITH_CODE( | |
5666 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, | |
5667 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), | |
5668 | "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", | |
5669 | return -1); | |
5670 | } | |
5671 | ||
5672 | data->need_update_smu7_dpm_table = 0; | |
5673 | ||
5674 | return 0; | |
5675 | } | |
5676 | ||
5677 | static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input) | |
5678 | { | |
5679 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; | |
5680 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5681 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); | |
5682 | uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps); | |
5683 | uint8_t request; | |
5684 | ||
5685 | if (data->pspp_notify_required || | |
5686 | data->pcie_performance_request) { | |
5687 | if (target_link_speed == PP_PCIEGen3) | |
5688 | request = PCIE_PERF_REQ_GEN3; | |
5689 | else if (target_link_speed == PP_PCIEGen2) | |
5690 | request = PCIE_PERF_REQ_GEN2; | |
5691 | else | |
5692 | request = PCIE_PERF_REQ_GEN1; | |
5693 | ||
5694 | if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) { | |
5695 | data->pcie_performance_request = false; | |
5696 | return 0; | |
5697 | } | |
5698 | ||
5699 | if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) { | |
5700 | if (PP_PCIEGen2 == target_link_speed) | |
5701 | printk("PSPP request to switch to Gen2 from Gen3 Failed!"); | |
5702 | else | |
5703 | printk("PSPP request to switch to Gen1 from Gen2 Failed!"); | |
5704 | } | |
5705 | } | |
5706 | ||
5707 | data->pcie_performance_request = false; | |
5708 | return 0; | |
5709 | } | |
5710 | ||
5711 | static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) | |
5712 | { | |
5713 | int tmp_result, result = 0; | |
5714 | ||
5715 | tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input); | |
5716 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result); | |
5717 | ||
5718 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { | |
5719 | tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input); | |
5720 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result); | |
5721 | } | |
5722 | ||
5723 | tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr); | |
5724 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result); | |
5725 | ||
5726 | tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); | |
5727 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result); | |
5728 | ||
5729 | tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input); | |
5730 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result); | |
5731 | ||
5732 | tmp_result = tonga_update_vce_dpm(hwmgr, input); | |
5733 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result); | |
5734 | ||
5735 | tmp_result = tonga_update_sclk_threshold(hwmgr); | |
5736 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result); | |
5737 | ||
5738 | tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr); | |
5739 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result); | |
5740 | ||
5741 | tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr); | |
5742 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result); | |
5743 | ||
5744 | tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr); | |
5745 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result); | |
5746 | ||
5747 | tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr); | |
5748 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result); | |
5749 | ||
5750 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { | |
5751 | tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input); | |
5752 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result); | |
5753 | } | |
5754 | ||
5755 | return result; | |
5756 | } | |
5757 | ||
1e4854e9 RZ |
5758 | /** |
5759 | * Set maximum target operating fan output PWM | |
5760 | * | |
5761 | * @param pHwMgr: the address of the powerplay hardware manager. | |
5762 | * @param usMaxFanPwm: max operating fan PWM in percents | |
5763 | * @return The response that came from the SMC. | |
5764 | */ | |
5765 | static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) | |
5766 | { | |
5767 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; | |
5768 | ||
5769 | if (phm_is_hw_access_blocked(hwmgr)) | |
5770 | return 0; | |
5771 | ||
c15c8d70 | 5772 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1); |
1e4854e9 | 5773 | } |
bbb207f3 RZ |
5774 | |
5775 | int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) | |
5776 | { | |
5777 | uint32_t num_active_displays = 0; | |
5778 | struct cgs_display_info info = {0}; | |
5779 | info.mode_info = NULL; | |
5780 | ||
5781 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5782 | ||
5783 | num_active_displays = info.display_count; | |
5784 | ||
5785 | if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ | |
5786 | tonga_notify_smc_display_change(hwmgr, false); | |
5787 | else | |
5788 | tonga_notify_smc_display_change(hwmgr, true); | |
5789 | ||
5790 | return 0; | |
5791 | } | |
5792 | ||
5793 | /** | |
5794 | * Programs the display gap | |
5795 | * | |
5796 | * @param hwmgr the address of the powerplay hardware manager. | |
5797 | * @return always OK | |
5798 | */ | |
5799 | int tonga_program_display_gap(struct pp_hwmgr *hwmgr) | |
5800 | { | |
5801 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5802 | uint32_t num_active_displays = 0; | |
5803 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); | |
5804 | uint32_t display_gap2; | |
5805 | uint32_t pre_vbi_time_in_us; | |
5806 | uint32_t frame_time_in_us; | |
5807 | uint32_t ref_clock; | |
5808 | uint32_t refresh_rate = 0; | |
5809 | struct cgs_display_info info = {0}; | |
5810 | struct cgs_mode_info mode_info; | |
5811 | ||
5812 | info.mode_info = &mode_info; | |
5813 | ||
5814 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5815 | num_active_displays = info.display_count; | |
5816 | ||
5817 | display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); | |
5818 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); | |
5819 | ||
5820 | ref_clock = mode_info.ref_clock; | |
5821 | refresh_rate = mode_info.refresh_rate; | |
5822 | ||
5823 | if(0 == refresh_rate) | |
5824 | refresh_rate = 60; | |
5825 | ||
5826 | frame_time_in_us = 1000000 / refresh_rate; | |
5827 | ||
5828 | pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; | |
5829 | display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); | |
5830 | ||
5831 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); | |
5832 | ||
5833 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64); | |
5834 | ||
5835 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); | |
5836 | ||
5837 | if (num_active_displays == 1) | |
5838 | tonga_notify_smc_display_change(hwmgr, true); | |
5839 | ||
5840 | return 0; | |
5841 | } | |
5842 | ||
5843 | int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr) | |
5844 | { | |
5845 | ||
5846 | tonga_program_display_gap(hwmgr); | |
5847 | ||
5848 | /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */ | |
5849 | return 0; | |
5850 | } | |
5851 | ||
1e4854e9 RZ |
5852 | /** |
5853 | * Set maximum target operating fan output RPM | |
5854 | * | |
5855 | * @param pHwMgr: the address of the powerplay hardware manager. | |
5856 | * @param usMaxFanRpm: max operating fan RPM value. | |
5857 | * @return The response that came from the SMC. | |
5858 | */ | |
5859 | static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) | |
5860 | { | |
5861 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm; | |
5862 | ||
5863 | if (phm_is_hw_access_blocked(hwmgr)) | |
5864 | return 0; | |
5865 | ||
c15c8d70 | 5866 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1); |
1e4854e9 RZ |
5867 | } |
5868 | ||
5869 | uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr) | |
5870 | { | |
5871 | uint32_t reference_clock; | |
5872 | uint32_t tc; | |
5873 | uint32_t divide; | |
5874 | ||
5875 | ATOM_FIRMWARE_INFO *fw_info; | |
5876 | uint16_t size; | |
5877 | uint8_t frev, crev; | |
5878 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
5879 | ||
5880 | tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); | |
5881 | ||
5882 | if (tc) | |
5883 | return TCLK; | |
5884 | ||
5885 | fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index, | |
5886 | &size, &frev, &crev); | |
5887 | ||
5888 | if (!fw_info) | |
5889 | return 0; | |
5890 | ||
dcf799e5 | 5891 | reference_clock = le16_to_cpu(fw_info->usReferenceClock); |
1e4854e9 RZ |
5892 | |
5893 | divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); | |
5894 | ||
5895 | if (0 != divide) | |
5896 | return reference_clock / 4; | |
5897 | ||
5898 | return reference_clock; | |
5899 | } | |
5900 | ||
5901 | int tonga_dpm_set_interrupt_state(void *private_data, | |
5902 | unsigned src_id, unsigned type, | |
5903 | int enabled) | |
5904 | { | |
5905 | uint32_t cg_thermal_int; | |
5906 | struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr; | |
5907 | ||
5908 | if (hwmgr == NULL) | |
5909 | return -EINVAL; | |
5910 | ||
5911 | switch (type) { | |
5912 | case AMD_THERMAL_IRQ_LOW_TO_HIGH: | |
5913 | if (enabled) { | |
5914 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5915 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; | |
5916 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5917 | } else { | |
5918 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5919 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; | |
5920 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5921 | } | |
5922 | break; | |
5923 | ||
5924 | case AMD_THERMAL_IRQ_HIGH_TO_LOW: | |
5925 | if (enabled) { | |
5926 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5927 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; | |
5928 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5929 | } else { | |
5930 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); | |
5931 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; | |
5932 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); | |
5933 | } | |
5934 | break; | |
5935 | default: | |
5936 | break; | |
5937 | } | |
5938 | return 0; | |
5939 | } | |
5940 | ||
5941 | int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, | |
5942 | const void *thermal_interrupt_info) | |
5943 | { | |
5944 | int result; | |
5945 | const struct pp_interrupt_registration_info *info = | |
5946 | (const struct pp_interrupt_registration_info *)thermal_interrupt_info; | |
5947 | ||
5948 | if (info == NULL) | |
5949 | return -EINVAL; | |
5950 | ||
5951 | result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST, | |
5952 | tonga_dpm_set_interrupt_state, | |
5953 | info->call_back, info->context); | |
5954 | ||
5955 | if (result) | |
5956 | return -EINVAL; | |
5957 | ||
5958 | result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST, | |
5959 | tonga_dpm_set_interrupt_state, | |
5960 | info->call_back, info->context); | |
5961 | ||
5962 | if (result) | |
5963 | return -EINVAL; | |
5964 | ||
5965 | return 0; | |
5966 | } | |
5967 | ||
e829ecdb RZ |
5968 | bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) |
5969 | { | |
5970 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
5971 | bool is_update_required = false; | |
5972 | struct cgs_display_info info = {0,0,NULL}; | |
5973 | ||
5974 | cgs_get_active_displays_info(hwmgr->device, &info); | |
5975 | ||
5976 | if (data->display_timing.num_existing_displays != info.display_count) | |
5977 | is_update_required = true; | |
5978 | /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL | |
5979 | if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { | |
5980 | cgs_get_min_clock_settings(hwmgr->device, &min_clocks); | |
5981 | if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) | |
5982 | is_update_required = true; | |
5983 | */ | |
5984 | return is_update_required; | |
5985 | } | |
5986 | ||
5987 | static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1, | |
5988 | const struct tonga_performance_level *pl2) | |
5989 | { | |
5990 | return ((pl1->memory_clock == pl2->memory_clock) && | |
5991 | (pl1->engine_clock == pl2->engine_clock) && | |
5992 | (pl1->pcie_gen == pl2->pcie_gen) && | |
5993 | (pl1->pcie_lane == pl2->pcie_lane)); | |
5994 | } | |
5995 | ||
5996 | int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) | |
5997 | { | |
5998 | const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1); | |
5999 | const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2); | |
6000 | int i; | |
6001 | ||
c15c8d70 | 6002 | if (equal == NULL || psa == NULL || psb == NULL) |
e829ecdb RZ |
6003 | return -EINVAL; |
6004 | ||
6005 | /* If the two states don't even have the same number of performance levels they cannot be the same state. */ | |
6006 | if (psa->performance_level_count != psb->performance_level_count) { | |
6007 | *equal = false; | |
6008 | return 0; | |
6009 | } | |
6010 | ||
6011 | for (i = 0; i < psa->performance_level_count; i++) { | |
6012 | if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { | |
6013 | /* If we have found even one performance level pair that is different the states are different. */ | |
6014 | *equal = false; | |
6015 | return 0; | |
6016 | } | |
6017 | } | |
6018 | ||
6019 | /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ | |
6020 | *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK)); | |
6021 | *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK)); | |
6022 | *equal &= (psa->sclk_threshold == psb->sclk_threshold); | |
6023 | *equal &= (psa->acp_clk == psb->acp_clk); | |
6024 | ||
6025 | return 0; | |
6026 | } | |
6027 | ||
9dcfc193 EH |
6028 | static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) |
6029 | { | |
6030 | if (mode) { | |
6031 | /* stop auto-manage */ | |
6032 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
6033 | PHM_PlatformCaps_MicrocodeFanControl)) | |
6034 | tonga_fan_ctrl_stop_smc_fan_control(hwmgr); | |
6035 | tonga_fan_ctrl_set_static_mode(hwmgr, mode); | |
6036 | } else | |
6037 | /* restart auto-manage */ | |
6038 | tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr); | |
6039 | ||
6040 | return 0; | |
6041 | } | |
6042 | ||
6043 | static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr) | |
6044 | { | |
6045 | if (hwmgr->fan_ctrl_is_in_default_mode) | |
6046 | return hwmgr->fan_ctrl_default_mode; | |
6047 | else | |
6048 | return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, | |
6049 | CG_FDO_CTRL2, FDO_PWM_MODE); | |
6050 | } | |
6051 | ||
5d37a63d | 6052 | static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, |
5632708f | 6053 | enum pp_clock_type type, uint32_t mask) |
5d37a63d EH |
6054 | { |
6055 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
6056 | ||
6057 | if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) | |
6058 | return -EINVAL; | |
6059 | ||
6060 | switch (type) { | |
6061 | case PP_SCLK: | |
6062 | if (!data->sclk_dpm_key_disabled) | |
6063 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
6064 | PPSMC_MSG_SCLKDPM_SetEnabledMask, | |
5632708f | 6065 | data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); |
5d37a63d EH |
6066 | break; |
6067 | case PP_MCLK: | |
6068 | if (!data->mclk_dpm_key_disabled) | |
6069 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
6070 | PPSMC_MSG_MCLKDPM_SetEnabledMask, | |
5632708f | 6071 | data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); |
5d37a63d EH |
6072 | break; |
6073 | case PP_PCIE: | |
5632708f EH |
6074 | { |
6075 | uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; | |
6076 | uint32_t level = 0; | |
6077 | ||
6078 | while (tmp >>= 1) | |
6079 | level++; | |
6080 | ||
5d37a63d EH |
6081 | if (!data->pcie_dpm_key_disabled) |
6082 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, | |
6083 | PPSMC_MSG_PCIeDPM_ForceLevel, | |
5632708f | 6084 | level); |
5d37a63d | 6085 | break; |
5632708f | 6086 | } |
5d37a63d EH |
6087 | default: |
6088 | break; | |
6089 | } | |
6090 | ||
6091 | return 0; | |
6092 | } | |
6093 | ||
6094 | static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr, | |
6095 | enum pp_clock_type type, char *buf) | |
6096 | { | |
6097 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
6098 | struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); | |
6099 | struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); | |
6100 | struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); | |
6101 | int i, now, size = 0; | |
6102 | uint32_t clock, pcie_speed; | |
6103 | ||
6104 | switch (type) { | |
6105 | case PP_SCLK: | |
6106 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); | |
6107 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
6108 | ||
6109 | for (i = 0; i < sclk_table->count; i++) { | |
6110 | if (clock > sclk_table->dpm_levels[i].value) | |
6111 | continue; | |
6112 | break; | |
6113 | } | |
6114 | now = i; | |
6115 | ||
6116 | for (i = 0; i < sclk_table->count; i++) | |
6117 | size += sprintf(buf + size, "%d: %uMhz %s\n", | |
6118 | i, sclk_table->dpm_levels[i].value / 100, | |
6119 | (i == now) ? "*" : ""); | |
6120 | break; | |
6121 | case PP_MCLK: | |
6122 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); | |
6123 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); | |
6124 | ||
6125 | for (i = 0; i < mclk_table->count; i++) { | |
6126 | if (clock > mclk_table->dpm_levels[i].value) | |
6127 | continue; | |
6128 | break; | |
6129 | } | |
6130 | now = i; | |
6131 | ||
6132 | for (i = 0; i < mclk_table->count; i++) | |
6133 | size += sprintf(buf + size, "%d: %uMhz %s\n", | |
6134 | i, mclk_table->dpm_levels[i].value / 100, | |
6135 | (i == now) ? "*" : ""); | |
6136 | break; | |
6137 | case PP_PCIE: | |
6138 | pcie_speed = tonga_get_current_pcie_speed(hwmgr); | |
6139 | for (i = 0; i < pcie_table->count; i++) { | |
6140 | if (pcie_speed != pcie_table->dpm_levels[i].value) | |
6141 | continue; | |
6142 | break; | |
6143 | } | |
6144 | now = i; | |
6145 | ||
6146 | for (i = 0; i < pcie_table->count; i++) | |
6147 | size += sprintf(buf + size, "%d: %s %s\n", i, | |
6148 | (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : | |
6149 | (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : | |
6150 | (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", | |
6151 | (i == now) ? "*" : ""); | |
6152 | break; | |
6153 | default: | |
6154 | break; | |
6155 | } | |
6156 | return size; | |
6157 | } | |
6158 | ||
9ccd4e13 EH |
6159 | static int tonga_get_sclk_od(struct pp_hwmgr *hwmgr) |
6160 | { | |
6161 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
6162 | struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); | |
6163 | struct tonga_single_dpm_table *golden_sclk_table = | |
6164 | &(data->golden_dpm_table.sclk_table); | |
6165 | int value; | |
6166 | ||
6167 | value = (sclk_table->dpm_levels[sclk_table->count - 1].value - | |
6168 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * | |
6169 | 100 / | |
6170 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; | |
6171 | ||
6172 | return value; | |
6173 | } | |
6174 | ||
6175 | static int tonga_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) | |
6176 | { | |
6177 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
6178 | struct tonga_single_dpm_table *golden_sclk_table = | |
6179 | &(data->golden_dpm_table.sclk_table); | |
6180 | struct pp_power_state *ps; | |
6181 | struct tonga_power_state *tonga_ps; | |
6182 | ||
6183 | if (value > 20) | |
6184 | value = 20; | |
6185 | ||
6186 | ps = hwmgr->request_ps; | |
6187 | ||
6188 | if (ps == NULL) | |
6189 | return -EINVAL; | |
6190 | ||
6191 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); | |
6192 | ||
6193 | tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].engine_clock = | |
6194 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * | |
6195 | value / 100 + | |
6196 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; | |
6197 | ||
6198 | return 0; | |
6199 | } | |
6200 | ||
f715d5b3 EH |
6201 | static int tonga_get_mclk_od(struct pp_hwmgr *hwmgr) |
6202 | { | |
6203 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
6204 | struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); | |
6205 | struct tonga_single_dpm_table *golden_mclk_table = | |
6206 | &(data->golden_dpm_table.mclk_table); | |
6207 | int value; | |
6208 | ||
6209 | value = (mclk_table->dpm_levels[mclk_table->count - 1].value - | |
6210 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * | |
6211 | 100 / | |
6212 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; | |
6213 | ||
6214 | return value; | |
6215 | } | |
6216 | ||
6217 | static int tonga_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) | |
6218 | { | |
6219 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | |
6220 | struct tonga_single_dpm_table *golden_mclk_table = | |
6221 | &(data->golden_dpm_table.mclk_table); | |
6222 | struct pp_power_state *ps; | |
6223 | struct tonga_power_state *tonga_ps; | |
6224 | ||
6225 | if (value > 20) | |
6226 | value = 20; | |
6227 | ||
6228 | ps = hwmgr->request_ps; | |
6229 | ||
6230 | if (ps == NULL) | |
6231 | return -EINVAL; | |
6232 | ||
6233 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); | |
6234 | ||
6235 | tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock = | |
6236 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * | |
6237 | value / 100 + | |
6238 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; | |
6239 | ||
6240 | return 0; | |
6241 | } | |
6242 | ||
c82baa28 | 6243 | static const struct pp_hwmgr_func tonga_hwmgr_funcs = { |
6244 | .backend_init = &tonga_hwmgr_backend_init, | |
6245 | .backend_fini = &tonga_hwmgr_backend_fini, | |
6246 | .asic_setup = &tonga_setup_asic_task, | |
6247 | .dynamic_state_management_enable = &tonga_enable_dpm_tasks, | |
57461af7 | 6248 | .dynamic_state_management_disable = &tonga_disable_dpm_tasks, |
c82baa28 | 6249 | .apply_state_adjust_rules = tonga_apply_state_adjust_rules, |
6250 | .force_dpm_level = &tonga_force_dpm_level, | |
6251 | .power_state_set = tonga_set_power_state_tasks, | |
6252 | .get_power_state_size = tonga_get_power_state_size, | |
6253 | .get_mclk = tonga_dpm_get_mclk, | |
6254 | .get_sclk = tonga_dpm_get_sclk, | |
6255 | .patch_boot_state = tonga_dpm_patch_boot_state, | |
6256 | .get_pp_table_entry = tonga_get_pp_table_entry, | |
6257 | .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, | |
6258 | .print_current_perforce_level = tonga_print_current_perforce_level, | |
0859ed3d RZ |
6259 | .powerdown_uvd = tonga_phm_powerdown_uvd, |
6260 | .powergate_uvd = tonga_phm_powergate_uvd, | |
6261 | .powergate_vce = tonga_phm_powergate_vce, | |
6262 | .disable_clock_power_gating = tonga_phm_disable_clock_power_gating, | |
ce90dbd9 | 6263 | .update_clock_gatings = tonga_phm_update_clock_gatings, |
bbb207f3 RZ |
6264 | .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment, |
6265 | .display_config_changed = tonga_display_configuration_changed_task, | |
1e4854e9 RZ |
6266 | .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output, |
6267 | .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output, | |
6268 | .get_temperature = tonga_thermal_get_temperature, | |
6269 | .stop_thermal_controller = tonga_thermal_stop_thermal_controller, | |
6270 | .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info, | |
6271 | .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent, | |
6272 | .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent, | |
6273 | .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default, | |
6274 | .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm, | |
6275 | .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm, | |
6276 | .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller, | |
6277 | .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt, | |
e829ecdb RZ |
6278 | .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration, |
6279 | .check_states_equal = tonga_check_states_equal, | |
9dcfc193 EH |
6280 | .set_fan_control_mode = tonga_set_fan_control_mode, |
6281 | .get_fan_control_mode = tonga_get_fan_control_mode, | |
5d37a63d EH |
6282 | .force_clock_level = tonga_force_clock_level, |
6283 | .print_clock_levels = tonga_print_clock_levels, | |
9ccd4e13 EH |
6284 | .get_sclk_od = tonga_get_sclk_od, |
6285 | .set_sclk_od = tonga_set_sclk_od, | |
f715d5b3 EH |
6286 | .get_mclk_od = tonga_get_mclk_od, |
6287 | .set_mclk_od = tonga_set_mclk_od, | |
c82baa28 | 6288 | }; |
6289 | ||
6290 | int tonga_hwmgr_init(struct pp_hwmgr *hwmgr) | |
6291 | { | |
c82baa28 | 6292 | hwmgr->hwmgr_func = &tonga_hwmgr_funcs; |
6293 | hwmgr->pptable_func = &tonga_pptable_funcs; | |
1e4854e9 | 6294 | pp_tonga_thermal_initialize(hwmgr); |
c82baa28 | 6295 | return 0; |
6296 | } | |
6297 |