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drm/amd/powerplay: refine the logic of whether need to update power state.
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / tonga_hwmgr.c
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c82baa28 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include "linux/delay.h"
27#include "pp_acpi.h"
28#include "hwmgr.h"
29#include <atombios.h>
30#include "tonga_hwmgr.h"
31#include "pptable.h"
32#include "processpptables.h"
33#include "tonga_processpptables.h"
34#include "tonga_pptable.h"
35#include "pp_debug.h"
36#include "tonga_ppsmc.h"
37#include "cgs_common.h"
38#include "pppcielanes.h"
39#include "tonga_dyn_defaults.h"
40#include "smumgr.h"
41#include "tonga_smumgr.h"
0859ed3d 42#include "tonga_clockpowergating.h"
1e4854e9 43#include "tonga_thermal.h"
c82baa28 44
45#include "smu/smu_7_1_2_d.h"
46#include "smu/smu_7_1_2_sh_mask.h"
47
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50
51#include "bif/bif_5_0_d.h"
52#include "bif/bif_5_0_sh_mask.h"
53
1e4854e9
RZ		 54#include "cgs_linux.h"
55#include "eventmgr.h"
56
c82baa28 57#define MC_CG_ARB_FREQ_F0 0x0a
58#define MC_CG_ARB_FREQ_F1 0x0b
59#define MC_CG_ARB_FREQ_F2 0x0c
60#define MC_CG_ARB_FREQ_F3 0x0d
61
62#define MC_CG_SEQ_DRAMCONF_S0 0x05
63#define MC_CG_SEQ_DRAMCONF_S1 0x06
64#define MC_CG_SEQ_YCLK_SUSPEND 0x04
65#define MC_CG_SEQ_YCLK_RESUME 0x0a
66
67#define PCIE_BUS_CLK 10000
68#define TCLK (PCIE_BUS_CLK / 10)
69
70#define SMC_RAM_END 0x40000
71#define SMC_CG_IND_START 0xc0030000
72#define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
73
74#define VOLTAGE_SCALE 4
75#define VOLTAGE_VID_OFFSET_SCALE1 625
76#define VOLTAGE_VID_OFFSET_SCALE2 100
77
78#define VDDC_VDDCI_DELTA 200
79#define VDDC_VDDGFX_DELTA 300
80
81#define MC_SEQ_MISC0_GDDR5_SHIFT 28
82#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
83#define MC_SEQ_MISC0_GDDR5_VALUE 5
84
85typedef uint32_t PECI_RegistryValue;
86
87/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
88uint16_t PP_ClockStretcherLookupTable[2][4] = {
89 {600, 1050, 3, 0},
90 {600, 1050, 6, 1} };
91
92/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
93uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
94 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
95 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
96
97/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
98uint8_t PP_ClockStretchAmountConversion[2][6] = {
99 {0, 1, 3, 2, 4, 5},
100 {0, 2, 4, 5, 6, 5} };
101
102/* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
103enum DPM_EVENT_SRC {
104 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
105 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
106 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
107 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
108 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
109};
110typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
111
112enum DISPLAY_GAP {
113 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
114 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
115 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
116 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
117};
118typedef enum DISPLAY_GAP DISPLAY_GAP;
119
120const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
121
122struct tonga_power_state *cast_phw_tonga_power_state(
123 struct pp_hw_power_state *hw_ps)
124{
125 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
126 "Invalid Powerstate Type!",
127 return NULL;);
128
129 return (struct tonga_power_state *)hw_ps;
130}
131
132const struct tonga_power_state *cast_const_phw_tonga_power_state(
133 const struct pp_hw_power_state *hw_ps)
134{
135 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
136 "Invalid Powerstate Type!",
137 return NULL;);
138
139 return (const struct tonga_power_state *)hw_ps;
140}
141
142int tonga_add_voltage(struct pp_hwmgr *hwmgr,
143 phm_ppt_v1_voltage_lookup_table *look_up_table,
144 phm_ppt_v1_voltage_lookup_record *record)
145{
146 uint32_t i;
147 PP_ASSERT_WITH_CODE((NULL != look_up_table),
148 "Lookup Table empty.", return -1;);
149 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
150 "Lookup Table empty.", return -1;);
151 PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
152 "Lookup Table is full.", return -1;);
153
154 /* This is to avoid entering duplicate calculated records. */
155 for (i = 0; i < look_up_table->count; i++) {
156 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
157 if (look_up_table->entries[i].us_calculated == 1)
158 return 0;
159 else
160 break;
161 }
162 }
163
164 look_up_table->entries[i].us_calculated = 1;
165 look_up_table->entries[i].us_vdd = record->us_vdd;
166 look_up_table->entries[i].us_cac_low = record->us_cac_low;
167 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
168 look_up_table->entries[i].us_cac_high = record->us_cac_high;
169 /* Only increment the count when we're appending, not replacing duplicate entry. */
170 if (i == look_up_table->count)
171 look_up_table->count++;
172
173 return 0;
174}
175
bbb207f3
RZ		 176int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
177{
178 PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
179
180 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
181}
182
c82baa28 183uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
184 uint32_t voltage)
185{
186 uint8_t count = (uint8_t) (voltage_table->count);
187 uint8_t i = 0;
188
189 PP_ASSERT_WITH_CODE((NULL != voltage_table),
190 "Voltage Table empty.", return 0;);
191 PP_ASSERT_WITH_CODE((0 != count),
192 "Voltage Table empty.", return 0;);
193
194 for (i = 0; i < count; i++) {
195 /* find first voltage bigger than requested */
196 if (voltage_table->entries[i].value >= voltage)
197 return i;
198 }
199
200 /* voltage is bigger than max voltage in the table */
201 return i - 1;
202}
203
204/**
205 * @brief PhwTonga_GetVoltageOrder
206 * Returns index of requested voltage record in lookup(table)
207 * @param hwmgr - pointer to hardware manager
208 * @param lookupTable - lookup list to search in
209 * @param voltage - voltage to look for
210 * @return 0 on success
211 */
212uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
213 uint16_t voltage)
214{
215 uint8_t count = (uint8_t) (look_up_table->count);
216 uint8_t i;
217
218 PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
219 PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
220
221 for (i = 0; i < count; i++) {
222 /* find first voltage equal or bigger than requested */
223 if (look_up_table->entries[i].us_vdd >= voltage)
224 return i;
225 }
226
227 /* voltage is bigger than max voltage in the table */
228 return i-1;
229}
230
231bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
232{
233 /*
234 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
235 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
236 * whereas voltage control is a fundemental change that will not be disabled
237 */
238
239 return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
240 FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
241}
242
243/**
244 * Re-generate the DPM level mask value
245 * @param hwmgr the address of the hardware manager
246 */
247static uint32_t tonga_get_dpm_level_enable_mask_value(
248 struct tonga_single_dpm_table * dpm_table)
249{
250 uint32_t i;
251 uint32_t mask_value = 0;
252
253 for (i = dpm_table->count; i > 0; i--) {
254 mask_value = mask_value << 1;
255
256 if (dpm_table->dpm_levels[i-1].enabled)
257 mask_value |= 0x1;
258 else
259 mask_value &= 0xFFFFFFFE;
260 }
261 return mask_value;
262}
263
264/**
265 * Retrieve DPM default values from registry (if available)
266 *
267 * @param hwmgr the address of the powerplay hardware manager.
268 */
269void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
270{
271 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
272 phw_tonga_ulv_parm *ulv = &(data->ulv);
273 uint32_t tmp;
274
275 ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
276 data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
277 data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
278 data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
279 data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
280 data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
281 data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
282 data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
283 data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
284
285 data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
286 data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
287
288 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
289 PHM_PlatformCaps_ABM);
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_NonABMSupportInPPLib);
292
293 tmp = 0;
294 if (tmp == 0)
295 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
296 PHM_PlatformCaps_DynamicACTiming);
297
298 tmp = 0;
299 if (0 != tmp)
300 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
301 PHM_PlatformCaps_DisableMemoryTransition);
302
303 data->mclk_strobe_mode_threshold = 40000;
304 data->mclk_stutter_mode_threshold = 30000;
305 data->mclk_edc_enable_threshold = 40000;
306 data->mclk_edc_wr_enable_threshold = 40000;
307
308 tmp = 0;
309 if (tmp != 0)
310 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
311 PHM_PlatformCaps_DisableMCLS);
312
313 data->pcie_gen_performance.max = PP_PCIEGen1;
314 data->pcie_gen_performance.min = PP_PCIEGen3;
315 data->pcie_gen_power_saving.max = PP_PCIEGen1;
316 data->pcie_gen_power_saving.min = PP_PCIEGen3;
317
318 data->pcie_lane_performance.max = 0;
319 data->pcie_lane_performance.min = 16;
320 data->pcie_lane_power_saving.max = 0;
321 data->pcie_lane_power_saving.min = 16;
322
323 tmp = 0;
324
325 if (tmp)
326 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
327 PHM_PlatformCaps_SclkThrottleLowNotification);
328
329 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
330 PHM_PlatformCaps_DynamicUVDState);
331
332}
333
334int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
335{
336 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
337
338 int result = 0;
339 uint32_t low_sclk_interrupt_threshold = 0;
340
341 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
342 PHM_PlatformCaps_SclkThrottleLowNotification)
343 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
344 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
345 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
346
347 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
348
349 result = tonga_copy_bytes_to_smc(
350 hwmgr->smumgr,
351 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
352 LowSclkInterruptThreshold),
353 (uint8_t *)&low_sclk_interrupt_threshold,
354 sizeof(uint32_t),
355 data->sram_end
356 );
357 }
358
359 return result;
360}
361
362/**
363 * Find SCLK value that is associated with specified virtual_voltage_Id.
364 *
365 * @param hwmgr the address of the powerplay hardware manager.
366 * @param virtual_voltage_Id voltageId to look for.
367 * @param sclk output value .
368 * @return always 0 if success and 2 if association not found
369 */
370static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
371 phm_ppt_v1_voltage_lookup_table *lookup_table,
372 uint16_t virtual_voltage_id, uint32_t *sclk)
373{
374 uint8_t entryId;
375 uint8_t voltageId;
376 struct phm_ppt_v1_information *pptable_info =
377 (struct phm_ppt_v1_information *)(hwmgr->pptable);
378
379 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
380
381 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
382 for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
383 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
384 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
385 break;
386 }
387
388 PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
389 "Can't find requested voltage id in vdd_dep_on_sclk table!",
390 return -1;
391 );
392
393 *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
394
395 return 0;
396}
397
398/**
399 * Get Leakage VDDC based on leakage ID.
400 *
401 * @param hwmgr the address of the powerplay hardware manager.
402 * @return 2 if vddgfx returned is greater than 2V or if BIOS
403 */
404int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
405{
406 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
407 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
408 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
409 uint16_t virtual_voltage_id;
410 uint16_t vddc = 0;
411 uint16_t vddgfx = 0;
412 uint16_t i, j;
413 uint32_t sclk = 0;
414
415 /* retrieve voltage for leakage ID (0xff01 + i) */
416 for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
417 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
418
419 /* in split mode we should have only vddgfx EVV leakages */
420 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
421 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
422 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
423 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
424 PHM_PlatformCaps_ClockStretcher)) {
425 for (j = 1; j < sclk_table->count; j++) {
426 if (sclk_table->entries[j].clk == sclk &&
427 sclk_table->entries[j].cks_enable == 0) {
428 sclk += 5000;
429 break;
430 }
431 }
432 }
433 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
434 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
435 virtual_voltage_id, &vddgfx),
436 "Error retrieving EVV voltage value!", continue);
437
438 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
439 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
440
441 /* the voltage should not be zero nor equal to leakage ID */
442 if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
443 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
444 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
445 data->vddcgfx_leakage.count++;
446 }
447 }
448 } else {
449 /* in merged mode we have only vddc EVV leakages */
450 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
451 pptable_info->vddc_lookup_table,
452 virtual_voltage_id, &sclk)) {
453 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
454 (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
455 virtual_voltage_id, &vddc),
456 "Error retrieving EVV voltage value!", continue);
457
458 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
459 if (vddc > 2000)
460 printk(KERN_ERR "[ powerplay ] Invalid VDDC value! \n");
461
462 /* the voltage should not be zero nor equal to leakage ID */
463 if (vddc != 0 && vddc != virtual_voltage_id) {
464 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
465 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
466 data->vddc_leakage.count++;
467 }
468 }
469 }
470 }
471
472 return 0;
473}
474
475int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
476{
477 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
478
479 /* enable SCLK dpm */
480 if (0 == data->sclk_dpm_key_disabled) {
481 PP_ASSERT_WITH_CODE(
482 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
483 PPSMC_MSG_DPM_Enable)),
484 "Failed to enable SCLK DPM during DPM Start Function!",
485 return -1);
486 }
487
488 /* enable MCLK dpm */
489 if (0 == data->mclk_dpm_key_disabled) {
490 PP_ASSERT_WITH_CODE(
491 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
492 PPSMC_MSG_MCLKDPM_Enable)),
493 "Failed to enable MCLK DPM during DPM Start Function!",
494 return -1);
495
496 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
497
498 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
499 ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
500 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
501 ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
502 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
503 ixLCAC_CPL_CNTL, 0x100005);/*Read */
504
505 udelay(10);
506
507 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
508 ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
509 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
510 ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
511 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
512 ixLCAC_CPL_CNTL, 0x500005);/* write */
513
514 }
515
516 return 0;
517}
518
519int tonga_start_dpm(struct pp_hwmgr *hwmgr)
520{
521 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
522
523 /* enable general power management */
524 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
525 /* enable sclk deep sleep */
526 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
527
528 /* prepare for PCIE DPM */
529 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
530 offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
531
532 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
533
534 PP_ASSERT_WITH_CODE(
535 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
536 PPSMC_MSG_Voltage_Cntl_Enable)),
537 "Failed to enable voltage DPM during DPM Start Function!",
538 return -1);
539
540 if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
541 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
542 }
543
544 /* enable PCIE dpm */
545 if (0 == data->pcie_dpm_key_disabled) {
546 PP_ASSERT_WITH_CODE(
547 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
548 PPSMC_MSG_PCIeDPM_Enable)),
549 "Failed to enable pcie DPM during DPM Start Function!",
550 return -1
551 );
552 }
553
554 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
555 PHM_PlatformCaps_Falcon_QuickTransition)) {
556 smum_send_msg_to_smc(hwmgr->smumgr,
557 PPSMC_MSG_EnableACDCGPIOInterrupt);
558 }
559
560 return 0;
561}
562
563int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
564{
565 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
566
567 /* disable SCLK dpm */
568 if (0 == data->sclk_dpm_key_disabled) {
569 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
570 PP_ASSERT_WITH_CODE(
571 (0 == tonga_is_dpm_running(hwmgr)),
572 "Trying to Disable SCLK DPM when DPM is disabled",
573 return -1
574 );
575
576 PP_ASSERT_WITH_CODE(
577 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
578 PPSMC_MSG_DPM_Disable)),
579 "Failed to disable SCLK DPM during DPM stop Function!",
580 return -1);
581 }
582
583 /* disable MCLK dpm */
584 if (0 == data->mclk_dpm_key_disabled) {
585 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
586 PP_ASSERT_WITH_CODE(
587 (0 == tonga_is_dpm_running(hwmgr)),
588 "Trying to Disable MCLK DPM when DPM is disabled",
589 return -1
590 );
591
592 PP_ASSERT_WITH_CODE(
593 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
594 PPSMC_MSG_MCLKDPM_Disable)),
595 "Failed to Disable MCLK DPM during DPM stop Function!",
596 return -1);
597 }
598
599 return 0;
600}
601
602int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
603{
604 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
605
606 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
607 /* disable sclk deep sleep*/
608 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
609
610 /* disable PCIE dpm */
611 if (0 == data->pcie_dpm_key_disabled) {
612 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
613 PP_ASSERT_WITH_CODE(
614 (0 == tonga_is_dpm_running(hwmgr)),
615 "Trying to Disable PCIE DPM when DPM is disabled",
616 return -1
617 );
618 PP_ASSERT_WITH_CODE(
619 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
620 PPSMC_MSG_PCIeDPM_Disable)),
621 "Failed to disable pcie DPM during DPM stop Function!",
622 return -1);
623 }
624
625 if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
626 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
627
628 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
629 PP_ASSERT_WITH_CODE(
630 (0 == tonga_is_dpm_running(hwmgr)),
631 "Trying to Disable Voltage CNTL when DPM is disabled",
632 return -1
633 );
634
635 PP_ASSERT_WITH_CODE(
636 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
637 PPSMC_MSG_Voltage_Cntl_Disable)),
638 "Failed to disable voltage DPM during DPM stop Function!",
639 return -1);
640
641 return 0;
642}
643
644int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
645{
646 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
647
648 return 0;
649}
650
651/**
652 * Send a message to the SMC and return a parameter
653 *
654 * @param hwmgr: the address of the powerplay hardware manager.
655 * @param msg: the message to send.
656 * @param parameter: pointer to the received parameter
657 * @return The response that came from the SMC.
658 */
659PPSMC_Result tonga_send_msg_to_smc_return_parameter(
660 struct pp_hwmgr *hwmgr,
661 PPSMC_Msg msg,
662 uint32_t *parameter)
663{
664 int result;
665
666 result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
667
668 if ((0 == result) && parameter) {
669 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
670 }
671
672 return result;
673}
674
675/**
676 * force DPM power State
677 *
678 * @param hwmgr: the address of the powerplay hardware manager.
679 * @param n : DPM level
680 * @return The response that came from the SMC.
681 */
682int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
683{
684 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
685 uint32_t level_mask = 1 << n;
686
687 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
688 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
689 "Trying to force SCLK when DPM is disabled", return -1;);
690 if (0 == data->sclk_dpm_key_disabled)
691 return (0 == smum_send_msg_to_smc_with_parameter(
692 hwmgr->smumgr,
693 (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
694 level_mask) ? 0 : 1);
695
696 return 0;
697}
698
699/**
700 * force DPM power State
701 *
702 * @param hwmgr: the address of the powerplay hardware manager.
703 * @param n : DPM level
704 * @return The response that came from the SMC.
705 */
706int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
707{
708 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
709 uint32_t level_mask = 1 << n;
710
711 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
712 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
713 "Trying to Force MCLK when DPM is disabled", return -1;);
714 if (0 == data->mclk_dpm_key_disabled)
715 return (0 == smum_send_msg_to_smc_with_parameter(
716 hwmgr->smumgr,
717 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
718 level_mask) ? 0 : 1);
719
720 return 0;
721}
722
723/**
724 * force DPM power State
725 *
726 * @param hwmgr: the address of the powerplay hardware manager.
727 * @param n : DPM level
728 * @return The response that came from the SMC.
729 */
730int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
731{
732 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
733
734 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
735 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
736 "Trying to Force PCIE level when DPM is disabled", return -1;);
737 if (0 == data->pcie_dpm_key_disabled)
738 return (0 == smum_send_msg_to_smc_with_parameter(
739 hwmgr->smumgr,
740 (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
741 n) ? 0 : 1);
742
743 return 0;
744}
745
746/**
747 * Set the initial state by calling SMC to switch to this state directly
748 *
749 * @param hwmgr the address of the powerplay hardware manager.
750 * @return always 0
751 */
752int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
753{
754 /*
755 * SMC only stores one state that SW will ask to switch too,
756 * so we switch the the just uploaded one
757 */
758 return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
759}
760
761/**
762 * Get the location of various tables inside the FW image.
763 *
764 * @param hwmgr the address of the powerplay hardware manager.
765 * @return always 0
766 */
767int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
768{
769 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
770 struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
771
772 uint32_t tmp;
773 int result;
774 bool error = 0;
775
776 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
777 SMU72_FIRMWARE_HEADER_LOCATION +
778 offsetof(SMU72_Firmware_Header, DpmTable),
779 &tmp, data->sram_end);
780
781 if (0 == result) {
782 data->dpm_table_start = tmp;
783 }
784
785 error |= (0 != result);
786
787 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
788 SMU72_FIRMWARE_HEADER_LOCATION +
789 offsetof(SMU72_Firmware_Header, SoftRegisters),
790 &tmp, data->sram_end);
791
792 if (0 == result) {
793 data->soft_regs_start = tmp;
794 tonga_smu->ulSoftRegsStart = tmp;
795 }
796
797 error |= (0 != result);
798
799
800 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
801 SMU72_FIRMWARE_HEADER_LOCATION +
802 offsetof(SMU72_Firmware_Header, mcRegisterTable),
803 &tmp, data->sram_end);
804
805 if (0 == result) {
806 data->mc_reg_table_start = tmp;
807 }
808
809 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
810 SMU72_FIRMWARE_HEADER_LOCATION +
811 offsetof(SMU72_Firmware_Header, FanTable),
812 &tmp, data->sram_end);
813
814 if (0 == result) {
815 data->fan_table_start = tmp;
816 }
817
818 error |= (0 != result);
819
820 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
821 SMU72_FIRMWARE_HEADER_LOCATION +
822 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
823 &tmp, data->sram_end);
824
825 if (0 == result) {
826 data->arb_table_start = tmp;
827 }
828
829 error |= (0 != result);
830
831
832 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
833 SMU72_FIRMWARE_HEADER_LOCATION +
834 offsetof(SMU72_Firmware_Header, Version),
835 &tmp, data->sram_end);
836
837 if (0 == result) {
838 hwmgr->microcode_version_info.SMC = tmp;
839 }
840
841 error |= (0 != result);
842
843 return error ? 1 : 0;
844}
845
846/**
847 * Read clock related registers.
848 *
849 * @param hwmgr the address of the powerplay hardware manager.
850 * @return always 0
851 */
852int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
853{
854 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
855
856 data->clock_registers.vCG_SPLL_FUNC_CNTL =
857 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
858 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
859 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
860 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
861 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
862 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
863 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
864 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
865 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
866 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
867 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
868 data->clock_registers.vDLL_CNTL =
869 cgs_read_register(hwmgr->device, mmDLL_CNTL);
870 data->clock_registers.vMCLK_PWRMGT_CNTL =
871 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
872 data->clock_registers.vMPLL_AD_FUNC_CNTL =
873 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
874 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
875 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
876 data->clock_registers.vMPLL_FUNC_CNTL =
877 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
878 data->clock_registers.vMPLL_FUNC_CNTL_1 =
879 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
880 data->clock_registers.vMPLL_FUNC_CNTL_2 =
881 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
882 data->clock_registers.vMPLL_SS1 =
883 cgs_read_register(hwmgr->device, mmMPLL_SS1);
884 data->clock_registers.vMPLL_SS2 =
885 cgs_read_register(hwmgr->device, mmMPLL_SS2);
886
887 return 0;
888}
889
890/**
891 * Find out if memory is GDDR5.
892 *
893 * @param hwmgr the address of the powerplay hardware manager.
894 * @return always 0
895 */
896int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
897{
898 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
899 uint32_t temp;
900
901 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
902
903 data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
904 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
905 MC_SEQ_MISC0_GDDR5_SHIFT));
906
907 return 0;
908}
909
910/**
911 * Enables Dynamic Power Management by SMC
912 *
913 * @param hwmgr the address of the powerplay hardware manager.
914 * @return always 0
915 */
916int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
917{
918 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
919
920 return 0;
921}
922
923/**
924 * Initialize PowerGating States for different engines
925 *
926 * @param hwmgr the address of the powerplay hardware manager.
927 * @return always 0
928 */
929int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
930{
931 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
932
933 data->uvd_power_gated = 0;
934 data->vce_power_gated = 0;
935 data->samu_power_gated = 0;
936 data->acp_power_gated = 0;
937 data->pg_acp_init = 1;
938
939 return 0;
940}
941
942/**
943 * Checks if DPM is enabled
944 *
945 * @param hwmgr the address of the powerplay hardware manager.
946 * @return always 0
947 */
948int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
949{
950 /*
951 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
952 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
953 * whereas voltage control is a fundemental change that will not be disabled
954 */
955 return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
956}
957
958/**
959 * Checks if DPM is stopped
960 *
961 * @param hwmgr the address of the powerplay hardware manager.
962 * @return always 0
963 */
964int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
965{
966 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
967
968 if (0 != tonga_is_dpm_running(hwmgr)) {
969 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
970 if (!data->dpm_table_start) {
971 return 1;
972 }
973 }
974
975 return 0;
976}
977
978/**
979 * Remove repeated voltage values and create table with unique values.
980 *
981 * @param hwmgr the address of the powerplay hardware manager.
982 * @param voltage_table the pointer to changing voltage table
983 * @return 1 in success
984 */
985
986static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
987 pp_atomctrl_voltage_table *voltage_table)
988{
989 uint32_t table_size, i, j;
990 uint16_t vvalue;
991 bool bVoltageFound = 0;
992 pp_atomctrl_voltage_table *table;
993
994 PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
995 table_size = sizeof(pp_atomctrl_voltage_table);
996 table = kzalloc(table_size, GFP_KERNEL);
997
998 if (NULL == table)
999 return -ENOMEM;
1000
1001 memset(table, 0x00, table_size);
1002 table->mask_low = voltage_table->mask_low;
1003 table->phase_delay = voltage_table->phase_delay;
1004
1005 for (i = 0; i < voltage_table->count; i++) {
1006 vvalue = voltage_table->entries[i].value;
1007 bVoltageFound = 0;
1008
1009 for (j = 0; j < table->count; j++) {
1010 if (vvalue == table->entries[j].value) {
1011 bVoltageFound = 1;
1012 break;
1013 }
1014 }
1015
1016 if (!bVoltageFound) {
1017 table->entries[table->count].value = vvalue;
1018 table->entries[table->count].smio_low =
1019 voltage_table->entries[i].smio_low;
1020 table->count++;
1021 }
1022 }
1023
1024 memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1025
1026 kfree(table);
1027
1028 return 0;
1029}
1030
1031static int tonga_get_svi2_vdd_ci_voltage_table(
1032 struct pp_hwmgr *hwmgr,
1033 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1034{
1035 uint32_t i;
1036 int result;
1037 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1038 pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1039
1040 PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1041 "Voltage Dependency Table empty.", return -1;);
1042
1043 vddci_voltage_table->mask_low = 0;
1044 vddci_voltage_table->phase_delay = 0;
1045 vddci_voltage_table->count = voltage_dependency_table->count;
1046
1047 for (i = 0; i < voltage_dependency_table->count; i++) {
1048 vddci_voltage_table->entries[i].value =
1049 voltage_dependency_table->entries[i].vddci;
1050 vddci_voltage_table->entries[i].smio_low = 0;
1051 }
1052
1053 result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1054 PP_ASSERT_WITH_CODE((0 == result),
1055 "Failed to trim VDDCI table.", return result;);
1056
1057 return 0;
1058}
1059
1060
1061
1062static int tonga_get_svi2_vdd_voltage_table(
1063 struct pp_hwmgr *hwmgr,
1064 phm_ppt_v1_voltage_lookup_table *look_up_table,
1065 pp_atomctrl_voltage_table *voltage_table)
1066{
1067 uint8_t i = 0;
1068
1069 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1070 "Voltage Lookup Table empty.", return -1;);
1071
1072 voltage_table->mask_low = 0;
1073 voltage_table->phase_delay = 0;
1074
1075 voltage_table->count = look_up_table->count;
1076
1077 for (i = 0; i < voltage_table->count; i++) {
1078 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1079 voltage_table->entries[i].smio_low = 0;
1080 }
1081
1082 return 0;
1083}
1084
1085/*
1086 * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1087 * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1088 */
1089
1090static void tonga_trim_voltage_table_to_fit_state_table(
1091 struct pp_hwmgr *hwmgr,
1092 uint32_t max_voltage_steps,
1093 pp_atomctrl_voltage_table *voltage_table)
1094{
1095 unsigned int i, diff;
1096
1097 if (voltage_table->count <= max_voltage_steps) {
1098 return;
1099 }
1100
1101 diff = voltage_table->count - max_voltage_steps;
1102
1103 for (i = 0; i < max_voltage_steps; i++) {
1104 voltage_table->entries[i] = voltage_table->entries[i + diff];
1105 }
1106
1107 voltage_table->count = max_voltage_steps;
1108
1109 return;
1110}
1111
1112/**
1113 * Create Voltage Tables.
1114 *
1115 * @param hwmgr the address of the powerplay hardware manager.
1116 * @return always 0
1117 */
1118int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1119{
1120 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1121 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1122 int result;
1123
1124 /* MVDD has only GPIO voltage control */
1125 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1126 result = atomctrl_get_voltage_table_v3(hwmgr,
1127 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1128 PP_ASSERT_WITH_CODE((0 == result),
1129 "Failed to retrieve MVDD table.", return result;);
1130 }
1131
1132 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1133 /* GPIO voltage */
1134 result = atomctrl_get_voltage_table_v3(hwmgr,
1135 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1136 PP_ASSERT_WITH_CODE((0 == result),
1137 "Failed to retrieve VDDCI table.", return result;);
1138 } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1139 /* SVI2 voltage */
1140 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1141 pptable_info->vdd_dep_on_mclk);
1142 PP_ASSERT_WITH_CODE((0 == result),
1143 "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1144 }
1145
1146 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1147 /* VDDGFX has only SVI2 voltage control */
1148 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1149 pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1150 PP_ASSERT_WITH_CODE((0 == result),
1151 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1152 }
1153
1154 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1155 /* VDDC has only SVI2 voltage control */
1156 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1157 pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1158 PP_ASSERT_WITH_CODE((0 == result),
1159 "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1160 }
1161
1162 PP_ASSERT_WITH_CODE(
1163 (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1164 "Too many voltage values for VDDC. Trimming to fit state table.",
1165 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1166 SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1167 );
1168
1169 PP_ASSERT_WITH_CODE(
1170 (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1171 "Too many voltage values for VDDGFX. Trimming to fit state table.",
1172 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1173 SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1174 );
1175
1176 PP_ASSERT_WITH_CODE(
1177 (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1178 "Too many voltage values for VDDCI. Trimming to fit state table.",
1179 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1180 SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1181 );
1182
1183 PP_ASSERT_WITH_CODE(
1184 (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1185 "Too many voltage values for MVDD. Trimming to fit state table.",
1186 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1187 SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1188 );
1189
1190 return 0;
1191}
1192
1193/**
1194 * Vddc table preparation for SMC.
1195 *
1196 * @param hwmgr the address of the hardware manager
1197 * @param table the SMC DPM table structure to be populated
1198 * @return always 0
1199 */
1200static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1201 SMU72_Discrete_DpmTable *table)
1202{
1203 unsigned int count;
1204 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1205
1206 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1207 table->VddcLevelCount = data->vddc_voltage_table.count;
1208 for (count = 0; count < table->VddcLevelCount; count++) {
1209 table->VddcTable[count] =
1210 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1211 }
1212 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1213 }
1214 return 0;
1215}
1216
1217/**
1218 * VddGfx table preparation for SMC.
1219 *
1220 * @param hwmgr the address of the hardware manager
1221 * @param table the SMC DPM table structure to be populated
1222 * @return always 0
1223 */
1224static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1225 SMU72_Discrete_DpmTable *table)
1226{
1227 unsigned int count;
1228 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1229
1230 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1231 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1232 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1233 table->VddGfxTable[count] =
1234 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1235 }
1236 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1237 }
1238 return 0;
1239}
1240
1241/**
1242 * Vddci table preparation for SMC.
1243 *
1244 * @param *hwmgr The address of the hardware manager.
1245 * @param *table The SMC DPM table structure to be populated.
1246 * @return 0
1247 */
1248static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1249 SMU72_Discrete_DpmTable *table)
1250{
1251 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1252 uint32_t count;
1253
1254 table->VddciLevelCount = data->vddci_voltage_table.count;
1255 for (count = 0; count < table->VddciLevelCount; count++) {
1256 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1257 table->VddciTable[count] =
1258 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1259 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1260 table->SmioTable1.Pattern[count].Voltage =
1261 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1262 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1263 table->SmioTable1.Pattern[count].Smio =
1264 (uint8_t) count;
1265 table->Smio[count] |=
1266 data->vddci_voltage_table.entries[count].smio_low;
1267 table->VddciTable[count] =
1268 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1269 }
1270 }
1271
1272 table->SmioMask1 = data->vddci_voltage_table.mask_low;
1273 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1274
1275 return 0;
1276}
1277
1278/**
1279 * Mvdd table preparation for SMC.
1280 *
1281 * @param *hwmgr The address of the hardware manager.
1282 * @param *table The SMC DPM table structure to be populated.
1283 * @return 0
1284 */
1285static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1286 SMU72_Discrete_DpmTable *table)
1287{
1288 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1289 uint32_t count;
1290
1291 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1292 table->MvddLevelCount = data->mvdd_voltage_table.count;
1293 for (count = 0; count < table->MvddLevelCount; count++) {
1294 table->SmioTable2.Pattern[count].Voltage =
1295 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1296 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1297 table->SmioTable2.Pattern[count].Smio =
1298 (uint8_t) count;
1299 table->Smio[count] |=
1300 data->mvdd_voltage_table.entries[count].smio_low;
1301 }
1302 table->SmioMask2 = data->vddci_voltage_table.mask_low;
1303
1304 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1305 }
1306
1307 return 0;
1308}
1309
1310/**
1311 * Convert a voltage value in mv unit to VID number required by SMU firmware
1312 */
1313static uint8_t convert_to_vid(uint16_t vddc)
1314{
1315 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1316}
1317
1318
1319/**
1320 * Preparation of vddc and vddgfx CAC tables for SMC.
1321 *
1322 * @param hwmgr the address of the hardware manager
1323 * @param table the SMC DPM table structure to be populated
1324 * @return always 0
1325 */
1326static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1327 SMU72_Discrete_DpmTable *table)
1328{
1329 uint32_t count;
1330 uint8_t index;
1331 int result = 0;
1332 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1333 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1334 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1335 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1336
1337 /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1338 uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1339 uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1340
1341 for (count = 0; count < vddcLevelCount; count++) {
1342 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1343 index = tonga_get_voltage_index(vddc_lookup_table,
1344 data->vddc_voltage_table.entries[count].value);
1345 table->BapmVddcVidLoSidd[count] =
1346 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1347 table->BapmVddcVidHiSidd[count] =
1348 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1349 table->BapmVddcVidHiSidd2[count] =
1350 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1351 }
1352
1353 if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1354 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1355 for (count = 0; count < vddgfxLevelCount; count++) {
1356 index = tonga_get_voltage_index(vddgfx_lookup_table,
1357 data->vddgfx_voltage_table.entries[count].value);
1358 table->BapmVddGfxVidLoSidd[count] =
1359 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1360 table->BapmVddGfxVidHiSidd[count] =
1361 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1362 table->BapmVddGfxVidHiSidd2[count] =
1363 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1364 }
1365 } else {
1366 for (count = 0; count < vddcLevelCount; count++) {
1367 index = tonga_get_voltage_index(vddc_lookup_table,
1368 data->vddc_voltage_table.entries[count].value);
1369 table->BapmVddGfxVidLoSidd[count] =
1370 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1371 table->BapmVddGfxVidHiSidd[count] =
1372 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1373 table->BapmVddGfxVidHiSidd2[count] =
1374 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1375 }
1376 }
1377
1378 return result;
1379}
1380
1381
1382/**
1383 * Preparation of voltage tables for SMC.
1384 *
1385 * @param hwmgr the address of the hardware manager
1386 * @param table the SMC DPM table structure to be populated
1387 * @return always 0
1388 */
1389
1390int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1391 SMU72_Discrete_DpmTable *table)
1392{
1393 int result;
1394
1395 result = tonga_populate_smc_vddc_table(hwmgr, table);
1396 PP_ASSERT_WITH_CODE(0 == result,
1397 "can not populate VDDC voltage table to SMC", return -1);
1398
1399 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1400 PP_ASSERT_WITH_CODE(0 == result,
1401 "can not populate VDDCI voltage table to SMC", return -1);
1402
1403 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1404 PP_ASSERT_WITH_CODE(0 == result,
1405 "can not populate VDDGFX voltage table to SMC", return -1);
1406
1407 result = tonga_populate_smc_mvdd_table(hwmgr, table);
1408 PP_ASSERT_WITH_CODE(0 == result,
1409 "can not populate MVDD voltage table to SMC", return -1);
1410
1411 result = tonga_populate_cac_tables(hwmgr, table);
1412 PP_ASSERT_WITH_CODE(0 == result,
1413 "can not populate CAC voltage tables to SMC", return -1);
1414
1415 return 0;
1416}
1417
1418/**
1419 * Populates the SMC VRConfig field in DPM table.
1420 *
1421 * @param hwmgr the address of the hardware manager
1422 * @param table the SMC DPM table structure to be populated
1423 * @return always 0
1424 */
1425static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1426 SMU72_Discrete_DpmTable *table)
1427{
1428 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1429 uint16_t config;
1430
1431 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1432 /* Splitted mode */
1433 config = VR_SVI2_PLANE_1;
1434 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1435
1436 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1437 config = VR_SVI2_PLANE_2;
1438 table->VRConfig |= config;
1439 } else {
1440 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1441 }
1442 } else {
1443 /* Merged mode */
1444 config = VR_MERGED_WITH_VDDC;
1445 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1446
1447 /* Set Vddc Voltage Controller */
1448 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1449 config = VR_SVI2_PLANE_1;
1450 table->VRConfig |= config;
1451 } else {
1452 printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1453 }
1454 }
1455
1456 /* Set Vddci Voltage Controller */
1457 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1458 config = VR_SVI2_PLANE_2; /* only in merged mode */
1459 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1460 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1461 config = VR_SMIO_PATTERN_1;
1462 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1463 }
1464
1465 /* Set Mvdd Voltage Controller */
1466 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1467 config = VR_SMIO_PATTERN_2;
1468 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1469 }
1470
1471 return 0;
1472}
1473
1474static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1475 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1476 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1477{
1478 uint32_t i = 0;
1479 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1480 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1481
1482 /* clock - voltage dependency table is empty table */
1483 if (allowed_clock_voltage_table->count == 0)
1484 return -1;
1485
1486 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1487 /* find first sclk bigger than request */
1488 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1489 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1490 allowed_clock_voltage_table->entries[i].vddgfx);
1491
1492 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1493 allowed_clock_voltage_table->entries[i].vddc);
1494
1495 if (allowed_clock_voltage_table->entries[i].vddci) {
1496 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1497 allowed_clock_voltage_table->entries[i].vddci);
1498 } else {
1499 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1500 allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1501 }
1502
1503 if (allowed_clock_voltage_table->entries[i].mvdd) {
1504 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1505 }
1506
1507 voltage->Phases = 1;
1508 return 0;
1509 }
1510 }
1511
1512 /* sclk is bigger than max sclk in the dependence table */
1513 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1514 allowed_clock_voltage_table->entries[i-1].vddgfx);
1515 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1516 allowed_clock_voltage_table->entries[i-1].vddc);
1517
1518 if (allowed_clock_voltage_table->entries[i-1].vddci) {
1519 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1520 allowed_clock_voltage_table->entries[i-1].vddci);
1521 }
1522 if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1523 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1524 }
1525
1526 return 0;
1527}
1528
1529/**
1530 * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1531 *
1532 * @param hwmgr the address of the powerplay hardware manager.
1533 * @return always 0
1534 */
1535int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1536{
1537 return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1538}
1539
1540int tonga_populate_memory_timing_parameters(
1541 struct pp_hwmgr *hwmgr,
1542 uint32_t engine_clock,
1543 uint32_t memory_clock,
1544 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1545 )
1546{
1547 uint32_t dramTiming;
1548 uint32_t dramTiming2;
1549 uint32_t burstTime;
1550 int result;
1551
1552 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1553 engine_clock, memory_clock);
1554
1555 PP_ASSERT_WITH_CODE(result == 0,
1556 "Error calling VBIOS to set DRAM_TIMING.", return result);
1557
1558 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1559 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1560 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1561
1562 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1563 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1564 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1565
1566 return 0;
1567}
1568
1569/**
1570 * Setup parameters for the MC ARB.
1571 *
1572 * @param hwmgr the address of the powerplay hardware manager.
1573 * @return always 0
1574 * This function is to be called from the SetPowerState table.
1575 */
1576int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1577{
1578 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1579 int result = 0;
1580 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1581 uint32_t i, j;
1582
1583 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1584
1585 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1586 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1587 result = tonga_populate_memory_timing_parameters
1588 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1589 data->dpm_table.mclk_table.dpm_levels[j].value,
1590 &arb_regs.entries[i][j]);
1591
1592 if (0 != result) {
1593 break;
1594 }
1595 }
1596 }
1597
1598 if (0 == result) {
1599 result = tonga_copy_bytes_to_smc(
1600 hwmgr->smumgr,
1601 data->arb_table_start,
1602 (uint8_t *)&arb_regs,
1603 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1604 data->sram_end
1605 );
1606 }
1607
1608 return result;
1609}
1610
1611static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1612{
1613 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1614 struct tonga_dpm_table *dpm_table = &data->dpm_table;
1615 uint32_t i;
1616
1617 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1618 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1619 table->LinkLevel[i].PcieGenSpeed =
1620 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1621 table->LinkLevel[i].PcieLaneCount =
1622 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1623 table->LinkLevel[i].EnabledForActivity =
1624 1;
1625 table->LinkLevel[i].SPC =
1626 (uint8_t)(data->pcie_spc_cap & 0xff);
1627 table->LinkLevel[i].DownThreshold =
1628 PP_HOST_TO_SMC_UL(5);
1629 table->LinkLevel[i].UpThreshold =
1630 PP_HOST_TO_SMC_UL(30);
1631 }
1632
1633 data->smc_state_table.LinkLevelCount =
1634 (uint8_t)dpm_table->pcie_speed_table.count;
1635 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1636 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1637
1638 return 0;
1639}
1640
1641
1642static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1643 SMU72_Discrete_DpmTable *table)
1644{
1645 int result = 0;
1646
1647 uint8_t count;
1648 pp_atomctrl_clock_dividers_vi dividers;
1649 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1650 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1651 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1652
1653 table->VceLevelCount = (uint8_t) (mm_table->count);
1654 table->VceBootLevel = 0;
1655
1656 for (count = 0; count < table->VceLevelCount; count++) {
1657 table->VceLevel[count].Frequency =
1658 mm_table->entries[count].eclk;
1659 table->VceLevel[count].MinVoltage.Vddc =
1660 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1661 mm_table->entries[count].vddc);
1662 table->VceLevel[count].MinVoltage.VddGfx =
1663 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1664 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1665 mm_table->entries[count].vddgfx) : 0;
1666 table->VceLevel[count].MinVoltage.Vddci =
1667 tonga_get_voltage_id(&data->vddci_voltage_table,
1668 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1669 table->VceLevel[count].MinVoltage.Phases = 1;
1670
1671 /* retrieve divider value for VBIOS */
1672 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1673 table->VceLevel[count].Frequency, &dividers);
1674 PP_ASSERT_WITH_CODE((0 == result),
1675 "can not find divide id for VCE engine clock", return result);
1676
1677 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1678
1679 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1680 }
1681
1682 return result;
1683}
1684
1685static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1686 SMU72_Discrete_DpmTable *table)
1687{
1688 int result = 0;
1689 uint8_t count;
1690 pp_atomctrl_clock_dividers_vi dividers;
1691 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1692 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1693 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1694
1695 table->AcpLevelCount = (uint8_t) (mm_table->count);
1696 table->AcpBootLevel = 0;
1697
1698 for (count = 0; count < table->AcpLevelCount; count++) {
1699 table->AcpLevel[count].Frequency =
1700 pptable_info->mm_dep_table->entries[count].aclk;
1701 table->AcpLevel[count].MinVoltage.Vddc =
1702 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1703 mm_table->entries[count].vddc);
1704 table->AcpLevel[count].MinVoltage.VddGfx =
1705 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1706 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1707 mm_table->entries[count].vddgfx) : 0;
1708 table->AcpLevel[count].MinVoltage.Vddci =
1709 tonga_get_voltage_id(&data->vddci_voltage_table,
1710 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1711 table->AcpLevel[count].MinVoltage.Phases = 1;
1712
1713 /* retrieve divider value for VBIOS */
1714 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1715 table->AcpLevel[count].Frequency, &dividers);
1716 PP_ASSERT_WITH_CODE((0 == result),
1717 "can not find divide id for engine clock", return result);
1718
1719 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1720
1721 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1722 }
1723
1724 return result;
1725}
1726
1727static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1728 SMU72_Discrete_DpmTable *table)
1729{
1730 int result = 0;
1731 uint8_t count;
1732 pp_atomctrl_clock_dividers_vi dividers;
1733 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1734 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1735 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1736
1737 table->SamuBootLevel = 0;
1738 table->SamuLevelCount = (uint8_t) (mm_table->count);
1739
1740 for (count = 0; count < table->SamuLevelCount; count++) {
1741 /* not sure whether we need evclk or not */
1742 table->SamuLevel[count].Frequency =
1743 pptable_info->mm_dep_table->entries[count].samclock;
1744 table->SamuLevel[count].MinVoltage.Vddc =
1745 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1746 mm_table->entries[count].vddc);
1747 table->SamuLevel[count].MinVoltage.VddGfx =
1748 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1749 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1750 mm_table->entries[count].vddgfx) : 0;
1751 table->SamuLevel[count].MinVoltage.Vddci =
1752 tonga_get_voltage_id(&data->vddci_voltage_table,
1753 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1754 table->SamuLevel[count].MinVoltage.Phases = 1;
1755
1756 /* retrieve divider value for VBIOS */
1757 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1758 table->SamuLevel[count].Frequency, &dividers);
1759 PP_ASSERT_WITH_CODE((0 == result),
1760 "can not find divide id for samu clock", return result);
1761
1762 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1763
1764 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1765 }
1766
1767 return result;
1768}
1769
1770/**
1771 * Populates the SMC MCLK structure using the provided memory clock
1772 *
1773 * @param hwmgr the address of the hardware manager
1774 * @param memory_clock the memory clock to use to populate the structure
1775 * @param sclk the SMC SCLK structure to be populated
1776 */
1777static int tonga_calculate_mclk_params(
1778 struct pp_hwmgr *hwmgr,
1779 uint32_t memory_clock,
1780 SMU72_Discrete_MemoryLevel *mclk,
1781 bool strobe_mode,
1782 bool dllStateOn
1783 )
1784{
1785 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1786 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1787 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1788 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1789 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1790 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1791 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1792 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1793 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1794 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1795
1796 pp_atomctrl_memory_clock_param mpll_param;
1797 int result;
1798
1799 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1800 memory_clock, &mpll_param, strobe_mode);
1801 PP_ASSERT_WITH_CODE(0 == result,
1802 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1803
1804 /* MPLL_FUNC_CNTL setup*/
1805 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1806
1807 /* MPLL_FUNC_CNTL_1 setup*/
1808 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1809 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1810 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1811 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1812 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1813 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1814
1815 /* MPLL_AD_FUNC_CNTL setup*/
1816 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1817 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1818
1819 if (data->is_memory_GDDR5) {
1820 /* MPLL_DQ_FUNC_CNTL setup*/
1821 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1822 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1823 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1824 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1825 }
1826
1827 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1828 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1829 /*
1830 ************************************
1831 Fref = Reference Frequency
1832 NF = Feedback divider ratio
1833 NR = Reference divider ratio
1834 Fnom = Nominal VCO output frequency = Fref * NF / NR
1835 Fs = Spreading Rate
1836 D = Percentage down-spread / 2
1837 Fint = Reference input frequency to PFD = Fref / NR
1838 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1839 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1840 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1841 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1842 *************************************
1843 */
1844 pp_atomctrl_internal_ss_info ss_info;
1845 uint32_t freq_nom;
1846 uint32_t tmp;
1847 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1848
1849 /* for GDDR5 for all modes and DDR3 */
1850 if (1 == mpll_param.qdr)
1851 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1852 else
1853 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1854
1855 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1856 tmp = (freq_nom / reference_clock);
1857 tmp = tmp * tmp;
1858
1859 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1860 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1861 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1862 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1863 /* = reference_clock * 5 / speed_spectrum_rate */
1864 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1865
1866 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1867 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1868 uint32_t clkv =
1869 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1870 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1871
1872 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1873 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1874 }
1875 }
1876
1877 /* MCLK_PWRMGT_CNTL setup */
1878 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1879 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1880 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1881 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1882 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1883 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1884
1885
1886 /* Save the result data to outpupt memory level structure */
1887 mclk->MclkFrequency = memory_clock;
1888 mclk->MpllFuncCntl = mpll_func_cntl;
1889 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1890 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1891 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1892 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1893 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1894 mclk->DllCntl = dll_cntl;
1895 mclk->MpllSs1 = mpll_ss1;
1896 mclk->MpllSs2 = mpll_ss2;
1897
1898 return 0;
1899}
1900
1901static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1902 bool strobe_mode)
1903{
1904 uint8_t mc_para_index;
1905
1906 if (strobe_mode) {
1907 if (memory_clock < 12500) {
1908 mc_para_index = 0x00;
1909 } else if (memory_clock > 47500) {
1910 mc_para_index = 0x0f;
1911 } else {
1912 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1913 }
1914 } else {
1915 if (memory_clock < 65000) {
1916 mc_para_index = 0x00;
1917 } else if (memory_clock > 135000) {
1918 mc_para_index = 0x0f;
1919 } else {
1920 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1921 }
1922 }
1923
1924 return mc_para_index;
1925}
1926
1927static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1928{
1929 uint8_t mc_para_index;
1930
1931 if (memory_clock < 10000) {
1932 mc_para_index = 0;
1933 } else if (memory_clock >= 80000) {
1934 mc_para_index = 0x0f;
1935 } else {
1936 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1937 }
1938
1939 return mc_para_index;
1940}
1941
1942static int tonga_populate_single_memory_level(
1943 struct pp_hwmgr *hwmgr,
1944 uint32_t memory_clock,
1945 SMU72_Discrete_MemoryLevel *memory_level
1946 )
1947{
1948 uint32_t minMvdd = 0;
1949 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1950 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1951 int result = 0;
1952 bool dllStateOn;
1953 struct cgs_display_info info = {0};
1954
1955
1956 if (NULL != pptable_info->vdd_dep_on_mclk) {
1957 result = tonga_get_dependecy_volt_by_clk(hwmgr,
1958 pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
1959 PP_ASSERT_WITH_CODE((0 == result),
1960 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1961 }
1962
1963 if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
1964 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
1965 } else {
1966 memory_level->MinMvdd = minMvdd;
1967 }
1968 memory_level->EnabledForThrottle = 1;
1969 memory_level->EnabledForActivity = 0;
1970 memory_level->UpHyst = 0;
1971 memory_level->DownHyst = 100;
1972 memory_level->VoltageDownHyst = 0;
1973
1974 /* Indicates maximum activity level for this performance level.*/
1975 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1976 memory_level->StutterEnable = 0;
1977 memory_level->StrobeEnable = 0;
1978 memory_level->EdcReadEnable = 0;
1979 memory_level->EdcWriteEnable = 0;
1980 memory_level->RttEnable = 0;
1981
1982 /* default set to low watermark. Highest level will be set to high later.*/
1983 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1984
1985 cgs_get_active_displays_info(hwmgr->device, &info);
1986 data->display_timing.num_existing_displays = info.display_count;
1987
1988 if ((data->mclk_stutter_mode_threshold != 0) &&
1989 (memory_clock <= data->mclk_stutter_mode_threshold) &&
1990 (data->is_uvd_enabled == 0)
1991#if defined(LINUX)
1992 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
1993 && (data->display_timing.num_existing_displays <= 2)
1994 && (data->display_timing.num_existing_displays != 0)
1995#endif
1996 )
1997 memory_level->StutterEnable = 1;
1998
1999 /* decide strobe mode*/
2000 memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2001 (memory_clock <= data->mclk_strobe_mode_threshold);
2002
2003 /* decide EDC mode and memory clock ratio*/
2004 if (data->is_memory_GDDR5) {
2005 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2006 memory_level->StrobeEnable);
2007
2008 if ((data->mclk_edc_enable_threshold != 0) &&
2009 (memory_clock > data->mclk_edc_enable_threshold)) {
2010 memory_level->EdcReadEnable = 1;
2011 }
2012
2013 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2014 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2015 memory_level->EdcWriteEnable = 1;
2016 }
2017
2018 if (memory_level->StrobeEnable) {
2019 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2020 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2021 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2022 } else {
2023 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2024 }
2025
2026 } else {
2027 dllStateOn = data->dll_defaule_on;
2028 }
2029 } else {
2030 memory_level->StrobeRatio =
2031 tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2032 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2033 }
2034
2035 result = tonga_calculate_mclk_params(hwmgr,
2036 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2037
2038 if (0 == result) {
2039 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2040 /* MCLK frequency in units of 10KHz*/
2041 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2042 /* Indicates maximum activity level for this performance level.*/
2043 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2044 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2045 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2046 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2047 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2048 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2049 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2050 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2051 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2052 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2053 }
2054
2055 return result;
2056}
2057
2058/**
2059 * Populates the SMC MVDD structure using the provided memory clock.
2060 *
2061 * @param hwmgr the address of the hardware manager
2062 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2063 * @param voltage the SMC VOLTAGE structure to be populated
2064 */
2065int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2066{
2067 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2068 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2069 uint32_t i = 0;
2070
2071 if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2072 /* find mvdd value which clock is more than request */
2073 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2074 if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2075 /* Always round to higher voltage. */
2076 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2077 break;
2078 }
2079 }
2080
2081 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2082 "MVDD Voltage is outside the supported range.", return -1);
2083
2084 } else {
2085 return -1;
2086 }
2087
2088 return 0;
2089}
2090
2091
2092static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2093 SMU72_Discrete_DpmTable *table)
2094{
2095 int result = 0;
2096 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2097 pp_atomctrl_clock_dividers_vi dividers;
2098 SMIO_Pattern voltage_level;
2099 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2100 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2101 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
2102 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
2103
2104 /* The ACPI state should not do DPM on DC (or ever).*/
2105 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2106
2107 table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2108
2109 /* assign zero for now*/
2110 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2111
2112 /* get the engine clock dividers for this clock value*/
2113 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2114 table->ACPILevel.SclkFrequency, &dividers);
2115
2116 PP_ASSERT_WITH_CODE(result == 0,
2117 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2118
2119 /* divider ID for required SCLK*/
2120 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2121 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2122 table->ACPILevel.DeepSleepDivId = 0;
2123
2124 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2125 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
2126 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2127 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
2128 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
2129 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
2130
2131 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2132 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2133 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2134 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2135 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2136 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2137 table->ACPILevel.CcPwrDynRm = 0;
2138 table->ACPILevel.CcPwrDynRm1 = 0;
2139
2140
2141 /* For various features to be enabled/disabled while this level is active.*/
2142 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2143 /* SCLK frequency in units of 10KHz*/
2144 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2145 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2149 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2150 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2151 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2152 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2153
2154 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2155 table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2156
2157 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2158
2159 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2160 table->MemoryACPILevel.MinMvdd =
2161 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2162 else
2163 table->MemoryACPILevel.MinMvdd = 0;
2164
2165 /* Force reset on DLL*/
2166 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2167 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2168 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2169 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2170
2171 /* Disable DLL in ACPIState*/
2172 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2173 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2174 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2175 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2176
2177 /* Enable DLL bypass signal*/
2178 dll_cntl = PHM_SET_FIELD(dll_cntl,
2179 DLL_CNTL, MRDCK0_BYPASS, 0);
2180 dll_cntl = PHM_SET_FIELD(dll_cntl,
2181 DLL_CNTL, MRDCK1_BYPASS, 0);
2182
2183 table->MemoryACPILevel.DllCntl =
2184 PP_HOST_TO_SMC_UL(dll_cntl);
2185 table->MemoryACPILevel.MclkPwrmgtCntl =
2186 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2187 table->MemoryACPILevel.MpllAdFuncCntl =
2188 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2189 table->MemoryACPILevel.MpllDqFuncCntl =
2190 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2191 table->MemoryACPILevel.MpllFuncCntl =
2192 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2193 table->MemoryACPILevel.MpllFuncCntl_1 =
2194 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2195 table->MemoryACPILevel.MpllFuncCntl_2 =
2196 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2197 table->MemoryACPILevel.MpllSs1 =
2198 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2199 table->MemoryACPILevel.MpllSs2 =
2200 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2201
2202 table->MemoryACPILevel.EnabledForThrottle = 0;
2203 table->MemoryACPILevel.EnabledForActivity = 0;
2204 table->MemoryACPILevel.UpHyst = 0;
2205 table->MemoryACPILevel.DownHyst = 100;
2206 table->MemoryACPILevel.VoltageDownHyst = 0;
2207 /* Indicates maximum activity level for this performance level.*/
2208 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2209
2210 table->MemoryACPILevel.StutterEnable = 0;
2211 table->MemoryACPILevel.StrobeEnable = 0;
2212 table->MemoryACPILevel.EdcReadEnable = 0;
2213 table->MemoryACPILevel.EdcWriteEnable = 0;
2214 table->MemoryACPILevel.RttEnable = 0;
2215
2216 return result;
2217}
2218
2219static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2220{
2221 int result = 0;
2222 uint32_t i;
2223
2224 for (i = 0; i < table->count; i++) {
2225 if (value == table->dpm_levels[i].value) {
2226 *boot_level = i;
2227 result = 0;
2228 }
2229 }
2230 return result;
2231}
2232
2233static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2234 SMU72_Discrete_DpmTable *table)
2235{
2236 int result = 0;
2237 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2238
2239 table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2240 table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2241
2242 /* find boot level from dpm table*/
2243 result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2244 data->vbios_boot_state.sclk_bootup_value,
2245 (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2246
2247 if (0 != result) {
2248 data->smc_state_table.GraphicsBootLevel = 0;
2249 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2250 in dependency table. Using Graphics DPM level 0!");
2251 result = 0;
2252 }
2253
2254 result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2255 data->vbios_boot_state.mclk_bootup_value,
2256 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2257
2258 if (0 != result) {
2259 data->smc_state_table.MemoryBootLevel = 0;
2260 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2261 in dependency table. Using Memory DPM level 0!");
2262 result = 0;
2263 }
2264
2265 table->BootVoltage.Vddc =
2266 tonga_get_voltage_id(&(data->vddc_voltage_table),
2267 data->vbios_boot_state.vddc_bootup_value);
2268 table->BootVoltage.VddGfx =
2269 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2270 data->vbios_boot_state.vddgfx_bootup_value);
2271 table->BootVoltage.Vddci =
2272 tonga_get_voltage_id(&(data->vddci_voltage_table),
2273 data->vbios_boot_state.vddci_bootup_value);
2274 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2275
2276 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2277
2278 return result;
2279}
2280
2281
2282/**
2283 * Calculates the SCLK dividers using the provided engine clock
2284 *
2285 * @param hwmgr the address of the hardware manager
2286 * @param engine_clock the engine clock to use to populate the structure
2287 * @param sclk the SMC SCLK structure to be populated
2288 */
2289int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2290 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2291{
2292 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2293 pp_atomctrl_clock_dividers_vi dividers;
2294 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2295 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2296 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2297 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2298 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2299 uint32_t reference_clock;
2300 uint32_t reference_divider;
2301 uint32_t fbdiv;
2302 int result;
2303
2304 /* get the engine clock dividers for this clock value*/
2305 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
2306
2307 PP_ASSERT_WITH_CODE(result == 0,
2308 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2309
2310 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2311 reference_clock = atomctrl_get_reference_clock(hwmgr);
2312
2313 reference_divider = 1 + dividers.uc_pll_ref_div;
2314
2315 /* low 14 bits is fraction and high 12 bits is divider*/
2316 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2317
2318 /* SPLL_FUNC_CNTL setup*/
2319 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2320 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2321 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2322 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
2323
2324 /* SPLL_FUNC_CNTL_3 setup*/
2325 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2326 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2327
2328 /* set to use fractional accumulation*/
2329 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2330 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2331
2332 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2333 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2334 pp_atomctrl_internal_ss_info ss_info;
2335
2336 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2337 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2338 /*
2339 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2340 * ss_info.speed_spectrum_rate -- in unit of khz
2341 */
2342 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2343 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2344
2345 /* clkv = 2 * D * fbdiv / NS */
2346 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2347
2348 cg_spll_spread_spectrum =
2349 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2350 cg_spll_spread_spectrum =
2351 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2352 cg_spll_spread_spectrum_2 =
2353 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2354 }
2355 }
2356
2357 sclk->SclkFrequency = engine_clock;
2358 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2359 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2360 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2361 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2362 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
2363
2364 return 0;
2365}
2366
2367/**
2368 * Populates single SMC SCLK structure using the provided engine clock
2369 *
2370 * @param hwmgr the address of the hardware manager
2371 * @param engine_clock the engine clock to use to populate the structure
2372 * @param sclk the SMC SCLK structure to be populated
2373 */
2374static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2375{
2376 int result;
2377 uint32_t threshold;
2378 uint32_t mvdd;
2379 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2380 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2381
2382 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2383
2384
2385 /* populate graphics levels*/
2386 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2387 pptable_info->vdd_dep_on_sclk, engine_clock,
2388 &graphic_level->MinVoltage, &mvdd);
2389 PP_ASSERT_WITH_CODE((0 == result),
2390 "can not find VDDC voltage value for VDDC \
2391 engine clock dependency table", return result);
2392
2393 /* SCLK frequency in units of 10KHz*/
2394 graphic_level->SclkFrequency = engine_clock;
2395
2396 /* Indicates maximum activity level for this performance level. 50% for now*/
2397 graphic_level->ActivityLevel = sclk_activity_level_threshold;
2398
2399 graphic_level->CcPwrDynRm = 0;
2400 graphic_level->CcPwrDynRm1 = 0;
2401 /* this level can be used if activity is high enough.*/
2402 graphic_level->EnabledForActivity = 0;
2403 /* this level can be used for throttling.*/
2404 graphic_level->EnabledForThrottle = 1;
2405 graphic_level->UpHyst = 0;
2406 graphic_level->DownHyst = 0;
2407 graphic_level->VoltageDownHyst = 0;
2408 graphic_level->PowerThrottle = 0;
2409
2410 threshold = engine_clock * data->fast_watemark_threshold / 100;
2411/*
2412 *get the DAL clock. do it in funture.
2413 PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2414 data->display_timing.min_clock_insr = minClocks.engineClockInSR;
2415
2416 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
2417 {
2418 graphic_level->DeepSleepDivId = PhwTonga_GetSleepDividerIdFromClock(hwmgr, engine_clock, minClocks.engineClockInSR);
2419 }
2420*/
2421
2422 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2423 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2424
2425 if (0 == result) {
2426 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2427 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2428 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2429 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2430 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2431 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2432 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2433 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2434 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2435 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2436 }
2437
2438 return result;
2439}
2440
2441/**
2442 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2443 *
2444 * @param hwmgr the address of the hardware manager
2445 */
2446static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2447{
2448 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2449 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2450 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2451 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2452 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2453 int result = 0;
2454 uint32_t level_array_adress = data->dpm_table_start +
2455 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2456 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2457 SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/
2458 SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2459 uint32_t i, maxEntry;
2460 uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2461 PECI_RegistryValue reg_value;
2462 memset(levels, 0x00, level_array_size);
2463
2464 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2465 result = tonga_populate_single_graphic_level(hwmgr,
2466 dpm_table->sclk_table.dpm_levels[i].value,
2467 (uint16_t)data->activity_target[i],
2468 &(data->smc_state_table.GraphicsLevel[i]));
2469
2470 if (0 != result)
2471 return result;
2472
2473 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2474 if (i > 1)
2475 data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2476
2477 if (0 == i) {
2478 reg_value = 0;
2479 if (reg_value != 0)
2480 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2481 }
2482
2483 if (1 == i) {
2484 reg_value = 0;
2485 if (reg_value != 0)
2486 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2487 }
2488 }
2489
2490 /* Only enable level 0 for now. */
2491 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2492
2493 /* set highest level watermark to high */
2494 if (dpm_table->sclk_table.count > 1)
2495 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2496 PPSMC_DISPLAY_WATERMARK_HIGH;
2497
2498 data->smc_state_table.GraphicsDpmLevelCount =
2499 (uint8_t)dpm_table->sclk_table.count;
2500 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2501 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2502
2503 if (pcie_table != NULL) {
2504 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2505 "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2506 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2507 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2508 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2509 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2510 }
2511 } else {
2512 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2513 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2514
2515 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2516 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2517 (1<<(highest_pcie_level_enabled+1))) != 0)) {
2518 highest_pcie_level_enabled++;
2519 }
2520
2521 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2522 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2523 (1<<lowest_pcie_level_enabled)) == 0)) {
2524 lowest_pcie_level_enabled++;
2525 }
2526
2527 while ((count < highest_pcie_level_enabled) &&
2528 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2529 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2530 count++;
2531 }
2532 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2533 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2534
2535
2536 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2537 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2538 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2539 }
2540
2541 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2542 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2543
2544 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2545 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2546 }
2547 /* level count will send to smc once at init smc table and never change*/
2548 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2549
2550 if (0 != result)
2551 return result;
2552
2553 return 0;
2554}
2555
2556/**
2557 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2558 *
2559 * @param hwmgr the address of the hardware manager
2560 */
2561
2562static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2563{
2564 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2565 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2566 int result;
2567 /* populate MCLK dpm table to SMU7 */
2568 uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2569 uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2570 SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2571 uint32_t i;
2572
2573 memset(levels, 0x00, level_array_size);
2574
2575 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2576 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2577 "can not populate memory level as memory clock is zero", return -1);
2578 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2579 &(data->smc_state_table.MemoryLevel[i]));
2580 if (0 != result) {
2581 return result;
2582 }
2583 }
2584
2585 /* Only enable level 0 for now.*/
2586 data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2587
2588 /*
2589 * in order to prevent MC activity from stutter mode to push DPM up.
2590 * the UVD change complements this by putting the MCLK in a higher state
2591 * by default such that we are not effected by up threshold or and MCLK DPM latency.
2592 */
2593 data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2594 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2595
2596 data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2597 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2598 /* set highest level watermark to high*/
2599 data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2600
2601 /* level count will send to smc once at init smc table and never change*/
2602 result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2603 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2604
2605 if (0 != result) {
2606 return result;
2607 }
2608
2609 return 0;
2610}
2611
2612struct TONGA_DLL_SPEED_SETTING {
2613 uint16_t Min; /* Minimum Data Rate*/
2614 uint16_t Max; /* Maximum Data Rate*/
2615 uint32_t dll_speed; /* The desired DLL_SPEED setting*/
2616};
2617
2618static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2619{
2620 return 0;
2621}
2622
2623/* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2624
2625
2626static int tonga_reset_single_dpm_table(
2627 struct pp_hwmgr *hwmgr,
2628 struct tonga_single_dpm_table *dpm_table,
2629 uint32_t count)
2630{
2631 uint32_t i;
2632 if (!(count <= MAX_REGULAR_DPM_NUMBER))
2633 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2634 table entries to exceed max number! \n");
2635
2636 dpm_table->count = count;
2637 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2638 dpm_table->dpm_levels[i].enabled = 0;
2639 }
2640
2641 return 0;
2642}
2643
2644static void tonga_setup_pcie_table_entry(
2645 struct tonga_single_dpm_table *dpm_table,
2646 uint32_t index, uint32_t pcie_gen,
2647 uint32_t pcie_lanes)
2648{
2649 dpm_table->dpm_levels[index].value = pcie_gen;
2650 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2651 dpm_table->dpm_levels[index].enabled = 1;
2652}
2653
2654bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
2655{
2656 if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2657 return 1;
2658
2659 return 0;
2660}
2661
2662bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
2663{
2664 if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
2665 return 1;
2666
2667 return 0;
2668}
2669
2670/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
2671uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen)
2672{
2673 uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
2674 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
2675 uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &
2676 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
2677
2678 switch (asic_pcie_link_speed_cap) {
2679 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
2680 return PP_PCIEGen1;
2681
2682 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
2683 return PP_PCIEGen2;
2684
2685 case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
2686 return PP_PCIEGen3;
2687
2688 default:
2689 if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
2690 (ns_pcie_gen == PP_PCIEGen3)) {
2691 return PP_PCIEGen3;
2692 } else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
2693 ((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
2694 return PP_PCIEGen2;
2695 }
2696 }
2697
2698 return PP_PCIEGen1;
2699}
2700
2701uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes)
2702{
2703 int i, j;
2704 uint16_t new_pcie_lanes = ns_pcie_lanes;
2705 uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
2706
2707 switch (pcie_lane_width_cap) {
2708 case 0:
2709 printk(KERN_ERR "[ powerplay ] No valid PCIE lane width reported by CAIL!");
2710 break;
2711 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
2712 new_pcie_lanes = 1;
2713 break;
2714 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
2715 new_pcie_lanes = 2;
2716 break;
2717 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
2718 new_pcie_lanes = 4;
2719 break;
2720 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
2721 new_pcie_lanes = 8;
2722 break;
2723 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
2724 new_pcie_lanes = 12;
2725 break;
2726 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
2727 new_pcie_lanes = 16;
2728 break;
2729 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
2730 new_pcie_lanes = 32;
2731 break;
2732 default:
2733 for (i = 0; i < 7; i++) {
2734 if (ns_pcie_lanes == pcie_lanes[i]) {
2735 if (pcie_lane_width_cap & (0x10000 << i)) {
2736 break;
2737 } else {
2738 for (j = i - 1; j >= 0; j--) {
2739 if (pcie_lane_width_cap & (0x10000 << j)) {
2740 new_pcie_lanes = pcie_lanes[j];
2741 break;
2742 }
2743 }
2744
2745 if (j < 0) {
2746 for (j = i + 1; j < 7; j++) {
2747 if (pcie_lane_width_cap & (0x10000 << j)) {
2748 new_pcie_lanes = pcie_lanes[j];
2749 break;
2750 }
2751 }
2752 if (j > 7)
2753 printk(KERN_ERR "[ powerplay ] Cannot find a valid PCIE lane width!");
2754 }
2755 }
2756 break;
2757 }
2758 }
2759 break;
2760 }
2761
2762 return new_pcie_lanes;
2763}
2764
2765static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2766{
2767 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2768 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2769 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2770 uint32_t i, maxEntry;
2771
2772 if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2773 data->pcie_gen_power_saving = data->pcie_gen_performance;
2774 data->pcie_lane_power_saving = data->pcie_lane_performance;
2775 } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2776 data->pcie_gen_performance = data->pcie_gen_power_saving;
2777 data->pcie_lane_performance = data->pcie_lane_power_saving;
2778 }
2779
2780 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2781
2782 if (pcie_table != NULL) {
2783 /*
2784 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2785 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2786 */
2787 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2788 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2789 for (i = 1; i < maxEntry; i++) {
2790 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2791 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2792 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2793 }
2794 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2795 } else {
2796 /* Hardcode Pcie Table */
2797 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2798 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2799 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2800 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2801 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2802 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2803 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2804 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2805 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2806 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2807 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2808 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2809 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2810 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2811 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2812 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2813 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2814 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2815 data->dpm_table.pcie_speed_table.count = 6;
2816 }
2817 /* Populate last level for boot PCIE level, but do not increment count. */
2818 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2819 data->dpm_table.pcie_speed_table.count,
2820 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2821 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2822
2823 return 0;
2824
2825}
2826
2827/*
2828 * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2829 * Dynamic state patching function will then trim these state tables to the allowed range based
2830 * on the power policy or external client requests, such as UVD request, etc.
2831 */
2832static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2833{
2834 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2835 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2836 uint32_t i;
2837
2838 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2839 pptable_info->vdd_dep_on_sclk;
2840 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2841 pptable_info->vdd_dep_on_mclk;
2842
2843 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2844 "SCLK dependency table is missing. This table is mandatory", return -1);
2845 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2846 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2847
2848 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2849 "MCLK dependency table is missing. This table is mandatory", return -1);
2850 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2851 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2852
2853 /* clear the state table to reset everything to default */
2854 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2855 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2856 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2857 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2858 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2859 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2860 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2861
2862 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2863 "SCLK dependency table is missing. This table is mandatory", return -1);
2864 /* Initialize Sclk DPM table based on allow Sclk values*/
2865 data->dpm_table.sclk_table.count = 0;
2866
2867 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2868 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2869 allowed_vdd_sclk_table->entries[i].clk) {
2870 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2871 allowed_vdd_sclk_table->entries[i].clk;
2872 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
2873 data->dpm_table.sclk_table.count++;
2874 }
2875 }
2876
2877 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2878 "MCLK dependency table is missing. This table is mandatory", return -1);
2879 /* Initialize Mclk DPM table based on allow Mclk values */
2880 data->dpm_table.mclk_table.count = 0;
2881 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2882 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2883 allowed_vdd_mclk_table->entries[i].clk) {
2884 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2885 allowed_vdd_mclk_table->entries[i].clk;
2886 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
2887 data->dpm_table.mclk_table.count++;
2888 }
2889 }
2890
2891 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
2892 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2893 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
2894 /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
2895 /* param1 is for corresponding std voltage */
2896 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
2897 }
2898 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
2899
2900 if (NULL != allowed_vdd_mclk_table) {
2901 /* Initialize Vddci DPM table based on allow Mclk values */
2902 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2903 data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
2904 data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
2905 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
2906 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
2907 }
2908 data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
2909 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
2910 }
2911
2912 /* setup PCIE gen speed levels*/
2913 tonga_setup_default_pcie_tables(hwmgr);
2914
2915 /* save a copy of the default DPM table*/
2916 memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2917
2918 return 0;
2919}
2920
2921int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2922 const struct tonga_power_state *bootState)
2923{
2924 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2925 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2926 uint8_t count, level;
2927
2928 count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2929 for (level = 0; level < count; level++) {
2930 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2931 bootState->performance_levels[0].engine_clock) {
2932 data->smc_state_table.GraphicsBootLevel = level;
2933 break;
2934 }
2935 }
2936
2937 count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2938 for (level = 0; level < count; level++) {
2939 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2940 bootState->performance_levels[0].memory_clock) {
2941 data->smc_state_table.MemoryBootLevel = level;
2942 break;
2943 }
2944 }
2945
2946 return 0;
2947}
2948
2949/**
2950 * Initializes the SMC table and uploads it
2951 *
2952 * @param hwmgr the address of the powerplay hardware manager.
2953 * @param pInput the pointer to input data (PowerState)
2954 * @return always 0
2955 */
2956int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2957{
2958 int result;
2959 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2960 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2961 SMU72_Discrete_DpmTable *table = &(data->smc_state_table);
2962 const phw_tonga_ulv_parm *ulv = &(data->ulv);
2963 uint8_t i;
2964 PECI_RegistryValue reg_value;
2965 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2966
2967 result = tonga_setup_default_dpm_tables(hwmgr);
2968 PP_ASSERT_WITH_CODE(0 == result,
2969 "Failed to setup default DPM tables!", return result;);
2970 memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2971 if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2972 tonga_populate_smc_voltage_tables(hwmgr, table);
2973 }
2974
2975 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2976 PHM_PlatformCaps_AutomaticDCTransition)) {
2977 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2978 }
2979
2980 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2981 PHM_PlatformCaps_StepVddc)) {
2982 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2983 }
2984
2985 if (data->is_memory_GDDR5) {
2986 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2987 }
2988
2989 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2990
2991 if (i == 1 || i == 0) {
2992 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2993 }
2994
2995 if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2996 PP_ASSERT_WITH_CODE(0 == result,
2997 "Failed to initialize ULV state!", return result;);
2998
2999 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3000 ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
3001 }
3002
3003 result = tonga_populate_smc_link_level(hwmgr, table);
3004 PP_ASSERT_WITH_CODE(0 == result,
3005 "Failed to initialize Link Level!", return result;);
3006
3007 result = tonga_populate_all_graphic_levels(hwmgr);
3008 PP_ASSERT_WITH_CODE(0 == result,
3009 "Failed to initialize Graphics Level!", return result;);
3010
3011 result = tonga_populate_all_memory_levels(hwmgr);
3012 PP_ASSERT_WITH_CODE(0 == result,
3013 "Failed to initialize Memory Level!", return result;);
3014
3015 result = tonga_populate_smv_acpi_level(hwmgr, table);
3016 PP_ASSERT_WITH_CODE(0 == result,
3017 "Failed to initialize ACPI Level!", return result;);
3018
3019 result = tonga_populate_smc_vce_level(hwmgr, table);
3020 PP_ASSERT_WITH_CODE(0 == result,
3021 "Failed to initialize VCE Level!", return result;);
3022
3023 result = tonga_populate_smc_acp_level(hwmgr, table);
3024 PP_ASSERT_WITH_CODE(0 == result,
3025 "Failed to initialize ACP Level!", return result;);
3026
3027 result = tonga_populate_smc_samu_level(hwmgr, table);
3028 PP_ASSERT_WITH_CODE(0 == result,
3029 "Failed to initialize SAMU Level!", return result;);
3030
3031 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
3032 /* need to populate the ARB settings for the initial state. */
3033 result = tonga_program_memory_timing_parameters(hwmgr);
3034 PP_ASSERT_WITH_CODE(0 == result,
3035 "Failed to Write ARB settings for the initial state.", return result;);
3036
3037 result = tonga_populate_smc_boot_level(hwmgr, table);
3038 PP_ASSERT_WITH_CODE(0 == result,
3039 "Failed to initialize Boot Level!", return result;);
3040
3041 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3042 PHM_PlatformCaps_ClockStretcher)) {
3043 result = tonga_populate_clock_stretcher_data_table(hwmgr);
3044 PP_ASSERT_WITH_CODE(0 == result,
3045 "Failed to populate Clock Stretcher Data Table!", return result;);
3046 }
3047 table->GraphicsVoltageChangeEnable = 1;
3048 table->GraphicsThermThrottleEnable = 1;
3049 table->GraphicsInterval = 1;
3050 table->VoltageInterval = 1;
3051 table->ThermalInterval = 1;
3052 table->TemperatureLimitHigh =
3053 pptable_info->cac_dtp_table->usTargetOperatingTemp *
3054 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3055 table->TemperatureLimitLow =
3056 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3057 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3058 table->MemoryVoltageChangeEnable = 1;
3059 table->MemoryInterval = 1;
3060 table->VoltageResponseTime = 0;
3061 table->PhaseResponseTime = 0;
3062 table->MemoryThermThrottleEnable = 1;
3063
3064 /*
3065 * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3066 * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3067 * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3068 * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3069 */
3070 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3071 "There must be 1 or more PCIE levels defined in PPTable.",
3072 return -1);
3073
3074 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3075
3076 table->PCIeGenInterval = 1;
3077
3078 result = tonga_populate_vr_config(hwmgr, table);
3079 PP_ASSERT_WITH_CODE(0 == result,
3080 "Failed to populate VRConfig setting!", return result);
3081
3082 table->ThermGpio = 17;
3083 table->SclkStepSize = 0x4000;
3084
3085 reg_value = 0;
3086 if ((0 == reg_value) &&
3087 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3088 VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
3089 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3090 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3091 PHM_PlatformCaps_RegulatorHot);
3092 } else {
3093 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3094 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3095 PHM_PlatformCaps_RegulatorHot);
3096 }
3097
3098 /* ACDC Switch GPIO */
3099 reg_value = 0;
3100 if ((0 == reg_value) &&
3101 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3102 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
3103 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3104 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3105 PHM_PlatformCaps_AutomaticDCTransition);
3106 } else {
3107 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3108 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3109 PHM_PlatformCaps_AutomaticDCTransition);
3110 }
3111
3112 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3113 PHM_PlatformCaps_Falcon_QuickTransition);
3114
3115 reg_value = 0;
3116 if (1 == reg_value) {
3117 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3118 PHM_PlatformCaps_AutomaticDCTransition);
3119 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3120 PHM_PlatformCaps_Falcon_QuickTransition);
3121 }
3122
3123 reg_value = 0;
3124 if ((0 == reg_value) &&
3125 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3126 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3127 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3128 PHM_PlatformCaps_ThermalOutGPIO);
3129
3130 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3131
3132 table->ThermOutPolarity =
3133 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3134 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3135
3136 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3137
3138 /* if required, combine VRHot/PCC with thermal out GPIO*/
3139 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3140 PHM_PlatformCaps_RegulatorHot) &&
3141 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3142 PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3143 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3144 }
3145 } else {
3146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3147 PHM_PlatformCaps_ThermalOutGPIO);
3148
3149 table->ThermOutGpio = 17;
3150 table->ThermOutPolarity = 1;
3151 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3152 }
3153
3154 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3155 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3156 }
3157 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3158 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3159 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3160 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3161 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3162 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3163 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3164 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3165 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3166
3167 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3168 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3169 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3170 (uint8_t *)&(table->SystemFlags),
3171 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3172 data->sram_end);
3173
3174 PP_ASSERT_WITH_CODE(0 == result,
3175 "Failed to upload dpm data to SMC memory!", return result;);
3176
3177 return result;
3178}
3179
3180/* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3181static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3182{
3183 return;
3184}
3185
3186int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3187{
3188 PPSMC_Result result;
3189 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3190
3191 /* Apply minimum voltage based on DAL's request level */
3192 tonga_apply_dal_minimum_voltage_request(hwmgr);
3193
3194 if (0 == data->sclk_dpm_key_disabled) {
3195 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3196 if (0 != tonga_is_dpm_running(hwmgr))
3197 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3198
3199 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3200 result = smum_send_msg_to_smc_with_parameter(
3201 hwmgr->smumgr,
3202 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3203 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3204 PP_ASSERT_WITH_CODE((0 == result),
3205 "Set Sclk Dpm enable Mask failed", return -1);
3206 }
3207 }
3208
3209 if (0 == data->mclk_dpm_key_disabled) {
3210 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3211 if (0 != tonga_is_dpm_running(hwmgr))
3212 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3213
3214 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3215 result = smum_send_msg_to_smc_with_parameter(
3216 hwmgr->smumgr,
3217 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3218 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3219 PP_ASSERT_WITH_CODE((0 == result),
3220 "Set Mclk Dpm enable Mask failed", return -1);
3221 }
3222 }
3223
3224 return 0;
3225}
3226
3227
3228int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3229{
3230 uint32_t level, tmp;
3231 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3232
3233 if (0 == data->pcie_dpm_key_disabled) {
3234 /* PCIE */
3235 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3236 level = 0;
3237 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3238 while (tmp >>= 1)
3239 level++ ;
3240
3241 if (0 != level) {
3242 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3243 "force highest pcie dpm state failed!", return -1);
3244 }
3245 }
3246 }
3247
3248 if (0 == data->sclk_dpm_key_disabled) {
3249 /* SCLK */
3250 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3251 level = 0;
3252 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3253 while (tmp >>= 1)
3254 level++ ;
3255
3256 if (0 != level) {
3257 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3258 "force highest sclk dpm state failed!", return -1);
3259 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3260 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3261 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3262 Curr_Sclk_Index does not match the level \n");
3263
3264 }
3265 }
3266 }
3267
3268 if (0 == data->mclk_dpm_key_disabled) {
3269 /* MCLK */
3270 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3271 level = 0;
3272 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3273 while (tmp >>= 1)
3274 level++ ;
3275
3276 if (0 != level) {
3277 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3278 "force highest mclk dpm state failed!", return -1);
3279 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3280 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3281 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3282 Curr_Sclk_Index does not match the level \n");
3283 }
3284 }
3285 }
3286
3287 return 0;
3288}
3289
3290/**
3291 * Find the MC microcode version and store it in the HwMgr struct
3292 *
3293 * @param hwmgr the address of the powerplay hardware manager.
3294 * @return always 0
3295 */
3296int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3297{
3298 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3299
3300 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3301
3302 return 0;
3303}
3304
3305/**
3306 * Initialize Dynamic State Adjustment Rule Settings
3307 *
3308 * @param hwmgr the address of the powerplay hardware manager.
3309 */
3310int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3311{
3312 uint32_t table_size;
3313 struct phm_clock_voltage_dependency_table *table_clk_vlt;
3314 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3315
3316 hwmgr->dyn_state.mclk_sclk_ratio = 4;
3317 hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */
3318 hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */
3319
3320 /* initialize vddc_dep_on_dal_pwrl table */
3321 table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3322 table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3323
3324 if (NULL == table_clk_vlt) {
3325 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3326 return -ENOMEM;
3327 } else {
3328 table_clk_vlt->count = 4;
3329 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3330 table_clk_vlt->entries[0].v = 0;
3331 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3332 table_clk_vlt->entries[1].v = 720;
3333 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3334 table_clk_vlt->entries[2].v = 810;
3335 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3336 table_clk_vlt->entries[3].v = 900;
3337 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3338 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3339 }
3340
3341 return 0;
3342}
3343
3344static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3345{
3346 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3347 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3348
3349 phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3350 pptable_info->vdd_dep_on_sclk;
3351 phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3352 pptable_info->vdd_dep_on_mclk;
3353
3354 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3355 "VDD dependency on SCLK table is missing. \
3356 This table is mandatory", return -1);
3357 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3358 "VDD dependency on SCLK table has to have is missing. \
3359 This table is mandatory", return -1);
3360
3361 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3362 "VDD dependency on MCLK table is missing. \
3363 This table is mandatory", return -1);
3364 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3365 "VDD dependency on MCLK table has to have is missing. \
3366 This table is mandatory", return -1);
3367
3368 data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3369 data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3370
3371 pptable_info->max_clock_voltage_on_ac.sclk =
3372 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3373 pptable_info->max_clock_voltage_on_ac.mclk =
3374 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3375 pptable_info->max_clock_voltage_on_ac.vddc =
3376 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3377 pptable_info->max_clock_voltage_on_ac.vddci =
3378 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3379
3380 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3381 pptable_info->max_clock_voltage_on_ac.sclk;
3382 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3383 pptable_info->max_clock_voltage_on_ac.mclk;
3384 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3385 pptable_info->max_clock_voltage_on_ac.vddc;
3386 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3387 pptable_info->max_clock_voltage_on_ac.vddci;
3388
3389 return 0;
3390}
3391
3392int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3393{
3394 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3395 int result = 1;
3396
3397 PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
3398 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3399 return result);
3400
3401 if (0 == data->pcie_dpm_key_disabled) {
3402 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3403 hwmgr->smumgr,
3404 PPSMC_MSG_PCIeDPM_UnForceLevel)),
3405 "unforce pcie level failed!",
3406 return -1);
3407 }
3408
3409 result = tonga_upload_dpm_level_enable_mask(hwmgr);
3410
3411 return result;
3412}
3413
3414static uint32_t tonga_get_lowest_enable_level(
3415 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3416{
3417 uint32_t level = 0;
3418
3419 while (0 == (level_mask & (1 << level)))
3420 level++;
3421
3422 return level;
3423}
3424
3425static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3426{
3427 uint32_t level = 0;
3428 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3429
3430 /* for now force only sclk */
3431 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3432 level = tonga_get_lowest_enable_level(hwmgr,
3433 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3434
3435 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3436 "force sclk dpm state failed!", return -1);
3437
3438 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3439 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3440 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3441 Curr_Sclk_Index does not match the level \n");
3442 }
3443
3444 return 0;
3445}
3446
3447static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3448{
3449 uint8_t entryId;
3450 uint8_t voltageId;
3451 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3452 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3453
3454 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3455 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3456 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3457
3458 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3459 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3460 voltageId = sclk_table->entries[entryId].vddInd;
3461 sclk_table->entries[entryId].vddgfx =
3462 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3463 }
3464 } else {
3465 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3466 voltageId = sclk_table->entries[entryId].vddInd;
3467 sclk_table->entries[entryId].vddc =
3468 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3469 }
3470 }
3471
3472 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3473 voltageId = mclk_table->entries[entryId].vddInd;
3474 mclk_table->entries[entryId].vddc =
3475 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3476 }
3477
3478 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3479 voltageId = mm_table->entries[entryId].vddcInd;
3480 mm_table->entries[entryId].vddc =
3481 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3482 }
3483
3484 return 0;
3485
3486}
3487
3488static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3489{
3490 uint8_t entryId;
3491 phm_ppt_v1_voltage_lookup_record v_record;
3492 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3493 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3494
3495 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3496 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3497
3498 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3499 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3500 if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3501 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3502 sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3503 else
3504 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3505 sclk_table->entries[entryId].vdd_offset;
3506
3507 sclk_table->entries[entryId].vddc =
3508 v_record.us_cac_low = v_record.us_cac_mid =
3509 v_record.us_cac_high = v_record.us_vdd;
3510
3511 tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3512 }
3513
3514 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3515 if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3516 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3517 mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3518 else
3519 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3520 mclk_table->entries[entryId].vdd_offset;
3521
3522 mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3523 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3524 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3525 }
3526 }
3527
3528 return 0;
3529
3530}
3531
3532static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3533{
3534 uint32_t entryId;
3535 phm_ppt_v1_voltage_lookup_record v_record;
3536 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3537 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3538 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3539
3540 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3541 for (entryId = 0; entryId < mm_table->count; entryId++) {
3542 if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3543 v_record.us_vdd = mm_table->entries[entryId].vddc +
3544 mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3545 else
3546 v_record.us_vdd = mm_table->entries[entryId].vddc +
3547 mm_table->entries[entryId].vddgfx_offset;
3548
3549 /* Add the calculated VDDGFX to the VDDGFX lookup table */
3550 mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3551 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3552 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3553 }
3554 }
3555 return 0;
3556}
3557
3558
3559/**
3560 * Change virtual leakage voltage to actual value.
3561 *
3562 * @param hwmgr the address of the powerplay hardware manager.
3563 * @param pointer to changing voltage
3564 * @param pointer to leakage table
3565 */
3566static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3567 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3568{
3569 uint32_t leakage_index;
3570
3571 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3572 for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3573 /* if this voltage matches a leakage voltage ID */
3574 /* patch with actual leakage voltage */
3575 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3576 *voltage = pLeakageTable->actual_voltage[leakage_index];
3577 break;
3578 }
3579 }
3580
3581 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3582 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3583}
3584
3585/**
3586 * Patch voltage lookup table by EVV leakages.
3587 *
3588 * @param hwmgr the address of the powerplay hardware manager.
3589 * @param pointer to voltage lookup table
3590 * @param pointer to leakage table
3591 * @return always 0
3592 */
3593static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3594 phm_ppt_v1_voltage_lookup_table *lookup_table,
3595 phw_tonga_leakage_voltage *pLeakageTable)
3596{
3597 uint32_t i;
3598
3599 for (i = 0; i < lookup_table->count; i++) {
3600 tonga_patch_with_vdd_leakage(hwmgr,
3601 &lookup_table->entries[i].us_vdd, pLeakageTable);
3602 }
3603
3604 return 0;
3605}
3606
3607static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3608 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3609{
3610 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3611
3612 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3613 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3614 pptable_info->max_clock_voltage_on_dc.vddc;
3615
3616 return 0;
3617}
3618
3619static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3620 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3621 uint16_t *Vddgfx)
3622{
3623 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3624 return 0;
3625}
3626
3627int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3628 phm_ppt_v1_voltage_lookup_table *lookup_table)
3629{
3630 uint32_t table_size, i, j;
3631 phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3632 table_size = lookup_table->count;
3633
3634 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3635 "Lookup table is empty", return -1);
3636
3637 /* Sorting voltages */
3638 for (i = 0; i < table_size - 1; i++) {
3639 for (j = i + 1; j > 0; j--) {
3640 if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3641 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3642 lookup_table->entries[j-1] = lookup_table->entries[j];
3643 lookup_table->entries[j] = tmp_voltage_lookup_record;
3644 }
3645 }
3646 }
3647
3648 return 0;
3649}
3650
3651static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3652{
3653 int result = 0;
3654 int tmp_result;
3655 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3656 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3657
3658 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3659 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3660 pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3661 if (tmp_result != 0)
3662 result = tmp_result;
3663
3664 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3665 &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3666 if (tmp_result != 0)
3667 result = tmp_result;
3668 } else {
3669 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3670 pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3671 if (tmp_result != 0)
3672 result = tmp_result;
3673
3674 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3675 &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3676 if (tmp_result != 0)
3677 result = tmp_result;
3678 }
3679
3680 tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3681 if (tmp_result != 0)
3682 result = tmp_result;
3683
3684 tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3685 if (tmp_result != 0)
3686 result = tmp_result;
3687
3688 tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3689 if (tmp_result != 0)
3690 result = tmp_result;
3691
3692 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3693 if (tmp_result != 0)
3694 result = tmp_result;
3695
3696 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3697 if (tmp_result != 0)
3698 result = tmp_result;
3699
3700 return result;
3701}
3702
3703int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3704{
3705 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3706 data->low_sclk_interrupt_threshold = 0;
3707
3708 return 0;
3709}
3710
3711int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3712{
3713 int tmp_result, result = 0;
3714
3715 tmp_result = tonga_read_clock_registers(hwmgr);
3716 PP_ASSERT_WITH_CODE((0 == tmp_result),
3717 "Failed to read clock registers!", result = tmp_result);
3718
3719 tmp_result = tonga_get_memory_type(hwmgr);
3720 PP_ASSERT_WITH_CODE((0 == tmp_result),
3721 "Failed to get memory type!", result = tmp_result);
3722
3723 tmp_result = tonga_enable_acpi_power_management(hwmgr);
3724 PP_ASSERT_WITH_CODE((0 == tmp_result),
3725 "Failed to enable ACPI power management!", result = tmp_result);
3726
3727 tmp_result = tonga_init_power_gate_state(hwmgr);
3728 PP_ASSERT_WITH_CODE((0 == tmp_result),
3729 "Failed to init power gate state!", result = tmp_result);
3730
3731 tmp_result = tonga_get_mc_microcode_version(hwmgr);
3732 PP_ASSERT_WITH_CODE((0 == tmp_result),
3733 "Failed to get MC microcode version!", result = tmp_result);
3734
3735 tmp_result = tonga_init_sclk_threshold(hwmgr);
3736 PP_ASSERT_WITH_CODE((0 == tmp_result),
3737 "Failed to init sclk threshold!", result = tmp_result);
3738
3739 return result;
3740}
3741
3742/**
3743 * Enable voltage control
3744 *
3745 * @param hwmgr the address of the powerplay hardware manager.
3746 * @return always 0
3747 */
3748int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3749{
3750 /* enable voltage control */
3751 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3752
3753 return 0;
3754}
3755
3756/**
3757 * Checks if we want to support voltage control
3758 *
3759 * @param hwmgr the address of the powerplay hardware manager.
3760 */
3761bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3762{
3763 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3764
3765 return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3766}
3767
3768/*---------------------------MC----------------------------*/
3769
3770uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3771{
3772 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3773}
3774
3775bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3776{
3777 bool result = 1;
3778
3779 switch (inReg) {
3780 case mmMC_SEQ_RAS_TIMING:
3781 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3782 break;
3783
3784 case mmMC_SEQ_DLL_STBY:
3785 *outReg = mmMC_SEQ_DLL_STBY_LP;
3786 break;
3787
3788 case mmMC_SEQ_G5PDX_CMD0:
3789 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3790 break;
3791
3792 case mmMC_SEQ_G5PDX_CMD1:
3793 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3794 break;
3795
3796 case mmMC_SEQ_G5PDX_CTRL:
3797 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3798 break;
3799
3800 case mmMC_SEQ_CAS_TIMING:
3801 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3802 break;
3803
3804 case mmMC_SEQ_MISC_TIMING:
3805 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3806 break;
3807
3808 case mmMC_SEQ_MISC_TIMING2:
3809 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3810 break;
3811
3812 case mmMC_SEQ_PMG_DVS_CMD:
3813 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3814 break;
3815
3816 case mmMC_SEQ_PMG_DVS_CTL:
3817 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3818 break;
3819
3820 case mmMC_SEQ_RD_CTL_D0:
3821 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3822 break;
3823
3824 case mmMC_SEQ_RD_CTL_D1:
3825 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3826 break;
3827
3828 case mmMC_SEQ_WR_CTL_D0:
3829 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3830 break;
3831
3832 case mmMC_SEQ_WR_CTL_D1:
3833 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3834 break;
3835
3836 case mmMC_PMG_CMD_EMRS:
3837 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3838 break;
3839
3840 case mmMC_PMG_CMD_MRS:
3841 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3842 break;
3843
3844 case mmMC_PMG_CMD_MRS1:
3845 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3846 break;
3847
3848 case mmMC_SEQ_PMG_TIMING:
3849 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3850 break;
3851
3852 case mmMC_PMG_CMD_MRS2:
3853 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3854 break;
3855
3856 case mmMC_SEQ_WR_CTL_2:
3857 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3858 break;
3859
3860 default:
3861 result = 0;
3862 break;
3863 }
3864
3865 return result;
3866}
3867
3868int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3869{
3870 uint32_t i;
3871 uint16_t address;
3872
3873 for (i = 0; i < table->last; i++) {
3874 table->mc_reg_address[i].s0 =
3875 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3876 ? address : table->mc_reg_address[i].s1;
3877 }
3878 return 0;
3879}
3880
3881int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3882{
3883 uint8_t i, j;
3884
3885 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3886 "Invalid VramInfo table.", return -1);
3887 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3888 "Invalid VramInfo table.", return -1);
3889
3890 for (i = 0; i < table->last; i++) {
3891 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3892 }
3893 ni_table->last = table->last;
3894
3895 for (i = 0; i < table->num_entries; i++) {
3896 ni_table->mc_reg_table_entry[i].mclk_max =
3897 table->mc_reg_table_entry[i].mclk_max;
3898 for (j = 0; j < table->last; j++) {
3899 ni_table->mc_reg_table_entry[i].mc_data[j] =
3900 table->mc_reg_table_entry[i].mc_data[j];
3901 }
3902 }
3903 ni_table->num_entries = table->num_entries;
3904
3905 return 0;
3906}
3907
3908/**
3909 * VBIOS omits some information to reduce size, we need to recover them here.
3910 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3911 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3912 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3913 * 3. need to set these data for each clock range
3914 *
3915 * @param hwmgr the address of the powerplay hardware manager.
3916 * @param table the address of MCRegTable
3917 * @return always 0
3918 */
3919int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3920{
3921 uint8_t i, j, k;
3922 uint32_t temp_reg;
3923 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3924
3925 for (i = 0, j = table->last; i < table->last; i++) {
3926 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3927 "Invalid VramInfo table.", return -1);
3928 switch (table->mc_reg_address[i].s1) {
3929 /*
3930 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3931 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3932 */
3933 case mmMC_SEQ_MISC1:
3934 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3935 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3936 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3937 for (k = 0; k < table->num_entries; k++) {
3938 table->mc_reg_table_entry[k].mc_data[j] =
3939 ((temp_reg & 0xffff0000)) |
3940 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3941 }
3942 j++;
3943 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3944 "Invalid VramInfo table.", return -1);
3945
3946 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3947 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3948 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3949 for (k = 0; k < table->num_entries; k++) {
3950 table->mc_reg_table_entry[k].mc_data[j] =
3951 (temp_reg & 0xffff0000) |
3952 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3953
3954 if (!data->is_memory_GDDR5) {
3955 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3956 }
3957 }
3958 j++;
3959 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3960 "Invalid VramInfo table.", return -1);
3961
3962 if (!data->is_memory_GDDR5) {
3963 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3964 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3965 for (k = 0; k < table->num_entries; k++) {
3966 table->mc_reg_table_entry[k].mc_data[j] =
3967 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3968 }
3969 j++;
3970 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3971 "Invalid VramInfo table.", return -1);
3972 }
3973
3974 break;
3975
3976 case mmMC_SEQ_RESERVE_M:
3977 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3978 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3979 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3980 for (k = 0; k < table->num_entries; k++) {
3981 table->mc_reg_table_entry[k].mc_data[j] =
3982 (temp_reg & 0xffff0000) |
3983 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3984 }
3985 j++;
3986 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3987 "Invalid VramInfo table.", return -1);
3988 break;
3989
3990 default:
3991 break;
3992 }
3993
3994 }
3995
3996 table->last = j;
3997
3998 return 0;
3999}
4000
4001int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
4002{
4003 uint8_t i, j;
4004 for (i = 0; i < table->last; i++) {
4005 for (j = 1; j < table->num_entries; j++) {
4006 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4007 table->mc_reg_table_entry[j].mc_data[i]) {
4008 table->validflag |= (1<<i);
4009 break;
4010 }
4011 }
4012 }
4013
4014 return 0;
4015}
4016
4017int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
4018{
4019 int result;
4020 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4021 pp_atomctrl_mc_reg_table *table;
4022 phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
4023 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
4024
4025 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
4026
4027 if (NULL == table)
4028 return -1;
4029
4030 /* Program additional LP registers that are no longer programmed by VBIOS */
4031 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4032 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4033 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4034 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4035 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4036 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4037 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4038 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4039 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4040 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4041 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4042 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4043 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4044 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4045 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4046 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4047 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4048 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4049 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4050 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4051
4052 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4053
4054 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4055
4056 if (0 == result)
4057 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4058
4059 if (0 == result) {
4060 tonga_set_s0_mc_reg_index(ni_table);
4061 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4062 }
4063
4064 if (0 == result)
4065 tonga_set_valid_flag(ni_table);
4066
4067 kfree(table);
4068 return result;
4069}
4070
4071/*
4072* Copy one arb setting to another and then switch the active set.
4073* arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4074*/
4075int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4076 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4077{
4078 uint32_t mc_arb_dram_timing;
4079 uint32_t mc_arb_dram_timing2;
4080 uint32_t burst_time;
4081 uint32_t mc_cg_config;
4082
4083 switch (arbFreqSrc) {
4084 case MC_CG_ARB_FREQ_F0:
4085 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4086 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4087 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4088 break;
4089
4090 case MC_CG_ARB_FREQ_F1:
4091 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4092 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4093 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4094 break;
4095
4096 default:
4097 return -1;
4098 }
4099
4100 switch (arbFreqDest) {
4101 case MC_CG_ARB_FREQ_F0:
4102 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4103 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4104 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4105 break;
4106
4107 case MC_CG_ARB_FREQ_F1:
4108 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4109 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4110 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4111 break;
4112
4113 default:
4114 return -1;
4115 }
4116
4117 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4118 mc_cg_config |= 0x0000000F;
4119 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4120 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4121
4122 return 0;
4123}
4124
4125/**
4126 * Initial switch from ARB F0->F1
4127 *
4128 * @param hwmgr the address of the powerplay hardware manager.
4129 * @return always 0
4130 * This function is to be called from the SetPowerState table.
4131 */
4132int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4133{
4134 return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4135}
4136
4137/**
4138 * Initialize the ARB DRAM timing table's index field.
4139 *
4140 * @param hwmgr the address of the powerplay hardware manager.
4141 * @return always 0
4142 */
4143int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4144{
4145 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4146 uint32_t tmp;
4147 int result;
4148
4149 /*
4150 * This is a read-modify-write on the first byte of the ARB table.
4151 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4152 * This solution is ugly, but we never write the whole table only individual fields in it.
4153 * In reality this field should not be in that structure but in a soft register.
4154 */
4155 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4156 data->arb_table_start, &tmp, data->sram_end);
4157
4158 if (0 != result)
4159 return result;
4160
4161 tmp &= 0x00FFFFFF;
4162 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4163
4164 return tonga_write_smc_sram_dword(hwmgr->smumgr,
4165 data->arb_table_start, tmp, data->sram_end);
4166}
4167
4168int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4169{
4170 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4171
4172 uint32_t i, j;
4173
4174 for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4175 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4176 PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4177 "Index of mc_reg_table->address[] array out of boundary", return -1);
4178 mc_reg_table->address[i].s0 =
4179 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4180 mc_reg_table->address[i].s1 =
4181 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4182 i++;
4183 }
4184 }
4185
4186 mc_reg_table->last = (uint8_t)i;
4187
4188 return 0;
4189}
4190
4191/*convert register values from driver to SMC format */
4192void tonga_convert_mc_registers(
4193 const phw_tonga_mc_reg_entry * pEntry,
4194 SMU72_Discrete_MCRegisterSet *pData,
4195 uint32_t numEntries, uint32_t validflag)
4196{
4197 uint32_t i, j;
4198
4199 for (i = 0, j = 0; j < numEntries; j++) {
4200 if (validflag & 1<<j) {
4201 pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4202 i++;
4203 }
4204 }
4205}
4206
4207/* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4208int tonga_convert_mc_reg_table_entry_to_smc(
4209 struct pp_hwmgr *hwmgr,
4210 const uint32_t memory_clock,
4211 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4212 )
4213{
4214 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4215 uint32_t i = 0;
4216
4217 for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4218 if (memory_clock <=
4219 data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4220 break;
4221 }
4222 }
4223
4224 if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4225 --i;
4226
4227 tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4228 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4229
4230 return 0;
4231}
4232
4233int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4234 SMU72_Discrete_MCRegisters *mc_reg_table)
4235{
4236 int result = 0;
4237 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4238 int res;
4239 uint32_t i;
4240
4241 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4242 res = tonga_convert_mc_reg_table_entry_to_smc(
4243 hwmgr,
4244 data->dpm_table.mclk_table.dpm_levels[i].value,
4245 &mc_reg_table->data[i]
4246 );
4247
4248 if (0 != res)
4249 result = res;
4250 }
4251
4252 return result;
4253}
4254
4255int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4256{
4257 int result;
4258 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4259
4260 memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4261 result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4262 PP_ASSERT_WITH_CODE(0 == result,
4263 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4264
4265 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4266 PP_ASSERT_WITH_CODE(0 == result,
4267 "Failed to initialize MCRegTable for driver state!", return result;);
4268
4269 return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4270 (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4271}
4272
4273/**
4274 * Programs static screed detection parameters
4275 *
4276 * @param hwmgr the address of the powerplay hardware manager.
4277 * @return always 0
4278 */
4279int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4280{
4281 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4282
4283 /* Set static screen threshold unit*/
4284 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4285 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4286 data->static_screen_threshold_unit);
4287 /* Set static screen threshold*/
4288 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4289 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4290 data->static_screen_threshold);
4291
4292 return 0;
4293}
4294
4295/**
4296 * Setup display gap for glitch free memory clock switching.
4297 *
4298 * @param hwmgr the address of the powerplay hardware manager.
4299 * @return always 0
4300 */
4301int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4302{
4303 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4304 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4305
4306 display_gap = PHM_SET_FIELD(display_gap,
4307 CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4308
4309 display_gap = PHM_SET_FIELD(display_gap,
4310 CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4311
4312 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4313 ixCG_DISPLAY_GAP_CNTL, display_gap);
4314
4315 return 0;
4316}
4317
4318/**
4319 * Programs activity state transition voting clients
4320 *
4321 * @param hwmgr the address of the powerplay hardware manager.
4322 * @return always 0
4323 */
4324int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4325{
4326 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4327
4328 /* Clear reset for voting clients before enabling DPM */
4329 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4330 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4331 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4332 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4333
4334 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4335 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4336 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4337 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4338 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4339 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4340 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4341 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4342 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4343 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4344 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4345 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4346 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4347 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4348 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4349 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4350
4351 return 0;
4352}
4353
4354
4355int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4356{
4357 int tmp_result, result = 0;
4358
4359 tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4360
4361 if (cf_tonga_voltage_control(hwmgr)) {
4362 tmp_result = tonga_enable_voltage_control(hwmgr);
4363 PP_ASSERT_WITH_CODE((0 == tmp_result),
4364 "Failed to enable voltage control!", result = tmp_result);
4365
4366 tmp_result = tonga_construct_voltage_tables(hwmgr);
4367 PP_ASSERT_WITH_CODE((0 == tmp_result),
4368 "Failed to contruct voltage tables!", result = tmp_result);
4369 }
4370
4371 tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4372 PP_ASSERT_WITH_CODE((0 == tmp_result),
4373 "Failed to initialize MC reg table!", result = tmp_result);
4374
4375 tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4376 PP_ASSERT_WITH_CODE((0 == tmp_result),
4377 "Failed to program static screen threshold parameters!", result = tmp_result);
4378
4379 tmp_result = tonga_enable_display_gap(hwmgr);
4380 PP_ASSERT_WITH_CODE((0 == tmp_result),
4381 "Failed to enable display gap!", result = tmp_result);
4382
4383 tmp_result = tonga_program_voting_clients(hwmgr);
4384 PP_ASSERT_WITH_CODE((0 == tmp_result),
4385 "Failed to program voting clients!", result = tmp_result);
4386
4387 tmp_result = tonga_process_firmware_header(hwmgr);
4388 PP_ASSERT_WITH_CODE((0 == tmp_result),
4389 "Failed to process firmware header!", result = tmp_result);
4390
4391 tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4392 PP_ASSERT_WITH_CODE((0 == tmp_result),
4393 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4394
4395 tmp_result = tonga_init_smc_table(hwmgr);
4396 PP_ASSERT_WITH_CODE((0 == tmp_result),
4397 "Failed to initialize SMC table!", result = tmp_result);
4398
4399 tmp_result = tonga_init_arb_table_index(hwmgr);
4400 PP_ASSERT_WITH_CODE((0 == tmp_result),
4401 "Failed to initialize ARB table index!", result = tmp_result);
4402
4403 tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4404 PP_ASSERT_WITH_CODE((0 == tmp_result),
4405 "Failed to populate initialize MC Reg table!", result = tmp_result);
4406
bbb207f3
RZ		 4407 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4408 PP_ASSERT_WITH_CODE((0 == tmp_result),
4409 "Failed to notify no display!", result = tmp_result);
4410
c82baa28 4411 /* enable SCLK control */
4412 tmp_result = tonga_enable_sclk_control(hwmgr);
4413 PP_ASSERT_WITH_CODE((0 == tmp_result),
4414 "Failed to enable SCLK control!", result = tmp_result);
4415
4416 /* enable DPM */
4417 tmp_result = tonga_start_dpm(hwmgr);
4418 PP_ASSERT_WITH_CODE((0 == tmp_result),
4419 "Failed to start DPM!", result = tmp_result);
4420
4421 return result;
4422}
4423
4424int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4425{
4426 int tmp_result, result = 0;
4427
4428 tmp_result = tonga_check_for_dpm_running(hwmgr);
4429 PP_ASSERT_WITH_CODE((0 == tmp_result),
4430 "SMC is still running!", return 0);
4431
4432 tmp_result = tonga_stop_dpm(hwmgr);
4433 PP_ASSERT_WITH_CODE((0 == tmp_result),
4434 "Failed to stop DPM!", result = tmp_result);
4435
4436 tmp_result = tonga_reset_to_default(hwmgr);
4437 PP_ASSERT_WITH_CODE((0 == tmp_result),
4438 "Failed to reset to default!", result = tmp_result);
4439
4440 return result;
4441}
4442
4443int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4444{
4445 int result;
4446
4447 result = tonga_set_boot_state(hwmgr);
4448 if (0 != result)
4449 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4450
4451 return result;
4452}
4453
4454int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4455{
4456 if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
4457 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
4458 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
4459 }
4460
4461 if (NULL != hwmgr->backend) {
4462 kfree(hwmgr->backend);
4463 hwmgr->backend = NULL;
4464 }
4465
4466 return 0;
4467}
4468
4469/**
4470 * Initializes the Volcanic Islands Hardware Manager
4471 *
4472 * @param hwmgr the address of the powerplay hardware manager.
4473 * @return 1 if success; otherwise appropriate error code.
4474 */
4475int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4476{
4477 int result = 0;
4478 SMU72_Discrete_DpmTable *table = NULL;
4479 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4480 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4481 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4482 phw_tonga_ulv_parm *ulv;
4483
4484 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4485 "Invalid Parameter!", return -1;);
4486
4487 data->dll_defaule_on = 0;
4488 data->sram_end = SMC_RAM_END;
4489
4490 data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4491 data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4492 data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4493 data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4494 data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4495 data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4496 data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4497 data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4498
4499 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4500 data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4501 data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4502
4503 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4504 PHM_PlatformCaps_DisableVoltageIsland);
4505
4506 data->sclk_dpm_key_disabled = 0;
4507 data->mclk_dpm_key_disabled = 0;
4508 data->pcie_dpm_key_disabled = 0;
4509 data->pcc_monitor_enabled = 0;
4510
4511 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4512 PHM_PlatformCaps_UnTabledHardwareInterface);
4513
4514 data->gpio_debug = 0;
4515 data->engine_clock_data = 0;
4516 data->memory_clock_data = 0;
4517 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4518 PHM_PlatformCaps_DynamicPatchPowerState);
4519
4520 /* need to set voltage control types before EVV patching*/
4521 data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4522 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4523 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4524 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4525
3ec2cdb8 4526 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4527 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4528 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4529 }
4530
4531 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4532 PHM_PlatformCaps_ControlVDDGFX)) {
3ec2cdb8 4533 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4534 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4535 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4536 }
4537 }
4538
4539 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4540 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4541 PHM_PlatformCaps_ControlVDDGFX);
4542 }
4543
4544 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4545 PHM_PlatformCaps_EnableMVDDControl)) {
3ec2cdb8 4546 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4547 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4548 data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4549 }
4550 }
4551
4552 if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4553 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4554 PHM_PlatformCaps_EnableMVDDControl);
4555 }
4556
4557 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4558 PHM_PlatformCaps_ControlVDDCI)) {
3ec2cdb8 4559 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4560 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4561 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
3ec2cdb8 4562 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4563 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4564 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4565 }
4566
4567 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4568 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4569 PHM_PlatformCaps_ControlVDDCI);
4570
4571 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4572 PHM_PlatformCaps_TablelessHardwareInterface);
4573
4574 if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4575 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4576 PHM_PlatformCaps_ClockStretcher);
4577
4578 /* Initializes DPM default values*/
4579 tonga_initialize_dpm_defaults(hwmgr);
4580
4581 /* Get leakage voltage based on leakage ID.*/
4582 PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4583 "Get EVV Voltage Failed. Abort Driver loading!", return -1);
4584
4585 tonga_complete_dependency_tables(hwmgr);
4586
4587 /* Parse pptable data read from VBIOS*/
4588 tonga_set_private_var_based_on_pptale(hwmgr);
4589
4590 /* ULV Support*/
4591 ulv = &(data->ulv);
4592 ulv->ulv_supported = 0;
4593
4594 /* Initalize Dynamic State Adjustment Rule Settings*/
4595 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
4596 data->uvd_enabled = 0;
4597
4598 table = &(data->smc_state_table);
4599
4600 /*
4601 * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4602 * Peak Current Control feature is enabled and we should program PCC HW register
4603 */
4604 if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4605 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4606 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4607
4608 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4609 case 0:
4610 temp_reg = PHM_SET_FIELD(temp_reg,
4611 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4612 break;
4613 case 1:
4614 temp_reg = PHM_SET_FIELD(temp_reg,
4615 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4616 break;
4617 case 2:
4618 temp_reg = PHM_SET_FIELD(temp_reg,
4619 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4620 break;
4621 case 3:
4622 temp_reg = PHM_SET_FIELD(temp_reg,
4623 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4624 break;
4625 case 4:
4626 temp_reg = PHM_SET_FIELD(temp_reg,
4627 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4628 break;
4629 default:
4630 printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4631 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4632 break;
4633 }
4634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4635 ixCNB_PWRMGT_CNTL, temp_reg);
4636 }
4637
4638 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4639 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4640 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4641 PHM_PlatformCaps_SMU7);
4642
4643 data->vddc_phase_shed_control = 0;
4644
4645 if (0 == result) {
4646 data->is_tlu_enabled = 0;
4647 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4648 TONGA_MAX_HARDWARE_POWERLEVELS;
4649 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4650 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
4651
4652 data->pcie_gen_cap = 0x30007;
4653 data->pcie_lane_cap = 0x2f0000;
4654 } else {
4655 /* Ignore return value in here, we are cleaning up a mess. */
4656 tonga_hwmgr_backend_fini(hwmgr);
4657 }
4658
4659 return result;
4660}
4661
4662static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4663 enum amd_dpm_forced_level level)
4664{
4665 int ret = 0;
4666
4667 switch (level) {
4668 case AMD_DPM_FORCED_LEVEL_HIGH:
4669 ret = tonga_force_dpm_highest(hwmgr);
4670 if (ret)
4671 return ret;
4672 break;
4673 case AMD_DPM_FORCED_LEVEL_LOW:
4674 ret = tonga_force_dpm_lowest(hwmgr);
4675 if (ret)
4676 return ret;
4677 break;
4678 case AMD_DPM_FORCED_LEVEL_AUTO:
4679 ret = tonga_unforce_dpm_levels(hwmgr);
4680 if (ret)
4681 return ret;
4682 break;
4683 default:
4684 break;
4685 }
4686
4687 hwmgr->dpm_level = level;
4688 return ret;
4689}
4690
4691static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4692 struct pp_power_state *prequest_ps,
4693 const struct pp_power_state *pcurrent_ps)
4694{
4695 struct tonga_power_state *tonga_ps =
4696 cast_phw_tonga_power_state(&prequest_ps->hardware);
4697
4698 uint32_t sclk;
4699 uint32_t mclk;
4700 struct PP_Clocks minimum_clocks = {0};
4701 bool disable_mclk_switching;
4702 bool disable_mclk_switching_for_frame_lock;
4703 struct cgs_display_info info = {0};
4704 const struct phm_clock_and_voltage_limits *max_limits;
4705 uint32_t i;
4706 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4707 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4708
4709 int32_t count;
4710 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4711
4712 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4713
4714 PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4715 "VI should always have 2 performance levels",
4716 );
4717
4718 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4719 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4720 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4721
4722 if (PP_PowerSource_DC == hwmgr->power_source) {
4723 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4724 if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4725 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4726 if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4727 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4728 }
4729 }
4730
4731 tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4732 tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4733
4734 tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4735
4736 cgs_get_active_displays_info(hwmgr->device, &info);
4737
4738 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4739
4740 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4741
4742 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4743
4744 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4745 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4746
4747 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4748 if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4749 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4750 break;
4751 }
4752 }
4753
4754 if (count < 0)
4755 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4756
4757 stable_pstate_mclk = max_limits->mclk;
4758
4759 minimum_clocks.engineClock = stable_pstate_sclk;
4760 minimum_clocks.memoryClock = stable_pstate_mclk;
4761 }
4762
4763 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4764 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4765
4766 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4767 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4768
4769 tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4770
4771 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4772 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4773 "Overdrive sclk exceeds limit",
4774 hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4775
4776 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4777 tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4778 }
4779
4780 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4781 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4782 "Overdrive mclk exceeds limit",
4783 hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4784
4785 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4786 tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4787 }
4788
4789 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4790 hwmgr->platform_descriptor.platformCaps,
4791 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4792
4793 disable_mclk_switching = (1 < info.display_count) ||
4794 disable_mclk_switching_for_frame_lock;
4795
4796 sclk = tonga_ps->performance_levels[0].engine_clock;
4797 mclk = tonga_ps->performance_levels[0].memory_clock;
4798
4799 if (disable_mclk_switching)
4800 mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4801
4802 if (sclk < minimum_clocks.engineClock)
4803 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4804
4805 if (mclk < minimum_clocks.memoryClock)
4806 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4807
4808 tonga_ps->performance_levels[0].engine_clock = sclk;
4809 tonga_ps->performance_levels[0].memory_clock = mclk;
4810
4811 tonga_ps->performance_levels[1].engine_clock =
4812 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4813 tonga_ps->performance_levels[1].engine_clock :
4814 tonga_ps->performance_levels[0].engine_clock;
4815
4816 if (disable_mclk_switching) {
4817 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4818 mclk = tonga_ps->performance_levels[1].memory_clock;
4819
4820 tonga_ps->performance_levels[0].memory_clock = mclk;
4821 tonga_ps->performance_levels[1].memory_clock = mclk;
4822 } else {
4823 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4824 tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4825 }
4826
4827 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4828 for (i=0; i < tonga_ps->performance_level_count; i++) {
4829 tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4830 tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4831 tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4832 tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4833 }
4834 }
4835
4836 return 0;
4837}
4838
4839int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4840{
4841 return sizeof(struct tonga_power_state);
4842}
4843
4844static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4845{
4846 struct pp_power_state *ps;
4847 struct tonga_power_state *tonga_ps;
4848
4849 if (hwmgr == NULL)
4850 return -EINVAL;
4851
4852 ps = hwmgr->request_ps;
4853
4854 if (ps == NULL)
4855 return -EINVAL;
4856
4857 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4858
4859 if (low)
4860 return tonga_ps->performance_levels[0].memory_clock;
4861 else
4862 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4863}
4864
4865static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4866{
4867 struct pp_power_state *ps;
4868 struct tonga_power_state *tonga_ps;
4869
4870 if (hwmgr == NULL)
4871 return -EINVAL;
4872
4873 ps = hwmgr->request_ps;
4874
4875 if (ps == NULL)
4876 return -EINVAL;
4877
4878 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4879
4880 if (low)
4881 return tonga_ps->performance_levels[0].engine_clock;
4882 else
4883 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4884}
4885
4886static uint16_t tonga_get_current_pcie_speed(
4887 struct pp_hwmgr *hwmgr)
4888{
4889 uint32_t speed_cntl = 0;
4890
4891 speed_cntl = cgs_read_ind_register(hwmgr->device,
4892 CGS_IND_REG__PCIE,
4893 ixPCIE_LC_SPEED_CNTL);
4894 return((uint16_t)PHM_GET_FIELD(speed_cntl,
4895 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4896}
4897
4898static int tonga_get_current_pcie_lane_number(
4899 struct pp_hwmgr *hwmgr)
4900{
4901 uint32_t link_width;
4902
4903 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4904 CGS_IND_REG__PCIE,
4905 PCIE_LC_LINK_WIDTH_CNTL,
4906 LC_LINK_WIDTH_RD);
4907
4908 PP_ASSERT_WITH_CODE((7 >= link_width),
4909 "Invalid PCIe lane width!", return 0);
4910
4911 return decode_pcie_lane_width(link_width);
4912}
4913
4914static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4915 struct pp_hw_power_state *hw_ps)
4916{
4917 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4918 struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4919 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4920 uint16_t size;
4921 uint8_t frev, crev;
4922 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4923
4924 /* First retrieve the Boot clocks and VDDC from the firmware info table.
4925 * We assume here that fw_info is unchanged if this call fails.
4926 */
4927 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4928 hwmgr->device, index,
4929 &size, &frev, &crev);
4930 if (!fw_info)
4931 /* During a test, there is no firmware info table. */
4932 return 0;
4933
4934 /* Patch the state. */
4935 data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock);
4936 data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4937 data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4938 data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4939 data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4940 data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4941 data->vbios_boot_state.pcie_lane_bootup_value =
4942 (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4943
4944 /* set boot power state */
4945 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4946 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4947 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4948 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4949
4950 return 0;
4951}
4952
4953static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4954 void *state, struct pp_power_state *power_state,
4955 void *pp_table, uint32_t classification_flag)
4956{
4957 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4958
4959 struct tonga_power_state *tonga_ps =
4960 (struct tonga_power_state *)(&(power_state->hardware));
4961
4962 struct tonga_performance_level *performance_level;
4963
4964 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4965
4966 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4967 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4968
4969 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4970 (ATOM_Tonga_SCLK_Dependency_Table *)
4971 (((uint64_t)powerplay_table) +
4972 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4973
4974 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
4975 (ATOM_Tonga_MCLK_Dependency_Table *)
4976 (((uint64_t)powerplay_table) +
4977 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
4978
4979 /* The following fields are not initialized here: id orderedList allStatesList */
4980 power_state->classification.ui_label =
4981 (le16_to_cpu(state_entry->usClassification) &
4982 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
4983 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
4984 power_state->classification.flags = classification_flag;
4985 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
4986
4987 power_state->classification.temporary_state = false;
4988 power_state->classification.to_be_deleted = false;
4989
4990 power_state->validation.disallowOnDC =
4991 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
4992
4993 power_state->pcie.lanes = 0;
4994
4995 power_state->display.disableFrameModulation = false;
4996 power_state->display.limitRefreshrate = false;
4997 power_state->display.enableVariBright =
4998 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
4999
5000 power_state->validation.supportedPowerLevels = 0;
5001 power_state->uvd_clocks.VCLK = 0;
5002 power_state->uvd_clocks.DCLK = 0;
5003 power_state->temperatures.min = 0;
5004 power_state->temperatures.max = 0;
5005
5006 performance_level = &(tonga_ps->performance_levels
5007 [tonga_ps->performance_level_count++]);
5008
5009 PP_ASSERT_WITH_CODE(
5010 (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5011 "Performance levels exceeds SMC limit!",
5012 return -1);
5013
5014 PP_ASSERT_WITH_CODE(
5015 (tonga_ps->performance_level_count <=
5016 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5017 "Performance levels exceeds Driver limit!",
5018 return -1);
5019
5020 /* Performance levels are arranged from low to high. */
5021 performance_level->memory_clock =
5022 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5023
5024 performance_level->engine_clock =
5025 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5026
5027 performance_level->pcie_gen = get_pcie_gen_support(
5028 data->pcie_gen_cap,
5029 state_entry->ucPCIEGenLow);
5030
5031 performance_level->pcie_lane = get_pcie_lane_support(
5032 data->pcie_lane_cap,
5033 state_entry->ucPCIELaneHigh);
5034
5035 performance_level =
5036 &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5037
5038 performance_level->memory_clock =
5039 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5040
5041 performance_level->engine_clock =
5042 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5043
5044 performance_level->pcie_gen = get_pcie_gen_support(
5045 data->pcie_gen_cap,
5046 state_entry->ucPCIEGenHigh);
5047
5048 performance_level->pcie_lane = get_pcie_lane_support(
5049 data->pcie_lane_cap,
5050 state_entry->ucPCIELaneHigh);
5051
5052 return 0;
5053}
5054
5055static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5056 unsigned long entry_index, struct pp_power_state *ps)
5057{
5058 int result;
5059 struct tonga_power_state *tonga_ps;
5060 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5061
5062 struct phm_ppt_v1_information *table_info =
5063 (struct phm_ppt_v1_information *)(hwmgr->pptable);
5064
5065 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5066 table_info->vdd_dep_on_mclk;
5067
5068 ps->hardware.magic = PhwTonga_Magic;
5069
5070 tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5071
5072 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5073 tonga_get_pp_table_entry_callback_func);
5074
5075 /* This is the earliest time we have all the dependency table and the VBIOS boot state
5076 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5077 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5078 */
5079 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5080 if (dep_mclk_table->entries[0].clk !=
5081 data->vbios_boot_state.mclk_bootup_value)
5082 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5083 "does not match VBIOS boot MCLK level");
5084 if (dep_mclk_table->entries[0].vddci !=
5085 data->vbios_boot_state.vddci_bootup_value)
5086 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5087 "does not match VBIOS boot VDDCI level");
5088 }
5089
5090 /* set DC compatible flag if this state supports DC */
5091 if (!ps->validation.disallowOnDC)
5092 tonga_ps->dc_compatible = true;
5093
5094 if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5095 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5096 else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5097 if (data->bacos.best_match == 0xffff) {
5098 /* For V.I. use boot state as base BACO state */
5099 data->bacos.best_match = PP_StateClassificationFlag_Boot;
5100 data->bacos.performance_level = tonga_ps->performance_levels[0];
5101 }
5102 }
5103
5104 tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5105 tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5106
5107 if (!result) {
5108 uint32_t i;
5109
5110 switch (ps->classification.ui_label) {
5111 case PP_StateUILabel_Performance:
5112 data->use_pcie_performance_levels = true;
5113
5114 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5115 if (data->pcie_gen_performance.max <
5116 tonga_ps->performance_levels[i].pcie_gen)
5117 data->pcie_gen_performance.max =
5118 tonga_ps->performance_levels[i].pcie_gen;
5119
5120 if (data->pcie_gen_performance.min >
5121 tonga_ps->performance_levels[i].pcie_gen)
5122 data->pcie_gen_performance.min =
5123 tonga_ps->performance_levels[i].pcie_gen;
5124
5125 if (data->pcie_lane_performance.max <
5126 tonga_ps->performance_levels[i].pcie_lane)
5127 data->pcie_lane_performance.max =
5128 tonga_ps->performance_levels[i].pcie_lane;
5129
5130 if (data->pcie_lane_performance.min >
5131 tonga_ps->performance_levels[i].pcie_lane)
5132 data->pcie_lane_performance.min =
5133 tonga_ps->performance_levels[i].pcie_lane;
5134 }
5135 break;
5136 case PP_StateUILabel_Battery:
5137 data->use_pcie_power_saving_levels = true;
5138
5139 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5140 if (data->pcie_gen_power_saving.max <
5141 tonga_ps->performance_levels[i].pcie_gen)
5142 data->pcie_gen_power_saving.max =
5143 tonga_ps->performance_levels[i].pcie_gen;
5144
5145 if (data->pcie_gen_power_saving.min >
5146 tonga_ps->performance_levels[i].pcie_gen)
5147 data->pcie_gen_power_saving.min =
5148 tonga_ps->performance_levels[i].pcie_gen;
5149
5150 if (data->pcie_lane_power_saving.max <
5151 tonga_ps->performance_levels[i].pcie_lane)
5152 data->pcie_lane_power_saving.max =
5153 tonga_ps->performance_levels[i].pcie_lane;
5154
5155 if (data->pcie_lane_power_saving.min >
5156 tonga_ps->performance_levels[i].pcie_lane)
5157 data->pcie_lane_power_saving.min =
5158 tonga_ps->performance_levels[i].pcie_lane;
5159 }
5160 break;
5161 default:
5162 break;
5163 }
5164 }
5165 return 0;
5166}
5167
5168static void
5169tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5170{
5171 uint32_t sclk, mclk;
5172
5173 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5174
5175 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5176
5177 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5178
5179 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5180 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
5181}
5182
5183static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5184{
5185 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5186 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5187 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5188 struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5189 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5190 struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5191 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5192 struct PP_Clocks min_clocks = {0};
5193 uint32_t i;
5194 struct cgs_display_info info = {0};
5195
5196 data->need_update_smu7_dpm_table = 0;
5197
5198 for (i = 0; i < psclk_table->count; i++) {
5199 if (sclk == psclk_table->dpm_levels[i].value)
5200 break;
5201 }
5202
5203 if (i >= psclk_table->count)
5204 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5205 else {
5206 /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5207 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5208 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5209 }
5210
5211 for (i=0; i < pmclk_table->count; i++) {
5212 if (mclk == pmclk_table->dpm_levels[i].value)
5213 break;
5214 }
5215
5216 if (i >= pmclk_table->count)
5217 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5218
5219 cgs_get_active_displays_info(hwmgr->device, &info);
5220
5221 if (data->display_timing.num_existing_displays != info.display_count)
5222 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5223
5224 return 0;
5225}
5226
5227static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5228{
5229 uint32_t i;
5230 uint32_t sclk, max_sclk = 0;
5231 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5232 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5233
5234 for (i = 0; i < hw_ps->performance_level_count; i++) {
5235 sclk = hw_ps->performance_levels[i].engine_clock;
5236 if (max_sclk < sclk)
5237 max_sclk = sclk;
5238 }
5239
5240 for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5241 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5242 return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5243 pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5244 pdpm_table->pcie_speed_table.dpm_levels[i].value);
5245 }
5246
5247 return 0;
5248}
5249
5250static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5251{
5252 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5253 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5254 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5255 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5256
5257 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5258 uint16_t current_link_speed;
5259
5260 if (data->force_pcie_gen == PP_PCIEGenInvalid)
5261 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5262 else
5263 current_link_speed = data->force_pcie_gen;
5264
5265 data->force_pcie_gen = PP_PCIEGenInvalid;
5266 data->pspp_notify_required = false;
5267 if (target_link_speed > current_link_speed) {
5268 switch(target_link_speed) {
5269 case PP_PCIEGen3:
5270 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5271 break;
5272 data->force_pcie_gen = PP_PCIEGen2;
5273 if (current_link_speed == PP_PCIEGen2)
5274 break;
5275 case PP_PCIEGen2:
5276 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5277 break;
5278 default:
5279 data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5280 break;
5281 }
5282 } else {
5283 if (target_link_speed < current_link_speed)
5284 data->pspp_notify_required = true;
5285 }
5286
5287 return 0;
5288}
5289
5290static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5291{
5292 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5293
5294 if (0 == data->need_update_smu7_dpm_table)
5295 return 0;
5296
5297 if ((0 == data->sclk_dpm_key_disabled) &&
5298 (data->need_update_smu7_dpm_table &
5299 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5300 PP_ASSERT_WITH_CODE(
5301 true == tonga_is_dpm_running(hwmgr),
5302 "Trying to freeze SCLK DPM when DPM is disabled",
5303 );
5304 PP_ASSERT_WITH_CODE(
5305 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5306 PPSMC_MSG_SCLKDPM_FreezeLevel),
5307 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5308 return -1);
5309 }
5310
5311 if ((0 == data->mclk_dpm_key_disabled) &&
5312 (data->need_update_smu7_dpm_table &
5313 DPMTABLE_OD_UPDATE_MCLK)) {
5314 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5315 "Trying to freeze MCLK DPM when DPM is disabled",
5316 );
5317 PP_ASSERT_WITH_CODE(
5318 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5319 PPSMC_MSG_MCLKDPM_FreezeLevel),
5320 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5321 return -1);
5322 }
5323
5324 return 0;
5325}
5326
5327static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5328{
5329 int result = 0;
5330
5331 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5332 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5333 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5334 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5335 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5336 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5337
5338 struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5339 uint32_t dpm_count, clock_percent;
5340 uint32_t i;
5341
5342 if (0 == data->need_update_smu7_dpm_table)
5343 return 0;
5344
5345 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5346 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5347
5348 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5349 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5350 /* Need to do calculation based on the golden DPM table
5351 * as the Heatmap GPU Clock axis is also based on the default values
5352 */
5353 PP_ASSERT_WITH_CODE(
5354 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5355 "Divide by 0!",
5356 return -1);
5357 dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5358 for (i = dpm_count; i > 1; i--) {
5359 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5360 clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5361 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5362
5363 pdpm_table->sclk_table.dpm_levels[i].value =
5364 pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5365 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5366
5367 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5368 clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5369 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5370
5371 pdpm_table->sclk_table.dpm_levels[i].value =
5372 pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5373 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5374 } else
5375 pdpm_table->sclk_table.dpm_levels[i].value =
5376 pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5377 }
5378 }
5379 }
5380
5381 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5382 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5383
5384 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5385 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5386
5387 PP_ASSERT_WITH_CODE(
5388 (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5389 "Divide by 0!",
5390 return -1);
5391 dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5392 for (i = dpm_count; i > 1; i--) {
5393 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5394 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5395 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5396
5397 pdpm_table->mclk_table.dpm_levels[i].value =
5398 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5399 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5400
5401 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5402 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5403 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5404
5405 pdpm_table->mclk_table.dpm_levels[i].value =
5406 pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5407 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5408 } else
5409 pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5410 }
5411 }
5412 }
5413
5414 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5415 result = tonga_populate_all_memory_levels(hwmgr);
5416 PP_ASSERT_WITH_CODE((0 == result),
5417 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5418 return result);
5419 }
5420
5421 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5422 /*populate MCLK dpm table to SMU7 */
5423 result = tonga_populate_all_memory_levels(hwmgr);
5424 PP_ASSERT_WITH_CODE((0 == result),
5425 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5426 return result);
5427 }
5428
5429 return result;
5430}
5431
5432static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5433 struct tonga_single_dpm_table * pdpm_table,
5434 uint32_t low_limit, uint32_t high_limit)
5435{
5436 uint32_t i;
5437
5438 for (i = 0; i < pdpm_table->count; i++) {
5439 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5440 (pdpm_table->dpm_levels[i].value > high_limit))
5441 pdpm_table->dpm_levels[i].enabled = false;
5442 else
5443 pdpm_table->dpm_levels[i].enabled = true;
5444 }
5445 return 0;
5446}
5447
5448static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5449{
5450 int result = 0;
5451 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5452 uint32_t high_limit_count;
5453
5454 PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5455 "power state did not have any performance level",
5456 return -1);
5457
5458 high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5459
5460 tonga_trim_single_dpm_states(hwmgr,
5461 &(data->dpm_table.sclk_table),
5462 hw_state->performance_levels[0].engine_clock,
5463 hw_state->performance_levels[high_limit_count].engine_clock);
5464
5465 tonga_trim_single_dpm_states(hwmgr,
5466 &(data->dpm_table.mclk_table),
5467 hw_state->performance_levels[0].memory_clock,
5468 hw_state->performance_levels[high_limit_count].memory_clock);
5469
5470 return result;
5471}
5472
5473static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5474{
5475 int result;
5476 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5477 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5478 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5479
5480
5481 result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5482 if (0 != result)
5483 return result;
5484
5485 data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5486 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5487 data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5488 if (data->uvd_enabled)
5489 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5490
5491 data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5492
5493 return 0;
5494}
5495
0859ed3d 5496int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
c82baa28 5497{
0859ed3d 5498 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
c82baa28 5499 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5500 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5501}
5502
0859ed3d
RZ		 5503int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5504{
5505 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5506 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5507 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5508}
5509
5510int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5511{
5512 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5513 uint32_t mm_boot_level_offset, mm_boot_level_value;
5514 struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5515
5516 if (!bgate) {
5517 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5518 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5519 mm_boot_level_offset /= 4;
5520 mm_boot_level_offset *= 4;
5521 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5522 mm_boot_level_value &= 0x00FFFFFF;
5523 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5524 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5525
5526 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5527 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5528 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5529 PPSMC_MSG_UVDDPM_SetEnabledMask,
5530 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5531 }
5532
5533 return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5534}
5535
5536int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
c82baa28 5537{
5538 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5539 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5540 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5541 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5542
5543 uint32_t mm_boot_level_offset, mm_boot_level_value;
5544 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5545
0859ed3d 5546 if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
c82baa28 5547 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5548
5549 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5550 mm_boot_level_offset /= 4;
5551 mm_boot_level_offset *= 4;
5552 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5553 mm_boot_level_value &= 0xFF00FFFF;
5554 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5555 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5556
0859ed3d
RZ		 5557 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5558 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5559 PPSMC_MSG_VCEDPM_SetEnabledMask,
5560 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
c82baa28 5561
0859ed3d
RZ		 5562 tonga_enable_disable_vce_dpm(hwmgr, true);
5563 } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5564 tonga_enable_disable_vce_dpm(hwmgr, false);
c82baa28 5565
5566 return 0;
5567}
5568
5569static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5570{
5571 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5572
5573 uint32_t address;
5574 int32_t result;
5575
5576 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5577 return 0;
5578
5579
5580 memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5581
5582 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5583
5584 if(result != 0)
5585 return result;
5586
5587
5588 address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5589
5590 return tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5591 (uint8_t *)&data->mc_reg_table.data[0],
5592 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5593 data->sram_end);
5594}
5595
5596static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5597{
5598 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5599
5600 if (data->need_update_smu7_dpm_table &
5601 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5602 return tonga_program_memory_timing_parameters(hwmgr);
5603
5604 return 0;
5605}
5606
5607static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5608{
5609 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5610
5611 if (0 == data->need_update_smu7_dpm_table)
5612 return 0;
5613
5614 if ((0 == data->sclk_dpm_key_disabled) &&
5615 (data->need_update_smu7_dpm_table &
5616 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5617
5618 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5619 "Trying to Unfreeze SCLK DPM when DPM is disabled",
5620 );
5621 PP_ASSERT_WITH_CODE(
5622 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5623 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5624 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5625 return -1);
5626 }
5627
5628 if ((0 == data->mclk_dpm_key_disabled) &&
5629 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5630
5631 PP_ASSERT_WITH_CODE(
5632 true == tonga_is_dpm_running(hwmgr),
5633 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5634 );
5635 PP_ASSERT_WITH_CODE(
5636 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5637 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5638 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5639 return -1);
5640 }
5641
5642 data->need_update_smu7_dpm_table = 0;
5643
5644 return 0;
5645}
5646
5647static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5648{
5649 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5650 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5651 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5652 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5653 uint8_t request;
5654
5655 if (data->pspp_notify_required ||
5656 data->pcie_performance_request) {
5657 if (target_link_speed == PP_PCIEGen3)
5658 request = PCIE_PERF_REQ_GEN3;
5659 else if (target_link_speed == PP_PCIEGen2)
5660 request = PCIE_PERF_REQ_GEN2;
5661 else
5662 request = PCIE_PERF_REQ_GEN1;
5663
5664 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5665 data->pcie_performance_request = false;
5666 return 0;
5667 }
5668
5669 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5670 if (PP_PCIEGen2 == target_link_speed)
5671 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5672 else
5673 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5674 }
5675 }
5676
5677 data->pcie_performance_request = false;
5678 return 0;
5679}
5680
5681static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5682{
5683 int tmp_result, result = 0;
5684
5685 tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5686 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5687
5688 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5689 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5690 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5691 }
5692
5693 tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5694 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5695
5696 tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5697 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5698
5699 tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5700 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5701
5702 tmp_result = tonga_update_vce_dpm(hwmgr, input);
5703 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5704
5705 tmp_result = tonga_update_sclk_threshold(hwmgr);
5706 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5707
5708 tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5709 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5710
5711 tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5712 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5713
5714 tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5715 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5716
5717 tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5718 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5719
5720 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5721 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5722 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5723 }
5724
5725 return result;
5726}
5727
1e4854e9
RZ		 5728/**
5729* Set maximum target operating fan output PWM
5730*
5731* @param pHwMgr: the address of the powerplay hardware manager.
5732* @param usMaxFanPwm: max operating fan PWM in percents
5733* @return The response that came from the SMC.
5734*/
5735static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5736{
5737 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5738
5739 if (phm_is_hw_access_blocked(hwmgr))
5740 return 0;
5741
5742 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -EINVAL);
5743}
bbb207f3
RZ		 5744
5745int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5746{
5747 uint32_t num_active_displays = 0;
5748 struct cgs_display_info info = {0};
5749 info.mode_info = NULL;
5750
5751 cgs_get_active_displays_info(hwmgr->device, &info);
5752
5753 num_active_displays = info.display_count;
5754
5755 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5756 tonga_notify_smc_display_change(hwmgr, false);
5757 else
5758 tonga_notify_smc_display_change(hwmgr, true);
5759
5760 return 0;
5761}
5762
5763/**
5764* Programs the display gap
5765*
5766* @param hwmgr the address of the powerplay hardware manager.
5767* @return always OK
5768*/
5769int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5770{
5771 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5772 uint32_t num_active_displays = 0;
5773 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5774 uint32_t display_gap2;
5775 uint32_t pre_vbi_time_in_us;
5776 uint32_t frame_time_in_us;
5777 uint32_t ref_clock;
5778 uint32_t refresh_rate = 0;
5779 struct cgs_display_info info = {0};
5780 struct cgs_mode_info mode_info;
5781
5782 info.mode_info = &mode_info;
5783
5784 cgs_get_active_displays_info(hwmgr->device, &info);
5785 num_active_displays = info.display_count;
5786
5787 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5788 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5789
5790 ref_clock = mode_info.ref_clock;
5791 refresh_rate = mode_info.refresh_rate;
5792
5793 if(0 == refresh_rate)
5794 refresh_rate = 60;
5795
5796 frame_time_in_us = 1000000 / refresh_rate;
5797
5798 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5799 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5800
5801 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5802
5803 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5804
5805 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5806
5807 if (num_active_displays == 1)
5808 tonga_notify_smc_display_change(hwmgr, true);
5809
5810 return 0;
5811}
5812
5813int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5814{
5815
5816 tonga_program_display_gap(hwmgr);
5817
5818 /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5819 return 0;
5820}
5821
1e4854e9
RZ		 5822/**
5823* Set maximum target operating fan output RPM
5824*
5825* @param pHwMgr: the address of the powerplay hardware manager.
5826* @param usMaxFanRpm: max operating fan RPM value.
5827* @return The response that came from the SMC.
5828*/
5829static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5830{
5831 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5832
5833 if (phm_is_hw_access_blocked(hwmgr))
5834 return 0;
5835
5836 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -EINVAL);
5837}
5838
5839uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5840{
5841 uint32_t reference_clock;
5842 uint32_t tc;
5843 uint32_t divide;
5844
5845 ATOM_FIRMWARE_INFO *fw_info;
5846 uint16_t size;
5847 uint8_t frev, crev;
5848 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5849
5850 tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5851
5852 if (tc)
5853 return TCLK;
5854
5855 fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5856 &size, &frev, &crev);
5857
5858 if (!fw_info)
5859 return 0;
5860
5861 reference_clock = le16_to_cpu(fw_info->usMinPixelClockPLL_Output);
5862
5863 divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5864
5865 if (0 != divide)
5866 return reference_clock / 4;
5867
5868 return reference_clock;
5869}
5870
5871int tonga_dpm_set_interrupt_state(void *private_data,
5872 unsigned src_id, unsigned type,
5873 int enabled)
5874{
5875 uint32_t cg_thermal_int;
5876 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5877
5878 if (hwmgr == NULL)
5879 return -EINVAL;
5880
5881 switch (type) {
5882 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5883 if (enabled) {
5884 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5885 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5886 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5887 } else {
5888 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5889 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5890 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5891 }
5892 break;
5893
5894 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5895 if (enabled) {
5896 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5897 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5898 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5899 } else {
5900 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5901 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5902 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5903 }
5904 break;
5905 default:
5906 break;
5907 }
5908 return 0;
5909}
5910
5911int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5912 const void *thermal_interrupt_info)
5913{
5914 int result;
5915 const struct pp_interrupt_registration_info *info =
5916 (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5917
5918 if (info == NULL)
5919 return -EINVAL;
5920
5921 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5922 tonga_dpm_set_interrupt_state,
5923 info->call_back, info->context);
5924
5925 if (result)
5926 return -EINVAL;
5927
5928 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5929 tonga_dpm_set_interrupt_state,
5930 info->call_back, info->context);
5931
5932 if (result)
5933 return -EINVAL;
5934
5935 return 0;
5936}
5937
e829ecdb
RZ		 5938bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5939{
5940 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5941 bool is_update_required = false;
5942 struct cgs_display_info info = {0,0,NULL};
5943
5944 cgs_get_active_displays_info(hwmgr->device, &info);
5945
5946 if (data->display_timing.num_existing_displays != info.display_count)
5947 is_update_required = true;
5948/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5949 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5950 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5951 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5952 is_update_required = true;
5953*/
5954 return is_update_required;
5955}
5956
5957static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5958 const struct tonga_performance_level *pl2)
5959{
5960 return ((pl1->memory_clock == pl2->memory_clock) &&
5961 (pl1->engine_clock == pl2->engine_clock) &&
5962 (pl1->pcie_gen == pl2->pcie_gen) &&
5963 (pl1->pcie_lane == pl2->pcie_lane));
5964}
5965
5966int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5967{
5968 const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
5969 const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
5970 int i;
5971
5972 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
5973 return -EINVAL;
5974
5975 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5976 if (psa->performance_level_count != psb->performance_level_count) {
5977 *equal = false;
5978 return 0;
5979 }
5980
5981 for (i = 0; i < psa->performance_level_count; i++) {
5982 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5983 /* If we have found even one performance level pair that is different the states are different. */
5984 *equal = false;
5985 return 0;
5986 }
5987 }
5988
5989 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5990 *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
5991 *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
5992 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5993 *equal &= (psa->acp_clk == psb->acp_clk);
5994
5995 return 0;
5996}
5997
c82baa28 5998static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
5999 .backend_init = &tonga_hwmgr_backend_init,
6000 .backend_fini = &tonga_hwmgr_backend_fini,
6001 .asic_setup = &tonga_setup_asic_task,
6002 .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6003 .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6004 .force_dpm_level = &tonga_force_dpm_level,
6005 .power_state_set = tonga_set_power_state_tasks,
6006 .get_power_state_size = tonga_get_power_state_size,
6007 .get_mclk = tonga_dpm_get_mclk,
6008 .get_sclk = tonga_dpm_get_sclk,
6009 .patch_boot_state = tonga_dpm_patch_boot_state,
6010 .get_pp_table_entry = tonga_get_pp_table_entry,
6011 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6012 .print_current_perforce_level = tonga_print_current_perforce_level,
0859ed3d
RZ		 6013 .powerdown_uvd = tonga_phm_powerdown_uvd,
6014 .powergate_uvd = tonga_phm_powergate_uvd,
6015 .powergate_vce = tonga_phm_powergate_vce,
6016 .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
bbb207f3
RZ		 6017 .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6018 .display_config_changed = tonga_display_configuration_changed_task,
1e4854e9
RZ		 6019 .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6020 .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6021 .get_temperature = tonga_thermal_get_temperature,
6022 .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6023 .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6024 .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6025 .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6026 .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6027 .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6028 .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6029 .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6030 .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
e829ecdb
RZ		 6031 .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6032 .check_states_equal = tonga_check_states_equal,
c82baa28 6033};
6034
6035int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6036{
6037 tonga_hwmgr *data;
6038
6039 data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
6040 if (data == NULL)
6041 return -ENOMEM;
6042 memset(data, 0x00, sizeof(tonga_hwmgr));
6043
6044 hwmgr->backend = data;
6045 hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6046 hwmgr->pptable_func = &tonga_pptable_funcs;
1e4854e9 6047 pp_tonga_thermal_initialize(hwmgr);
c82baa28 6048 return 0;
6049}
6050
Linux kernel - Deliverables
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