[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / inc / hwmgr.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _HWMGR_H_
#define _HWMGR_H_

#include "amd_powerplay.h"
#include "pp_instance.h"
#include "hardwaremanager.h"
#include "pp_power_source.h"

struct pp_instance;
struct pp_hwmgr;
struct pp_hw_power_state;
struct pp_power_state;
struct PP_VCEState;

enum PP_Result {
	PP_Result_TableImmediateExit = 0x13,
};

#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
#define PCIE_PERF_REQ_FORCE_LOWPOWER    1
#define PCIE_PERF_REQ_GEN1         2
#define PCIE_PERF_REQ_GEN2         3
#define PCIE_PERF_REQ_GEN3         4

enum PHM_BackEnd_Magic {
	PHM_Dummy_Magic       = 0xAA5555AA,
	PHM_RV770_Magic       = 0xDCBAABCD,
	PHM_Kong_Magic        = 0x239478DF,
	PHM_NIslands_Magic    = 0x736C494E,
	PHM_Sumo_Magic        = 0x8339FA11,
	PHM_SIslands_Magic    = 0x369431AC,
	PHM_Trinity_Magic     = 0x96751873,
	PHM_CIslands_Magic    = 0x38AC78B0,
	PHM_Kv_Magic          = 0xDCBBABC0,
	PHM_VIslands_Magic    = 0x20130307,
	PHM_Cz_Magic          = 0x67DCBA25
};

enum PP_DAL_POWERLEVEL {
	PP_DAL_POWERLEVEL_INVALID = 0,
	PP_DAL_POWERLEVEL_ULTRALOW,
	PP_DAL_POWERLEVEL_LOW,
	PP_DAL_POWERLEVEL_NOMINAL,
	PP_DAL_POWERLEVEL_PERFORMANCE,

	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
};

#define PHM_PCIE_POWERGATING_TARGET_GFX            0
#define PHM_PCIE_POWERGATING_TARGET_DDI            1
#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
#define PHM_PCIE_POWERGATING_TARGET_PHY            3

typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
				  void *output, void *storage, int result);

typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);

struct phm_acp_arbiter {
	uint32_t acpclk;
};

struct phm_uvd_arbiter {
	uint32_t vclk;
	uint32_t dclk;
	uint32_t vclk_ceiling;
	uint32_t dclk_ceiling;
};

struct phm_vce_arbiter {
	uint32_t   evclk;
	uint32_t   ecclk;
};

struct phm_gfx_arbiter {
	uint32_t sclk;
	uint32_t mclk;
	uint32_t sclk_over_drive;
	uint32_t mclk_over_drive;
	uint32_t sclk_threshold;
	uint32_t num_cus;
};

/* Entries in the master tables */
struct phm_master_table_item {
	phm_check_function isFunctionNeededInRuntimeTable;
	phm_table_function tableFunction;
};

enum phm_master_table_flag {
	PHM_MasterTableFlag_None         = 0,
	PHM_MasterTableFlag_ExitOnError  = 1,
};

/* The header of the master tables */
struct phm_master_table_header {
	uint32_t storage_size;
	uint32_t flags;
	struct phm_master_table_item *master_list;
};

struct phm_runtime_table_header {
	uint32_t storage_size;
	bool exit_error;
	phm_table_function *function_list;
};

struct phm_clock_array {
	uint32_t count;
	uint32_t values[1];
};

struct phm_clock_voltage_dependency_record {
	uint32_t clk;
	uint32_t v;
};

struct phm_vceclock_voltage_dependency_record {
	uint32_t ecclk;
	uint32_t evclk;
	uint32_t v;
};

struct phm_uvdclock_voltage_dependency_record {
	uint32_t vclk;
	uint32_t dclk;
	uint32_t v;
};

struct phm_samuclock_voltage_dependency_record {
	uint32_t samclk;
	uint32_t v;
};

struct phm_acpclock_voltage_dependency_record {
	uint32_t acpclk;
	uint32_t v;
};

struct phm_clock_voltage_dependency_table {
	uint32_t count;										/* Number of entries. */
	struct phm_clock_voltage_dependency_record entries[1];		/* Dynamically allocate count entries. */
};

struct phm_phase_shedding_limits_record {
	uint32_t  Voltage;
	uint32_t    Sclk;
	uint32_t    Mclk;
};


extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
			      struct phm_runtime_table_header *rt_table,
			      void *input, void *output);

extern int phm_construct_table(struct pp_hwmgr *hwmgr,
			       struct phm_master_table_header *master_table,
			       struct phm_runtime_table_header *rt_table);

extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
			     struct phm_runtime_table_header *rt_table);


struct phm_uvd_clock_voltage_dependency_record {
	uint32_t vclk;
	uint32_t dclk;
	uint32_t v;
};

struct phm_uvd_clock_voltage_dependency_table {
	uint8_t count;
	struct phm_uvd_clock_voltage_dependency_record entries[1];
};

struct phm_acp_clock_voltage_dependency_record {
	uint32_t acpclk;
	uint32_t v;
};

struct phm_acp_clock_voltage_dependency_table {
	uint32_t count;
	struct phm_acp_clock_voltage_dependency_record entries[1];
};

struct phm_vce_clock_voltage_dependency_record {
	uint32_t ecclk;
	uint32_t evclk;
	uint32_t v;
};

struct phm_phase_shedding_limits_table {
	uint32_t                           count;
	struct phm_phase_shedding_limits_record  entries[1];
};

struct phm_vceclock_voltage_dependency_table {
	uint8_t count;                                    /* Number of entries. */
	struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};

struct phm_uvdclock_voltage_dependency_table {
	uint8_t count;                                    /* Number of entries. */
	struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};

struct phm_samuclock_voltage_dependency_table {
	uint8_t count;                                    /* Number of entries. */
	struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};

struct phm_acpclock_voltage_dependency_table {
	uint32_t count;                                    /* Number of entries. */
	struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};

struct phm_vce_clock_voltage_dependency_table {
	uint8_t count;
	struct phm_vce_clock_voltage_dependency_record entries[1];
};

struct pp_hwmgr_func {
	int (*backend_init)(struct pp_hwmgr *hw_mgr);
	int (*backend_fini)(struct pp_hwmgr *hw_mgr);
	int (*asic_setup)(struct pp_hwmgr *hw_mgr);
	int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
	int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, enum amd_dpm_forced_level level);
	int (*dynamic_state_management_enable)(struct pp_hwmgr *hw_mgr);
	int (*patch_boot_state)(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps);
	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, unsigned long, struct pp_power_state *);
	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
};

struct pp_table_func {
	int (*pptable_init)(struct pp_hwmgr *hw_mgr);
	int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
	int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
	int (*pptable_get_vce_state_table_entry)(
						struct pp_hwmgr *hwmgr,
						unsigned long i,
						struct PP_VCEState *vce_state,
						void **clock_info,
						unsigned long *flag);
};

union phm_cac_leakage_record {
	struct {
		uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
		uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
	};
	struct {
		uint16_t Vddc1;
		uint16_t Vddc2;
		uint16_t Vddc3;
	};
};

struct phm_cac_leakage_table {
	uint32_t count;
	union phm_cac_leakage_record entries[1];
};

struct phm_samu_clock_voltage_dependency_record {
	uint32_t samclk;
	uint32_t v;
};


struct phm_samu_clock_voltage_dependency_table {
	uint8_t count;
	struct phm_samu_clock_voltage_dependency_record entries[1];
};

struct phm_cac_tdp_table {
	uint16_t usTDP;
	uint16_t usConfigurableTDP;
	uint16_t usTDC;
	uint16_t usBatteryPowerLimit;
	uint16_t usSmallPowerLimit;
	uint16_t usLowCACLeakage;
	uint16_t usHighCACLeakage;
	uint16_t usMaximumPowerDeliveryLimit;
	uint16_t usOperatingTempMinLimit;
	uint16_t usOperatingTempMaxLimit;
	uint16_t usOperatingTempStep;
	uint16_t usOperatingTempHyst;
	uint16_t usDefaultTargetOperatingTemp;
	uint16_t usTargetOperatingTemp;
	uint16_t usPowerTuneDataSetID;
	uint16_t usSoftwareShutdownTemp;
	uint16_t usClockStretchAmount;
	uint16_t usTemperatureLimitHotspot;
	uint16_t usTemperatureLimitLiquid1;
	uint16_t usTemperatureLimitLiquid2;
	uint16_t usTemperatureLimitVrVddc;
	uint16_t usTemperatureLimitVrMvdd;
	uint16_t usTemperatureLimitPlx;
	uint8_t  ucLiquid1_I2C_address;
	uint8_t  ucLiquid2_I2C_address;
	uint8_t  ucLiquid_I2C_Line;
	uint8_t  ucVr_I2C_address;
	uint8_t  ucVr_I2C_Line;
	uint8_t  ucPlx_I2C_address;
	uint8_t  ucPlx_I2C_Line;
};

struct phm_ppm_table {
	uint8_t   ppm_design;
	uint16_t  cpu_core_number;
	uint32_t  platform_tdp;
	uint32_t  small_ac_platform_tdp;
	uint32_t  platform_tdc;
	uint32_t  small_ac_platform_tdc;
	uint32_t  apu_tdp;
	uint32_t  dgpu_tdp;
	uint32_t  dgpu_ulv_power;
	uint32_t  tj_max;
};

struct phm_vq_budgeting_record {
	uint32_t ulCUs;
	uint32_t ulSustainableSOCPowerLimitLow;
	uint32_t ulSustainableSOCPowerLimitHigh;
	uint32_t ulMinSclkLow;
	uint32_t ulMinSclkHigh;
	uint8_t  ucDispConfig;
	uint32_t ulDClk;
	uint32_t ulEClk;
	uint32_t ulSustainableSclk;
	uint32_t ulSustainableCUs;
};

struct phm_vq_budgeting_table {
	uint8_t numEntries;
	struct phm_vq_budgeting_record entries[1];
};

struct phm_clock_and_voltage_limits {
	uint32_t sclk;
	uint32_t mclk;
	uint16_t vddc;
	uint16_t vddci;
	uint16_t vddgfx;
};


struct phm_dynamic_state_info {
	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
	struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
	struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
	struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
	struct phm_clock_array                    *valid_sclk_values;
	struct phm_clock_array                    *valid_mclk_values;
	struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
	struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
	uint32_t                                  mclk_sclk_ratio;
	uint32_t                                  sclk_mclk_delta;
	uint32_t                                  vddc_vddci_delta;
	uint32_t                                  min_vddc_for_pcie_gen2;
	struct phm_cac_leakage_table              *cac_leakage_table;
	struct phm_phase_shedding_limits_table	  *vddc_phase_shed_limits_table;

	struct phm_vce_clock_voltage_dependency_table
					    *vce_clocl_voltage_dependency_table;
	struct phm_uvd_clock_voltage_dependency_table
					    *uvd_clocl_voltage_dependency_table;
	struct phm_acp_clock_voltage_dependency_table
					    *acp_clock_voltage_dependency_table;
	struct phm_samu_clock_voltage_dependency_table
					   *samu_clock_voltage_dependency_table;

	struct phm_ppm_table                          *ppm_parameter_table;
	struct phm_cac_tdp_table                      *cac_dtp_table;
	struct phm_clock_voltage_dependency_table	  *vdd_gfx_dependency_on_sclk;
	struct phm_vq_budgeting_table		  		  *vq_budgeting_table;
};

struct pp_hwmgr {
	uint32_t chip_family;
	uint32_t chip_id;
	uint32_t hw_revision;
	uint32_t sub_sys_id;
	uint32_t sub_vendor_id;

	void *device;
	struct pp_smumgr *smumgr;
	const void *soft_pp_table;
	enum amd_dpm_forced_level dpm_level;

	struct phm_gfx_arbiter gfx_arbiter;
	struct phm_acp_arbiter acp_arbiter;
	struct phm_uvd_arbiter uvd_arbiter;
	struct phm_vce_arbiter vce_arbiter;
	uint32_t usec_timeout;
	void *pptable;
	struct phm_platform_descriptor platform_descriptor;
	void *backend;
	enum PP_DAL_POWERLEVEL	dal_power_level;
	struct phm_dynamic_state_info dyn_state;
	struct phm_runtime_table_header setup_asic;
	struct phm_runtime_table_header disable_dynamic_state_management;
	struct phm_runtime_table_header enable_dynamic_state_management;
	const struct pp_hwmgr_func *hwmgr_func;
	const struct pp_table_func *pptable_func;
	struct pp_power_state    *ps;
        enum pp_power_source  power_source;
	uint32_t num_ps;
	uint32_t ps_size;
	struct pp_power_state    *current_ps;
	struct pp_power_state    *request_ps;
	struct pp_power_state    *boot_ps;
	struct pp_power_state    *uvd_ps;
};


extern int hwmgr_init(struct amd_pp_init *pp_init,
		      struct pp_instance *handle);

extern int hwmgr_fini(struct pp_hwmgr *hwmgr);

extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);

extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
				uint32_t value, uint32_t mask);

extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
				uint32_t index, uint32_t value, uint32_t mask);


extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
				uint32_t indirect_port,
				uint32_t index,
				uint32_t value,
				uint32_t mask);

extern void phm_wait_for_indirect_register_unequal(
				struct pp_hwmgr *hwmgr,
				uint32_t indirect_port,
				uint32_t index,
				uint32_t value,
				uint32_t mask);

#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK

#define PHM_SET_FIELD(origval, reg, field, fieldval)	\
	(((origval) & ~PHM_FIELD_MASK(reg, field)) |	\
	 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))

#define PHM_GET_FIELD(value, reg, field)	\
	(((value) & PHM_FIELD_MASK(reg, field)) >>	\
	 PHM_FIELD_SHIFT(reg, field))


#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask)	\
	phm_wait_on_register(hwmgr, index, value, mask)

#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask)	\
	phm_wait_for_register_unequal(hwmgr, index, value, mask)

#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
	phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)

#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
	phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)

#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
	phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)

#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
	phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)

/* Operations on named registers. */

#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask)	\
	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)

#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)	\
	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)

#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)	\
	PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)	\
	PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)	\
	PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)	\
	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

/* Operations on named fields. */

#define PHM_READ_FIELD(device, reg, field)	\
	PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)

#define PHM_READ_INDIRECT_FIELD(device, port, reg, field)	\
	PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
			reg, field)

#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)	\
	PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
			reg, field)

#define PHM_WRITE_FIELD(device, reg, field, fieldval)	\
	cgs_write_register(device, mm##reg, PHM_SET_FIELD(	\
				cgs_read_register(device, mm##reg), reg, field, fieldval))

#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)	\
	cgs_write_ind_register(device, port, ix##reg,	\
			PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
				reg, field, fieldval))

#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)	\
	cgs_write_ind_register(device, port, ix##reg,	\
			PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
				reg, field, fieldval))

#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval)	\
	PHM_WAIT_REGISTER(hwmgr, reg, (fieldval)	\
			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)	\
	PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\
			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)	\
	PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\
			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)	\
	PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval)	\
			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)	\
	PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)	\
			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)	\
	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)	\
			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

/* Operations on arrays of registers & fields. */

#define PHM_READ_ARRAY_REGISTER(device, reg, offset)	\
	cgs_read_register(device, mm##reg + (offset))

#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value)	\
	cgs_write_register(device, mm##reg + (offset), value)

#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask)	\
	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)

#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask)	\
	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)

#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
	PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)

#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)	\
	PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset,	\
			PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset),	\
				reg, field, fieldvalue))

#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)	\
	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset),	\
			(fieldvalue) << PHM_FIELD_SHIFT(reg, field),	\
			PHM_FIELD_MASK(reg, field))

#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue)	\
	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset),	\
			(fieldvalue) << PHM_FIELD_SHIFT(reg, field),	\
			PHM_FIELD_MASK(reg, field))

#endif /* _HWMGR_H_ */
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef _HWMGR_H_
	24	#define _HWMGR_H_
	25
	26	#include "amd_powerplay.h"
	27	#include "pp_instance.h"
	28	#include "hardwaremanager.h"
	29	#include "pp_power_source.h"
	30
	31	struct pp_instance;
	32	struct pp_hwmgr;
	33	struct pp_hw_power_state;
	34	struct pp_power_state;
	35	struct PP_VCEState;
	36
	37	enum PP_Result {
	38	PP_Result_TableImmediateExit = 0x13,
	39	};
	40
	41	#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
	42	#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
	43	#define PCIE_PERF_REQ_GEN1 2
	44	#define PCIE_PERF_REQ_GEN2 3
	45	#define PCIE_PERF_REQ_GEN3 4
	46
	47	enum PHM_BackEnd_Magic {
	48	PHM_Dummy_Magic = 0xAA5555AA,
	49	PHM_RV770_Magic = 0xDCBAABCD,
	50	PHM_Kong_Magic = 0x239478DF,
	51	PHM_NIslands_Magic = 0x736C494E,
	52	PHM_Sumo_Magic = 0x8339FA11,
	53	PHM_SIslands_Magic = 0x369431AC,
	54	PHM_Trinity_Magic = 0x96751873,
	55	PHM_CIslands_Magic = 0x38AC78B0,
	56	PHM_Kv_Magic = 0xDCBBABC0,
	57	PHM_VIslands_Magic = 0x20130307,
	58	PHM_Cz_Magic = 0x67DCBA25
	59	};
	60
	61	enum PP_DAL_POWERLEVEL {
	62	PP_DAL_POWERLEVEL_INVALID = 0,
	63	PP_DAL_POWERLEVEL_ULTRALOW,
	64	PP_DAL_POWERLEVEL_LOW,
65	PP_DAL_POWERLEVEL_NOMINAL,
66	PP_DAL_POWERLEVEL_PERFORMANCE,
67
68	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
69	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
70	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
71	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
72	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
73	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
74	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
75	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
76	};
77
78	#define PHM_PCIE_POWERGATING_TARGET_GFX 0
79	#define PHM_PCIE_POWERGATING_TARGET_DDI 1
80	#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
81	#define PHM_PCIE_POWERGATING_TARGET_PHY 3
82
83	typedef int (phm_table_function)(struct pp_hwmgr hwmgr, void *input,
84	void output, void storage, int result);
85
86	typedef bool (phm_check_function)(struct pp_hwmgr hwmgr);
87
88	struct phm_acp_arbiter {
89	uint32_t acpclk;
90	};
91
92	struct phm_uvd_arbiter {
93	uint32_t vclk;
94	uint32_t dclk;
95	uint32_t vclk_ceiling;
96	uint32_t dclk_ceiling;
97	};
98
99	struct phm_vce_arbiter {
100	uint32_t evclk;
101	uint32_t ecclk;
102	};
103
104	struct phm_gfx_arbiter {
105	uint32_t sclk;
106	uint32_t mclk;
107	uint32_t sclk_over_drive;
108	uint32_t mclk_over_drive;
109	uint32_t sclk_threshold;
110	uint32_t num_cus;
111	};
112
113	/* Entries in the master tables */
114	struct phm_master_table_item {
115	phm_check_function isFunctionNeededInRuntimeTable;
116	phm_table_function tableFunction;
117	};
118
119	enum phm_master_table_flag {
120	PHM_MasterTableFlag_None = 0,
121	PHM_MasterTableFlag_ExitOnError = 1,
122	};
123
124	/* The header of the master tables */
125	struct phm_master_table_header {
126	uint32_t storage_size;
127	uint32_t flags;
128	struct phm_master_table_item *master_list;
129	};
130
131	struct phm_runtime_table_header {
132	uint32_t storage_size;
133	bool exit_error;
134	phm_table_function *function_list;
135	};
136
137	struct phm_clock_array {
138	uint32_t count;
139	uint32_t values[1];
140	};
141
142	struct phm_clock_voltage_dependency_record {
143	uint32_t clk;
144	uint32_t v;
145	};
146
147	struct phm_vceclock_voltage_dependency_record {
148	uint32_t ecclk;
149	uint32_t evclk;
150	uint32_t v;
151	};
152
153	struct phm_uvdclock_voltage_dependency_record {
154	uint32_t vclk;
155	uint32_t dclk;
156	uint32_t v;
157	};
158
159	struct phm_samuclock_voltage_dependency_record {
160	uint32_t samclk;
161	uint32_t v;
162	};
163
164	struct phm_acpclock_voltage_dependency_record {
165	uint32_t acpclk;
166	uint32_t v;
167	};
168
169	struct phm_clock_voltage_dependency_table {
170	uint32_t count; /* Number of entries. */
171	struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
172	};
173
174	struct phm_phase_shedding_limits_record {
175	uint32_t Voltage;
176	uint32_t Sclk;
177	uint32_t Mclk;
178	};
179
180
181	extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
182	struct phm_runtime_table_header *rt_table,
183	void input, void output);
184
185	extern int phm_construct_table(struct pp_hwmgr *hwmgr,
186	struct phm_master_table_header *master_table,
187	struct phm_runtime_table_header *rt_table);
188
189	extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
190	struct phm_runtime_table_header *rt_table);
191
192
193	struct phm_uvd_clock_voltage_dependency_record {
194	uint32_t vclk;
195	uint32_t dclk;
196	uint32_t v;
197	};
198
199	struct phm_uvd_clock_voltage_dependency_table {
200	uint8_t count;
201	struct phm_uvd_clock_voltage_dependency_record entries[1];
202	};
203
204	struct phm_acp_clock_voltage_dependency_record {
205	uint32_t acpclk;
206	uint32_t v;
207	};
208
209	struct phm_acp_clock_voltage_dependency_table {
210	uint32_t count;
211	struct phm_acp_clock_voltage_dependency_record entries[1];
212	};
213
214	struct phm_vce_clock_voltage_dependency_record {
215	uint32_t ecclk;
216	uint32_t evclk;
217	uint32_t v;
218	};
219
220	struct phm_phase_shedding_limits_table {
221	uint32_t count;
222	struct phm_phase_shedding_limits_record entries[1];
223	};
224
225	struct phm_vceclock_voltage_dependency_table {
226	uint8_t count; /* Number of entries. */
227	struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
228	};
229
230	struct phm_uvdclock_voltage_dependency_table {
231	uint8_t count; /* Number of entries. */
232	struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
233	};
234
235	struct phm_samuclock_voltage_dependency_table {
236	uint8_t count; /* Number of entries. */
237	struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
238	};
239
240	struct phm_acpclock_voltage_dependency_table {
241	uint32_t count; /* Number of entries. */
242	struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
243	};
244
245	struct phm_vce_clock_voltage_dependency_table {
246	uint8_t count;
247	struct phm_vce_clock_voltage_dependency_record entries[1];
248	};
249
250	struct pp_hwmgr_func {
251	int (backend_init)(struct pp_hwmgr hw_mgr);
252	int (backend_fini)(struct pp_hwmgr hw_mgr);
253	int (asic_setup)(struct pp_hwmgr hw_mgr);
254	int (get_power_state_size)(struct pp_hwmgr hw_mgr);
255	int (force_dpm_level)(struct pp_hwmgr hw_mgr, enum amd_dpm_forced_level level);
256	int (dynamic_state_management_enable)(struct pp_hwmgr hw_mgr);
257	int (patch_boot_state)(struct pp_hwmgr hwmgr, struct pp_hw_power_state *hw_ps);
258	int (get_pp_table_entry)(struct pp_hwmgr hwmgr, unsigned long, struct pp_power_state *);
259	int (get_num_of_pp_table_entries)(struct pp_hwmgr hwmgr);
260	};
261
262	struct pp_table_func {
263	int (pptable_init)(struct pp_hwmgr hw_mgr);
264	int (pptable_fini)(struct pp_hwmgr hw_mgr);
265	int (pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr hw_mgr);
266	int (*pptable_get_vce_state_table_entry)(
267	struct pp_hwmgr *hwmgr,
268	unsigned long i,
269	struct PP_VCEState *vce_state,
270	void **clock_info,
271	unsigned long *flag);
272	};
273
274	union phm_cac_leakage_record {
275	struct {
276	uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
277	uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
278	};
279	struct {
280	uint16_t Vddc1;
281	uint16_t Vddc2;
282	uint16_t Vddc3;
283	};
284	};
285
286	struct phm_cac_leakage_table {
287	uint32_t count;
288	union phm_cac_leakage_record entries[1];
289	};
290
291	struct phm_samu_clock_voltage_dependency_record {
292	uint32_t samclk;
293	uint32_t v;
294	};
295
296
297	struct phm_samu_clock_voltage_dependency_table {
298	uint8_t count;
299	struct phm_samu_clock_voltage_dependency_record entries[1];
300	};
301
302	struct phm_cac_tdp_table {
303	uint16_t usTDP;
304	uint16_t usConfigurableTDP;
305	uint16_t usTDC;
306	uint16_t usBatteryPowerLimit;
307	uint16_t usSmallPowerLimit;
308	uint16_t usLowCACLeakage;
309	uint16_t usHighCACLeakage;
310	uint16_t usMaximumPowerDeliveryLimit;
311	uint16_t usOperatingTempMinLimit;
312	uint16_t usOperatingTempMaxLimit;
313	uint16_t usOperatingTempStep;
314	uint16_t usOperatingTempHyst;
315	uint16_t usDefaultTargetOperatingTemp;
316	uint16_t usTargetOperatingTemp;
317	uint16_t usPowerTuneDataSetID;
318	uint16_t usSoftwareShutdownTemp;
319	uint16_t usClockStretchAmount;
320	uint16_t usTemperatureLimitHotspot;
321	uint16_t usTemperatureLimitLiquid1;
322	uint16_t usTemperatureLimitLiquid2;
323	uint16_t usTemperatureLimitVrVddc;
324	uint16_t usTemperatureLimitVrMvdd;
325	uint16_t usTemperatureLimitPlx;
326	uint8_t ucLiquid1_I2C_address;
327	uint8_t ucLiquid2_I2C_address;
328	uint8_t ucLiquid_I2C_Line;
329	uint8_t ucVr_I2C_address;
330	uint8_t ucVr_I2C_Line;
331	uint8_t ucPlx_I2C_address;
332	uint8_t ucPlx_I2C_Line;
333	};
334
335	struct phm_ppm_table {
336	uint8_t ppm_design;
337	uint16_t cpu_core_number;
338	uint32_t platform_tdp;
339	uint32_t small_ac_platform_tdp;
340	uint32_t platform_tdc;
341	uint32_t small_ac_platform_tdc;
342	uint32_t apu_tdp;
343	uint32_t dgpu_tdp;
344	uint32_t dgpu_ulv_power;
345	uint32_t tj_max;
346	};
347
348	struct phm_vq_budgeting_record {
349	uint32_t ulCUs;
350	uint32_t ulSustainableSOCPowerLimitLow;
351	uint32_t ulSustainableSOCPowerLimitHigh;
352	uint32_t ulMinSclkLow;
353	uint32_t ulMinSclkHigh;
354	uint8_t ucDispConfig;
355	uint32_t ulDClk;
356	uint32_t ulEClk;
357	uint32_t ulSustainableSclk;
358	uint32_t ulSustainableCUs;
359	};
360
361	struct phm_vq_budgeting_table {
362	uint8_t numEntries;
363	struct phm_vq_budgeting_record entries[1];
364	};
365
366	struct phm_clock_and_voltage_limits {
367	uint32_t sclk;
368	uint32_t mclk;
369	uint16_t vddc;
370	uint16_t vddci;
371	uint16_t vddgfx;
372	};
373
374
375
376	struct phm_dynamic_state_info {
377	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
378	struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
379	struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
380	struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
381	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
382	struct phm_clock_array *valid_sclk_values;
383	struct phm_clock_array *valid_mclk_values;
384	struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
385	struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
386	uint32_t mclk_sclk_ratio;
387	uint32_t sclk_mclk_delta;
388	uint32_t vddc_vddci_delta;
389	uint32_t min_vddc_for_pcie_gen2;
390	struct phm_cac_leakage_table *cac_leakage_table;
391	struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
392
393	struct phm_vce_clock_voltage_dependency_table
394	*vce_clocl_voltage_dependency_table;
395	struct phm_uvd_clock_voltage_dependency_table
396	*uvd_clocl_voltage_dependency_table;
397	struct phm_acp_clock_voltage_dependency_table
398	*acp_clock_voltage_dependency_table;
399	struct phm_samu_clock_voltage_dependency_table
400	*samu_clock_voltage_dependency_table;
401
402	struct phm_ppm_table *ppm_parameter_table;
403	struct phm_cac_tdp_table *cac_dtp_table;
404	struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
405	struct phm_vq_budgeting_table *vq_budgeting_table;
406	};
407
408	struct pp_hwmgr {
409	uint32_t chip_family;
410	uint32_t chip_id;
411	uint32_t hw_revision;
412	uint32_t sub_sys_id;
413	uint32_t sub_vendor_id;
414
415	void *device;
416	struct pp_smumgr *smumgr;
417	const void *soft_pp_table;
418	enum amd_dpm_forced_level dpm_level;
419
420	struct phm_gfx_arbiter gfx_arbiter;
421	struct phm_acp_arbiter acp_arbiter;
422	struct phm_uvd_arbiter uvd_arbiter;
423	struct phm_vce_arbiter vce_arbiter;
424	uint32_t usec_timeout;
425	void *pptable;
426	struct phm_platform_descriptor platform_descriptor;
427	void *backend;
428	enum PP_DAL_POWERLEVEL dal_power_level;
429	struct phm_dynamic_state_info dyn_state;
430	struct phm_runtime_table_header setup_asic;
431	struct phm_runtime_table_header disable_dynamic_state_management;
432	struct phm_runtime_table_header enable_dynamic_state_management;
433	const struct pp_hwmgr_func *hwmgr_func;
434	const struct pp_table_func *pptable_func;
435	struct pp_power_state *ps;
436	enum pp_power_source power_source;
437	uint32_t num_ps;
438	uint32_t ps_size;
439	struct pp_power_state *current_ps;
440	struct pp_power_state *request_ps;
441	struct pp_power_state *boot_ps;
442	struct pp_power_state *uvd_ps;
443	};
444
445
446	extern int hwmgr_init(struct amd_pp_init *pp_init,
447	struct pp_instance *handle);
448
449	extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
450
451	extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
452
453	extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
454	uint32_t value, uint32_t mask);
455
456	extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
457	uint32_t index, uint32_t value, uint32_t mask);
458
459
460
461	extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
462	uint32_t indirect_port,
463	uint32_t index,
464	uint32_t value,
465	uint32_t mask);
466
467	extern void phm_wait_for_indirect_register_unequal(
468	struct pp_hwmgr *hwmgr,
469	uint32_t indirect_port,
470	uint32_t index,
471	uint32_t value,
472	uint32_t mask);
473
474	#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
475	#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
476
477	#define PHM_SET_FIELD(origval, reg, field, fieldval) \
478	(((origval) & ~PHM_FIELD_MASK(reg, field)) \| \
479	(PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
480
481	#define PHM_GET_FIELD(value, reg, field) \
482	(((value) & PHM_FIELD_MASK(reg, field)) >> \
483	PHM_FIELD_SHIFT(reg, field))
484
485
486	#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \
487	phm_wait_on_register(hwmgr, index, value, mask)
488
489	#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \
490	phm_wait_for_register_unequal(hwmgr, index, value, mask)
491
492	#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
493	phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
494
495	#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
496	phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
497
498	#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
499	phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
500
501	#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
502	phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
503
504	/* Operations on named registers. */
505
506	#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \
507	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
508
509	#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
510	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
511
512	#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
513	PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
514
515	#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
516	PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
517
518	#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
519	PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
520
521	#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
522	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
523
524	/* Operations on named fields. */
525
526	#define PHM_READ_FIELD(device, reg, field) \
527	PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
528
529	#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
530	PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
531	reg, field)
532
533	#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
534	PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
535	reg, field)
536
537	#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
538	cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
539	cgs_read_register(device, mm##reg), reg, field, fieldval))
540
541	#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
542	cgs_write_ind_register(device, port, ix##reg, \
543	PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
544	reg, field, fieldval))
545
546	#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
547	cgs_write_ind_register(device, port, ix##reg, \
548	PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
549	reg, field, fieldval))
550
551	#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \
552	PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \
553	<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
554
555	#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
556	PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
557	<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
558
559	#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
560	PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
561	<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
562
563	#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
564	PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \
565	<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
566
567	#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
568	PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
569	<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
570
571	#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
572	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
573	<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
574
575	/* Operations on arrays of registers & fields. */
576
577	#define PHM_READ_ARRAY_REGISTER(device, reg, offset) \
578	cgs_read_register(device, mm##reg + (offset))
579
580	#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \
581	cgs_write_register(device, mm##reg + (offset), value)
582
583	#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \
584	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
585
586	#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \
587	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
588
589	#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
590	PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
591
592	#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
593	PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \
594	PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \
595	reg, field, fieldvalue))
596
597	#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
598	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
599	(fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
600	PHM_FIELD_MASK(reg, field))
601
602	#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \
603	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
604	(fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
605	PHM_FIELD_MASK(reg, field))
606
607	#endif /* _HWMGR_H_ */