[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / inc / smumgr.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _SMUMGR_H_
#define _SMUMGR_H_
#include <linux/types.h>
#include "pp_instance.h"
#include "amd_powerplay.h"

struct pp_smumgr;
struct pp_instance;

#define smu_lower_32_bits(n) ((uint32_t)(n))
#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))

enum AVFS_BTC_STATUS {
	AVFS_BTC_BOOT = 0,
	AVFS_BTC_BOOT_STARTEDSMU,
	AVFS_LOAD_VIRUS,
	AVFS_BTC_VIRUS_LOADED,
	AVFS_BTC_VIRUS_FAIL,
	AVFS_BTC_COMPLETED_PREVIOUSLY,
	AVFS_BTC_ENABLEAVFS,
	AVFS_BTC_STARTED,
	AVFS_BTC_FAILED,
	AVFS_BTC_RESTOREVFT_FAILED,
	AVFS_BTC_SAVEVFT_FAILED,
	AVFS_BTC_DPMTABLESETUP_FAILED,
	AVFS_BTC_COMPLETED_UNSAVED,
	AVFS_BTC_COMPLETED_SAVED,
	AVFS_BTC_COMPLETED_RESTORED,
	AVFS_BTC_DISABLED,
	AVFS_BTC_NOTSUPPORTED,
	AVFS_BTC_SMUMSG_ERROR
};

struct pp_smumgr_func {
	int (*smu_init)(struct pp_smumgr *smumgr);
	int (*smu_fini)(struct pp_smumgr *smumgr);
	int (*start_smu)(struct pp_smumgr *smumgr);
	int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
				    uint32_t firmware);
	int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
	int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
					    uint32_t firmware);
	int (*get_argument)(struct pp_smumgr *smumgr);
	int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
	int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
					  uint16_t msg, uint32_t parameter);
	int (*download_pptable_settings)(struct pp_smumgr *smumgr,
					 void **table);
	int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
};

struct pp_smumgr {
	uint32_t chip_family;
	uint32_t chip_id;
	uint32_t hw_revision;
	void *device;
	void *backend;
	uint32_t usec_timeout;
	bool reload_fw;
	const struct pp_smumgr_func *smumgr_funcs;
};


extern int smum_init(struct amd_pp_init *pp_init,
		     struct pp_instance *handle);

extern int smum_fini(struct pp_smumgr *smumgr);

extern int smum_get_argument(struct pp_smumgr *smumgr);

extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);

extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);

extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);

extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
					uint16_t msg, uint32_t parameter);

extern int smum_wait_on_register(struct pp_smumgr *smumgr,
				uint32_t index, uint32_t value, uint32_t mask);

extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
				uint32_t index, uint32_t value, uint32_t mask);

extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
				uint32_t indirect_port, uint32_t index,
				uint32_t value, uint32_t mask);


extern void smum_wait_for_indirect_register_unequal(
				struct pp_smumgr *smumgr,
				uint32_t indirect_port, uint32_t index,
				uint32_t value, uint32_t mask);

extern int smu_allocate_memory(void *device, uint32_t size,
			 enum cgs_gpu_mem_type type,
			 uint32_t byte_align, uint64_t *mc_addr,
			 void **kptr, void *handle);

extern int smu_free_memory(void *device, void *handle);

#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT

#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK

#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr,			\
					port, index, value, mask)	\
	smum_wait_on_indirect_register(smumgr,				\
				mm##port##_INDEX, index, value, mask)

#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask)    \
	    SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)

#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval)                          \
	    SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
			            SMUM_FIELD_MASK(reg, field) )

#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,         \
							index, value, mask) \
		smum_wait_for_register_unequal(smumgr,            \
					index, value, mask)

#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask)		\
	SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,			\
				mm##reg, value, mask)

#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval)		\
	SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg,				\
		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
		SMUM_FIELD_MASK(reg, field))

#define SMUM_GET_FIELD(value, reg, field)				\
		(((value) & SMUM_FIELD_MASK(reg, field))		\
		>> SMUM_FIELD_SHIFT(reg, field))

#define SMUM_READ_FIELD(device, reg, field)                           \
		SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)

#define SMUM_SET_FIELD(value, reg, field, field_val)                  \
		(((value) & ~SMUM_FIELD_MASK(reg, field)) |                    \
		(SMUM_FIELD_MASK(reg, field) & ((field_val) <<                 \
			SMUM_FIELD_SHIFT(reg, field))))

#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
	    SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
			   reg, field)

#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr,		\
				port, index, value, mask)		\
	smum_wait_on_indirect_register(smumgr,				\
		mm##port##_INDEX_0, index, value, mask)

#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,	\
				port, index, value, mask)		\
	smum_wait_for_indirect_register_unequal(smumgr,			\
		mm##port##_INDEX_0, index, value, mask)


#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
	SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)

#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask)     \
		SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)


/*Operations on named fields.*/

#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
		SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
			reg, field)

#define SMUM_WRITE_FIELD(device, reg, field, fieldval)            \
		cgs_write_register(device, mm##reg, \
		SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))

#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
		cgs_write_ind_register(device, port, ix##reg, \
			SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
			reg, field, fieldval))


#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    		\
		cgs_write_ind_register(device, port, ix##reg, 				\
			SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), 	\
				       reg, field, fieldval))


#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
	SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg,		\
		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
		SMUM_FIELD_MASK(reg, field))

#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
	SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg,	\
		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
		SMUM_FIELD_MASK(reg, field))

#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask)    \
	smum_wait_for_indirect_register_unequal(smumgr,			\
		mm##port##_INDEX, index, value, mask)

#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask)    \
	    SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)

#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval)                          \
	    SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
			            SMUM_FIELD_MASK(reg, field) )

#endif
Commit	Line	Data
ac885b3a JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef _SMUMGR_H_
	24	#define _SMUMGR_H_
	25	#include <linux/types.h>
	26	#include "pp_instance.h"
	27	#include "amd_powerplay.h"
	28
	29	struct pp_smumgr;
	30	struct pp_instance;
	31
	32	#define smu_lower_32_bits(n) ((uint32_t)(n))
	33	#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
	34
b5be3a6b	35	enum AVFS_BTC_STATUS {
	36	AVFS_BTC_BOOT = 0,
	37	AVFS_BTC_BOOT_STARTEDSMU,
	38	AVFS_LOAD_VIRUS,
	39	AVFS_BTC_VIRUS_LOADED,
	40	AVFS_BTC_VIRUS_FAIL,
	41	AVFS_BTC_COMPLETED_PREVIOUSLY,
	42	AVFS_BTC_ENABLEAVFS,
	43	AVFS_BTC_STARTED,
	44	AVFS_BTC_FAILED,
	45	AVFS_BTC_RESTOREVFT_FAILED,
	46	AVFS_BTC_SAVEVFT_FAILED,
	47	AVFS_BTC_DPMTABLESETUP_FAILED,
	48	AVFS_BTC_COMPLETED_UNSAVED,
	49	AVFS_BTC_COMPLETED_SAVED,
	50	AVFS_BTC_COMPLETED_RESTORED,
	51	AVFS_BTC_DISABLED,
	52	AVFS_BTC_NOTSUPPORTED,
	53	AVFS_BTC_SMUMSG_ERROR
	54	};
	55
ac885b3a JZ	56	struct pp_smumgr_func {
	57	int (smu_init)(struct pp_smumgr smumgr);
	58	int (smu_fini)(struct pp_smumgr smumgr);
	59	int (start_smu)(struct pp_smumgr smumgr);
	60	int (check_fw_load_finish)(struct pp_smumgr smumgr,
	61	uint32_t firmware);
	62	int (request_smu_load_fw)(struct pp_smumgr smumgr);
	63	int (request_smu_load_specific_fw)(struct pp_smumgr smumgr,
	64	uint32_t firmware);
	65	int (get_argument)(struct pp_smumgr smumgr);
	66	int (send_msg_to_smc)(struct pp_smumgr smumgr, uint16_t msg);
	67	int (send_msg_to_smc_with_parameter)(struct pp_smumgr smumgr,
	68	uint16_t msg, uint32_t parameter);
	69	int (download_pptable_settings)(struct pp_smumgr smumgr,
	70	void **table);
	71	int (upload_pptable_settings)(struct pp_smumgr smumgr);
	72	};
	73
	74	struct pp_smumgr {
	75	uint32_t chip_family;
	76	uint32_t chip_id;
	77	uint32_t hw_revision;
	78	void *device;
	79	void *backend;
	80	uint32_t usec_timeout;
	81	bool reload_fw;
	82	const struct pp_smumgr_func *smumgr_funcs;
	83	};
	84
	85
	86	extern int smum_init(struct amd_pp_init *pp_init,
	87	struct pp_instance *handle);
	88
	89	extern int smum_fini(struct pp_smumgr *smumgr);
	90
	91	extern int smum_get_argument(struct pp_smumgr *smumgr);
	92
	93	extern int smum_download_powerplay_table(struct pp_smumgr smumgr, void *table);
	94
	95	extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
	96
	97	extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
	98
	99	extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
	100	uint16_t msg, uint32_t parameter);
	101
	102	extern int smum_wait_on_register(struct pp_smumgr *smumgr,
	103	uint32_t index, uint32_t value, uint32_t mask);
	104
	105	extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
	106	uint32_t index, uint32_t value, uint32_t mask);
	107
	108	extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
	109	uint32_t indirect_port, uint32_t index,
	110	uint32_t value, uint32_t mask);
	111
	112
	113	extern void smum_wait_for_indirect_register_unequal(
	114	struct pp_smumgr *smumgr,
	115	uint32_t indirect_port, uint32_t index,
	116	uint32_t value, uint32_t mask);
	117
	118	extern int smu_allocate_memory(void *device, uint32_t size,
	119	enum cgs_gpu_mem_type type,
120	uint32_t byte_align, uint64_t *mc_addr,
121	void *kptr, void handle);
122
123	extern int smu_free_memory(void device, void handle);
124
125	#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
126
127	#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
128
129	#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
130	port, index, value, mask) \
131	smum_wait_on_indirect_register(smumgr, \
132	mm##port##_INDEX, index, value, mask)
133
be832d84 HR	134	#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
	135	SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
	136
	137	#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
	138	SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
	139	SMUM_FIELD_MASK(reg, field) )
ac885b3a JZ	140
	141	#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
	142	index, value, mask) \
	143	smum_wait_for_register_unequal(smumgr, \
	144	index, value, mask)
	145
	146	#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \
	147	SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
	148	mm##reg, value, mask)
	149
	150	#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \
	151	SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \
	152	(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
	153	SMUM_FIELD_MASK(reg, field))
	154
	155	#define SMUM_GET_FIELD(value, reg, field) \
	156	(((value) & SMUM_FIELD_MASK(reg, field)) \
	157	>> SMUM_FIELD_SHIFT(reg, field))
	158
	159	#define SMUM_READ_FIELD(device, reg, field) \
	160	SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
	161
	162	#define SMUM_SET_FIELD(value, reg, field, field_val) \
	163	(((value) & ~SMUM_FIELD_MASK(reg, field)) \| \
	164	(SMUM_FIELD_MASK(reg, field) & ((field_val) << \
	165	SMUM_FIELD_SHIFT(reg, field))))
	166
be832d84 HR	167	#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
	168	SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
	169	reg, field)
	170
ac885b3a JZ	171	#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
	172	port, index, value, mask) \
	173	smum_wait_on_indirect_register(smumgr, \
	174	mm##port##_INDEX_0, index, value, mask)
	175
	176	#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
	177	port, index, value, mask) \
	178	smum_wait_for_indirect_register_unequal(smumgr, \
	179	mm##port##_INDEX_0, index, value, mask)
	180
	181
	182	#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
	183	SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
	184
	185	#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
	186	SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
	187
	188
	189	/Operations on named fields./
	190
	191	#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
	192	SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
	193	reg, field)
	194
	195	#define SMUM_WRITE_FIELD(device, reg, field, fieldval) \
	196	cgs_write_register(device, mm##reg, \
	197	SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))
	198
	199	#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
	200	cgs_write_ind_register(device, port, ix##reg, \
	201	SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
	202	reg, field, fieldval))
	203
be832d84 HR	204
	205	#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
	206	cgs_write_ind_register(device, port, ix##reg, \
	207	SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
	208	reg, field, fieldval))
	209
	210
ac885b3a JZ	211	#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
	212	SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \
	213	(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
	214	SMUM_FIELD_MASK(reg, field))
	215
	216	#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
	217	SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \
	218	(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
	219	SMUM_FIELD_MASK(reg, field))
be832d84 HR	220
	221	#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \
	222	smum_wait_for_indirect_register_unequal(smumgr, \
	223	mm##port##_INDEX, index, value, mask)
	224
	225	#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
	226	SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
	227
	228	#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
	229	SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
	230	SMUM_FIELD_MASK(reg, field) )
	231
ac885b3a	232	#endif