projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'nvmf-4.8-rc' of git://git.infradead.org/nvme-fabrics into for-linus
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / smumgr / tonga_smumgr.c
CommitLineData
1060029f
JZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/gfp.h>
27
28#include "smumgr.h"
29#include "tonga_smumgr.h"
30#include "pp_debug.h"
31#include "smu_ucode_xfer_vi.h"
32#include "tonga_ppsmc.h"
33#include "smu/smu_7_1_2_d.h"
34#include "smu/smu_7_1_2_sh_mask.h"
35#include "cgs_common.h"
36
37#define TONGA_SMC_SIZE 0x20000
38#define BUFFER_SIZE 80000
39#define MAX_STRING_SIZE 15
40#define BUFFER_SIZETWO 131072 /*128 *1024*/
41
42/**
43* Set the address for reading/writing the SMC SRAM space.
44* @param smumgr the address of the powerplay hardware manager.
45* @param smcAddress the address in the SMC RAM to access.
46*/
47static int tonga_set_smc_sram_address(struct pp_smumgr *smumgr,
48 uint32_t smcAddress, uint32_t limit)
49{
50 if (smumgr == NULL || smumgr->device == NULL)
51 return -EINVAL;
52 PP_ASSERT_WITH_CODE((0 == (3 & smcAddress)),
53 "SMC address must be 4 byte aligned.",
54 return -1;);
55
56 PP_ASSERT_WITH_CODE((limit > (smcAddress + 3)),
57 "SMC address is beyond the SMC RAM area.",
58 return -1;);
59
60 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smcAddress);
61 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
62
63 return 0;
64}
65
66/**
67* Copy bytes from an array into the SMC RAM space.
68*
69* @param smumgr the address of the powerplay SMU manager.
70* @param smcStartAddress the start address in the SMC RAM to copy bytes to.
71* @param src the byte array to copy the bytes from.
72* @param byteCount the number of bytes to copy.
73*/
74int tonga_copy_bytes_to_smc(struct pp_smumgr *smumgr,
75 uint32_t smcStartAddress, const uint8_t *src,
76 uint32_t byteCount, uint32_t limit)
77{
78 uint32_t addr;
79 uint32_t data, orig_data;
80 int result = 0;
81 uint32_t extra_shift;
82
83 if (smumgr == NULL || smumgr->device == NULL)
84 return -EINVAL;
85 PP_ASSERT_WITH_CODE((0 == (3 & smcStartAddress)),
86 "SMC address must be 4 byte aligned.",
87 return 0;);
88
89 PP_ASSERT_WITH_CODE((limit > (smcStartAddress + byteCount)),
90 "SMC address is beyond the SMC RAM area.",
91 return 0;);
92
93 addr = smcStartAddress;
94
95 while (byteCount >= 4) {
96 /*
97 * Bytes are written into the
98 * SMC address space with the MSB first
99 */
100 data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
101
102 result = tonga_set_smc_sram_address(smumgr, addr, limit);
103
104 if (result)
105 goto out;
106
107 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
108
109 src += 4;
110 byteCount -= 4;
111 addr += 4;
112 }
113
114 if (0 != byteCount) {
115 /* Now write odd bytes left, do a read modify write cycle */
116 data = 0;
117
118 result = tonga_set_smc_sram_address(smumgr, addr, limit);
119 if (result)
120 goto out;
121
122 orig_data = cgs_read_register(smumgr->device,
123 mmSMC_IND_DATA_0);
124 extra_shift = 8 * (4 - byteCount);
125
126 while (byteCount > 0) {
127 data = (data << 8) + *src++;
128 byteCount--;
129 }
130
131 data <<= extra_shift;
132 data |= (orig_data & ~((~0UL) << extra_shift));
133
134 result = tonga_set_smc_sram_address(smumgr, addr, limit);
135 if (result)
136 goto out;
137
138 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
139 }
140
141out:
142 return result;
143}
144
145
146int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
147{
f498d9ed 148 static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
1060029f
JZ		 149
150 tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
151
152 return 0;
153}
154
155/**
156* Return if the SMC is currently running.
157*
158* @param smumgr the address of the powerplay hardware manager.
159*/
160static int tonga_is_smc_ram_running(struct pp_smumgr *smumgr)
161{
162 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
163 SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
164 && (0x20100 <= cgs_read_ind_register(smumgr->device,
165 CGS_IND_REG__SMC, ixSMC_PC_C)));
166}
167
168static int tonga_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
169{
170 if (smumgr == NULL || smumgr->device == NULL)
171 return -EINVAL;
172
173 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
174
175 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
176 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
177
178 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
179
180 return 0;
181}
182
183/**
184* Send a message to the SMC, and wait for its response.
185*
186* @param smumgr the address of the powerplay hardware manager.
187* @param msg the message to send.
188* @return The response that came from the SMC.
189*/
190static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
191{
192 if (smumgr == NULL || smumgr->device == NULL)
193 return -EINVAL;
194
195 if (!tonga_is_smc_ram_running(smumgr))
196 return -1;
197
198 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
199 PP_ASSERT_WITH_CODE(
200 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
201 "Failed to send Previous Message.",
f3b5cb3e 202 );
1060029f
JZ		 203
204 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
205
206 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
207 PP_ASSERT_WITH_CODE(
208 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
209 "Failed to send Message.",
f3b5cb3e 210 );
1060029f
JZ		 211
212 return 0;
213}
214
215/*
216* Send a message to the SMC, and do not wait for its response.
217*
218* @param smumgr the address of the powerplay hardware manager.
219* @param msg the message to send.
220* @return The response that came from the SMC.
221*/
222static int tonga_send_msg_to_smc_without_waiting
223 (struct pp_smumgr *smumgr, uint16_t msg)
224{
225 if (smumgr == NULL || smumgr->device == NULL)
226 return -EINVAL;
227
228 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
229 PP_ASSERT_WITH_CODE(
230 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
231 "Failed to send Previous Message.",
f3b5cb3e 232 );
1060029f
JZ		 233 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
234
235 return 0;
236}
237
238/*
239* Send a message to the SMC with parameter
240*
241* @param smumgr: the address of the powerplay hardware manager.
242* @param msg: the message to send.
243* @param parameter: the parameter to send
244* @return The response that came from the SMC.
245*/
246static int tonga_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
247 uint16_t msg, uint32_t parameter)
248{
249 if (smumgr == NULL || smumgr->device == NULL)
250 return -EINVAL;
251
252 if (!tonga_is_smc_ram_running(smumgr))
253 return PPSMC_Result_Failed;
254
255 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
256 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
257
258 return tonga_send_msg_to_smc(smumgr, msg);
259}
260
261/*
262* Send a message to the SMC with parameter, do not wait for response
263*
264* @param smumgr: the address of the powerplay hardware manager.
265* @param msg: the message to send.
266* @param parameter: the parameter to send
267* @return The response that came from the SMC.
268*/
269static int tonga_send_msg_to_smc_with_parameter_without_waiting(
270 struct pp_smumgr *smumgr,
271 uint16_t msg, uint32_t parameter)
272{
273 if (smumgr == NULL || smumgr->device == NULL)
274 return -EINVAL;
275
276 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
277
278 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
279
280 return tonga_send_msg_to_smc_without_waiting(smumgr, msg);
281}
282
283/*
284 * Read a 32bit value from the SMC SRAM space.
285 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
286 * @param smumgr the address of the powerplay hardware manager.
287 * @param smcAddress the address in the SMC RAM to access.
288 * @param value and output parameter for the data read from the SMC SRAM.
289 */
290int tonga_read_smc_sram_dword(struct pp_smumgr *smumgr,
291 uint32_t smcAddress, uint32_t *value,
292 uint32_t limit)
293{
294 int result;
295
296 result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
297
298 if (0 != result)
299 return result;
300
301 *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
302
303 return 0;
304}
305
306/*
307 * Write a 32bit value to the SMC SRAM space.
308 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
309 * @param smumgr the address of the powerplay hardware manager.
310 * @param smcAddress the address in the SMC RAM to access.
311 * @param value to write to the SMC SRAM.
312 */
313int tonga_write_smc_sram_dword(struct pp_smumgr *smumgr,
314 uint32_t smcAddress, uint32_t value,
315 uint32_t limit)
316{
317 int result;
318
319 result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
320
321 if (0 != result)
322 return result;
323
324 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, value);
325
326 return 0;
327}
328
329static int tonga_smu_fini(struct pp_smumgr *smumgr)
330{
86e4cdd6
ML		 331 struct tonga_smumgr *priv = (struct tonga_smumgr *)(smumgr->backend);
332
333 smu_free_memory(smumgr->device, (void *)priv->smu_buffer.handle);
334 smu_free_memory(smumgr->device, (void *)priv->header_buffer.handle);
335
1060029f
JZ		 336 if (smumgr->backend != NULL) {
337 kfree(smumgr->backend);
338 smumgr->backend = NULL;
339 }
5bbc16cc
ML		 340
341 cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
1060029f
JZ		 342 return 0;
343}
344
345static enum cgs_ucode_id tonga_convert_fw_type_to_cgs(uint32_t fw_type)
346{
347 enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
348
349 switch (fw_type) {
350 case UCODE_ID_SMU:
351 result = CGS_UCODE_ID_SMU;
352 break;
353 case UCODE_ID_SDMA0:
354 result = CGS_UCODE_ID_SDMA0;
355 break;
356 case UCODE_ID_SDMA1:
357 result = CGS_UCODE_ID_SDMA1;
358 break;
359 case UCODE_ID_CP_CE:
360 result = CGS_UCODE_ID_CP_CE;
361 break;
362 case UCODE_ID_CP_PFP:
363 result = CGS_UCODE_ID_CP_PFP;
364 break;
365 case UCODE_ID_CP_ME:
366 result = CGS_UCODE_ID_CP_ME;
367 break;
368 case UCODE_ID_CP_MEC:
369 result = CGS_UCODE_ID_CP_MEC;
370 break;
371 case UCODE_ID_CP_MEC_JT1:
372 result = CGS_UCODE_ID_CP_MEC_JT1;
373 break;
374 case UCODE_ID_CP_MEC_JT2:
375 result = CGS_UCODE_ID_CP_MEC_JT2;
376 break;
377 case UCODE_ID_RLC_G:
378 result = CGS_UCODE_ID_RLC_G;
379 break;
380 default:
381 break;
382 }
383
384 return result;
385}
386
387/**
388 * Convert the PPIRI firmware type to SMU type mask.
389 * For MEC, we need to check all MEC related type
390*/
391static uint16_t tonga_get_mask_for_firmware_type(uint16_t firmwareType)
392{
393 uint16_t result = 0;
394
395 switch (firmwareType) {
396 case UCODE_ID_SDMA0:
397 result = UCODE_ID_SDMA0_MASK;
398 break;
399 case UCODE_ID_SDMA1:
400 result = UCODE_ID_SDMA1_MASK;
401 break;
402 case UCODE_ID_CP_CE:
403 result = UCODE_ID_CP_CE_MASK;
404 break;
405 case UCODE_ID_CP_PFP:
406 result = UCODE_ID_CP_PFP_MASK;
407 break;
408 case UCODE_ID_CP_ME:
409 result = UCODE_ID_CP_ME_MASK;
410 break;
411 case UCODE_ID_CP_MEC:
412 case UCODE_ID_CP_MEC_JT1:
413 case UCODE_ID_CP_MEC_JT2:
414 result = UCODE_ID_CP_MEC_MASK;
415 break;
416 case UCODE_ID_RLC_G:
417 result = UCODE_ID_RLC_G_MASK;
418 break;
419 default:
420 break;
421 }
422
423 return result;
424}
425
426/**
427 * Check if the FW has been loaded,
428 * SMU will not return if loading has not finished.
429*/
430static int tonga_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fwType)
431{
432 uint16_t fwMask = tonga_get_mask_for_firmware_type(fwType);
433
434 if (0 != SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
435 SOFT_REGISTERS_TABLE_28, fwMask, fwMask)) {
436 printk(KERN_ERR "[ powerplay ] check firmware loading failed\n");
437 return -EINVAL;
438 }
439
440 return 0;
441}
442
443/* Populate one firmware image to the data structure */
444static int tonga_populate_single_firmware_entry(struct pp_smumgr *smumgr,
445 uint16_t firmware_type,
446 struct SMU_Entry *pentry)
447{
448 int result;
449 struct cgs_firmware_info info = {0};
450
451 result = cgs_get_firmware_info(
452 smumgr->device,
453 tonga_convert_fw_type_to_cgs(firmware_type),
454 &info);
455
456 if (result == 0) {
457 pentry->version = 0;
458 pentry->id = (uint16_t)firmware_type;
459 pentry->image_addr_high = smu_upper_32_bits(info.mc_addr);
460 pentry->image_addr_low = smu_lower_32_bits(info.mc_addr);
461 pentry->meta_data_addr_high = 0;
462 pentry->meta_data_addr_low = 0;
463 pentry->data_size_byte = info.image_size;
464 pentry->num_register_entries = 0;
465
466 if (firmware_type == UCODE_ID_RLC_G)
467 pentry->flags = 1;
468 else
469 pentry->flags = 0;
470 } else {
471 return result;
472 }
473
474 return result;
475}
476
477static int tonga_request_smu_reload_fw(struct pp_smumgr *smumgr)
478{
479 struct tonga_smumgr *tonga_smu =
480 (struct tonga_smumgr *)(smumgr->backend);
481 uint16_t fw_to_load;
1060029f
JZ		 482 struct SMU_DRAMData_TOC *toc;
483 /**
484 * First time this gets called during SmuMgr init,
485 * we haven't processed SMU header file yet,
486 * so Soft Register Start offset is unknown.
487 * However, for this case, UcodeLoadStatus is already 0,
488 * so we can skip this if the Soft Registers Start offset is 0.
489 */
490 cgs_write_ind_register(smumgr->device,
491 CGS_IND_REG__SMC, ixSOFT_REGISTERS_TABLE_28, 0);
492
493 tonga_send_msg_to_smc_with_parameter(smumgr,
494 PPSMC_MSG_SMU_DRAM_ADDR_HI,
495 tonga_smu->smu_buffer.mc_addr_high);
496 tonga_send_msg_to_smc_with_parameter(smumgr,
497 PPSMC_MSG_SMU_DRAM_ADDR_LO,
498 tonga_smu->smu_buffer.mc_addr_low);
499
500 toc = (struct SMU_DRAMData_TOC *)tonga_smu->pHeader;
501 toc->num_entries = 0;
502 toc->structure_version = 1;
503
504 PP_ASSERT_WITH_CODE(
505 0 == tonga_populate_single_firmware_entry(smumgr,
506 UCODE_ID_RLC_G,
507 &toc->entry[toc->num_entries++]),
508 "Failed to Get Firmware Entry.\n",
509 return -1);
510 PP_ASSERT_WITH_CODE(
511 0 == tonga_populate_single_firmware_entry(smumgr,
512 UCODE_ID_CP_CE,
513 &toc->entry[toc->num_entries++]),
514 "Failed to Get Firmware Entry.\n",
515 return -1);
516 PP_ASSERT_WITH_CODE(
517 0 == tonga_populate_single_firmware_entry
518 (smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
519 "Failed to Get Firmware Entry.\n", return -1);
520 PP_ASSERT_WITH_CODE(
521 0 == tonga_populate_single_firmware_entry
522 (smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
523 "Failed to Get Firmware Entry.\n", return -1);
524 PP_ASSERT_WITH_CODE(
525 0 == tonga_populate_single_firmware_entry
526 (smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
527 "Failed to Get Firmware Entry.\n", return -1);
528 PP_ASSERT_WITH_CODE(
529 0 == tonga_populate_single_firmware_entry
530 (smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
531 "Failed to Get Firmware Entry.\n", return -1);
532 PP_ASSERT_WITH_CODE(
533 0 == tonga_populate_single_firmware_entry
534 (smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
535 "Failed to Get Firmware Entry.\n", return -1);
536 PP_ASSERT_WITH_CODE(
537 0 == tonga_populate_single_firmware_entry
538 (smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
539 "Failed to Get Firmware Entry.\n", return -1);
540 PP_ASSERT_WITH_CODE(
541 0 == tonga_populate_single_firmware_entry
542 (smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
543 "Failed to Get Firmware Entry.\n", return -1);
544
545 tonga_send_msg_to_smc_with_parameter(smumgr,
546 PPSMC_MSG_DRV_DRAM_ADDR_HI,
547 tonga_smu->header_buffer.mc_addr_high);
548 tonga_send_msg_to_smc_with_parameter(smumgr,
549 PPSMC_MSG_DRV_DRAM_ADDR_LO,
550 tonga_smu->header_buffer.mc_addr_low);
551
552 fw_to_load = UCODE_ID_RLC_G_MASK
553 + UCODE_ID_SDMA0_MASK
554 + UCODE_ID_SDMA1_MASK
555 + UCODE_ID_CP_CE_MASK
556 + UCODE_ID_CP_ME_MASK
557 + UCODE_ID_CP_PFP_MASK
558 + UCODE_ID_CP_MEC_MASK;
559
560 PP_ASSERT_WITH_CODE(
561 0 == tonga_send_msg_to_smc_with_parameter_without_waiting(
562 smumgr, PPSMC_MSG_LoadUcodes, fw_to_load),
563 "Fail to Request SMU Load uCode", return 0);
564
538f1ef3 565 return 0;
1060029f
JZ		 566}
567
568static int tonga_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
569 uint32_t firmwareType)
570{
571 return 0;
572}
573
574/**
575 * Upload the SMC firmware to the SMC microcontroller.
576 *
577 * @param smumgr the address of the powerplay hardware manager.
578 * @param pFirmware the data structure containing the various sections of the firmware.
579 */
580static int tonga_smu_upload_firmware_image(struct pp_smumgr *smumgr)
581{
582 const uint8_t *src;
583 uint32_t byte_count;
584 uint32_t *data;
585 struct cgs_firmware_info info = {0};
586
587 if (smumgr == NULL || smumgr->device == NULL)
588 return -EINVAL;
589
590 cgs_get_firmware_info(smumgr->device,
591 tonga_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
592
593 if (info.image_size & 3) {
594 printk(KERN_ERR "[ powerplay ] SMC ucode is not 4 bytes aligned\n");
595 return -EINVAL;
596 }
597
598 if (info.image_size > TONGA_SMC_SIZE) {
599 printk(KERN_ERR "[ powerplay ] SMC address is beyond the SMC RAM area\n");
600 return -EINVAL;
601 }
602
603 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, 0x20000);
604 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
605
606 byte_count = info.image_size;
607 src = (const uint8_t *)info.kptr;
608
609 data = (uint32_t *)src;
610 for (; byte_count >= 4; data++, byte_count -= 4)
611 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data[0]);
612
613 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
614
615 return 0;
616}
617
618static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
619{
620 int result;
621
622 /* Assert reset */
623 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
624 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
625
626 result = tonga_smu_upload_firmware_image(smumgr);
627 if (result)
628 return result;
629
630 /* Clear status */
631 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
632 ixSMU_STATUS, 0);
633
634 /* Enable clock */
635 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
636 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
637
638 /* De-assert reset */
639 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
640 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
641
642 /* Set SMU Auto Start */
643 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
644 SMU_INPUT_DATA, AUTO_START, 1);
645
646 /* Clear firmware interrupt enable flag */
647 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
648 ixFIRMWARE_FLAGS, 0);
649
650 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
651 RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
652
653 /**
654 * Call Test SMU message with 0x20000 offset to trigger SMU start
655 */
656 tonga_send_msg_to_smc_offset(smumgr);
657
658 /* Wait for done bit to be set */
659 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
660 SMU_STATUS, SMU_DONE, 0);
661
662 /* Check pass/failed indicator */
663 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
664 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
665 printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
666 return -EINVAL;
667 }
668
669 /* Wait for firmware to initialize */
670 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
671 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
672
673 return 0;
674}
675
676
677static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
678{
679 int result = 0;
680
681 /* wait for smc boot up */
682 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
683 RCU_UC_EVENTS, boot_seq_done, 0);
684
685 /*Clear firmware interrupt enable flag*/
686 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
687 ixFIRMWARE_FLAGS, 0);
688
689
690 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
691 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
692
693 result = tonga_smu_upload_firmware_image(smumgr);
694
695 if (result != 0)
696 return result;
697
698 /* Set smc instruct start point at 0x0 */
699 tonga_program_jump_on_start(smumgr);
700
701
702 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
703 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
704
705 /*De-assert reset*/
706 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
707 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
708
709 /* Wait for firmware to initialize */
710 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
711 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
712
713 return result;
714}
715
716static int tonga_start_smu(struct pp_smumgr *smumgr)
717{
718 int result;
719
720 /* Only start SMC if SMC RAM is not running */
721 if (!tonga_is_smc_ram_running(smumgr)) {
722 /*Check if SMU is running in protected mode*/
723 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
724 SMU_FIRMWARE, SMU_MODE)) {
725 result = tonga_start_in_non_protection_mode(smumgr);
726 if (result)
727 return result;
728 } else {
729 result = tonga_start_in_protection_mode(smumgr);
730 if (result)
731 return result;
732 }
733 }
734
735 result = tonga_request_smu_reload_fw(smumgr);
736
737 return result;
738}
739
740/**
741 * Write a 32bit value to the SMC SRAM space.
742 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
743 * @param smumgr the address of the powerplay hardware manager.
744 * @param smcAddress the address in the SMC RAM to access.
745 * @param value to write to the SMC SRAM.
746 */
747static int tonga_smu_init(struct pp_smumgr *smumgr)
748{
749 struct tonga_smumgr *tonga_smu;
750 uint8_t *internal_buf;
751 uint64_t mc_addr = 0;
752 /* Allocate memory for backend private data */
753 tonga_smu = (struct tonga_smumgr *)(smumgr->backend);
754 tonga_smu->header_buffer.data_size =
755 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
756 tonga_smu->smu_buffer.data_size = 200*4096;
757
758 smu_allocate_memory(smumgr->device,
759 tonga_smu->header_buffer.data_size,
760 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
761 PAGE_SIZE,
762 &mc_addr,
763 &tonga_smu->header_buffer.kaddr,
764 &tonga_smu->header_buffer.handle);
765
766 tonga_smu->pHeader = tonga_smu->header_buffer.kaddr;
767 tonga_smu->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
768 tonga_smu->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
769
770 PP_ASSERT_WITH_CODE((NULL != tonga_smu->pHeader),
771 "Out of memory.",
772 kfree(smumgr->backend);
773 cgs_free_gpu_mem(smumgr->device,
774 (cgs_handle_t)tonga_smu->header_buffer.handle);
775 return -1);
776
777 smu_allocate_memory(smumgr->device,
778 tonga_smu->smu_buffer.data_size,
779 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
780 PAGE_SIZE,
781 &mc_addr,
782 &tonga_smu->smu_buffer.kaddr,
783 &tonga_smu->smu_buffer.handle);
784
785 internal_buf = tonga_smu->smu_buffer.kaddr;
786 tonga_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
787 tonga_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
788
789 PP_ASSERT_WITH_CODE((NULL != internal_buf),
790 "Out of memory.",
791 kfree(smumgr->backend);
792 cgs_free_gpu_mem(smumgr->device,
793 (cgs_handle_t)tonga_smu->smu_buffer.handle);
794 return -1;);
795
796 return 0;
797}
798
799static const struct pp_smumgr_func tonga_smu_funcs = {
800 .smu_init = &tonga_smu_init,
801 .smu_fini = &tonga_smu_fini,
802 .start_smu = &tonga_start_smu,
803 .check_fw_load_finish = &tonga_check_fw_load_finish,
804 .request_smu_load_fw = &tonga_request_smu_reload_fw,
805 .request_smu_load_specific_fw = &tonga_request_smu_load_specific_fw,
806 .send_msg_to_smc = &tonga_send_msg_to_smc,
807 .send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter,
808 .download_pptable_settings = NULL,
809 .upload_pptable_settings = NULL,
810};
811
812int tonga_smum_init(struct pp_smumgr *smumgr)
813{
814 struct tonga_smumgr *tonga_smu = NULL;
815
816 tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
817
818 if (tonga_smu == NULL)
c15c8d70 819 return -ENOMEM;
1060029f
JZ		 820
821 smumgr->backend = tonga_smu;
822 smumgr->smumgr_funcs = &tonga_smu_funcs;
823
824 return 0;
825}
Linux kernel - Deliverables
This page took 0.126448 seconds and 5 git commands to generate.