[deliverable/linux.git] / drivers / gpu / drm / ast / ast_main.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors: Dave Airlie <airlied@redhat.com>
 */
#include <drm/drmP.h>
#include "ast_drv.h"


#include <drm/drm_fb_helper.h>
#include <drm/drm_crtc_helper.h>

#include "ast_dram_tables.h"

void ast_set_index_reg_mask(struct ast_private *ast,
			    uint32_t base, uint8_t index,
			    uint8_t mask, uint8_t val)
{
	u8 tmp;
	ast_io_write8(ast, base, index);
	tmp = (ast_io_read8(ast, base + 1) & mask) | val;
	ast_set_index_reg(ast, base, index, tmp);
}

uint8_t ast_get_index_reg(struct ast_private *ast,
			  uint32_t base, uint8_t index)
{
	uint8_t ret;
	ast_io_write8(ast, base, index);
	ret = ast_io_read8(ast, base + 1);
	return ret;
}

uint8_t ast_get_index_reg_mask(struct ast_private *ast,
			       uint32_t base, uint8_t index, uint8_t mask)
{
	uint8_t ret;
	ast_io_write8(ast, base, index);
	ret = ast_io_read8(ast, base + 1) & mask;
	return ret;
}


static int ast_detect_chip(struct drm_device *dev, bool *need_post)
{
	struct ast_private *ast = dev->dev_private;
	uint32_t data, jreg;

	if (dev->pdev->device == PCI_CHIP_AST1180) {
		ast->chip = AST1100;
		DRM_INFO("AST 1180 detected\n");
	} else {
		if (dev->pdev->revision >= 0x30) {
			ast->chip = AST2400;
			DRM_INFO("AST 2400 detected\n");
		} else if (dev->pdev->revision >= 0x20) {
			ast->chip = AST2300;
			DRM_INFO("AST 2300 detected\n");
		} else if (dev->pdev->revision >= 0x10) {
			uint32_t data;
			ast_write32(ast, 0xf004, 0x1e6e0000);
			ast_write32(ast, 0xf000, 0x1);

			data = ast_read32(ast, 0x1207c);
			switch (data & 0x0300) {
			case 0x0200:
				ast->chip = AST1100;
				DRM_INFO("AST 1100 detected\n");
				break;
			case 0x0100:
				ast->chip = AST2200;
				DRM_INFO("AST 2200 detected\n");
				break;
			case 0x0000:
				ast->chip = AST2150;
				DRM_INFO("AST 2150 detected\n");
				break;
			default:
				ast->chip = AST2100;
				DRM_INFO("AST 2100 detected\n");
				break;
			}
			ast->vga2_clone = false;
		} else {
			ast->chip = 2000;
			DRM_INFO("AST 2000 detected\n");
		}
	}

	/*
	 * If VGA isn't enabled, we need to enable now or subsequent
	 * access to the scratch registers will fail. We also inform
	 * our caller that it needs to POST the chip
	 * (Assumption: VGA not enabled -> need to POST)
	 */
	if (!ast_is_vga_enabled(dev)) {
		ast_enable_vga(dev);
		ast_enable_mmio(dev);
		DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
		*need_post = true;
	} else
		*need_post = false;

	/* Check if we support wide screen */
	switch (ast->chip) {
	case AST1180:
		ast->support_wide_screen = true;
		break;
	case AST2000:
		ast->support_wide_screen = false;
		break;
	default:
		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
		if (!(jreg & 0x80))
			ast->support_wide_screen = true;
		else if (jreg & 0x01)
			ast->support_wide_screen = true;
		else {
			ast->support_wide_screen = false;
			/* Read SCU7c (silicon revision register) */
			ast_write32(ast, 0xf004, 0x1e6e0000);
			ast_write32(ast, 0xf000, 0x1);
			data = ast_read32(ast, 0x1207c);
			data &= 0x300;
			if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
				ast->support_wide_screen = true;
			if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
				ast->support_wide_screen = true;
		}
		break;
	}

	/* Check 3rd Tx option (digital output afaik) */
	ast->tx_chip_type = AST_TX_NONE;

	/*
	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
	 */
	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
	if (jreg & 0x80)
		ast->tx_chip_type = AST_TX_SIL164;

	if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
		/*
		 * On AST2300 and 2400, look the configuration set by the SoC in
		 * the SOC scratch register #1 bits 11:8 (interestingly marked
		 * as "reserved" in the spec
		 */
		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
		switch (jreg) {
		case 0x04:
			ast->tx_chip_type = AST_TX_SIL164;
			break;
		case 0x08:
			ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
			if (ast->dp501_fw_addr) {
				/* backup firmware */
				if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
					kfree(ast->dp501_fw_addr);
					ast->dp501_fw_addr = NULL;
				}
			}
			/* fallthrough */
		case 0x0c:
			ast->tx_chip_type = AST_TX_DP501;
		}
	}

	/* Print stuff for diagnostic purposes */
	switch(ast->tx_chip_type) {
	case AST_TX_SIL164:
		DRM_INFO("Using Sil164 TMDS transmitter\n");
		break;
	case AST_TX_DP501:
		DRM_INFO("Using DP501 DisplayPort transmitter\n");
		break;
	default:
		DRM_INFO("Analog VGA only\n");
	}
	return 0;
}

static int ast_get_dram_info(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	uint32_t data, data2;
	uint32_t denum, num, div, ref_pll;

	ast_write32(ast, 0xf004, 0x1e6e0000);
	ast_write32(ast, 0xf000, 0x1);


	ast_write32(ast, 0x10000, 0xfc600309);

	do {
		;
	} while (ast_read32(ast, 0x10000) != 0x01);
	data = ast_read32(ast, 0x10004);

	if (data & 0x400)
		ast->dram_bus_width = 16;
	else
		ast->dram_bus_width = 32;

	if (ast->chip == AST2300 || ast->chip == AST2400) {
		switch (data & 0x03) {
		case 0:
			ast->dram_type = AST_DRAM_512Mx16;
			break;
		default:
		case 1:
			ast->dram_type = AST_DRAM_1Gx16;
			break;
		case 2:
			ast->dram_type = AST_DRAM_2Gx16;
			break;
		case 3:
			ast->dram_type = AST_DRAM_4Gx16;
			break;
		}
	} else {
		switch (data & 0x0c) {
		case 0:
		case 4:
			ast->dram_type = AST_DRAM_512Mx16;
			break;
		case 8:
			if (data & 0x40)
				ast->dram_type = AST_DRAM_1Gx16;
			else
				ast->dram_type = AST_DRAM_512Mx32;
			break;
		case 0xc:
			ast->dram_type = AST_DRAM_1Gx32;
			break;
		}
	}

	data = ast_read32(ast, 0x10120);
	data2 = ast_read32(ast, 0x10170);
	if (data2 & 0x2000)
		ref_pll = 14318;
	else
		ref_pll = 12000;

	denum = data & 0x1f;
	num = (data & 0x3fe0) >> 5;
	data = (data & 0xc000) >> 14;
	switch (data) {
	case 3:
		div = 0x4;
		break;
	case 2:
	case 1:
		div = 0x2;
		break;
	default:
		div = 0x1;
		break;
	}
	ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
	return 0;
}

static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb);
	if (ast_fb->obj)
		drm_gem_object_unreference_unlocked(ast_fb->obj);

	drm_framebuffer_cleanup(fb);
	kfree(fb);
}

static const struct drm_framebuffer_funcs ast_fb_funcs = {
	.destroy = ast_user_framebuffer_destroy,
};


int ast_framebuffer_init(struct drm_device *dev,
			 struct ast_framebuffer *ast_fb,
			 struct drm_mode_fb_cmd2 *mode_cmd,
			 struct drm_gem_object *obj)
{
	int ret;

	drm_helper_mode_fill_fb_struct(&ast_fb->base, mode_cmd);
	ast_fb->obj = obj;
	ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}
	return 0;
}

static struct drm_framebuffer *
ast_user_framebuffer_create(struct drm_device *dev,
	       struct drm_file *filp,
	       struct drm_mode_fb_cmd2 *mode_cmd)
{
	struct drm_gem_object *obj;
	struct ast_framebuffer *ast_fb;
	int ret;

	obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]);
	if (obj == NULL)
		return ERR_PTR(-ENOENT);

	ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL);
	if (!ast_fb) {
		drm_gem_object_unreference_unlocked(obj);
		return ERR_PTR(-ENOMEM);
	}

	ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(obj);
		kfree(ast_fb);
		return ERR_PTR(ret);
	}
	return &ast_fb->base;
}

static const struct drm_mode_config_funcs ast_mode_funcs = {
	.fb_create = ast_user_framebuffer_create,
};

static u32 ast_get_vram_info(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	u8 jreg;
	u32 vram_size;
	ast_open_key(ast);

	vram_size = AST_VIDMEM_DEFAULT_SIZE;
	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
	switch (jreg & 3) {
	case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
	case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
	case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
	case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
	}

	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
	switch (jreg & 0x03) {
	case 1:
		vram_size -= 0x100000;
		break;
	case 2:
		vram_size -= 0x200000;
		break;
	case 3:
		vram_size -= 0x400000;
		break;
	}

	return vram_size;
}

int ast_driver_load(struct drm_device *dev, unsigned long flags)
{
	struct ast_private *ast;
	bool need_post;
	int ret = 0;

	ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
	if (!ast)
		return -ENOMEM;

	dev->dev_private = ast;
	ast->dev = dev;

	ast->regs = pci_iomap(dev->pdev, 1, 0);
	if (!ast->regs) {
		ret = -EIO;
		goto out_free;
	}

	/*
	 * If we don't have IO space at all, use MMIO now and
	 * assume the chip has MMIO enabled by default (rev 0x20
	 * and higher).
	 */
	if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
		DRM_INFO("platform has no IO space, trying MMIO\n");
		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
	}

	/* "map" IO regs if the above hasn't done so already */
	if (!ast->ioregs) {
		ast->ioregs = pci_iomap(dev->pdev, 2, 0);
		if (!ast->ioregs) {
			ret = -EIO;
			goto out_free;
		}
	}

	ast_detect_chip(dev, &need_post);

	if (ast->chip != AST1180) {
		ast_get_dram_info(dev);
		ast->vram_size = ast_get_vram_info(dev);
		DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
	}

	if (need_post)
		ast_post_gpu(dev);

	ret = ast_mm_init(ast);
	if (ret)
		goto out_free;

	drm_mode_config_init(dev);

	dev->mode_config.funcs = (void *)&ast_mode_funcs;
	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;
	dev->mode_config.preferred_depth = 24;
	dev->mode_config.prefer_shadow = 1;

	if (ast->chip == AST2100 ||
	    ast->chip == AST2200 ||
	    ast->chip == AST2300 ||
	    ast->chip == AST2400 ||
	    ast->chip == AST1180) {
		dev->mode_config.max_width = 1920;
		dev->mode_config.max_height = 2048;
	} else {
		dev->mode_config.max_width = 1600;
		dev->mode_config.max_height = 1200;
	}

	ret = ast_mode_init(dev);
	if (ret)
		goto out_free;

	ret = ast_fbdev_init(dev);
	if (ret)
		goto out_free;

	return 0;
out_free:
	kfree(ast);
	dev->dev_private = NULL;
	return ret;
}

int ast_driver_unload(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;

	kfree(ast->dp501_fw_addr);
	ast_mode_fini(dev);
	ast_fbdev_fini(dev);
	drm_mode_config_cleanup(dev);

	ast_mm_fini(ast);
	pci_iounmap(dev->pdev, ast->ioregs);
	pci_iounmap(dev->pdev, ast->regs);
	kfree(ast);
	return 0;
}

int ast_gem_create(struct drm_device *dev,
		   u32 size, bool iskernel,
		   struct drm_gem_object **obj)
{
	struct ast_bo *astbo;
	int ret;

	*obj = NULL;

	size = roundup(size, PAGE_SIZE);
	if (size == 0)
		return -EINVAL;

	ret = ast_bo_create(dev, size, 0, 0, &astbo);
	if (ret) {
		if (ret != -ERESTARTSYS)
			DRM_ERROR("failed to allocate GEM object\n");
		return ret;
	}
	*obj = &astbo->gem;
	return 0;
}

int ast_dumb_create(struct drm_file *file,
		    struct drm_device *dev,
		    struct drm_mode_create_dumb *args)
{
	int ret;
	struct drm_gem_object *gobj;
	u32 handle;

	args->pitch = args->width * ((args->bpp + 7) / 8);
	args->size = args->pitch * args->height;

	ret = ast_gem_create(dev, args->size, false,
			     &gobj);
	if (ret)
		return ret;

	ret = drm_gem_handle_create(file, gobj, &handle);
	drm_gem_object_unreference_unlocked(gobj);
	if (ret)
		return ret;

	args->handle = handle;
	return 0;
}

static void ast_bo_unref(struct ast_bo **bo)
{
	struct ttm_buffer_object *tbo;

	if ((*bo) == NULL)
		return;

	tbo = &((*bo)->bo);
	ttm_bo_unref(&tbo);
	*bo = NULL;
}

void ast_gem_free_object(struct drm_gem_object *obj)
{
	struct ast_bo *ast_bo = gem_to_ast_bo(obj);

	ast_bo_unref(&ast_bo);
}


static inline u64 ast_bo_mmap_offset(struct ast_bo *bo)
{
	return drm_vma_node_offset_addr(&bo->bo.vma_node);
}
int
ast_dumb_mmap_offset(struct drm_file *file,
		     struct drm_device *dev,
		     uint32_t handle,
		     uint64_t *offset)
{
	struct drm_gem_object *obj;
	int ret;
	struct ast_bo *bo;

	mutex_lock(&dev->struct_mutex);
	obj = drm_gem_object_lookup(dev, file, handle);
	if (obj == NULL) {
		ret = -ENOENT;
		goto out_unlock;
	}

	bo = gem_to_ast_bo(obj);
	*offset = ast_bo_mmap_offset(bo);

	drm_gem_object_unreference(obj);
	ret = 0;
out_unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;

}
Commit	Line	Data
312fec14 DA	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the
	6	* "Software"), to deal in the Software without restriction, including
	7	* without limitation the rights to use, copy, modify, merge, publish,
	8	* distribute, sub license, and/or sell copies of the Software, and to
	9	* permit persons to whom the Software is furnished to do so, subject to
	10	* the following conditions:
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	16	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	17	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	18	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* The above copyright notice and this permission notice (including the
	21	* next paragraph) shall be included in all copies or substantial portions
	22	* of the Software.
	23	*
	24	*/
	25	/*
	26	* Authors: Dave Airlie <airlied@redhat.com>
	27	*/
760285e7	28	#include <drm/drmP.h>
312fec14 DA	29	#include "ast_drv.h"
	30
	31
760285e7 DH	32	#include <drm/drm_fb_helper.h>
760285e7 DH	33	#include <drm/drm_crtc_helper.h>
312fec14 DA	34
	35	#include "ast_dram_tables.h"
	36
	37	void ast_set_index_reg_mask(struct ast_private *ast,
	38	uint32_t base, uint8_t index,
	39	uint8_t mask, uint8_t val)
	40	{
	41	u8 tmp;
	42	ast_io_write8(ast, base, index);
	43	tmp = (ast_io_read8(ast, base + 1) & mask) \| val;
	44	ast_set_index_reg(ast, base, index, tmp);
	45	}
	46
	47	uint8_t ast_get_index_reg(struct ast_private *ast,
	48	uint32_t base, uint8_t index)
	49	{
	50	uint8_t ret;
	51	ast_io_write8(ast, base, index);
	52	ret = ast_io_read8(ast, base + 1);
	53	return ret;
	54	}
	55
	56	uint8_t ast_get_index_reg_mask(struct ast_private *ast,
	57	uint32_t base, uint8_t index, uint8_t mask)
	58	{
	59	uint8_t ret;
	60	ast_io_write8(ast, base, index);
	61	ret = ast_io_read8(ast, base + 1) & mask;
	62	return ret;
	63	}
	64
	65
d1b98557	66	static int ast_detect_chip(struct drm_device dev, bool need_post)
312fec14 DA	67	{
312fec14 DA	68	struct ast_private *ast = dev->dev_private;
f1f62f2c	69	uint32_t data, jreg;
312fec14 DA	70
	71	if (dev->pdev->device == PCI_CHIP_AST1180) {
	72	ast->chip = AST1100;
	73	DRM_INFO("AST 1180 detected\n");
	74	} else {
1453bf4c DA	75	if (dev->pdev->revision >= 0x30) {
	76	ast->chip = AST2400;
	77	DRM_INFO("AST 2400 detected\n");
	78	} else if (dev->pdev->revision >= 0x20) {
312fec14 DA	79	ast->chip = AST2300;
	80	DRM_INFO("AST 2300 detected\n");
	81	} else if (dev->pdev->revision >= 0x10) {
	82	uint32_t data;
	83	ast_write32(ast, 0xf004, 0x1e6e0000);
	84	ast_write32(ast, 0xf000, 0x1);
	85
	86	data = ast_read32(ast, 0x1207c);
	87	switch (data & 0x0300) {
	88	case 0x0200:
	89	ast->chip = AST1100;
	90	DRM_INFO("AST 1100 detected\n");
	91	break;
	92	case 0x0100:
	93	ast->chip = AST2200;
	94	DRM_INFO("AST 2200 detected\n");
	95	break;
	96	case 0x0000:
	97	ast->chip = AST2150;
	98	DRM_INFO("AST 2150 detected\n");
	99	break;
	100	default:
	101	ast->chip = AST2100;
	102	DRM_INFO("AST 2100 detected\n");
	103	break;
	104	}
	105	ast->vga2_clone = false;
	106	} else {
	107	ast->chip = 2000;
	108	DRM_INFO("AST 2000 detected\n");
	109	}
	110	}
f1f62f2c	111
d1b98557 BH	112	/*
	113	* If VGA isn't enabled, we need to enable now or subsequent
	114	* access to the scratch registers will fail. We also inform
	115	* our caller that it needs to POST the chip
	116	* (Assumption: VGA not enabled -> need to POST)
	117	*/
	118	if (!ast_is_vga_enabled(dev)) {
	119	ast_enable_vga(dev);
	120	ast_enable_mmio(dev);
	121	DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
	122	*need_post = true;
	123	} else
	124	*need_post = false;
	125
	126	/* Check if we support wide screen */
f1f62f2c DA	127	switch (ast->chip) {
	128	case AST1180:
	129	ast->support_wide_screen = true;
	130	break;
	131	case AST2000:
	132	ast->support_wide_screen = false;
	133	break;
	134	default:
	135	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
	136	if (!(jreg & 0x80))
	137	ast->support_wide_screen = true;
	138	else if (jreg & 0x01)
	139	ast->support_wide_screen = true;
	140	else {
	141	ast->support_wide_screen = false;
d1b98557	142	/* Read SCU7c (silicon revision register) */
1453bf4c DA	143	ast_write32(ast, 0xf004, 0x1e6e0000);
	144	ast_write32(ast, 0xf000, 0x1);
	145	data = ast_read32(ast, 0x1207c);
	146	data &= 0x300;
	147	if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
	148	ast->support_wide_screen = true;
	149	if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
	150	ast->support_wide_screen = true;
f1f62f2c DA	151	}
	152	break;
	153	}
	154
d1b98557	155	/* Check 3rd Tx option (digital output afaik) */
83c6620b	156	ast->tx_chip_type = AST_TX_NONE;
d1b98557 BH	157
	158	/*
	159	* VGACRA3 Enhanced Color Mode Register, check if DVO is already
	160	* enabled, in that case, assume we have a SIL164 TMDS transmitter
	161	*/
83c6620b DA	162	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
	163	if (jreg & 0x80)
	164	ast->tx_chip_type = AST_TX_SIL164;
d1b98557	165
83c6620b	166	if ((ast->chip == AST2300) \|\| (ast->chip == AST2400)) {
d1b98557 BH	167	/*
	168	* On AST2300 and 2400, look the configuration set by the SoC in
	169	* the SOC scratch register #1 bits 11:8 (interestingly marked
	170	* as "reserved" in the spec
	171	*/
83c6620b DA	172	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
	173	switch (jreg) {
	174	case 0x04:
	175	ast->tx_chip_type = AST_TX_SIL164;
	176	break;
	177	case 0x08:
	178	ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
	179	if (ast->dp501_fw_addr) {
	180	/* backup firmware */
	181	if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
	182	kfree(ast->dp501_fw_addr);
	183	ast->dp501_fw_addr = NULL;
	184	}
	185	}
	186	/* fallthrough */
	187	case 0x0c:
	188	ast->tx_chip_type = AST_TX_DP501;
	189	}
	190	}
	191
d1b98557 BH	192	/* Print stuff for diagnostic purposes */
	193	switch(ast->tx_chip_type) {
	194	case AST_TX_SIL164:
	195	DRM_INFO("Using Sil164 TMDS transmitter\n");
	196	break;
	197	case AST_TX_DP501:
	198	DRM_INFO("Using DP501 DisplayPort transmitter\n");
	199	break;
	200	default:
	201	DRM_INFO("Analog VGA only\n");
	202	}
312fec14 DA	203	return 0;
	204	}
	205
	206	static int ast_get_dram_info(struct drm_device *dev)
	207	{
	208	struct ast_private *ast = dev->dev_private;
	209	uint32_t data, data2;
	210	uint32_t denum, num, div, ref_pll;
	211
	212	ast_write32(ast, 0xf004, 0x1e6e0000);
	213	ast_write32(ast, 0xf000, 0x1);
	214
	215
	216	ast_write32(ast, 0x10000, 0xfc600309);
	217
	218	do {
	219	;
	220	} while (ast_read32(ast, 0x10000) != 0x01);
	221	data = ast_read32(ast, 0x10004);
	222
	223	if (data & 0x400)
	224	ast->dram_bus_width = 16;
	225	else
	226	ast->dram_bus_width = 32;
	227
1453bf4c	228	if (ast->chip == AST2300 \|\| ast->chip == AST2400) {
312fec14 DA	229	switch (data & 0x03) {
	230	case 0:
	231	ast->dram_type = AST_DRAM_512Mx16;
	232	break;
	233	default:
	234	case 1:
	235	ast->dram_type = AST_DRAM_1Gx16;
	236	break;
	237	case 2:
	238	ast->dram_type = AST_DRAM_2Gx16;
	239	break;
	240	case 3:
	241	ast->dram_type = AST_DRAM_4Gx16;
	242	break;
	243	}
	244	} else {
	245	switch (data & 0x0c) {
	246	case 0:
	247	case 4:
	248	ast->dram_type = AST_DRAM_512Mx16;
	249	break;
	250	case 8:
	251	if (data & 0x40)
	252	ast->dram_type = AST_DRAM_1Gx16;
	253	else
	254	ast->dram_type = AST_DRAM_512Mx32;
	255	break;
	256	case 0xc:
	257	ast->dram_type = AST_DRAM_1Gx32;
	258	break;
	259	}
	260	}
	261
	262	data = ast_read32(ast, 0x10120);
	263	data2 = ast_read32(ast, 0x10170);
	264	if (data2 & 0x2000)
	265	ref_pll = 14318;
	266	else
	267	ref_pll = 12000;
	268
	269	denum = data & 0x1f;
	270	num = (data & 0x3fe0) >> 5;
	271	data = (data & 0xc000) >> 14;
	272	switch (data) {
	273	case 3:
	274	div = 0x4;
	275	break;
	276	case 2:
	277	case 1:
	278	div = 0x2;
	279	break;
	280	default:
	281	div = 0x1;
	282	break;
	283	}
	284	ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
	285	return 0;
	286	}
	287
312fec14 DA	288	static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb)
	289	{
	290	struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb);
	291	if (ast_fb->obj)
	292	drm_gem_object_unreference_unlocked(ast_fb->obj);
	293
	294	drm_framebuffer_cleanup(fb);
	295	kfree(fb);
	296	}
	297
312fec14 DA	298	static const struct drm_framebuffer_funcs ast_fb_funcs = {
312fec14 DA	299	.destroy = ast_user_framebuffer_destroy,
312fec14 DA	300	};
	301
	302
	303	int ast_framebuffer_init(struct drm_device *dev,
	304	struct ast_framebuffer *ast_fb,
	305	struct drm_mode_fb_cmd2 *mode_cmd,
	306	struct drm_gem_object *obj)
	307	{
	308	int ret;
	309
c7d73f6a DV	310	drm_helper_mode_fill_fb_struct(&ast_fb->base, mode_cmd);
c7d73f6a DV	311	ast_fb->obj = obj;
312fec14 DA	312	ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs);
	313	if (ret) {
	314	DRM_ERROR("framebuffer init failed %d\n", ret);
	315	return ret;
	316	}
312fec14 DA	317	return 0;
	318	}
	319
	320	static struct drm_framebuffer *
	321	ast_user_framebuffer_create(struct drm_device *dev,
	322	struct drm_file *filp,
	323	struct drm_mode_fb_cmd2 *mode_cmd)
	324	{
	325	struct drm_gem_object *obj;
	326	struct ast_framebuffer *ast_fb;
	327	int ret;
	328
	329	obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]);
	330	if (obj == NULL)
	331	return ERR_PTR(-ENOENT);
	332
	333	ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL);
	334	if (!ast_fb) {
	335	drm_gem_object_unreference_unlocked(obj);
	336	return ERR_PTR(-ENOMEM);
	337	}
	338
	339	ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj);
	340	if (ret) {
	341	drm_gem_object_unreference_unlocked(obj);
	342	kfree(ast_fb);
	343	return ERR_PTR(ret);
	344	}
	345	return &ast_fb->base;
	346	}
	347
	348	static const struct drm_mode_config_funcs ast_mode_funcs = {
	349	.fb_create = ast_user_framebuffer_create,
	350	};
	351
	352	static u32 ast_get_vram_info(struct drm_device *dev)
	353	{
	354	struct ast_private *ast = dev->dev_private;
	355	u8 jreg;
83c6620b	356	u32 vram_size;
312fec14 DA	357	ast_open_key(ast);
312fec14 DA	358
83c6620b	359	vram_size = AST_VIDMEM_DEFAULT_SIZE;
312fec14 DA	360	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
312fec14 DA	361	switch (jreg & 3) {
83c6620b DA	362	case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
	363	case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
	364	case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
	365	case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
312fec14	366	}
83c6620b DA	367
	368	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
	369	switch (jreg & 0x03) {
	370	case 1:
	371	vram_size -= 0x100000;
	372	break;
	373	case 2:
	374	vram_size -= 0x200000;
	375	break;
	376	case 3:
	377	vram_size -= 0x400000;
	378	break;
	379	}
	380
	381	return vram_size;
312fec14 DA	382	}
	383
	384	int ast_driver_load(struct drm_device *dev, unsigned long flags)
	385	{
	386	struct ast_private *ast;
d1b98557	387	bool need_post;
312fec14 DA	388	int ret = 0;
	389
	390	ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
	391	if (!ast)
	392	return -ENOMEM;
	393
	394	dev->dev_private = ast;
	395	ast->dev = dev;
	396
	397	ast->regs = pci_iomap(dev->pdev, 1, 0);
	398	if (!ast->regs) {
	399	ret = -EIO;
	400	goto out_free;
	401	}
0dd68309 BH	402
	403	/*
	404	* If we don't have IO space at all, use MMIO now and
	405	* assume the chip has MMIO enabled by default (rev 0x20
	406	* and higher).
	407	*/
	408	if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
	409	DRM_INFO("platform has no IO space, trying MMIO\n");
	410	ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
	411	}
	412
	413	/* "map" IO regs if the above hasn't done so already */
312fec14	414	if (!ast->ioregs) {
0dd68309 BH	415	ast->ioregs = pci_iomap(dev->pdev, 2, 0);
	416	if (!ast->ioregs) {
	417	ret = -EIO;
	418	goto out_free;
	419	}
312fec14 DA	420	}
312fec14 DA	421
d1b98557	422	ast_detect_chip(dev, &need_post);
312fec14 DA	423
	424	if (ast->chip != AST1180) {
	425	ast_get_dram_info(dev);
	426	ast->vram_size = ast_get_vram_info(dev);
	427	DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
	428	}
	429
d1b98557 BH	430	if (need_post)
	431	ast_post_gpu(dev);
	432
312fec14 DA	433	ret = ast_mm_init(ast);
	434	if (ret)
	435	goto out_free;
	436
	437	drm_mode_config_init(dev);
	438
	439	dev->mode_config.funcs = (void *)&ast_mode_funcs;
	440	dev->mode_config.min_width = 0;
	441	dev->mode_config.min_height = 0;
	442	dev->mode_config.preferred_depth = 24;
	443	dev->mode_config.prefer_shadow = 1;
	444
	445	if (ast->chip == AST2100 \|\|
	446	ast->chip == AST2200 \|\|
	447	ast->chip == AST2300 \|\|
1453bf4c	448	ast->chip == AST2400 \|\|
312fec14 DA	449	ast->chip == AST1180) {
	450	dev->mode_config.max_width = 1920;
	451	dev->mode_config.max_height = 2048;
	452	} else {
	453	dev->mode_config.max_width = 1600;
	454	dev->mode_config.max_height = 1200;
	455	}
	456
	457	ret = ast_mode_init(dev);
	458	if (ret)
	459	goto out_free;
	460
	461	ret = ast_fbdev_init(dev);
	462	if (ret)
	463	goto out_free;
	464
	465	return 0;
	466	out_free:
	467	kfree(ast);
	468	dev->dev_private = NULL;
	469	return ret;
	470	}
	471
	472	int ast_driver_unload(struct drm_device *dev)
	473	{
	474	struct ast_private *ast = dev->dev_private;
	475
83c6620b	476	kfree(ast->dp501_fw_addr);
312fec14 DA	477	ast_mode_fini(dev);
	478	ast_fbdev_fini(dev);
	479	drm_mode_config_cleanup(dev);
	480
	481	ast_mm_fini(ast);
	482	pci_iounmap(dev->pdev, ast->ioregs);
	483	pci_iounmap(dev->pdev, ast->regs);
	484	kfree(ast);
	485	return 0;
	486	}
	487
	488	int ast_gem_create(struct drm_device *dev,
	489	u32 size, bool iskernel,
	490	struct drm_gem_object **obj)
	491	{
	492	struct ast_bo *astbo;
	493	int ret;
	494
	495	*obj = NULL;
	496
	497	size = roundup(size, PAGE_SIZE);
	498	if (size == 0)
	499	return -EINVAL;
	500
	501	ret = ast_bo_create(dev, size, 0, 0, &astbo);
	502	if (ret) {
	503	if (ret != -ERESTARTSYS)
	504	DRM_ERROR("failed to allocate GEM object\n");
	505	return ret;
	506	}
	507	*obj = &astbo->gem;
	508	return 0;
	509	}
	510
	511	int ast_dumb_create(struct drm_file *file,
	512	struct drm_device *dev,
	513	struct drm_mode_create_dumb *args)
	514	{
	515	int ret;
	516	struct drm_gem_object *gobj;
	517	u32 handle;
	518
	519	args->pitch = args->width * ((args->bpp + 7) / 8);
	520	args->size = args->pitch * args->height;
	521
	522	ret = ast_gem_create(dev, args->size, false,
	523	&gobj);
	524	if (ret)
	525	return ret;
	526
	527	ret = drm_gem_handle_create(file, gobj, &handle);
	528	drm_gem_object_unreference_unlocked(gobj);
	529	if (ret)
	530	return ret;
	531
	532	args->handle = handle;
	533	return 0;
	534	}
	535
f6109803	536	static void ast_bo_unref(struct ast_bo **bo)
312fec14 DA	537	{
	538	struct ttm_buffer_object *tbo;
	539
	540	if ((*bo) == NULL)
	541	return;
	542
	543	tbo = &((*bo)->bo);
	544	ttm_bo_unref(&tbo);
eb649a61	545	*bo = NULL;
312fec14	546	}
eb649a61	547
312fec14 DA	548	void ast_gem_free_object(struct drm_gem_object *obj)
	549	{
	550	struct ast_bo *ast_bo = gem_to_ast_bo(obj);
	551
312fec14 DA	552	ast_bo_unref(&ast_bo);
	553	}
	554
	555
	556	static inline u64 ast_bo_mmap_offset(struct ast_bo *bo)
	557	{
72525b3f	558	return drm_vma_node_offset_addr(&bo->bo.vma_node);
312fec14 DA	559	}
	560	int
	561	ast_dumb_mmap_offset(struct drm_file *file,
	562	struct drm_device *dev,
	563	uint32_t handle,
	564	uint64_t *offset)
	565	{
	566	struct drm_gem_object *obj;
	567	int ret;
	568	struct ast_bo *bo;
	569
	570	mutex_lock(&dev->struct_mutex);
	571	obj = drm_gem_object_lookup(dev, file, handle);
	572	if (obj == NULL) {
	573	ret = -ENOENT;
	574	goto out_unlock;
	575	}
	576
	577	bo = gem_to_ast_bo(obj);
	578	*offset = ast_bo_mmap_offset(bo);
	579
	580	drm_gem_object_unreference(obj);
	581	ret = 0;
	582	out_unlock:
	583	mutex_unlock(&dev->struct_mutex);
	584	return ret;
	585
	586	}
	587