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drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.h
[deliverable/linux.git] / drivers / gpu / drm / ast / ast_mode.c
CommitLineData
312fec14
DA		 1/*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27/*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
3cb9ae4f 34#include <drm/drm_plane_helper.h>
312fec14
DA		 35#include "ast_drv.h"
36
37#include "ast_tables.h"
38
39static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
40static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
41static int ast_cursor_set(struct drm_crtc *crtc,
42 struct drm_file *file_priv,
43 uint32_t handle,
44 uint32_t width,
45 uint32_t height);
46static int ast_cursor_move(struct drm_crtc *crtc,
47 int x, int y);
48
49static inline void ast_load_palette_index(struct ast_private *ast,
50 u8 index, u8 red, u8 green,
51 u8 blue)
52{
53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
54 ast_io_read8(ast, AST_IO_SEQ_PORT);
55 ast_io_write8(ast, AST_IO_DAC_DATA, red);
56 ast_io_read8(ast, AST_IO_SEQ_PORT);
57 ast_io_write8(ast, AST_IO_DAC_DATA, green);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61}
62
63static void ast_crtc_load_lut(struct drm_crtc *crtc)
64{
65 struct ast_private *ast = crtc->dev->dev_private;
66 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
67 int i;
68
69 if (!crtc->enabled)
70 return;
71
72 for (i = 0; i < 256; i++)
73 ast_load_palette_index(ast, i, ast_crtc->lut_r[i],
74 ast_crtc->lut_g[i], ast_crtc->lut_b[i]);
75}
76
77static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode,
79 struct ast_vbios_mode_info *vbios_mode)
80{
81 struct ast_private *ast = crtc->dev->dev_private;
82 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
83 u32 hborder, vborder;
94d12b13
C		 84 bool check_sync;
85 struct ast_vbios_enhtable *best = NULL;
312fec14 86
f4510a27 87 switch (crtc->primary->fb->bits_per_pixel) {
312fec14
DA		 88 case 8:
89 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
90 color_index = VGAModeIndex - 1;
91 break;
92 case 16:
93 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
94 color_index = HiCModeIndex;
95 break;
96 case 24:
97 case 32:
98 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
99 color_index = TrueCModeIndex;
100 break;
101 default:
102 return false;
103 }
104
105 switch (crtc->mode.crtc_hdisplay) {
106 case 640:
107 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
108 break;
109 case 800:
110 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
111 break;
112 case 1024:
113 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
114 break;
115 case 1280:
116 if (crtc->mode.crtc_vdisplay == 800)
117 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
118 else
119 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
120 break;
f1f62f2c
DA		 121 case 1360:
122 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
123 break;
312fec14
DA		 124 case 1440:
125 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
126 break;
127 case 1600:
f1f62f2c
DA		 128 if (crtc->mode.crtc_vdisplay == 900)
129 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
130 else
131 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
312fec14
DA		 132 break;
133 case 1680:
134 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
135 break;
136 case 1920:
137 if (crtc->mode.crtc_vdisplay == 1080)
138 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
139 else
140 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
141 break;
142 default:
143 return false;
144 }
145
146 refresh_rate = drm_mode_vrefresh(mode);
94d12b13
C		 147 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
148 do {
149 struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
150
151 while (loop->refresh_rate != 0xff) {
152 if ((check_sync) &&
153 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
154 (loop->flags & PVSync)) ||
155 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
156 (loop->flags & NVSync)) ||
157 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
158 (loop->flags & PHSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
160 (loop->flags & NHSync)))) {
161 loop++;
162 continue;
163 }
164 if (loop->refresh_rate <= refresh_rate
165 && (!best || loop->refresh_rate > best->refresh_rate))
166 best = loop;
167 loop++;
312fec14 168 }
94d12b13
C		 169 if (best || !check_sync)
170 break;
171 check_sync = 0;
172 } while (1);
173 if (best)
174 vbios_mode->enh_table = best;
312fec14
DA		 175
176 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
177 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
178
179 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
180 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
181 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
182 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
183 vbios_mode->enh_table->hfp;
184 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
185 vbios_mode->enh_table->hfp +
186 vbios_mode->enh_table->hsync);
187
188 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
189 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
190 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
191 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
192 vbios_mode->enh_table->vfp;
193 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
194 vbios_mode->enh_table->vfp +
195 vbios_mode->enh_table->vsync);
196
197 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
198 mode_id = vbios_mode->enh_table->mode_id;
199
200 if (ast->chip == AST1180) {
201 /* TODO 1180 */
202 } else {
203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
206
f1f62f2c
DA		 207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
208 if (vbios_mode->enh_table->flags & NewModeInfo) {
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
263432b0 210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
f1f62f2c
DA		 211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
312fec14 214
f1f62f2c
DA		 215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
217 }
312fec14
DA		 218 }
219
220 return true;
221
222
223}
224static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
225 struct ast_vbios_mode_info *vbios_mode)
226{
227 struct ast_private *ast = crtc->dev->dev_private;
228 struct ast_vbios_stdtable *stdtable;
229 u32 i;
230 u8 jreg;
231
232 stdtable = vbios_mode->std_table;
233
234 jreg = stdtable->misc;
235 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
236
237 /* Set SEQ */
238 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
239 for (i = 0; i < 4; i++) {
240 jreg = stdtable->seq[i];
241 if (!i)
242 jreg |= 0x20;
243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
244 }
245
246 /* Set CRTC */
247 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
248 for (i = 0; i < 25; i++)
249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
250
251 /* set AR */
252 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
253 for (i = 0; i < 20; i++) {
254 jreg = stdtable->ar[i];
255 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
256 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
257 }
258 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
259 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
260
261 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
262 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
263
264 /* Set GR */
265 for (i = 0; i < 9; i++)
266 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
267}
268
269static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
270 struct ast_vbios_mode_info *vbios_mode)
271{
272 struct ast_private *ast = crtc->dev->dev_private;
273 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
274 u16 temp;
275
276 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
277
278 temp = (mode->crtc_htotal >> 3) - 5;
279 if (temp & 0x100)
280 jregAC |= 0x01; /* HT D[8] */
281 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
282
283 temp = (mode->crtc_hdisplay >> 3) - 1;
284 if (temp & 0x100)
285 jregAC |= 0x04; /* HDE D[8] */
286 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
287
288 temp = (mode->crtc_hblank_start >> 3) - 1;
289 if (temp & 0x100)
290 jregAC |= 0x10; /* HBS D[8] */
291 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
292
293 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
294 if (temp & 0x20)
295 jreg05 |= 0x80; /* HBE D[5] */
296 if (temp & 0x40)
297 jregAD |= 0x01; /* HBE D[5] */
298 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
299
300 temp = (mode->crtc_hsync_start >> 3) - 1;
301 if (temp & 0x100)
302 jregAC |= 0x40; /* HRS D[5] */
303 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
304
305 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
306 if (temp & 0x20)
307 jregAD |= 0x04; /* HRE D[5] */
308 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
309
310 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
311 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
312
313 /* vert timings */
314 temp = (mode->crtc_vtotal) - 2;
315 if (temp & 0x100)
316 jreg07 |= 0x01;
317 if (temp & 0x200)
318 jreg07 |= 0x20;
319 if (temp & 0x400)
320 jregAE |= 0x01;
321 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
322
323 temp = (mode->crtc_vsync_start) - 1;
324 if (temp & 0x100)
325 jreg07 |= 0x04;
326 if (temp & 0x200)
327 jreg07 |= 0x80;
328 if (temp & 0x400)
329 jregAE |= 0x08;
330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
331
332 temp = (mode->crtc_vsync_end - 1) & 0x3f;
333 if (temp & 0x10)
334 jregAE |= 0x20;
335 if (temp & 0x20)
336 jregAE |= 0x40;
337 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
338
339 temp = mode->crtc_vdisplay - 1;
340 if (temp & 0x100)
341 jreg07 |= 0x02;
342 if (temp & 0x200)
343 jreg07 |= 0x40;
344 if (temp & 0x400)
345 jregAE |= 0x02;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
347
348 temp = mode->crtc_vblank_start - 1;
349 if (temp & 0x100)
350 jreg07 |= 0x08;
351 if (temp & 0x200)
352 jreg09 |= 0x20;
353 if (temp & 0x400)
354 jregAE |= 0x04;
355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
356
357 temp = mode->crtc_vblank_end - 1;
358 if (temp & 0x100)
359 jregAE |= 0x10;
360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
361
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
363 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
365
366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
367}
368
369static void ast_set_offset_reg(struct drm_crtc *crtc)
370{
371 struct ast_private *ast = crtc->dev->dev_private;
372
373 u16 offset;
374
f4510a27 375 offset = crtc->primary->fb->pitches[0] >> 3;
312fec14
DA		 376 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
377 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
378}
379
380static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
381 struct ast_vbios_mode_info *vbios_mode)
382{
383 struct ast_private *ast = dev->dev_private;
384 struct ast_vbios_dclk_info *clk_info;
385
386 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
387
388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
390 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
391 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
392}
393
394static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
395 struct ast_vbios_mode_info *vbios_mode)
396{
397 struct ast_private *ast = crtc->dev->dev_private;
398 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
399
f4510a27 400 switch (crtc->primary->fb->bits_per_pixel) {
312fec14
DA		 401 case 8:
402 jregA0 = 0x70;
403 jregA3 = 0x01;
404 jregA8 = 0x00;
405 break;
406 case 15:
407 case 16:
408 jregA0 = 0x70;
409 jregA3 = 0x04;
410 jregA8 = 0x02;
411 break;
412 case 32:
413 jregA0 = 0x70;
414 jregA3 = 0x08;
415 jregA8 = 0x02;
416 break;
417 }
418
419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
420 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
422
423 /* Set Threshold */
1453bf4c 424 if (ast->chip == AST2300 || ast->chip == AST2400) {
312fec14
DA		 425 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
426 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
427 } else if (ast->chip == AST2100 ||
428 ast->chip == AST1100 ||
429 ast->chip == AST2200 ||
430 ast->chip == AST2150) {
431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
432 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
433 } else {
434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
436 }
437}
438
7f5ccd44 439static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
312fec14
DA		 440 struct ast_vbios_mode_info *vbios_mode)
441{
442 struct ast_private *ast = dev->dev_private;
443 u8 jreg;
444
94d12b13
C		 445 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
446 jreg &= ~0xC0;
447 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
448 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
312fec14
DA		 449 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
450}
451
7f5ccd44 452static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
312fec14
DA		 453 struct ast_vbios_mode_info *vbios_mode)
454{
f4510a27 455 switch (crtc->primary->fb->bits_per_pixel) {
312fec14
DA		 456 case 8:
457 break;
458 default:
459 return false;
460 }
461 return true;
462}
463
7f5ccd44 464static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
312fec14
DA		 465{
466 struct ast_private *ast = crtc->dev->dev_private;
467 u32 addr;
468
469 addr = offset >> 2;
470 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
471 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
472 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
473
474}
475
476static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
477{
478 struct ast_private *ast = crtc->dev->dev_private;
479
480 if (ast->chip == AST1180)
481 return;
482
483 switch (mode) {
484 case DRM_MODE_DPMS_ON:
485 case DRM_MODE_DPMS_STANDBY:
486 case DRM_MODE_DPMS_SUSPEND:
487 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
83c6620b
DA		 488 if (ast->tx_chip_type == AST_TX_DP501)
489 ast_set_dp501_video_output(crtc->dev, 1);
312fec14
DA		 490 ast_crtc_load_lut(crtc);
491 break;
492 case DRM_MODE_DPMS_OFF:
83c6620b
DA		 493 if (ast->tx_chip_type == AST_TX_DP501)
494 ast_set_dp501_video_output(crtc->dev, 0);
312fec14
DA		 495 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
496 break;
497 }
498}
499
500static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae
LP		 501 const struct drm_display_mode *mode,
502 struct drm_display_mode *adjusted_mode)
312fec14
DA		 503{
504 return true;
505}
506
507/* ast is different - we will force move buffers out of VRAM */
508static int ast_crtc_do_set_base(struct drm_crtc *crtc,
509 struct drm_framebuffer *fb,
510 int x, int y, int atomic)
511{
512 struct ast_private *ast = crtc->dev->dev_private;
513 struct drm_gem_object *obj;
514 struct ast_framebuffer *ast_fb;
515 struct ast_bo *bo;
516 int ret;
517 u64 gpu_addr;
518
519 /* push the previous fb to system ram */
520 if (!atomic && fb) {
521 ast_fb = to_ast_framebuffer(fb);
522 obj = ast_fb->obj;
523 bo = gem_to_ast_bo(obj);
524 ret = ast_bo_reserve(bo, false);
525 if (ret)
526 return ret;
527 ast_bo_push_sysram(bo);
528 ast_bo_unreserve(bo);
529 }
530
f4510a27 531 ast_fb = to_ast_framebuffer(crtc->primary->fb);
312fec14
DA		 532 obj = ast_fb->obj;
533 bo = gem_to_ast_bo(obj);
534
535 ret = ast_bo_reserve(bo, false);
536 if (ret)
537 return ret;
538
539 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
540 if (ret) {
541 ast_bo_unreserve(bo);
542 return ret;
543 }
544
545 if (&ast->fbdev->afb == ast_fb) {
546 /* if pushing console in kmap it */
547 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
548 if (ret)
549 DRM_ERROR("failed to kmap fbcon\n");
550 }
551 ast_bo_unreserve(bo);
552
553 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
554
555 return 0;
556}
557
558static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
559 struct drm_framebuffer *old_fb)
560{
561 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
562}
563
564static int ast_crtc_mode_set(struct drm_crtc *crtc,
565 struct drm_display_mode *mode,
566 struct drm_display_mode *adjusted_mode,
567 int x, int y,
568 struct drm_framebuffer *old_fb)
569{
570 struct drm_device *dev = crtc->dev;
571 struct ast_private *ast = crtc->dev->dev_private;
572 struct ast_vbios_mode_info vbios_mode;
573 bool ret;
574 if (ast->chip == AST1180) {
575 DRM_ERROR("AST 1180 modesetting not supported\n");
576 return -EINVAL;
577 }
578
579 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
580 if (ret == false)
581 return -EINVAL;
582 ast_open_key(ast);
583
584 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
585
586 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
587 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
588 ast_set_offset_reg(crtc);
589 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
590 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
591 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
592 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
593
594 ast_crtc_mode_set_base(crtc, x, y, old_fb);
595
596 return 0;
597}
598
599static void ast_crtc_disable(struct drm_crtc *crtc)
600{
601
602}
603
604static void ast_crtc_prepare(struct drm_crtc *crtc)
605{
606
607}
608
609static void ast_crtc_commit(struct drm_crtc *crtc)
610{
611 struct ast_private *ast = crtc->dev->dev_private;
612 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
613}
614
615
616static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
617 .dpms = ast_crtc_dpms,
618 .mode_fixup = ast_crtc_mode_fixup,
619 .mode_set = ast_crtc_mode_set,
620 .mode_set_base = ast_crtc_mode_set_base,
621 .disable = ast_crtc_disable,
622 .load_lut = ast_crtc_load_lut,
312fec14
DA		 623 .prepare = ast_crtc_prepare,
624 .commit = ast_crtc_commit,
625
626};
627
628static void ast_crtc_reset(struct drm_crtc *crtc)
629{
630
631}
632
633static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
634 u16 *blue, uint32_t start, uint32_t size)
635{
636 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
637 int end = (start + size > 256) ? 256 : start + size, i;
638
639 /* userspace palettes are always correct as is */
640 for (i = start; i < end; i++) {
641 ast_crtc->lut_r[i] = red[i] >> 8;
642 ast_crtc->lut_g[i] = green[i] >> 8;
643 ast_crtc->lut_b[i] = blue[i] >> 8;
644 }
645 ast_crtc_load_lut(crtc);
646}
647
648
649static void ast_crtc_destroy(struct drm_crtc *crtc)
650{
651 drm_crtc_cleanup(crtc);
652 kfree(crtc);
653}
654
655static const struct drm_crtc_funcs ast_crtc_funcs = {
656 .cursor_set = ast_cursor_set,
657 .cursor_move = ast_cursor_move,
658 .reset = ast_crtc_reset,
659 .set_config = drm_crtc_helper_set_config,
660 .gamma_set = ast_crtc_gamma_set,
661 .destroy = ast_crtc_destroy,
662};
663
7f5ccd44 664static int ast_crtc_init(struct drm_device *dev)
312fec14
DA		 665{
666 struct ast_crtc *crtc;
667 int i;
668
669 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
670 if (!crtc)
671 return -ENOMEM;
672
673 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
674 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
675 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
676
677 for (i = 0; i < 256; i++) {
678 crtc->lut_r[i] = i;
679 crtc->lut_g[i] = i;
680 crtc->lut_b[i] = i;
681 }
682 return 0;
683}
684
685static void ast_encoder_destroy(struct drm_encoder *encoder)
686{
687 drm_encoder_cleanup(encoder);
688 kfree(encoder);
689}
690
691
692static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
693{
694 int enc_id = connector->encoder_ids[0];
312fec14 695 /* pick the encoder ids */
70e26260
RC		 696 if (enc_id)
697 return drm_encoder_find(connector->dev, enc_id);
312fec14
DA		 698 return NULL;
699}
700
701
702static const struct drm_encoder_funcs ast_enc_funcs = {
703 .destroy = ast_encoder_destroy,
704};
705
706static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
707{
708
709}
710
711static bool ast_mode_fixup(struct drm_encoder *encoder,
e811f5ae 712 const struct drm_display_mode *mode,
312fec14
DA		 713 struct drm_display_mode *adjusted_mode)
714{
715 return true;
716}
717
718static void ast_encoder_mode_set(struct drm_encoder *encoder,
719 struct drm_display_mode *mode,
720 struct drm_display_mode *adjusted_mode)
721{
722}
723
724static void ast_encoder_prepare(struct drm_encoder *encoder)
725{
726
727}
728
729static void ast_encoder_commit(struct drm_encoder *encoder)
730{
731
732}
733
734
735static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
736 .dpms = ast_encoder_dpms,
737 .mode_fixup = ast_mode_fixup,
738 .prepare = ast_encoder_prepare,
739 .commit = ast_encoder_commit,
740 .mode_set = ast_encoder_mode_set,
741};
742
7f5ccd44 743static int ast_encoder_init(struct drm_device *dev)
312fec14
DA		 744{
745 struct ast_encoder *ast_encoder;
746
747 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
748 if (!ast_encoder)
749 return -ENOMEM;
750
751 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
752 DRM_MODE_ENCODER_DAC);
753 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
754
755 ast_encoder->base.possible_crtcs = 1;
756 return 0;
757}
758
759static int ast_get_modes(struct drm_connector *connector)
760{
761 struct ast_connector *ast_connector = to_ast_connector(connector);
83c6620b 762 struct ast_private *ast = connector->dev->dev_private;
312fec14
DA		 763 struct edid *edid;
764 int ret;
83c6620b
DA		 765 bool flags = false;
766 if (ast->tx_chip_type == AST_TX_DP501) {
767 ast->dp501_maxclk = 0xff;
768 edid = kmalloc(128, GFP_KERNEL);
769 if (!edid)
770 return -ENOMEM;
771
772 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
773 if (flags)
774 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
775 else
776 kfree(edid);
777 }
778 if (!flags)
779 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
312fec14
DA		 780 if (edid) {
781 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
782 ret = drm_add_edid_modes(connector, edid);
993dcb05 783 kfree(edid);
312fec14
DA		 784 return ret;
785 } else
786 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
787 return 0;
788}
789
790static int ast_mode_valid(struct drm_connector *connector,
791 struct drm_display_mode *mode)
792{
f1f62f2c
DA		 793 struct ast_private *ast = connector->dev->dev_private;
794 int flags = MODE_NOMODE;
795 uint32_t jtemp;
796
797 if (ast->support_wide_screen) {
798 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
799 return MODE_OK;
800 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
801 return MODE_OK;
802 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
803 return MODE_OK;
804 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
805 return MODE_OK;
806 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
807 return MODE_OK;
808
1453bf4c 809 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
f1f62f2c
DA		 810 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
811 return MODE_OK;
812
813 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
814 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
815 if (jtemp & 0x01)
816 return MODE_NOMODE;
817 else
818 return MODE_OK;
819 }
820 }
821 }
822 switch (mode->hdisplay) {
823 case 640:
824 if (mode->vdisplay == 480) flags = MODE_OK;
825 break;
826 case 800:
827 if (mode->vdisplay == 600) flags = MODE_OK;
828 break;
829 case 1024:
830 if (mode->vdisplay == 768) flags = MODE_OK;
831 break;
832 case 1280:
833 if (mode->vdisplay == 1024) flags = MODE_OK;
834 break;
835 case 1600:
836 if (mode->vdisplay == 1200) flags = MODE_OK;
837 break;
838 default:
839 return flags;
840 }
841
842 return flags;
312fec14
DA		 843}
844
845static void ast_connector_destroy(struct drm_connector *connector)
846{
847 struct ast_connector *ast_connector = to_ast_connector(connector);
848 ast_i2c_destroy(ast_connector->i2c);
34ea3d38 849 drm_connector_unregister(connector);
312fec14
DA		 850 drm_connector_cleanup(connector);
851 kfree(connector);
852}
853
854static enum drm_connector_status
855ast_connector_detect(struct drm_connector *connector, bool force)
856{
857 return connector_status_connected;
858}
859
860static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
861 .mode_valid = ast_mode_valid,
862 .get_modes = ast_get_modes,
863 .best_encoder = ast_best_single_encoder,
864};
865
866static const struct drm_connector_funcs ast_connector_funcs = {
867 .dpms = drm_helper_connector_dpms,
868 .detect = ast_connector_detect,
869 .fill_modes = drm_helper_probe_single_connector_modes,
870 .destroy = ast_connector_destroy,
871};
872
7f5ccd44 873static int ast_connector_init(struct drm_device *dev)
312fec14
DA		 874{
875 struct ast_connector *ast_connector;
876 struct drm_connector *connector;
877 struct drm_encoder *encoder;
878
879 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
880 if (!ast_connector)
881 return -ENOMEM;
882
883 connector = &ast_connector->base;
884 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
885
886 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
887
888 connector->interlace_allowed = 0;
889 connector->doublescan_allowed = 0;
890
34ea3d38 891 drm_connector_register(connector);
312fec14
DA		 892
893 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
894
895 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
896 drm_mode_connector_attach_encoder(connector, encoder);
897
898 ast_connector->i2c = ast_i2c_create(dev);
899 if (!ast_connector->i2c)
900 DRM_ERROR("failed to add ddc bus for connector\n");
901
902 return 0;
903}
904
905/* allocate cursor cache and pin at start of VRAM */
7f5ccd44 906static int ast_cursor_init(struct drm_device *dev)
312fec14
DA		 907{
908 struct ast_private *ast = dev->dev_private;
909 int size;
910 int ret;
911 struct drm_gem_object *obj;
912 struct ast_bo *bo;
913 uint64_t gpu_addr;
914
915 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
916
917 ret = ast_gem_create(dev, size, true, &obj);
918 if (ret)
919 return ret;
920 bo = gem_to_ast_bo(obj);
921 ret = ast_bo_reserve(bo, false);
922 if (unlikely(ret != 0))
923 goto fail;
924
925 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
926 ast_bo_unreserve(bo);
927 if (ret)
928 goto fail;
929
930 /* kmap the object */
931 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
932 if (ret)
933 goto fail;
934
935 ast->cursor_cache = obj;
936 ast->cursor_cache_gpu_addr = gpu_addr;
0273de08 937 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
312fec14
DA		 938 return 0;
939fail:
940 return ret;
941}
942
7f5ccd44 943static void ast_cursor_fini(struct drm_device *dev)
312fec14
DA		 944{
945 struct ast_private *ast = dev->dev_private;
946 ttm_bo_kunmap(&ast->cache_kmap);
947 drm_gem_object_unreference_unlocked(ast->cursor_cache);
948}
949
950int ast_mode_init(struct drm_device *dev)
951{
952 ast_cursor_init(dev);
953 ast_crtc_init(dev);
954 ast_encoder_init(dev);
955 ast_connector_init(dev);
956 return 0;
957}
958
959void ast_mode_fini(struct drm_device *dev)
960{
961 ast_cursor_fini(dev);
962}
963
964static int get_clock(void *i2c_priv)
965{
966 struct ast_i2c_chan *i2c = i2c_priv;
967 struct ast_private *ast = i2c->dev->dev_private;
968 uint32_t val;
969
970 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
971 return val & 1 ? 1 : 0;
972}
973
974static int get_data(void *i2c_priv)
975{
976 struct ast_i2c_chan *i2c = i2c_priv;
977 struct ast_private *ast = i2c->dev->dev_private;
978 uint32_t val;
979
980 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
981 return val & 1 ? 1 : 0;
982}
983
984static void set_clock(void *i2c_priv, int clock)
985{
986 struct ast_i2c_chan *i2c = i2c_priv;
987 struct ast_private *ast = i2c->dev->dev_private;
988 int i;
989 u8 ujcrb7, jtemp;
990
991 for (i = 0; i < 0x10000; i++) {
992 ujcrb7 = ((clock & 0x01) ? 0 : 1);
993 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
994 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
995 if (ujcrb7 == jtemp)
996 break;
997 }
998}
999
1000static void set_data(void *i2c_priv, int data)
1001{
1002 struct ast_i2c_chan *i2c = i2c_priv;
1003 struct ast_private *ast = i2c->dev->dev_private;
1004 int i;
1005 u8 ujcrb7, jtemp;
1006
1007 for (i = 0; i < 0x10000; i++) {
1008 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1009 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
1010 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1011 if (ujcrb7 == jtemp)
1012 break;
1013 }
1014}
1015
1016static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1017{
1018 struct ast_i2c_chan *i2c;
1019 int ret;
1020
1021 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1022 if (!i2c)
1023 return NULL;
1024
1025 i2c->adapter.owner = THIS_MODULE;
1026 i2c->adapter.class = I2C_CLASS_DDC;
1027 i2c->adapter.dev.parent = &dev->pdev->dev;
1028 i2c->dev = dev;
1029 i2c_set_adapdata(&i2c->adapter, i2c);
1030 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1031 "AST i2c bit bus");
1032 i2c->adapter.algo_data = &i2c->bit;
1033
1034 i2c->bit.udelay = 20;
1035 i2c->bit.timeout = 2;
1036 i2c->bit.data = i2c;
1037 i2c->bit.setsda = set_data;
1038 i2c->bit.setscl = set_clock;
1039 i2c->bit.getsda = get_data;
1040 i2c->bit.getscl = get_clock;
1041 ret = i2c_bit_add_bus(&i2c->adapter);
1042 if (ret) {
1043 DRM_ERROR("Failed to register bit i2c\n");
1044 goto out_free;
1045 }
1046
1047 return i2c;
1048out_free:
1049 kfree(i2c);
1050 return NULL;
1051}
1052
1053static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1054{
1055 if (!i2c)
1056 return;
1057 i2c_del_adapter(&i2c->adapter);
1058 kfree(i2c);
1059}
1060
7f5ccd44 1061static void ast_show_cursor(struct drm_crtc *crtc)
312fec14
DA		 1062{
1063 struct ast_private *ast = crtc->dev->dev_private;
1064 u8 jreg;
1065
1066 jreg = 0x2;
1067 /* enable ARGB cursor */
1068 jreg |= 1;
1069 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1070}
1071
7f5ccd44 1072static void ast_hide_cursor(struct drm_crtc *crtc)
312fec14
DA		 1073{
1074 struct ast_private *ast = crtc->dev->dev_private;
1075 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1076}
1077
1078static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1079{
1080 union {
1081 u32 ul;
1082 u8 b[4];
1083 } srcdata32[2], data32;
1084 union {
1085 u16 us;
1086 u8 b[2];
1087 } data16;
1088 u32 csum = 0;
1089 s32 alpha_dst_delta, last_alpha_dst_delta;
1090 u8 *srcxor, *dstxor;
1091 int i, j;
1092 u32 per_pixel_copy, two_pixel_copy;
1093
1094 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1095 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1096
1097 srcxor = src;
1098 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1099 per_pixel_copy = width & 1;
1100 two_pixel_copy = width >> 1;
1101
1102 for (j = 0; j < height; j++) {
1103 for (i = 0; i < two_pixel_copy; i++) {
1104 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1105 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1106 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1107 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1e99cfa8
BH		 1108 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1109 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
312fec14
DA		 1110
1111 writel(data32.ul, dstxor);
1112 csum += data32.ul;
1113
1114 dstxor += 4;
1115 srcxor += 8;
1116
1117 }
1118
1119 for (i = 0; i < per_pixel_copy; i++) {
1120 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1121 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1122 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1123 writew(data16.us, dstxor);
1124 csum += (u32)data16.us;
1125
1126 dstxor += 2;
1127 srcxor += 4;
1128 }
1129 dstxor += last_alpha_dst_delta;
1130 }
1131 return csum;
1132}
1133
1134static int ast_cursor_set(struct drm_crtc *crtc,
1135 struct drm_file *file_priv,
1136 uint32_t handle,
1137 uint32_t width,
1138 uint32_t height)
1139{
1140 struct ast_private *ast = crtc->dev->dev_private;
1141 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1142 struct drm_gem_object *obj;
1143 struct ast_bo *bo;
1144 uint64_t gpu_addr;
1145 u32 csum;
1146 int ret;
1147 struct ttm_bo_kmap_obj uobj_map;
1148 u8 *src, *dst;
1149 bool src_isiomem, dst_isiomem;
1150 if (!handle) {
1151 ast_hide_cursor(crtc);
1152 return 0;
1153 }
1154
1155 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1156 return -EINVAL;
1157
1158 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
1159 if (!obj) {
1160 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1161 return -ENOENT;
1162 }
1163 bo = gem_to_ast_bo(obj);
1164
1165 ret = ast_bo_reserve(bo, false);
1166 if (ret)
1167 goto fail;
1168
1169 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1170
1171 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1172 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1173
1174 if (src_isiomem == true)
1175 DRM_ERROR("src cursor bo should be in main memory\n");
1176 if (dst_isiomem == false)
1177 DRM_ERROR("dst bo should be in VRAM\n");
1178
1179 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1180
1181 /* do data transfer to cursor cache */
1182 csum = copy_cursor_image(src, dst, width, height);
1183
1184 /* write checksum + signature */
1185 ttm_bo_kunmap(&uobj_map);
1186 ast_bo_unreserve(bo);
1187 {
1188 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1189 writel(csum, dst);
1190 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1191 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1192 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1193 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1194
1195 /* set pattern offset */
1196 gpu_addr = ast->cursor_cache_gpu_addr;
1197 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1198 gpu_addr >>= 3;
1199 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1200 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1201 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1202 }
1203 ast_crtc->cursor_width = width;
1204 ast_crtc->cursor_height = height;
1205 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1206 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1207
1208 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1209
1210 ast_show_cursor(crtc);
1211
1212 drm_gem_object_unreference_unlocked(obj);
1213 return 0;
1214fail:
1215 drm_gem_object_unreference_unlocked(obj);
1216 return ret;
1217}
1218
1219static int ast_cursor_move(struct drm_crtc *crtc,
1220 int x, int y)
1221{
1222 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1223 struct ast_private *ast = crtc->dev->dev_private;
1224 int x_offset, y_offset;
1225 u8 *sig;
1226
1227 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1228 writel(x, sig + AST_HWC_SIGNATURE_X);
1229 writel(y, sig + AST_HWC_SIGNATURE_Y);
1230
1231 x_offset = ast_crtc->offset_x;
1232 y_offset = ast_crtc->offset_y;
1233 if (x < 0) {
1234 x_offset = (-x) + ast_crtc->offset_x;
1235 x = 0;
1236 }
1237
1238 if (y < 0) {
1239 y_offset = (-y) + ast_crtc->offset_y;
1240 y = 0;
1241 }
1242 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1243 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1244 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1247 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1248
1249 /* dummy write to fire HWC */
1250 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
1251
1252 return 0;
1253}
Linux kernel - Deliverables
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