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drm/tegra: Atomic conversion, phase 2
[deliverable/linux.git] / drivers / gpu / drm / bridge / dw_hdmi.c
CommitLineData
9aaf880e
FE		 1/*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
b21f4b65 9 * Designware High-Definition Multimedia Interface (HDMI) driver
9aaf880e
FE		 10 *
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
12 */
b21f4b65 13#include <linux/module.h>
9aaf880e
FE		 14#include <linux/irq.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
5a819ed6 18#include <linux/hdmi.h>
9aaf880e
FE		 19#include <linux/of_device.h>
20
3d1b35a3 21#include <drm/drm_of.h>
9aaf880e
FE		 22#include <drm/drmP.h>
23#include <drm/drm_crtc_helper.h>
24#include <drm/drm_edid.h>
25#include <drm/drm_encoder_slave.h>
b21f4b65 26#include <drm/bridge/dw_hdmi.h>
9aaf880e 27
b21f4b65 28#include "dw_hdmi.h"
9aaf880e
FE		 29
30#define HDMI_EDID_LEN 512
31
32#define RGB 0
33#define YCBCR444 1
34#define YCBCR422_16BITS 2
35#define YCBCR422_8BITS 3
36#define XVYCC444 4
37
38enum hdmi_datamap {
39 RGB444_8B = 0x01,
40 RGB444_10B = 0x03,
41 RGB444_12B = 0x05,
42 RGB444_16B = 0x07,
43 YCbCr444_8B = 0x09,
44 YCbCr444_10B = 0x0B,
45 YCbCr444_12B = 0x0D,
46 YCbCr444_16B = 0x0F,
47 YCbCr422_8B = 0x16,
48 YCbCr422_10B = 0x14,
49 YCbCr422_12B = 0x12,
50};
51
9aaf880e
FE		 52static const u16 csc_coeff_default[3][4] = {
53 { 0x2000, 0x0000, 0x0000, 0x0000 },
54 { 0x0000, 0x2000, 0x0000, 0x0000 },
55 { 0x0000, 0x0000, 0x2000, 0x0000 }
56};
57
58static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
59 { 0x2000, 0x6926, 0x74fd, 0x010e },
60 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
61 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
62};
63
64static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
65 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
66 { 0x2000, 0x3264, 0x0000, 0x7e6d },
67 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
68};
69
70static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
71 { 0x2591, 0x1322, 0x074b, 0x0000 },
72 { 0x6535, 0x2000, 0x7acc, 0x0200 },
73 { 0x6acd, 0x7534, 0x2000, 0x0200 }
74};
75
76static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
77 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
78 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
79 { 0x6756, 0x78ab, 0x2000, 0x0200 }
80};
81
82struct hdmi_vmode {
83 bool mdvi;
84 bool mhsyncpolarity;
85 bool mvsyncpolarity;
86 bool minterlaced;
87 bool mdataenablepolarity;
88
89 unsigned int mpixelclock;
90 unsigned int mpixelrepetitioninput;
91 unsigned int mpixelrepetitionoutput;
92};
93
94struct hdmi_data_info {
95 unsigned int enc_in_format;
96 unsigned int enc_out_format;
97 unsigned int enc_color_depth;
98 unsigned int colorimetry;
99 unsigned int pix_repet_factor;
100 unsigned int hdcp_enable;
101 struct hdmi_vmode video_mode;
102};
103
b21f4b65 104struct dw_hdmi {
9aaf880e 105 struct drm_connector connector;
3d1b35a3
AY		 106 struct drm_encoder *encoder;
107 struct drm_bridge *bridge;
9aaf880e 108
b21f4b65 109 enum dw_hdmi_devtype dev_type;
9aaf880e
FE		 110 struct device *dev;
111 struct clk *isfr_clk;
112 struct clk *iahb_clk;
113
114 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 115 const struct dw_hdmi_plat_data *plat_data;
116
9aaf880e
FE		 117 int vic;
118
119 u8 edid[HDMI_EDID_LEN];
120 bool cable_plugin;
121
122 bool phy_enabled;
123 struct drm_display_mode previous_mode;
124
125 struct regmap *regmap;
126 struct i2c_adapter *ddc;
127 void __iomem *regs;
128
9aaf880e
FE		 129 unsigned int sample_rate;
130 int ratio;
0cd9d142
AY		 131
132 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
133 u8 (*read)(struct dw_hdmi *hdmi, int offset);
9aaf880e
FE		 134};
135
0cd9d142
AY		 136static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
137{
138 writel(val, hdmi->regs + (offset << 2));
139}
140
141static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
142{
143 return readl(hdmi->regs + (offset << 2));
144}
145
146static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
9aaf880e
FE		 147{
148 writeb(val, hdmi->regs + offset);
149}
150
0cd9d142 151static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
9aaf880e
FE		 152{
153 return readb(hdmi->regs + offset);
154}
155
0cd9d142
AY		 156static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
157{
158 hdmi->write(hdmi, val, offset);
159}
160
161static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
162{
163 return hdmi->read(hdmi, offset);
164}
165
b21f4b65 166static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615
RK		 167{
168 u8 val = hdmi_readb(hdmi, reg) & ~mask;
b44ab1b0 169
812bc615
RK		 170 val |= data & mask;
171 hdmi_writeb(hdmi, val, reg);
172}
173
b21f4b65 174static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 175 u8 shift, u8 mask)
9aaf880e 176{
812bc615 177 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 178}
179
b21f4b65 180static void hdmi_set_clock_regenerator_n(struct dw_hdmi *hdmi,
9aaf880e
FE		 181 unsigned int value)
182{
9aaf880e
FE		 183 hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
184 hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
185 hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
186
187 /* nshift factor = 0 */
812bc615 188 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e
FE		 189}
190
b21f4b65 191static void hdmi_regenerate_cts(struct dw_hdmi *hdmi, unsigned int cts)
9aaf880e 192{
9aaf880e 193 /* Must be set/cleared first */
812bc615 194 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 195
196 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
197 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
198 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
199 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
200}
201
202static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
203 unsigned int ratio)
204{
205 unsigned int n = (128 * freq) / 1000;
206
207 switch (freq) {
208 case 32000:
209 if (pixel_clk == 25170000)
210 n = (ratio == 150) ? 9152 : 4576;
211 else if (pixel_clk == 27020000)
212 n = (ratio == 150) ? 8192 : 4096;
213 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
214 n = 11648;
215 else
216 n = 4096;
217 break;
218
219 case 44100:
220 if (pixel_clk == 25170000)
221 n = 7007;
222 else if (pixel_clk == 74170000)
223 n = 17836;
224 else if (pixel_clk == 148350000)
225 n = (ratio == 150) ? 17836 : 8918;
226 else
227 n = 6272;
228 break;
229
230 case 48000:
231 if (pixel_clk == 25170000)
232 n = (ratio == 150) ? 9152 : 6864;
233 else if (pixel_clk == 27020000)
234 n = (ratio == 150) ? 8192 : 6144;
235 else if (pixel_clk == 74170000)
236 n = 11648;
237 else if (pixel_clk == 148350000)
238 n = (ratio == 150) ? 11648 : 5824;
239 else
240 n = 6144;
241 break;
242
243 case 88200:
244 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
245 break;
246
247 case 96000:
248 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
249 break;
250
251 case 176400:
252 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
253 break;
254
255 case 192000:
256 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
257 break;
258
259 default:
260 break;
261 }
262
263 return n;
264}
265
266static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
267 unsigned int ratio)
268{
269 unsigned int cts = 0;
270
271 pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
272 pixel_clk, ratio);
273
274 switch (freq) {
275 case 32000:
276 if (pixel_clk == 297000000) {
277 cts = 222750;
278 break;
279 }
280 case 48000:
281 case 96000:
282 case 192000:
283 switch (pixel_clk) {
284 case 25200000:
285 case 27000000:
286 case 54000000:
287 case 74250000:
288 case 148500000:
289 cts = pixel_clk / 1000;
290 break;
291 case 297000000:
292 cts = 247500;
293 break;
294 /*
295 * All other TMDS clocks are not supported by
296 * DWC_hdmi_tx. The TMDS clocks divided or
297 * multiplied by 1,001 coefficients are not
298 * supported.
299 */
300 default:
301 break;
302 }
303 break;
304 case 44100:
305 case 88200:
306 case 176400:
307 switch (pixel_clk) {
308 case 25200000:
309 cts = 28000;
310 break;
311 case 27000000:
312 cts = 30000;
313 break;
314 case 54000000:
315 cts = 60000;
316 break;
317 case 74250000:
318 cts = 82500;
319 break;
320 case 148500000:
321 cts = 165000;
322 break;
323 case 297000000:
324 cts = 247500;
325 break;
326 default:
327 break;
328 }
329 break;
330 default:
331 break;
332 }
333 if (ratio == 100)
334 return cts;
7557b6e1 335 return (cts * ratio) / 100;
9aaf880e
FE		 336}
337
b21f4b65 338static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b5878339 339 unsigned long pixel_clk)
9aaf880e
FE		 340{
341 unsigned int clk_n, clk_cts;
342
40678388 343 clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
9aaf880e 344 hdmi->ratio);
40678388 345 clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
9aaf880e
FE		 346 hdmi->ratio);
347
348 if (!clk_cts) {
349 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
b5878339 350 __func__, pixel_clk);
9aaf880e
FE		 351 return;
352 }
353
354 dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n",
355 __func__, hdmi->sample_rate, hdmi->ratio,
40678388 356 pixel_clk, clk_n, clk_cts);
9aaf880e
FE		 357
358 hdmi_set_clock_regenerator_n(hdmi, clk_n);
359 hdmi_regenerate_cts(hdmi, clk_cts);
360}
361
b21f4b65 362static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 363{
40678388 364 hdmi_set_clk_regenerator(hdmi, 74250000);
9aaf880e
FE		 365}
366
b21f4b65 367static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 368{
40678388 369 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
9aaf880e
FE		 370}
371
372/*
373 * this submodule is responsible for the video data synchronization.
374 * for example, for RGB 4:4:4 input, the data map is defined as
375 * pin{47~40} <==> R[7:0]
376 * pin{31~24} <==> G[7:0]
377 * pin{15~8} <==> B[7:0]
378 */
b21f4b65 379static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 380{
381 int color_format = 0;
382 u8 val;
383
384 if (hdmi->hdmi_data.enc_in_format == RGB) {
385 if (hdmi->hdmi_data.enc_color_depth == 8)
386 color_format = 0x01;
387 else if (hdmi->hdmi_data.enc_color_depth == 10)
388 color_format = 0x03;
389 else if (hdmi->hdmi_data.enc_color_depth == 12)
390 color_format = 0x05;
391 else if (hdmi->hdmi_data.enc_color_depth == 16)
392 color_format = 0x07;
393 else
394 return;
395 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
396 if (hdmi->hdmi_data.enc_color_depth == 8)
397 color_format = 0x09;
398 else if (hdmi->hdmi_data.enc_color_depth == 10)
399 color_format = 0x0B;
400 else if (hdmi->hdmi_data.enc_color_depth == 12)
401 color_format = 0x0D;
402 else if (hdmi->hdmi_data.enc_color_depth == 16)
403 color_format = 0x0F;
404 else
405 return;
406 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
407 if (hdmi->hdmi_data.enc_color_depth == 8)
408 color_format = 0x16;
409 else if (hdmi->hdmi_data.enc_color_depth == 10)
410 color_format = 0x14;
411 else if (hdmi->hdmi_data.enc_color_depth == 12)
412 color_format = 0x12;
413 else
414 return;
415 }
416
417 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
418 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
419 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
420 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
421
422 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
423 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
424 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
425 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
426 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
427 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
428 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
429 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
430 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
431 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
432 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
433}
434
b21f4b65 435static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 436{
ba92b225 437 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
9aaf880e
FE		 438}
439
b21f4b65 440static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 441{
ba92b225
FE		 442 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
443 return 0;
444 if (hdmi->hdmi_data.enc_in_format == RGB ||
445 hdmi->hdmi_data.enc_in_format == YCBCR444)
446 return 1;
447 return 0;
9aaf880e
FE		 448}
449
b21f4b65 450static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 451{
ba92b225
FE		 452 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
453 return 0;
454 if (hdmi->hdmi_data.enc_out_format == RGB ||
455 hdmi->hdmi_data.enc_out_format == YCBCR444)
456 return 1;
457 return 0;
9aaf880e
FE		 458}
459
b21f4b65 460static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 461{
462 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 463 unsigned i;
9aaf880e 464 u32 csc_scale = 1;
9aaf880e
FE		 465
466 if (is_color_space_conversion(hdmi)) {
467 if (hdmi->hdmi_data.enc_out_format == RGB) {
256a38b0
GK		 468 if (hdmi->hdmi_data.colorimetry ==
469 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 470 csc_coeff = &csc_coeff_rgb_out_eitu601;
471 else
472 csc_coeff = &csc_coeff_rgb_out_eitu709;
473 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
256a38b0
GK		 474 if (hdmi->hdmi_data.colorimetry ==
475 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 476 csc_coeff = &csc_coeff_rgb_in_eitu601;
477 else
478 csc_coeff = &csc_coeff_rgb_in_eitu709;
479 csc_scale = 0;
480 }
481 }
482
c082f9d7
RK		 483 /* The CSC registers are sequential, alternating MSB then LSB */
484 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
485 u16 coeff_a = (*csc_coeff)[0][i];
486 u16 coeff_b = (*csc_coeff)[1][i];
487 u16 coeff_c = (*csc_coeff)[2][i];
488
b5878339 489 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 490 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
491 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
492 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 493 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 494 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
495 }
9aaf880e 496
812bc615
RK		 497 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
498 HDMI_CSC_SCALE);
9aaf880e
FE		 499}
500
b21f4b65 501static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 502{
503 int color_depth = 0;
504 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
505 int decimation = 0;
9aaf880e
FE		 506
507 /* YCC422 interpolation to 444 mode */
508 if (is_color_space_interpolation(hdmi))
509 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
510 else if (is_color_space_decimation(hdmi))
511 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
512
513 if (hdmi->hdmi_data.enc_color_depth == 8)
514 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
515 else if (hdmi->hdmi_data.enc_color_depth == 10)
516 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
517 else if (hdmi->hdmi_data.enc_color_depth == 12)
518 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
519 else if (hdmi->hdmi_data.enc_color_depth == 16)
520 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
521 else
522 return;
523
524 /* Configure the CSC registers */
525 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 526 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
527 HDMI_CSC_SCALE);
9aaf880e 528
b21f4b65 529 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 530}
531
532/*
533 * HDMI video packetizer is used to packetize the data.
534 * for example, if input is YCC422 mode or repeater is used,
535 * data should be repacked this module can be bypassed.
536 */
b21f4b65 537static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 538{
539 unsigned int color_depth = 0;
540 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
541 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
542 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 543 u8 val, vp_conf;
9aaf880e 544
b5878339
AY		 545 if (hdmi_data->enc_out_format == RGB ||
546 hdmi_data->enc_out_format == YCBCR444) {
547 if (!hdmi_data->enc_color_depth) {
9aaf880e 548 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 549 } else if (hdmi_data->enc_color_depth == 8) {
9aaf880e
FE		 550 color_depth = 4;
551 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 552 } else if (hdmi_data->enc_color_depth == 10) {
9aaf880e 553 color_depth = 5;
b5878339 554 } else if (hdmi_data->enc_color_depth == 12) {
9aaf880e 555 color_depth = 6;
b5878339 556 } else if (hdmi_data->enc_color_depth == 16) {
9aaf880e 557 color_depth = 7;
b5878339 558 } else {
9aaf880e 559 return;
b5878339 560 }
9aaf880e
FE		 561 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
562 if (!hdmi_data->enc_color_depth ||
563 hdmi_data->enc_color_depth == 8)
564 remap_size = HDMI_VP_REMAP_YCC422_16bit;
565 else if (hdmi_data->enc_color_depth == 10)
566 remap_size = HDMI_VP_REMAP_YCC422_20bit;
567 else if (hdmi_data->enc_color_depth == 12)
568 remap_size = HDMI_VP_REMAP_YCC422_24bit;
569 else
570 return;
571 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 572 } else {
9aaf880e 573 return;
b5878339 574 }
9aaf880e
FE		 575
576 /* set the packetizer registers */
577 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
578 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
579 ((hdmi_data->pix_repet_factor <<
580 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
581 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
582 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
583
812bc615
RK		 584 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
585 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 586
587 /* Data from pixel repeater block */
588 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 589 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
590 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 591 } else { /* data from packetizer block */
bebdf664
RK		 592 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
593 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 594 }
595
bebdf664
RK		 596 hdmi_modb(hdmi, vp_conf,
597 HDMI_VP_CONF_PR_EN_MASK |
598 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
599
812bc615
RK		 600 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
601 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 602
603 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
604
605 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 606 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
607 HDMI_VP_CONF_PP_EN_ENABLE |
608 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 609 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 610 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
611 HDMI_VP_CONF_PP_EN_DISABLE |
612 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 613 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 614 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
615 HDMI_VP_CONF_PP_EN_DISABLE |
616 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 617 } else {
618 return;
619 }
620
bebdf664
RK		 621 hdmi_modb(hdmi, vp_conf,
622 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
623 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
624
812bc615
RK		 625 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
626 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
627 HDMI_VP_STUFF_PP_STUFFING_MASK |
628 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 629
812bc615
RK		 630 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
631 HDMI_VP_CONF);
9aaf880e
FE		 632}
633
b21f4b65 634static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 635 unsigned char bit)
9aaf880e 636{
812bc615
RK		 637 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
638 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 639}
640
b21f4b65 641static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
b5878339 642 unsigned char bit)
9aaf880e 643{
812bc615
RK		 644 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
645 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 646}
647
b21f4b65 648static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
b5878339 649 unsigned char bit)
9aaf880e 650{
812bc615
RK		 651 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
652 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 653}
654
b21f4b65 655static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
b5878339 656 unsigned char bit)
9aaf880e
FE		 657{
658 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
659}
660
b21f4b65 661static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
b5878339 662 unsigned char bit)
9aaf880e
FE		 663{
664 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
665}
666
b21f4b65 667static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 668{
a4d3b8b0
AY		 669 u32 val;
670
671 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 672 if (msec-- == 0)
673 return false;
0e6bcf3a 674 udelay(1000);
9aaf880e 675 }
a4d3b8b0
AY		 676 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
677
9aaf880e
FE		 678 return true;
679}
680
b21f4b65 681static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 682 unsigned char addr)
9aaf880e
FE		 683{
684 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
685 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
686 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 687 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 688 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 689 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 690 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 691 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 692 hdmi_phy_wait_i2c_done(hdmi, 1000);
693}
694
b21f4b65 695static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 696 unsigned char addr)
9aaf880e
FE		 697{
698 __hdmi_phy_i2c_write(hdmi, data, addr);
699 return 0;
700}
701
b21f4b65 702static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 703{
704 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
705 HDMI_PHY_CONF0_PDZ_OFFSET,
706 HDMI_PHY_CONF0_PDZ_MASK);
707}
708
b21f4b65 709static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 710{
711 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
712 HDMI_PHY_CONF0_ENTMDS_OFFSET,
713 HDMI_PHY_CONF0_ENTMDS_MASK);
714}
715
d346c14e
AY		 716static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
717{
718 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
719 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
720 HDMI_PHY_CONF0_SPARECTRL_MASK);
721}
722
b21f4b65 723static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 724{
725 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
726 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
727 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
728}
729
b21f4b65 730static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 731{
732 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
733 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
734 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
735}
736
b21f4b65 737static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 738{
739 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
740 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
741 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
742}
743
b21f4b65 744static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 745{
746 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
747 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
748 HDMI_PHY_CONF0_SELDIPIF_MASK);
749}
750
b21f4b65 751static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
9aaf880e
FE		 752 unsigned char res, int cscon)
753{
3e46f152 754 unsigned res_idx, i;
9aaf880e 755 u8 val, msec;
b21f4b65
AY		 756 const struct dw_hdmi_mpll_config *mpll_config =
757 hdmi->plat_data->mpll_cfg;
758 const struct dw_hdmi_curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
759 const struct dw_hdmi_sym_term *sym_term = hdmi->plat_data->sym_term;
9aaf880e 760
9aaf880e
FE		 761 if (prep)
762 return -EINVAL;
3e46f152
RK		 763
764 switch (res) {
765 case 0: /* color resolution 0 is 8 bit colour depth */
766 case 8:
b21f4b65 767 res_idx = DW_HDMI_RES_8;
3e46f152
RK		 768 break;
769 case 10:
b21f4b65 770 res_idx = DW_HDMI_RES_10;
3e46f152
RK		 771 break;
772 case 12:
b21f4b65 773 res_idx = DW_HDMI_RES_12;
3e46f152
RK		 774 break;
775 default:
9aaf880e 776 return -EINVAL;
3e46f152 777 }
9aaf880e
FE		 778
779 /* Enable csc path */
780 if (cscon)
781 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
782 else
783 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
784
785 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
786
787 /* gen2 tx power off */
b21f4b65 788 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
9aaf880e
FE		 789
790 /* gen2 pddq */
b21f4b65 791 dw_hdmi_phy_gen2_pddq(hdmi, 1);
9aaf880e
FE		 792
793 /* PHY reset */
794 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
795 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
796
797 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
798
799 hdmi_phy_test_clear(hdmi, 1);
800 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
b5878339 801 HDMI_PHY_I2CM_SLAVE_ADDR);
9aaf880e
FE		 802 hdmi_phy_test_clear(hdmi, 0);
803
3e46f152 804 /* PLL/MPLL Cfg - always match on final entry */
aaa757a0 805 for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
3e46f152
RK		 806 if (hdmi->hdmi_data.video_mode.mpixelclock <=
807 mpll_config[i].mpixelclock)
9aaf880e 808 break;
9aaf880e 809
3e46f152
RK		 810 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
811 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
812
aaa757a0 813 for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
3e46f152
RK		 814 if (hdmi->hdmi_data.video_mode.mpixelclock <=
815 curr_ctrl[i].mpixelclock)
9aaf880e 816 break;
3e46f152 817
aaa757a0 818 if (curr_ctrl[i].mpixelclock == (~0UL)) {
b5878339
AY		 819 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
820 hdmi->hdmi_data.video_mode.mpixelclock);
9aaf880e
FE		 821 return -EINVAL;
822 }
823
3e46f152
RK		 824 /* CURRCTRL */
825 hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
826
9aaf880e
FE		 827 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
828 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
aaa757a0
AY		 829
830 for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
831 if (hdmi->hdmi_data.video_mode.mpixelclock <=
832 sym_term[i].mpixelclock)
833 break;
834
9aaf880e 835 /* RESISTANCE TERM 133Ohm Cfg */
aaa757a0 836 hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
9aaf880e 837 /* PREEMP Cgf 0.00 */
aaa757a0
AY		 838 hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
839
9aaf880e
FE		 840 /* TX/CK LVL 10 */
841 hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
842 /* REMOVE CLK TERM */
843 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
844
b21f4b65 845 dw_hdmi_phy_enable_power(hdmi, 1);
9aaf880e
FE		 846
847 /* toggle TMDS enable */
b21f4b65
AY		 848 dw_hdmi_phy_enable_tmds(hdmi, 0);
849 dw_hdmi_phy_enable_tmds(hdmi, 1);
9aaf880e
FE		 850
851 /* gen2 tx power on */
b21f4b65
AY		 852 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
853 dw_hdmi_phy_gen2_pddq(hdmi, 0);
9aaf880e 854
12b9f204
AY		 855 if (hdmi->dev_type == RK3288_HDMI)
856 dw_hdmi_phy_enable_spare(hdmi, 1);
857
9aaf880e
FE		 858 /*Wait for PHY PLL lock */
859 msec = 5;
860 do {
861 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
862 if (!val)
863 break;
864
865 if (msec == 0) {
866 dev_err(hdmi->dev, "PHY PLL not locked\n");
867 return -ETIMEDOUT;
868 }
869
870 udelay(1000);
871 msec--;
872 } while (1);
873
874 return 0;
875}
876
b21f4b65 877static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
9aaf880e
FE		 878{
879 int i, ret;
880 bool cscon = false;
881
882 /*check csc whether needed activated in HDMI mode */
883 cscon = (is_color_space_conversion(hdmi) &&
884 !hdmi->hdmi_data.video_mode.mdvi);
885
886 /* HDMI Phy spec says to do the phy initialization sequence twice */
887 for (i = 0; i < 2; i++) {
b21f4b65
AY		 888 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
889 dw_hdmi_phy_sel_interface_control(hdmi, 0);
890 dw_hdmi_phy_enable_tmds(hdmi, 0);
891 dw_hdmi_phy_enable_power(hdmi, 0);
9aaf880e
FE		 892
893 /* Enable CSC */
894 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
895 if (ret)
896 return ret;
897 }
898
899 hdmi->phy_enabled = true;
900 return 0;
901}
902
b21f4b65 903static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 904{
812bc615 905 u8 de;
9aaf880e
FE		 906
907 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
908 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
909 else
910 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
911
912 /* disable rx detect */
812bc615
RK		 913 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
914 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 915
812bc615 916 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 917
812bc615
RK		 918 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
919 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 920}
921
b21f4b65 922static void hdmi_config_AVI(struct dw_hdmi *hdmi)
9aaf880e
FE		 923{
924 u8 val, pix_fmt, under_scan;
925 u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
926 bool aspect_16_9;
927
928 aspect_16_9 = false; /* FIXME */
929
930 /* AVI Data Byte 1 */
931 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
932 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
933 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
934 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
935 else
936 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
937
938 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
939
940 /*
941 * Active format identification data is present in the AVI InfoFrame.
942 * Under scan info, no bar data
943 */
944 val = pix_fmt | under_scan |
945 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
946 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
947
948 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
949
950 /* AVI Data Byte 2 -Set the Aspect Ratio */
951 if (aspect_16_9) {
952 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
953 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
954 } else {
955 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
956 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
957 }
958
959 /* Set up colorimetry */
960 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
961 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
5a819ed6 962 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 963 ext_colorimetry =
964 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
5a819ed6 965 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
9aaf880e
FE		 966 ext_colorimetry =
967 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
968 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
5a819ed6 969 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
9aaf880e 970 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
5a819ed6 971 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
9aaf880e
FE		 972 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
973 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
974 } else { /* Carries no data */
975 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
976 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
977 }
978
979 val = colorimetry | coded_ratio | act_ratio;
980 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
981
982 /* AVI Data Byte 3 */
983 val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
984 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
985 HDMI_FC_AVICONF2_SCALING_NONE;
986 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
987
988 /* AVI Data Byte 4 */
989 hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
990
991 /* AVI Data Byte 5- set up input and output pixel repetition */
992 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
993 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
994 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
995 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
996 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
997 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
998 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
999
1000 /* IT Content and quantization range = don't care */
1001 val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1002 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1003 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1004
1005 /* AVI Data Bytes 6-13 */
1006 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1007 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1008 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1009 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1010 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1011 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1012 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1013 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1014}
1015
b21f4b65 1016static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1017 const struct drm_display_mode *mode)
1018{
1019 u8 inv_val;
1020 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1021 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1022
1023 vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1024 vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1025 vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1026 vmode->mpixelclock = mode->clock * 1000;
1027
1028 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1029
1030 /* Set up HDMI_FC_INVIDCONF */
1031 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1032 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1033 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1034
1035 inv_val |= (vmode->mvsyncpolarity ?
1036 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1037 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1038
1039 inv_val |= (vmode->mhsyncpolarity ?
1040 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1041 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1042
1043 inv_val |= (vmode->mdataenablepolarity ?
1044 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1045 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1046
1047 if (hdmi->vic == 39)
1048 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1049 else
1050 inv_val |= (vmode->minterlaced ?
1051 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1052 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1053
1054 inv_val |= (vmode->minterlaced ?
1055 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1056 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1057
1058 inv_val |= (vmode->mdvi ?
1059 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1060 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1061
1062 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1063
1064 /* Set up horizontal active pixel width */
1065 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1066 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1067
1068 /* Set up vertical active lines */
1069 hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1070 hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1071
1072 /* Set up horizontal blanking pixel region width */
1073 hblank = mode->htotal - mode->hdisplay;
1074 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1075 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1076
1077 /* Set up vertical blanking pixel region width */
1078 vblank = mode->vtotal - mode->vdisplay;
1079 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1080
1081 /* Set up HSYNC active edge delay width (in pixel clks) */
1082 h_de_hs = mode->hsync_start - mode->hdisplay;
1083 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1084 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1085
1086 /* Set up VSYNC active edge delay (in lines) */
1087 v_de_vs = mode->vsync_start - mode->vdisplay;
1088 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1089
1090 /* Set up HSYNC active pulse width (in pixel clks) */
1091 hsync_len = mode->hsync_end - mode->hsync_start;
1092 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1093 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1094
1095 /* Set up VSYNC active edge delay (in lines) */
1096 vsync_len = mode->vsync_end - mode->vsync_start;
1097 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1098}
1099
b21f4b65 1100static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
9aaf880e
FE		 1101{
1102 if (!hdmi->phy_enabled)
1103 return;
1104
b21f4b65
AY		 1105 dw_hdmi_phy_enable_tmds(hdmi, 0);
1106 dw_hdmi_phy_enable_power(hdmi, 0);
9aaf880e
FE		 1107
1108 hdmi->phy_enabled = false;
1109}
1110
1111/* HDMI Initialization Step B.4 */
b21f4b65 1112static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e
FE		 1113{
1114 u8 clkdis;
1115
1116 /* control period minimum duration */
1117 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1118 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1119 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1120
1121 /* Set to fill TMDS data channels */
1122 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1123 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1124 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1125
1126 /* Enable pixel clock and tmds data path */
1127 clkdis = 0x7F;
1128 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1129 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1130
1131 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1132 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1133
1134 /* Enable csc path */
1135 if (is_color_space_conversion(hdmi)) {
1136 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1137 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1138 }
1139}
1140
b21f4b65 1141static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
9aaf880e 1142{
812bc615 1143 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
9aaf880e
FE		 1144}
1145
1146/* Workaround to clear the overflow condition */
b21f4b65 1147static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e
FE		 1148{
1149 int count;
1150 u8 val;
1151
1152 /* TMDS software reset */
1153 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1154
1155 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1156 if (hdmi->dev_type == IMX6DL_HDMI) {
1157 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1158 return;
1159 }
1160
1161 for (count = 0; count < 4; count++)
1162 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1163}
1164
b21f4b65 1165static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1166{
1167 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1168 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1169}
1170
b21f4b65 1171static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1172{
1173 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1174 HDMI_IH_MUTE_FC_STAT2);
1175}
1176
b21f4b65 1177static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1178{
1179 int ret;
1180
1181 hdmi_disable_overflow_interrupts(hdmi);
1182
1183 hdmi->vic = drm_match_cea_mode(mode);
1184
1185 if (!hdmi->vic) {
1186 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1187 hdmi->hdmi_data.video_mode.mdvi = true;
1188 } else {
1189 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1190 hdmi->hdmi_data.video_mode.mdvi = false;
1191 }
1192
1193 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1194 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1195 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1196 (hdmi->vic == 17) || (hdmi->vic == 18))
5a819ed6 1197 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
9aaf880e 1198 else
5a819ed6 1199 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
9aaf880e
FE		 1200
1201 if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
b5878339
AY		 1202 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1203 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1204 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1205 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1206 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1207 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1208 (hdmi->vic == 37) || (hdmi->vic == 38))
9aaf880e
FE		 1209 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1210 else
1211 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1212
1213 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1214
1215 /* TODO: Get input format from IPU (via FB driver interface) */
1216 hdmi->hdmi_data.enc_in_format = RGB;
1217
1218 hdmi->hdmi_data.enc_out_format = RGB;
1219
1220 hdmi->hdmi_data.enc_color_depth = 8;
1221 hdmi->hdmi_data.pix_repet_factor = 0;
1222 hdmi->hdmi_data.hdcp_enable = 0;
1223 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1224
1225 /* HDMI Initialization Step B.1 */
1226 hdmi_av_composer(hdmi, mode);
1227
1228 /* HDMI Initializateion Step B.2 */
b21f4b65 1229 ret = dw_hdmi_phy_init(hdmi);
9aaf880e
FE		 1230 if (ret)
1231 return ret;
1232
1233 /* HDMI Initialization Step B.3 */
b21f4b65 1234 dw_hdmi_enable_video_path(hdmi);
9aaf880e
FE		 1235
1236 /* not for DVI mode */
b5878339 1237 if (hdmi->hdmi_data.video_mode.mdvi) {
9aaf880e 1238 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
b5878339 1239 } else {
9aaf880e
FE		 1240 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1241
1242 /* HDMI Initialization Step E - Configure audio */
1243 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1244 hdmi_enable_audio_clk(hdmi);
1245
1246 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1247 hdmi_config_AVI(hdmi);
1248 }
1249
1250 hdmi_video_packetize(hdmi);
1251 hdmi_video_csc(hdmi);
1252 hdmi_video_sample(hdmi);
1253 hdmi_tx_hdcp_config(hdmi);
1254
b21f4b65 1255 dw_hdmi_clear_overflow(hdmi);
9aaf880e
FE		 1256 if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1257 hdmi_enable_overflow_interrupts(hdmi);
1258
1259 return 0;
1260}
1261
1262/* Wait until we are registered to enable interrupts */
b21f4b65 1263static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
9aaf880e
FE		 1264{
1265 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1266 HDMI_PHY_I2CM_INT_ADDR);
1267
1268 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1269 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1270 HDMI_PHY_I2CM_CTLINT_ADDR);
1271
1272 /* enable cable hot plug irq */
1273 hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1274
1275 /* Clear Hotplug interrupts */
1276 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1277
9aaf880e
FE		 1278 return 0;
1279}
1280
b21f4b65 1281static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 1282{
1283 u8 ih_mute;
1284
1285 /*
1286 * Boot up defaults are:
1287 * HDMI_IH_MUTE = 0x03 (disabled)
1288 * HDMI_IH_MUTE_* = 0x00 (enabled)
1289 *
1290 * Disable top level interrupt bits in HDMI block
1291 */
1292 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1293 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1294 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1295
1296 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1297
1298 /* by default mask all interrupts */
1299 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1300 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1301 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1302 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1303 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1304 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1305 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1306 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1307 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1308 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1309 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1310 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1311 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1312 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1313 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1314
1315 /* Disable interrupts in the IH_MUTE_* registers */
1316 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1317 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1318 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1319 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1320 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1321 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1322 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1323 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1324 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1325 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1326
1327 /* Enable top level interrupt bits in HDMI block */
1328 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1329 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1330 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1331}
1332
b21f4b65 1333static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 1334{
b21f4b65 1335 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 1336}
1337
b21f4b65 1338static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 1339{
b21f4b65 1340 dw_hdmi_phy_disable(hdmi);
9aaf880e
FE		 1341}
1342
b21f4b65 1343static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
eb10d635
SL		 1344 struct drm_display_mode *orig_mode,
1345 struct drm_display_mode *mode)
3d1b35a3 1346{
b21f4b65 1347 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1348
b21f4b65 1349 dw_hdmi_setup(hdmi, mode);
3d1b35a3
AY		 1350
1351 /* Store the display mode for plugin/DKMS poweron events */
1352 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1353}
1354
b21f4b65
AY		 1355static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1356 const struct drm_display_mode *mode,
1357 struct drm_display_mode *adjusted_mode)
3d1b35a3
AY		 1358{
1359 return true;
1360}
1361
b21f4b65 1362static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
3d1b35a3 1363{
b21f4b65 1364 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1365
b21f4b65 1366 dw_hdmi_poweroff(hdmi);
3d1b35a3
AY		 1367}
1368
b21f4b65 1369static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
3d1b35a3 1370{
b21f4b65 1371 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1372
b21f4b65 1373 dw_hdmi_poweron(hdmi);
3d1b35a3
AY		 1374}
1375
b21f4b65 1376static void dw_hdmi_bridge_destroy(struct drm_bridge *bridge)
3d1b35a3
AY		 1377{
1378 drm_bridge_cleanup(bridge);
1379 kfree(bridge);
1380}
1381
b21f4b65 1382static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
3d1b35a3
AY		 1383{
1384 /* do nothing */
1385}
1386
b21f4b65
AY		 1387static enum drm_connector_status
1388dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 1389{
b21f4b65 1390 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 1391 connector);
98dbeada
RK		 1392
1393 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1394 connector_status_connected : connector_status_disconnected;
9aaf880e
FE		 1395}
1396
b21f4b65 1397static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 1398{
b21f4b65 1399 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1400 connector);
1401 struct edid *edid;
1402 int ret;
1403
1404 if (!hdmi->ddc)
1405 return 0;
1406
1407 edid = drm_get_edid(connector, hdmi->ddc);
1408 if (edid) {
1409 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1410 edid->width_cm, edid->height_cm);
1411
1412 drm_mode_connector_update_edid_property(connector, edid);
1413 ret = drm_add_edid_modes(connector, edid);
1414 kfree(edid);
1415 } else {
1416 dev_dbg(hdmi->dev, "failed to get edid\n");
1417 }
1418
1419 return 0;
1420}
1421
632d035b
AY		 1422static enum drm_mode_status
1423dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1424 struct drm_display_mode *mode)
1425{
1426 struct dw_hdmi *hdmi = container_of(connector,
1427 struct dw_hdmi, connector);
1428 enum drm_mode_status mode_status = MODE_OK;
1429
1430 if (hdmi->plat_data->mode_valid)
1431 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1432
1433 return mode_status;
1434}
1435
b21f4b65 1436static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
9aaf880e
FE		 1437 *connector)
1438{
b21f4b65 1439 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1440 connector);
1441
3d1b35a3 1442 return hdmi->encoder;
9aaf880e
FE		 1443}
1444
b21f4b65 1445static void dw_hdmi_connector_destroy(struct drm_connector *connector)
9aaf880e 1446{
3d1b35a3
AY		 1447 drm_connector_unregister(connector);
1448 drm_connector_cleanup(connector);
9aaf880e
FE		 1449}
1450
b21f4b65 1451static struct drm_connector_funcs dw_hdmi_connector_funcs = {
9aaf880e
FE		 1452 .dpms = drm_helper_connector_dpms,
1453 .fill_modes = drm_helper_probe_single_connector_modes,
b21f4b65
AY		 1454 .detect = dw_hdmi_connector_detect,
1455 .destroy = dw_hdmi_connector_destroy,
9aaf880e
FE		 1456};
1457
b21f4b65
AY		 1458static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1459 .get_modes = dw_hdmi_connector_get_modes,
632d035b 1460 .mode_valid = dw_hdmi_connector_mode_valid,
b21f4b65 1461 .best_encoder = dw_hdmi_connector_best_encoder,
9aaf880e
FE		 1462};
1463
b21f4b65
AY		 1464struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1465 .enable = dw_hdmi_bridge_enable,
1466 .disable = dw_hdmi_bridge_disable,
1467 .pre_enable = dw_hdmi_bridge_nop,
1468 .post_disable = dw_hdmi_bridge_nop,
1469 .mode_set = dw_hdmi_bridge_mode_set,
1470 .mode_fixup = dw_hdmi_bridge_mode_fixup,
1471 .destroy = dw_hdmi_bridge_destroy,
3d1b35a3
AY		 1472};
1473
b21f4b65 1474static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 1475{
b21f4b65 1476 struct dw_hdmi *hdmi = dev_id;
d94905e0
RK		 1477 u8 intr_stat;
1478
1479 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1480 if (intr_stat)
1481 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1482
1483 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1484}
1485
b21f4b65 1486static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 1487{
b21f4b65 1488 struct dw_hdmi *hdmi = dev_id;
9aaf880e
FE		 1489 u8 intr_stat;
1490 u8 phy_int_pol;
9aaf880e
FE		 1491
1492 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1493
1494 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1495
1496 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1497 if (phy_int_pol & HDMI_PHY_HPD) {
1498 dev_dbg(hdmi->dev, "EVENT=plugin\n");
1499
812bc615 1500 hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
9aaf880e 1501
b21f4b65 1502 dw_hdmi_poweron(hdmi);
9aaf880e
FE		 1503 } else {
1504 dev_dbg(hdmi->dev, "EVENT=plugout\n");
1505
256a38b0 1506 hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
b5878339 1507 HDMI_PHY_POL0);
9aaf880e 1508
b21f4b65 1509 dw_hdmi_poweroff(hdmi);
9aaf880e 1510 }
d94905e0 1511 drm_helper_hpd_irq_event(hdmi->connector.dev);
9aaf880e
FE		 1512 }
1513
1514 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
d94905e0 1515 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 1516
1517 return IRQ_HANDLED;
1518}
1519
b21f4b65 1520static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
9aaf880e 1521{
3d1b35a3
AY		 1522 struct drm_encoder *encoder = hdmi->encoder;
1523 struct drm_bridge *bridge;
9aaf880e
FE		 1524 int ret;
1525
3d1b35a3
AY		 1526 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1527 if (!bridge) {
1528 DRM_ERROR("Failed to allocate drm bridge\n");
1529 return -ENOMEM;
1530 }
9aaf880e 1531
3d1b35a3
AY		 1532 hdmi->bridge = bridge;
1533 bridge->driver_private = hdmi;
1534
b21f4b65 1535 ret = drm_bridge_init(drm, bridge, &dw_hdmi_bridge_funcs);
3d1b35a3
AY		 1536 if (ret) {
1537 DRM_ERROR("Failed to initialize bridge with drm\n");
1538 return -EINVAL;
1539 }
9aaf880e 1540
3d1b35a3
AY		 1541 encoder->bridge = bridge;
1542 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
9aaf880e
FE		 1543
1544 drm_connector_helper_add(&hdmi->connector,
b21f4b65
AY		 1545 &dw_hdmi_connector_helper_funcs);
1546 drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1b3f7675 1547 DRM_MODE_CONNECTOR_HDMIA);
9aaf880e 1548
3d1b35a3 1549 hdmi->connector.encoder = encoder;
9aaf880e 1550
3d1b35a3 1551 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
9aaf880e
FE		 1552
1553 return 0;
1554}
1555
b21f4b65 1556int dw_hdmi_bind(struct device *dev, struct device *master,
3d1b35a3
AY		 1557 void *data, struct drm_encoder *encoder,
1558 struct resource *iores, int irq,
1559 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 1560{
1b3f7675 1561 struct drm_device *drm = data;
17b5001b 1562 struct device_node *np = dev->of_node;
9aaf880e 1563 struct device_node *ddc_node;
b21f4b65 1564 struct dw_hdmi *hdmi;
3d1b35a3 1565 int ret;
0cd9d142 1566 u32 val = 1;
9aaf880e 1567
17b5001b 1568 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e
FE		 1569 if (!hdmi)
1570 return -ENOMEM;
1571
3d1b35a3 1572 hdmi->plat_data = plat_data;
17b5001b 1573 hdmi->dev = dev;
3d1b35a3 1574 hdmi->dev_type = plat_data->dev_type;
40678388
RK		 1575 hdmi->sample_rate = 48000;
1576 hdmi->ratio = 100;
3d1b35a3 1577 hdmi->encoder = encoder;
9aaf880e 1578
0cd9d142
AY		 1579 of_property_read_u32(np, "reg-io-width", &val);
1580
1581 switch (val) {
1582 case 4:
1583 hdmi->write = dw_hdmi_writel;
1584 hdmi->read = dw_hdmi_readl;
1585 break;
1586 case 1:
1587 hdmi->write = dw_hdmi_writeb;
1588 hdmi->read = dw_hdmi_readb;
1589 break;
1590 default:
1591 dev_err(dev, "reg-io-width must be 1 or 4\n");
1592 return -EINVAL;
1593 }
1594
b5d45901 1595 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e
FE		 1596 if (ddc_node) {
1597 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 1598 of_node_put(ddc_node);
1599 if (!hdmi->ddc) {
9aaf880e 1600 dev_dbg(hdmi->dev, "failed to read ddc node\n");
c2c38488
AY		 1601 return -EPROBE_DEFER;
1602 }
9aaf880e 1603
9aaf880e
FE		 1604 } else {
1605 dev_dbg(hdmi->dev, "no ddc property found\n");
1606 }
1607
17b5001b 1608 hdmi->regs = devm_ioremap_resource(dev, iores);
9aaf880e
FE		 1609 if (IS_ERR(hdmi->regs))
1610 return PTR_ERR(hdmi->regs);
1611
9aaf880e
FE		 1612 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1613 if (IS_ERR(hdmi->isfr_clk)) {
1614 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 1615 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9aaf880e
FE		 1616 return ret;
1617 }
1618
1619 ret = clk_prepare_enable(hdmi->isfr_clk);
1620 if (ret) {
b5878339 1621 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9aaf880e
FE		 1622 return ret;
1623 }
1624
1625 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1626 if (IS_ERR(hdmi->iahb_clk)) {
1627 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 1628 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 1629 goto err_isfr;
1630 }
1631
1632 ret = clk_prepare_enable(hdmi->iahb_clk);
1633 if (ret) {
b5878339 1634 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 1635 goto err_isfr;
1636 }
1637
1638 /* Product and revision IDs */
17b5001b 1639 dev_info(dev,
b5878339
AY		 1640 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1641 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1642 hdmi_readb(hdmi, HDMI_REVISION_ID),
1643 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1644 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
9aaf880e
FE		 1645
1646 initialize_hdmi_ih_mutes(hdmi);
1647
639a202c
PZ		 1648 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1649 dw_hdmi_irq, IRQF_SHARED,
1650 dev_name(dev), hdmi);
1651 if (ret)
1652 return ret;
1653
9aaf880e
FE		 1654 /*
1655 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1656 * N and cts values before enabling phy
1657 */
1658 hdmi_init_clk_regenerator(hdmi);
1659
1660 /*
1661 * Configure registers related to HDMI interrupt
1662 * generation before registering IRQ.
1663 */
1664 hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1665
1666 /* Clear Hotplug interrupts */
1667 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1668
b21f4b65 1669 ret = dw_hdmi_fb_registered(hdmi);
9aaf880e
FE		 1670 if (ret)
1671 goto err_iahb;
1672
b21f4b65 1673 ret = dw_hdmi_register(drm, hdmi);
9aaf880e
FE		 1674 if (ret)
1675 goto err_iahb;
1676
d94905e0
RK		 1677 /* Unmute interrupts */
1678 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
9aaf880e 1679
17b5001b 1680 dev_set_drvdata(dev, hdmi);
9aaf880e
FE		 1681
1682 return 0;
1683
1684err_iahb:
1685 clk_disable_unprepare(hdmi->iahb_clk);
1686err_isfr:
1687 clk_disable_unprepare(hdmi->isfr_clk);
1688
1689 return ret;
1690}
b21f4b65 1691EXPORT_SYMBOL_GPL(dw_hdmi_bind);
9aaf880e 1692
b21f4b65 1693void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
9aaf880e 1694{
b21f4b65 1695 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
9aaf880e 1696
d94905e0
RK		 1697 /* Disable all interrupts */
1698 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1699
1b3f7675 1700 hdmi->connector.funcs->destroy(&hdmi->connector);
3d1b35a3 1701 hdmi->encoder->funcs->destroy(hdmi->encoder);
9aaf880e
FE		 1702
1703 clk_disable_unprepare(hdmi->iahb_clk);
1704 clk_disable_unprepare(hdmi->isfr_clk);
1705 i2c_put_adapter(hdmi->ddc);
17b5001b 1706}
b21f4b65 1707EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e
FE		 1708
1709MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 1710MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1711MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
b21f4b65 1712MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 1713MODULE_LICENSE("GPL");
b21f4b65 1714MODULE_ALIAS("platform:dw-hdmi");
Linux kernel - Deliverables
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