[deliverable/linux.git] / drivers / gpu / drm / cirrus / cirrus_mode.c


/*
 * Copyright 2012 Red Hat
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License version 2. See the file COPYING in the main
 * directory of this archive for more details.
 *
 * Authors: Matthew Garrett
 *          Dave Airlie
 *
 * Portions of this code derived from cirrusfb.c:
 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
 *
 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
 */
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>

#include <video/cirrus.h>

#include "cirrus_drv.h"

#define CIRRUS_LUT_SIZE 256

#define PALETTE_INDEX 0x8
#define PALETTE_DATA 0x9

/*
 * This file contains setup code for the CRTC.
 */

static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
{
	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct cirrus_device *cdev = dev->dev_private;
	int i;

	if (!crtc->enabled)
		return;

	for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
		/* VGA registers */
		WREG8(PALETTE_INDEX, i);
		WREG8(PALETTE_DATA, cirrus_crtc->lut_r[i]);
		WREG8(PALETTE_DATA, cirrus_crtc->lut_g[i]);
		WREG8(PALETTE_DATA, cirrus_crtc->lut_b[i]);
	}
}

/*
 * The DRM core requires DPMS functions, but they make little sense in our
 * case and so are just stubs
 */

static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct drm_device *dev = crtc->dev;
	struct cirrus_device *cdev = dev->dev_private;
	u8 sr01, gr0e;

	switch (mode) {
	case DRM_MODE_DPMS_ON:
		sr01 = 0x00;
		gr0e = 0x00;
		break;
	case DRM_MODE_DPMS_STANDBY:
		sr01 = 0x20;
		gr0e = 0x02;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		sr01 = 0x20;
		gr0e = 0x04;
		break;
	case DRM_MODE_DPMS_OFF:
		sr01 = 0x20;
		gr0e = 0x06;
		break;
	default:
		return;
	}

	WREG8(SEQ_INDEX, 0x1);
	sr01 |= RREG8(SEQ_DATA) & ~0x20;
	WREG_SEQ(0x1, sr01);

	WREG8(GFX_INDEX, 0xe);
	gr0e |= RREG8(GFX_DATA) & ~0x06;
	WREG_GFX(0xe, gr0e);
}

static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
{
	struct cirrus_device *cdev = crtc->dev->dev_private;
	u32 addr;
	u8 tmp;

	addr = offset >> 2;
	WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff));
	WREG_CRT(0x0d, (u8)(addr & 0xff));

	WREG8(CRT_INDEX, 0x1b);
	tmp = RREG8(CRT_DATA);
	tmp &= 0xf2;
	tmp |= (addr >> 16) & 0x01;
	tmp |= (addr >> 15) & 0x0c;
	WREG_CRT(0x1b, tmp);
	WREG8(CRT_INDEX, 0x1d);
	tmp = RREG8(CRT_DATA);
	tmp &= 0x7f;
	tmp |= (addr >> 12) & 0x80;
	WREG_CRT(0x1d, tmp);
}

/* cirrus is different - we will force move buffers out of VRAM */
static int cirrus_crtc_do_set_base(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				int x, int y, int atomic)
{
	struct cirrus_device *cdev = crtc->dev->dev_private;
	struct drm_gem_object *obj;
	struct cirrus_framebuffer *cirrus_fb;
	struct cirrus_bo *bo;
	int ret;
	u64 gpu_addr;

	/* push the previous fb to system ram */
	if (!atomic && fb) {
		cirrus_fb = to_cirrus_framebuffer(fb);
		obj = cirrus_fb->obj;
		bo = gem_to_cirrus_bo(obj);
		ret = cirrus_bo_reserve(bo, false);
		if (ret)
			return ret;
		cirrus_bo_push_sysram(bo);
		cirrus_bo_unreserve(bo);
	}

	cirrus_fb = to_cirrus_framebuffer(crtc->primary->fb);
	obj = cirrus_fb->obj;
	bo = gem_to_cirrus_bo(obj);

	ret = cirrus_bo_reserve(bo, false);
	if (ret)
		return ret;

	ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
	if (ret) {
		cirrus_bo_unreserve(bo);
		return ret;
	}

	if (&cdev->mode_info.gfbdev->gfb == cirrus_fb) {
		/* if pushing console in kmap it */
		ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
		if (ret)
			DRM_ERROR("failed to kmap fbcon\n");
	}
	cirrus_bo_unreserve(bo);

	cirrus_set_start_address(crtc, (u32)gpu_addr);
	return 0;
}

static int cirrus_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
			     struct drm_framebuffer *old_fb)
{
	return cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
}

/*
 * The meat of this driver. The core passes us a mode and we have to program
 * it. The modesetting here is the bare minimum required to satisfy the qemu
 * emulation of this hardware, and running this against a real device is
 * likely to result in an inadequately programmed mode. We've already had
 * the opportunity to modify the mode, so whatever we receive here should
 * be something that can be correctly programmed and displayed
 */
static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode,
				int x, int y, struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct cirrus_device *cdev = dev->dev_private;
	int hsyncstart, hsyncend, htotal, hdispend;
	int vtotal, vdispend;
	int tmp;
	int sr07 = 0, hdr = 0;

	htotal = mode->htotal / 8;
	hsyncend = mode->hsync_end / 8;
	hsyncstart = mode->hsync_start / 8;
	hdispend = mode->hdisplay / 8;

	vtotal = mode->vtotal;
	vdispend = mode->vdisplay;

	vdispend -= 1;
	vtotal -= 2;

	htotal -= 5;
	hdispend -= 1;
	hsyncstart += 1;
	hsyncend += 1;

	WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20);
	WREG_CRT(VGA_CRTC_H_TOTAL, htotal);
	WREG_CRT(VGA_CRTC_H_DISP, hdispend);
	WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart);
	WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend);
	WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff);
	WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff);

	tmp = 0x40;
	if ((vdispend + 1) & 512)
		tmp |= 0x20;
	WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);

	/*
	 * Overflow bits for values that don't fit in the standard registers
	 */
	tmp = 16;
	if (vtotal & 256)
		tmp |= 1;
	if (vdispend & 256)
		tmp |= 2;
	if ((vdispend + 1) & 256)
		tmp |= 8;
	if (vtotal & 512)
		tmp |= 32;
	if (vdispend & 512)
		tmp |= 64;
	WREG_CRT(VGA_CRTC_OVERFLOW, tmp);

	tmp = 0;

	/* More overflow bits */

	if ((htotal + 5) & 64)
		tmp |= 16;
	if ((htotal + 5) & 128)
		tmp |= 32;
	if (vtotal & 256)
		tmp |= 64;
	if (vtotal & 512)
		tmp |= 128;

	WREG_CRT(CL_CRT1A, tmp);

	/* Disable Hercules/CGA compatibility */
	WREG_CRT(VGA_CRTC_MODE, 0x03);

	WREG8(SEQ_INDEX, 0x7);
	sr07 = RREG8(SEQ_DATA);
	sr07 &= 0xe0;
	hdr = 0;
	switch (crtc->primary->fb->bits_per_pixel) {
	case 8:
		sr07 |= 0x11;
		break;
	case 16:
		sr07 |= 0x17;
		hdr = 0xc1;
		break;
	case 24:
		sr07 |= 0x15;
		hdr = 0xc5;
		break;
	case 32:
		sr07 |= 0x19;
		hdr = 0xc5;
		break;
	default:
		return -1;
	}

	WREG_SEQ(0x7, sr07);

	/* Program the pitch */
	tmp = crtc->primary->fb->pitches[0] / 8;
	WREG_CRT(VGA_CRTC_OFFSET, tmp);

	/* Enable extended blanking and pitch bits, and enable full memory */
	tmp = 0x22;
	tmp |= (crtc->primary->fb->pitches[0] >> 7) & 0x10;
	tmp |= (crtc->primary->fb->pitches[0] >> 6) & 0x40;
	WREG_CRT(0x1b, tmp);

	/* Enable high-colour modes */
	WREG_GFX(VGA_GFX_MODE, 0x40);

	/* And set graphics mode */
	WREG_GFX(VGA_GFX_MISC, 0x01);

	WREG_HDR(hdr);
	cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);

	/* Unblank (needed on S3 resume, vgabios doesn't do it then) */
	outb(0x20, 0x3c0);
	return 0;
}

/*
 * This is called before a mode is programmed. A typical use might be to
 * enable DPMS during the programming to avoid seeing intermediate stages,
 * but that's not relevant to us
 */
static void cirrus_crtc_prepare(struct drm_crtc *crtc)
{
}

/*
 * This is called after a mode is programmed. It should reverse anything done
 * by the prepare function
 */
static void cirrus_crtc_commit(struct drm_crtc *crtc)
{
}

/*
 * The core can pass us a set of gamma values to program. We actually only
 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
 * but it's a requirement that we provide the function
 */
static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
				 u16 *blue, uint32_t size)
{
	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	int i;

	for (i = 0; i < size; i++) {
		cirrus_crtc->lut_r[i] = red[i];
		cirrus_crtc->lut_g[i] = green[i];
		cirrus_crtc->lut_b[i] = blue[i];
	}
	cirrus_crtc_load_lut(crtc);

	return 0;
}

/* Simple cleanup function */
static void cirrus_crtc_destroy(struct drm_crtc *crtc)
{
	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);

	drm_crtc_cleanup(crtc);
	kfree(cirrus_crtc);
}

/* These provide the minimum set of functions required to handle a CRTC */
static const struct drm_crtc_funcs cirrus_crtc_funcs = {
	.gamma_set = cirrus_crtc_gamma_set,
	.set_config = drm_crtc_helper_set_config,
	.destroy = cirrus_crtc_destroy,
};

static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
	.dpms = cirrus_crtc_dpms,
	.mode_set = cirrus_crtc_mode_set,
	.mode_set_base = cirrus_crtc_mode_set_base,
	.prepare = cirrus_crtc_prepare,
	.commit = cirrus_crtc_commit,
	.load_lut = cirrus_crtc_load_lut,
};

/* CRTC setup */
static void cirrus_crtc_init(struct drm_device *dev)
{
	struct cirrus_device *cdev = dev->dev_private;
	struct cirrus_crtc *cirrus_crtc;
	int i;

	cirrus_crtc = kzalloc(sizeof(struct cirrus_crtc) +
			      (CIRRUSFB_CONN_LIMIT * sizeof(struct drm_connector *)),
			      GFP_KERNEL);

	if (cirrus_crtc == NULL)
		return;

	drm_crtc_init(dev, &cirrus_crtc->base, &cirrus_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&cirrus_crtc->base, CIRRUS_LUT_SIZE);
	cdev->mode_info.crtc = cirrus_crtc;

	for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
		cirrus_crtc->lut_r[i] = i;
		cirrus_crtc->lut_g[i] = i;
		cirrus_crtc->lut_b[i] = i;
	}

	drm_crtc_helper_add(&cirrus_crtc->base, &cirrus_helper_funcs);
}

/** Sets the color ramps on behalf of fbcon */
void cirrus_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
			      u16 blue, int regno)
{
	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);

	cirrus_crtc->lut_r[regno] = red;
	cirrus_crtc->lut_g[regno] = green;
	cirrus_crtc->lut_b[regno] = blue;
}

/** Gets the color ramps on behalf of fbcon */
void cirrus_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			      u16 *blue, int regno)
{
	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);

	*red = cirrus_crtc->lut_r[regno];
	*green = cirrus_crtc->lut_g[regno];
	*blue = cirrus_crtc->lut_b[regno];
}

static void cirrus_encoder_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
}

static void cirrus_encoder_dpms(struct drm_encoder *encoder, int state)
{
	return;
}

static void cirrus_encoder_prepare(struct drm_encoder *encoder)
{
}

static void cirrus_encoder_commit(struct drm_encoder *encoder)
{
}

static void cirrus_encoder_destroy(struct drm_encoder *encoder)
{
	struct cirrus_encoder *cirrus_encoder = to_cirrus_encoder(encoder);
	drm_encoder_cleanup(encoder);
	kfree(cirrus_encoder);
}

static const struct drm_encoder_helper_funcs cirrus_encoder_helper_funcs = {
	.dpms = cirrus_encoder_dpms,
	.mode_set = cirrus_encoder_mode_set,
	.prepare = cirrus_encoder_prepare,
	.commit = cirrus_encoder_commit,
};

static const struct drm_encoder_funcs cirrus_encoder_encoder_funcs = {
	.destroy = cirrus_encoder_destroy,
};

static struct drm_encoder *cirrus_encoder_init(struct drm_device *dev)
{
	struct drm_encoder *encoder;
	struct cirrus_encoder *cirrus_encoder;

	cirrus_encoder = kzalloc(sizeof(struct cirrus_encoder), GFP_KERNEL);
	if (!cirrus_encoder)
		return NULL;

	encoder = &cirrus_encoder->base;
	encoder->possible_crtcs = 0x1;

	drm_encoder_init(dev, encoder, &cirrus_encoder_encoder_funcs,
			 DRM_MODE_ENCODER_DAC, NULL);
	drm_encoder_helper_add(encoder, &cirrus_encoder_helper_funcs);

	return encoder;
}


static int cirrus_vga_get_modes(struct drm_connector *connector)
{
	int count;

	/* Just add a static list of modes */
	if (cirrus_bpp <= 24) {
		count = drm_add_modes_noedid(connector, 1280, 1024);
		drm_set_preferred_mode(connector, 1024, 768);
	} else {
		count = drm_add_modes_noedid(connector, 800, 600);
		drm_set_preferred_mode(connector, 800, 600);
	}
	return count;
}

static struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
						  *connector)
{
	int enc_id = connector->encoder_ids[0];
	/* pick the encoder ids */
	if (enc_id)
		return drm_encoder_find(connector->dev, enc_id);
	return NULL;
}

static enum drm_connector_status cirrus_vga_detect(struct drm_connector
						   *connector, bool force)
{
	return connector_status_connected;
}

static void cirrus_connector_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_connector_helper_funcs cirrus_vga_connector_helper_funcs = {
	.get_modes = cirrus_vga_get_modes,
	.best_encoder = cirrus_connector_best_encoder,
};

static const struct drm_connector_funcs cirrus_vga_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = cirrus_vga_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = cirrus_connector_destroy,
};

static struct drm_connector *cirrus_vga_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct cirrus_connector *cirrus_connector;

	cirrus_connector = kzalloc(sizeof(struct cirrus_connector), GFP_KERNEL);
	if (!cirrus_connector)
		return NULL;

	connector = &cirrus_connector->base;

	drm_connector_init(dev, connector,
			   &cirrus_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);

	drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);

	drm_connector_register(connector);
	return connector;
}


int cirrus_modeset_init(struct cirrus_device *cdev)
{
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	int ret;

	drm_mode_config_init(cdev->dev);
	cdev->mode_info.mode_config_initialized = true;

	cdev->dev->mode_config.max_width = CIRRUS_MAX_FB_WIDTH;
	cdev->dev->mode_config.max_height = CIRRUS_MAX_FB_HEIGHT;

	cdev->dev->mode_config.fb_base = cdev->mc.vram_base;
	cdev->dev->mode_config.preferred_depth = 24;
	/* don't prefer a shadow on virt GPU */
	cdev->dev->mode_config.prefer_shadow = 0;

	cirrus_crtc_init(cdev->dev);

	encoder = cirrus_encoder_init(cdev->dev);
	if (!encoder) {
		DRM_ERROR("cirrus_encoder_init failed\n");
		return -1;
	}

	connector = cirrus_vga_init(cdev->dev);
	if (!connector) {
		DRM_ERROR("cirrus_vga_init failed\n");
		return -1;
	}

	drm_mode_connector_attach_encoder(connector, encoder);

	ret = cirrus_fbdev_init(cdev);
	if (ret) {
		DRM_ERROR("cirrus_fbdev_init failed\n");
		return ret;
	}

	return 0;
}

void cirrus_modeset_fini(struct cirrus_device *cdev)
{
	cirrus_fbdev_fini(cdev);

	if (cdev->mode_info.mode_config_initialized) {
		drm_mode_config_cleanup(cdev->dev);
		cdev->mode_info.mode_config_initialized = false;
	}
}
Commit	Line	Data
f9aa76a8 DA	1
	2	/*
	3	* Copyright 2012 Red Hat
	4	*
	5	* This file is subject to the terms and conditions of the GNU General
	6	* Public License version 2. See the file COPYING in the main
	7	* directory of this archive for more details.
	8	*
	9	* Authors: Matthew Garrett
	10	* Dave Airlie
	11	*
	12	* Portions of this code derived from cirrusfb.c:
	13	* drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
	14	*
	15	* Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
	16	*/
760285e7 DH	17	#include <drm/drmP.h>
760285e7 DH	18	#include <drm/drm_crtc_helper.h>
3cb9ae4f	19	#include <drm/drm_plane_helper.h>
f9aa76a8 DA	20
	21	#include <video/cirrus.h>
	22
	23	#include "cirrus_drv.h"
	24
	25	#define CIRRUS_LUT_SIZE 256
	26
	27	#define PALETTE_INDEX 0x8
	28	#define PALETTE_DATA 0x9
	29
	30	/*
	31	* This file contains setup code for the CRTC.
	32	*/
	33
	34	static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
	35	{
	36	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	37	struct drm_device *dev = crtc->dev;
	38	struct cirrus_device *cdev = dev->dev_private;
	39	int i;
	40
	41	if (!crtc->enabled)
	42	return;
	43
	44	for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
	45	/* VGA registers */
	46	WREG8(PALETTE_INDEX, i);
	47	WREG8(PALETTE_DATA, cirrus_crtc->lut_r[i]);
	48	WREG8(PALETTE_DATA, cirrus_crtc->lut_g[i]);
	49	WREG8(PALETTE_DATA, cirrus_crtc->lut_b[i]);
	50	}
	51	}
	52
	53	/*
	54	* The DRM core requires DPMS functions, but they make little sense in our
	55	* case and so are just stubs
	56	*/
	57
	58	static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
	59	{
	60	struct drm_device *dev = crtc->dev;
	61	struct cirrus_device *cdev = dev->dev_private;
	62	u8 sr01, gr0e;
	63
	64	switch (mode) {
	65	case DRM_MODE_DPMS_ON:
	66	sr01 = 0x00;
	67	gr0e = 0x00;
	68	break;
	69	case DRM_MODE_DPMS_STANDBY:
	70	sr01 = 0x20;
	71	gr0e = 0x02;
	72	break;
	73	case DRM_MODE_DPMS_SUSPEND:
	74	sr01 = 0x20;
	75	gr0e = 0x04;
	76	break;
	77	case DRM_MODE_DPMS_OFF:
	78	sr01 = 0x20;
	79	gr0e = 0x06;
	80	break;
	81	default:
	82	return;
	83	}
84
85	WREG8(SEQ_INDEX, 0x1);
86	sr01 \|= RREG8(SEQ_DATA) & ~0x20;
87	WREG_SEQ(0x1, sr01);
88
89	WREG8(GFX_INDEX, 0xe);
90	gr0e \|= RREG8(GFX_DATA) & ~0x06;
91	WREG_GFX(0xe, gr0e);
92	}
93
5e89440f	94	static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
f9aa76a8 DA	95	{
	96	struct cirrus_device *cdev = crtc->dev->dev_private;
	97	u32 addr;
	98	u8 tmp;
	99
	100	addr = offset >> 2;
	101	WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff));
	102	WREG_CRT(0x0d, (u8)(addr & 0xff));
	103
	104	WREG8(CRT_INDEX, 0x1b);
	105	tmp = RREG8(CRT_DATA);
	106	tmp &= 0xf2;
	107	tmp \|= (addr >> 16) & 0x01;
	108	tmp \|= (addr >> 15) & 0x0c;
	109	WREG_CRT(0x1b, tmp);
	110	WREG8(CRT_INDEX, 0x1d);
	111	tmp = RREG8(CRT_DATA);
	112	tmp &= 0x7f;
	113	tmp \|= (addr >> 12) & 0x80;
	114	WREG_CRT(0x1d, tmp);
	115	}
	116
	117	/* cirrus is different - we will force move buffers out of VRAM */
	118	static int cirrus_crtc_do_set_base(struct drm_crtc *crtc,
	119	struct drm_framebuffer *fb,
	120	int x, int y, int atomic)
	121	{
	122	struct cirrus_device *cdev = crtc->dev->dev_private;
	123	struct drm_gem_object *obj;
	124	struct cirrus_framebuffer *cirrus_fb;
	125	struct cirrus_bo *bo;
	126	int ret;
	127	u64 gpu_addr;
	128
	129	/* push the previous fb to system ram */
	130	if (!atomic && fb) {
	131	cirrus_fb = to_cirrus_framebuffer(fb);
	132	obj = cirrus_fb->obj;
	133	bo = gem_to_cirrus_bo(obj);
	134	ret = cirrus_bo_reserve(bo, false);
	135	if (ret)
	136	return ret;
	137	cirrus_bo_push_sysram(bo);
	138	cirrus_bo_unreserve(bo);
	139	}
	140
f4510a27	141	cirrus_fb = to_cirrus_framebuffer(crtc->primary->fb);
f9aa76a8 DA	142	obj = cirrus_fb->obj;
	143	bo = gem_to_cirrus_bo(obj);
	144
	145	ret = cirrus_bo_reserve(bo, false);
	146	if (ret)
	147	return ret;
	148
	149	ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
	150	if (ret) {
	151	cirrus_bo_unreserve(bo);
	152	return ret;
	153	}
	154
	155	if (&cdev->mode_info.gfbdev->gfb == cirrus_fb) {
	156	/* if pushing console in kmap it */
	157	ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
	158	if (ret)
	159	DRM_ERROR("failed to kmap fbcon\n");
	160	}
	161	cirrus_bo_unreserve(bo);
	162
	163	cirrus_set_start_address(crtc, (u32)gpu_addr);
	164	return 0;
	165	}
	166
	167	static int cirrus_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
	168	struct drm_framebuffer *old_fb)
	169	{
	170	return cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
	171	}
	172
	173	/*
	174	* The meat of this driver. The core passes us a mode and we have to program
	175	* it. The modesetting here is the bare minimum required to satisfy the qemu
	176	* emulation of this hardware, and running this against a real device is
	177	* likely to result in an inadequately programmed mode. We've already had
	178	* the opportunity to modify the mode, so whatever we receive here should
	179	* be something that can be correctly programmed and displayed
	180	*/
	181	static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
	182	struct drm_display_mode *mode,
	183	struct drm_display_mode *adjusted_mode,
	184	int x, int y, struct drm_framebuffer *old_fb)
	185	{
	186	struct drm_device *dev = crtc->dev;
	187	struct cirrus_device *cdev = dev->dev_private;
	188	int hsyncstart, hsyncend, htotal, hdispend;
	189	int vtotal, vdispend;
	190	int tmp;
	191	int sr07 = 0, hdr = 0;
	192
	193	htotal = mode->htotal / 8;
	194	hsyncend = mode->hsync_end / 8;
	195	hsyncstart = mode->hsync_start / 8;
	196	hdispend = mode->hdisplay / 8;
	197
	198	vtotal = mode->vtotal;
	199	vdispend = mode->vdisplay;
	200
	201	vdispend -= 1;
	202	vtotal -= 2;
	203
	204	htotal -= 5;
	205	hdispend -= 1;
206	hsyncstart += 1;
207	hsyncend += 1;
208
209	WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20);
210	WREG_CRT(VGA_CRTC_H_TOTAL, htotal);
211	WREG_CRT(VGA_CRTC_H_DISP, hdispend);
212	WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart);
213	WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend);
214	WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff);
215	WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff);
216
217	tmp = 0x40;
218	if ((vdispend + 1) & 512)
219	tmp \|= 0x20;
220	WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);
221
222	/*
223	* Overflow bits for values that don't fit in the standard registers
224	*/
225	tmp = 16;
226	if (vtotal & 256)
227	tmp \|= 1;
228	if (vdispend & 256)
229	tmp \|= 2;
230	if ((vdispend + 1) & 256)
231	tmp \|= 8;
232	if (vtotal & 512)
233	tmp \|= 32;
234	if (vdispend & 512)
235	tmp \|= 64;
236	WREG_CRT(VGA_CRTC_OVERFLOW, tmp);
237
238	tmp = 0;
239
240	/* More overflow bits */
241
242	if ((htotal + 5) & 64)
243	tmp \|= 16;
244	if ((htotal + 5) & 128)
245	tmp \|= 32;
246	if (vtotal & 256)
247	tmp \|= 64;
248	if (vtotal & 512)
249	tmp \|= 128;
250
251	WREG_CRT(CL_CRT1A, tmp);
252
253	/* Disable Hercules/CGA compatibility */
254	WREG_CRT(VGA_CRTC_MODE, 0x03);
255
256	WREG8(SEQ_INDEX, 0x7);
257	sr07 = RREG8(SEQ_DATA);
258	sr07 &= 0xe0;
259	hdr = 0;
f4510a27	260	switch (crtc->primary->fb->bits_per_pixel) {
f9aa76a8 DA	261	case 8:
	262	sr07 \|= 0x11;
	263	break;
	264	case 16:
2510538f TI	265	sr07 \|= 0x17;
2510538f TI	266	hdr = 0xc1;
f9aa76a8 DA	267	break;
	268	case 24:
	269	sr07 \|= 0x15;
	270	hdr = 0xc5;
	271	break;
	272	case 32:
	273	sr07 \|= 0x19;
	274	hdr = 0xc5;
	275	break;
	276	default:
	277	return -1;
	278	}
	279
	280	WREG_SEQ(0x7, sr07);
	281
	282	/* Program the pitch */
f4510a27	283	tmp = crtc->primary->fb->pitches[0] / 8;
f9aa76a8 DA	284	WREG_CRT(VGA_CRTC_OFFSET, tmp);
	285
	286	/* Enable extended blanking and pitch bits, and enable full memory */
	287	tmp = 0x22;
f4510a27 MR	288	tmp \|= (crtc->primary->fb->pitches[0] >> 7) & 0x10;
f4510a27 MR	289	tmp \|= (crtc->primary->fb->pitches[0] >> 6) & 0x40;
f9aa76a8 DA	290	WREG_CRT(0x1b, tmp);
	291
	292	/* Enable high-colour modes */
	293	WREG_GFX(VGA_GFX_MODE, 0x40);
	294
	295	/* And set graphics mode */
	296	WREG_GFX(VGA_GFX_MISC, 0x01);
	297
	298	WREG_HDR(hdr);
	299	cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
2f1e8007 GH	300
	301	/* Unblank (needed on S3 resume, vgabios doesn't do it then) */
	302	outb(0x20, 0x3c0);
f9aa76a8 DA	303	return 0;
	304	}
	305
	306	/*
	307	* This is called before a mode is programmed. A typical use might be to
	308	* enable DPMS during the programming to avoid seeing intermediate stages,
	309	* but that's not relevant to us
	310	*/
	311	static void cirrus_crtc_prepare(struct drm_crtc *crtc)
	312	{
	313	}
	314
	315	/*
	316	* This is called after a mode is programmed. It should reverse anything done
	317	* by the prepare function
	318	*/
	319	static void cirrus_crtc_commit(struct drm_crtc *crtc)
	320	{
	321	}
	322
	323	/*
	324	* The core can pass us a set of gamma values to program. We actually only
	325	* use this for 8-bit mode so can't perform smooth fades on deeper modes,
	326	* but it's a requirement that we provide the function
	327	*/
7ea77283 ML	328	static int cirrus_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
7ea77283 ML	329	u16 *blue, uint32_t size)
f9aa76a8 DA	330	{
	331	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	332	int i;
	333
7ea77283	334	for (i = 0; i < size; i++) {
f9aa76a8 DA	335	cirrus_crtc->lut_r[i] = red[i];
	336	cirrus_crtc->lut_g[i] = green[i];
	337	cirrus_crtc->lut_b[i] = blue[i];
	338	}
	339	cirrus_crtc_load_lut(crtc);
7ea77283 ML	340
7ea77283 ML	341	return 0;
f9aa76a8 DA	342	}
	343
	344	/* Simple cleanup function */
	345	static void cirrus_crtc_destroy(struct drm_crtc *crtc)
	346	{
	347	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	348
	349	drm_crtc_cleanup(crtc);
	350	kfree(cirrus_crtc);
	351	}
	352
	353	/* These provide the minimum set of functions required to handle a CRTC */
	354	static const struct drm_crtc_funcs cirrus_crtc_funcs = {
	355	.gamma_set = cirrus_crtc_gamma_set,
	356	.set_config = drm_crtc_helper_set_config,
	357	.destroy = cirrus_crtc_destroy,
	358	};
	359
	360	static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
	361	.dpms = cirrus_crtc_dpms,
f9aa76a8 DA	362	.mode_set = cirrus_crtc_mode_set,
	363	.mode_set_base = cirrus_crtc_mode_set_base,
	364	.prepare = cirrus_crtc_prepare,
	365	.commit = cirrus_crtc_commit,
	366	.load_lut = cirrus_crtc_load_lut,
	367	};
	368
	369	/* CRTC setup */
	370	static void cirrus_crtc_init(struct drm_device *dev)
	371	{
	372	struct cirrus_device *cdev = dev->dev_private;
	373	struct cirrus_crtc *cirrus_crtc;
	374	int i;
	375
	376	cirrus_crtc = kzalloc(sizeof(struct cirrus_crtc) +
	377	(CIRRUSFB_CONN_LIMIT * sizeof(struct drm_connector *)),
	378	GFP_KERNEL);
	379
	380	if (cirrus_crtc == NULL)
	381	return;
	382
	383	drm_crtc_init(dev, &cirrus_crtc->base, &cirrus_crtc_funcs);
	384
	385	drm_mode_crtc_set_gamma_size(&cirrus_crtc->base, CIRRUS_LUT_SIZE);
	386	cdev->mode_info.crtc = cirrus_crtc;
	387
	388	for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
	389	cirrus_crtc->lut_r[i] = i;
	390	cirrus_crtc->lut_g[i] = i;
	391	cirrus_crtc->lut_b[i] = i;
	392	}
	393
	394	drm_crtc_helper_add(&cirrus_crtc->base, &cirrus_helper_funcs);
	395	}
	396
	397	/** Sets the color ramps on behalf of fbcon */
	398	void cirrus_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	399	u16 blue, int regno)
	400	{
	401	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	402
	403	cirrus_crtc->lut_r[regno] = red;
	404	cirrus_crtc->lut_g[regno] = green;
	405	cirrus_crtc->lut_b[regno] = blue;
	406	}
	407
	408	/** Gets the color ramps on behalf of fbcon */
	409	void cirrus_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
	410	u16 *blue, int regno)
	411	{
	412	struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
	413
	414	*red = cirrus_crtc->lut_r[regno];
	415	*green = cirrus_crtc->lut_g[regno];
	416	*blue = cirrus_crtc->lut_b[regno];
	417	}
	418
f9aa76a8 DA	419	static void cirrus_encoder_mode_set(struct drm_encoder *encoder,
	420	struct drm_display_mode *mode,
	421	struct drm_display_mode *adjusted_mode)
	422	{
	423	}
	424
	425	static void cirrus_encoder_dpms(struct drm_encoder *encoder, int state)
	426	{
	427	return;
	428	}
	429
	430	static void cirrus_encoder_prepare(struct drm_encoder *encoder)
	431	{
	432	}
	433
	434	static void cirrus_encoder_commit(struct drm_encoder *encoder)
	435	{
	436	}
	437
5e89440f	438	static void cirrus_encoder_destroy(struct drm_encoder *encoder)
f9aa76a8 DA	439	{
	440	struct cirrus_encoder *cirrus_encoder = to_cirrus_encoder(encoder);
	441	drm_encoder_cleanup(encoder);
	442	kfree(cirrus_encoder);
	443	}
	444
	445	static const struct drm_encoder_helper_funcs cirrus_encoder_helper_funcs = {
	446	.dpms = cirrus_encoder_dpms,
f9aa76a8 DA	447	.mode_set = cirrus_encoder_mode_set,
	448	.prepare = cirrus_encoder_prepare,
	449	.commit = cirrus_encoder_commit,
	450	};
	451
	452	static const struct drm_encoder_funcs cirrus_encoder_encoder_funcs = {
	453	.destroy = cirrus_encoder_destroy,
	454	};
	455
	456	static struct drm_encoder cirrus_encoder_init(struct drm_device dev)
	457	{
	458	struct drm_encoder *encoder;
	459	struct cirrus_encoder *cirrus_encoder;
	460
	461	cirrus_encoder = kzalloc(sizeof(struct cirrus_encoder), GFP_KERNEL);
	462	if (!cirrus_encoder)
	463	return NULL;
	464
	465	encoder = &cirrus_encoder->base;
	466	encoder->possible_crtcs = 0x1;
	467
	468	drm_encoder_init(dev, encoder, &cirrus_encoder_encoder_funcs,
13a3d91f	469	DRM_MODE_ENCODER_DAC, NULL);
f9aa76a8 DA	470	drm_encoder_helper_add(encoder, &cirrus_encoder_helper_funcs);
	471
	472	return encoder;
	473	}
	474
	475
5e89440f	476	static int cirrus_vga_get_modes(struct drm_connector *connector)
f9aa76a8	477	{
121a6a17	478	int count;
f9aa76a8	479
121a6a17	480	/* Just add a static list of modes */
7f551b1e TI	481	if (cirrus_bpp <= 24) {
	482	count = drm_add_modes_noedid(connector, 1280, 1024);
	483	drm_set_preferred_mode(connector, 1024, 768);
	484	} else {
	485	count = drm_add_modes_noedid(connector, 800, 600);
	486	drm_set_preferred_mode(connector, 800, 600);
	487	}
121a6a17	488	return count;
f9aa76a8 DA	489	}
f9aa76a8 DA	490
5e89440f	491	static struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
f9aa76a8 DA	492	*connector)
	493	{
	494	int enc_id = connector->encoder_ids[0];
f9aa76a8	495	/* pick the encoder ids */
ef13aec4 RC	496	if (enc_id)
ef13aec4 RC	497	return drm_encoder_find(connector->dev, enc_id);
f9aa76a8 DA	498	return NULL;
	499	}
	500
	501	static enum drm_connector_status cirrus_vga_detect(struct drm_connector
	502	*connector, bool force)
	503	{
	504	return connector_status_connected;
	505	}
	506
	507	static void cirrus_connector_destroy(struct drm_connector *connector)
	508	{
	509	drm_connector_cleanup(connector);
	510	kfree(connector);
	511	}
	512
c8770900	513	static const struct drm_connector_helper_funcs cirrus_vga_connector_helper_funcs = {
f9aa76a8	514	.get_modes = cirrus_vga_get_modes,
f9aa76a8 DA	515	.best_encoder = cirrus_connector_best_encoder,
	516	};
	517
c8770900	518	static const struct drm_connector_funcs cirrus_vga_connector_funcs = {
f9aa76a8 DA	519	.dpms = drm_helper_connector_dpms,
	520	.detect = cirrus_vga_detect,
	521	.fill_modes = drm_helper_probe_single_connector_modes,
	522	.destroy = cirrus_connector_destroy,
	523	};
	524
	525	static struct drm_connector cirrus_vga_init(struct drm_device dev)
	526	{
	527	struct drm_connector *connector;
	528	struct cirrus_connector *cirrus_connector;
	529
	530	cirrus_connector = kzalloc(sizeof(struct cirrus_connector), GFP_KERNEL);
	531	if (!cirrus_connector)
	532	return NULL;
	533
	534	connector = &cirrus_connector->base;
	535
	536	drm_connector_init(dev, connector,
	537	&cirrus_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
	538
	539	drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);
	540
c5267091	541	drm_connector_register(connector);
f9aa76a8 DA	542	return connector;
	543	}
	544
	545
	546	int cirrus_modeset_init(struct cirrus_device *cdev)
	547	{
	548	struct drm_encoder *encoder;
	549	struct drm_connector *connector;
	550	int ret;
	551
	552	drm_mode_config_init(cdev->dev);
	553	cdev->mode_info.mode_config_initialized = true;
	554
	555	cdev->dev->mode_config.max_width = CIRRUS_MAX_FB_WIDTH;
	556	cdev->dev->mode_config.max_height = CIRRUS_MAX_FB_HEIGHT;
	557
	558	cdev->dev->mode_config.fb_base = cdev->mc.vram_base;
	559	cdev->dev->mode_config.preferred_depth = 24;
	560	/* don't prefer a shadow on virt GPU */
	561	cdev->dev->mode_config.prefer_shadow = 0;
	562
	563	cirrus_crtc_init(cdev->dev);
	564
	565	encoder = cirrus_encoder_init(cdev->dev);
	566	if (!encoder) {
	567	DRM_ERROR("cirrus_encoder_init failed\n");
	568	return -1;
	569	}
	570
	571	connector = cirrus_vga_init(cdev->dev);
	572	if (!connector) {
	573	DRM_ERROR("cirrus_vga_init failed\n");
	574	return -1;
	575	}
	576
	577	drm_mode_connector_attach_encoder(connector, encoder);
	578
	579	ret = cirrus_fbdev_init(cdev);
	580	if (ret) {
	581	DRM_ERROR("cirrus_fbdev_init failed\n");
	582	return ret;
	583	}
	584
	585	return 0;
	586	}
	587
	588	void cirrus_modeset_fini(struct cirrus_device *cdev)
	589	{
	590	cirrus_fbdev_fini(cdev);
	591
	592	if (cdev->mode_info.mode_config_initialized) {
	593	drm_mode_config_cleanup(cdev->dev);
	594	cdev->mode_info.mode_config_initialized = false;
	595	}
	596	}