[deliverable/linux.git] / drivers / gpu / drm / drm_dp_helper.c

/*
 * Copyright © 2009 Keith Packard
 *
 * Permission to use, copy, modify, distribute, and sell this software and its
 * documentation for any purpose is hereby granted without fee, provided that
 * the above copyright notice appear in all copies and that both that copyright
 * notice and this permission notice appear in supporting documentation, and
 * that the name of the copyright holders not be used in advertising or
 * publicity pertaining to distribution of the software without specific,
 * written prior permission.  The copyright holders make no representations
 * about the suitability of this software for any purpose.  It is provided "as
 * is" without express or implied warranty.
 *
 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
 * OF THIS SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/i2c.h>
#include <drm/drm_dp_helper.h>
#include <drm/drmP.h>

/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
static int
i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
			    uint8_t write_byte, uint8_t *read_byte)
{
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	int ret;

	ret = (*algo_data->aux_ch)(adapter, mode,
				   write_byte, read_byte);
	return ret;
}

/*
 * I2C over AUX CH
 */

/*
 * Send the address. If the I2C link is running, this 'restarts'
 * the connection with the new address, this is used for doing
 * a write followed by a read (as needed for DDC)
 */
static int
i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
{
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	int mode = MODE_I2C_START;
	int ret;

	if (reading)
		mode |= MODE_I2C_READ;
	else
		mode |= MODE_I2C_WRITE;
	algo_data->address = address;
	algo_data->running = true;
	ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
	return ret;
}

/*
 * Stop the I2C transaction. This closes out the link, sending
 * a bare address packet with the MOT bit turned off
 */
static void
i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
{
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	int mode = MODE_I2C_STOP;

	if (reading)
		mode |= MODE_I2C_READ;
	else
		mode |= MODE_I2C_WRITE;
	if (algo_data->running) {
		(void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
		algo_data->running = false;
	}
}

/*
 * Write a single byte to the current I2C address, the
 * the I2C link must be running or this returns -EIO
 */
static int
i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
{
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	int ret;

	if (!algo_data->running)
		return -EIO;

	ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
	return ret;
}

/*
 * Read a single byte from the current I2C address, the
 * I2C link must be running or this returns -EIO
 */
static int
i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
{
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	int ret;

	if (!algo_data->running)
		return -EIO;

	ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
	return ret;
}

static int
i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
		     struct i2c_msg *msgs,
		     int num)
{
	int ret = 0;
	bool reading = false;
	int m;
	int b;

	for (m = 0; m < num; m++) {
		u16 len = msgs[m].len;
		u8 *buf = msgs[m].buf;
		reading = (msgs[m].flags & I2C_M_RD) != 0;
		ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
		if (ret < 0)
			break;
		if (reading) {
			for (b = 0; b < len; b++) {
				ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
				if (ret < 0)
					break;
			}
		} else {
			for (b = 0; b < len; b++) {
				ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
				if (ret < 0)
					break;
			}
		}
		if (ret < 0)
			break;
	}
	if (ret >= 0)
		ret = num;
	i2c_algo_dp_aux_stop(adapter, reading);
	DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
	return ret;
}

static u32
i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
	       I2C_FUNC_SMBUS_READ_BLOCK_DATA |
	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
	       I2C_FUNC_10BIT_ADDR;
}

static const struct i2c_algorithm i2c_dp_aux_algo = {
	.master_xfer	= i2c_algo_dp_aux_xfer,
	.functionality	= i2c_algo_dp_aux_functionality,
};

static void
i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
{
	(void) i2c_algo_dp_aux_address(adapter, 0, false);
	(void) i2c_algo_dp_aux_stop(adapter, false);
}

static int
i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
{
	adapter->algo = &i2c_dp_aux_algo;
	adapter->retries = 3;
	i2c_dp_aux_reset_bus(adapter);
	return 0;
}

int
i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
{
	int error;

	error = i2c_dp_aux_prepare_bus(adapter);
	if (error)
		return error;
	error = i2c_add_adapter(adapter);
	return error;
}
EXPORT_SYMBOL(i2c_dp_aux_add_bus);

/* Helpers for DP link training */
static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
{
	return link_status[r - DP_LANE0_1_STATUS];
}

static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
			     int lane)
{
	int i = DP_LANE0_1_STATUS + (lane >> 1);
	int s = (lane & 1) * 4;
	u8 l = dp_link_status(link_status, i);
	return (l >> s) & 0xf;
}

bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
			  int lane_count)
{
	u8 lane_align;
	u8 lane_status;
	int lane;

	lane_align = dp_link_status(link_status,
				    DP_LANE_ALIGN_STATUS_UPDATED);
	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
		return false;
	for (lane = 0; lane < lane_count; lane++) {
		lane_status = dp_get_lane_status(link_status, lane);
		if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
			return false;
	}
	return true;
}
EXPORT_SYMBOL(drm_dp_channel_eq_ok);

bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
			      int lane_count)
{
	int lane;
	u8 lane_status;

	for (lane = 0; lane < lane_count; lane++) {
		lane_status = dp_get_lane_status(link_status, lane);
		if ((lane_status & DP_LANE_CR_DONE) == 0)
			return false;
	}
	return true;
}
EXPORT_SYMBOL(drm_dp_clock_recovery_ok);

u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
				     int lane)
{
	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
	int s = ((lane & 1) ?
		 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
		 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
	u8 l = dp_link_status(link_status, i);

	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);

u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
					  int lane)
{
	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
	int s = ((lane & 1) ?
		 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
		 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
	u8 l = dp_link_status(link_status, i);

	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);

void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
		udelay(100);
	else
		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);

void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
		udelay(400);
	else
		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);

u8 drm_dp_link_rate_to_bw_code(int link_rate)
{
	switch (link_rate) {
	case 162000:
	default:
		return DP_LINK_BW_1_62;
	case 270000:
		return DP_LINK_BW_2_7;
	case 540000:
		return DP_LINK_BW_5_4;
	}
}
EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);

int drm_dp_bw_code_to_link_rate(u8 link_bw)
{
	switch (link_bw) {
	case DP_LINK_BW_1_62:
	default:
		return 162000;
	case DP_LINK_BW_2_7:
		return 270000;
	case DP_LINK_BW_5_4:
		return 540000;
	}
}
EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
Commit	Line	Data
a4fc5ed6 KP	1	/*
	2	* Copyright © 2009 Keith Packard
	3	*
	4	* Permission to use, copy, modify, distribute, and sell this software and its
	5	* documentation for any purpose is hereby granted without fee, provided that
	6	* the above copyright notice appear in all copies and that both that copyright
	7	* notice and this permission notice appear in supporting documentation, and
	8	* that the name of the copyright holders not be used in advertising or
	9	* publicity pertaining to distribution of the software without specific,
	10	* written prior permission. The copyright holders make no representations
	11	* about the suitability of this software for any purpose. It is provided "as
	12	* is" without express or implied warranty.
	13	*
	14	* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
	15	* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
	16	* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
	17	* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
	18	* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
	19	* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
	20	* OF THIS SOFTWARE.
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/delay.h>
a4fc5ed6 KP	26	#include <linux/init.h>
	27	#include <linux/errno.h>
	28	#include <linux/sched.h>
	29	#include <linux/i2c.h>
760285e7 DH	30	#include <drm/drm_dp_helper.h>
760285e7 DH	31	#include <drm/drmP.h>
a4fc5ed6 KP	32
a4fc5ed6 KP	33	/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
a4fc5ed6 KP	34	static int
	35	i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
	36	uint8_t write_byte, uint8_t *read_byte)
	37	{
	38	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6	39	int ret;
00ae9a45	40
ab2c0672 DA	41	ret = (*algo_data->aux_ch)(adapter, mode,
	42	write_byte, read_byte);
	43	return ret;
a4fc5ed6 KP	44	}
	45
	46	/*
	47	* I2C over AUX CH
	48	*/
	49
	50	/*
	51	* Send the address. If the I2C link is running, this 'restarts'
	52	* the connection with the new address, this is used for doing
	53	* a write followed by a read (as needed for DDC)
	54	*/
	55	static int
	56	i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
	57	{
	58	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	59	int mode = MODE_I2C_START;
	60	int ret;
	61
	62	if (reading)
	63	mode \|= MODE_I2C_READ;
	64	else
	65	mode \|= MODE_I2C_WRITE;
	66	algo_data->address = address;
	67	algo_data->running = true;
	68	ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
	69	return ret;
	70	}
	71
	72	/*
	73	* Stop the I2C transaction. This closes out the link, sending
	74	* a bare address packet with the MOT bit turned off
	75	*/
	76	static void
	77	i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
	78	{
	79	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	80	int mode = MODE_I2C_STOP;
	81
	82	if (reading)
	83	mode \|= MODE_I2C_READ;
	84	else
	85	mode \|= MODE_I2C_WRITE;
	86	if (algo_data->running) {
	87	(void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
	88	algo_data->running = false;
	89	}
	90	}
	91
	92	/*
	93	* Write a single byte to the current I2C address, the
	94	* the I2C link must be running or this returns -EIO
	95	*/
	96	static int
	97	i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
	98	{
	99	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
	100	int ret;
	101
	102	if (!algo_data->running)
	103	return -EIO;
	104
	105	ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
	106	return ret;
	107	}
108
109	/*
110	* Read a single byte from the current I2C address, the
111	* I2C link must be running or this returns -EIO
112	*/
113	static int
114	i2c_algo_dp_aux_get_byte(struct i2c_adapter adapter, u8 byte_ret)
115	{
116	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
117	int ret;
118
119	if (!algo_data->running)
120	return -EIO;
121
122	ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
123	return ret;
124	}
125
126	static int
127	i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
128	struct i2c_msg *msgs,
129	int num)
130	{
131	int ret = 0;
132	bool reading = false;
133	int m;
134	int b;
135
136	for (m = 0; m < num; m++) {
137	u16 len = msgs[m].len;
138	u8 *buf = msgs[m].buf;
139	reading = (msgs[m].flags & I2C_M_RD) != 0;
140	ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
141	if (ret < 0)
142	break;
143	if (reading) {
144	for (b = 0; b < len; b++) {
145	ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
146	if (ret < 0)
147	break;
148	}
149	} else {
150	for (b = 0; b < len; b++) {
151	ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
152	if (ret < 0)
153	break;
154	}
155	}
156	if (ret < 0)
157	break;
158	}
159	if (ret >= 0)
160	ret = num;
161	i2c_algo_dp_aux_stop(adapter, reading);
28c97730	162	DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
a4fc5ed6 KP	163	return ret;
	164	}
	165
	166	static u32
	167	i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
	168	{
	169	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
	170	I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
	171	I2C_FUNC_SMBUS_BLOCK_PROC_CALL \|
	172	I2C_FUNC_10BIT_ADDR;
	173	}
	174
	175	static const struct i2c_algorithm i2c_dp_aux_algo = {
	176	.master_xfer = i2c_algo_dp_aux_xfer,
	177	.functionality = i2c_algo_dp_aux_functionality,
	178	};
	179
	180	static void
	181	i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
	182	{
	183	(void) i2c_algo_dp_aux_address(adapter, 0, false);
	184	(void) i2c_algo_dp_aux_stop(adapter, false);
a4fc5ed6 KP	185	}
	186
	187	static int
	188	i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
	189	{
	190	adapter->algo = &i2c_dp_aux_algo;
	191	adapter->retries = 3;
	192	i2c_dp_aux_reset_bus(adapter);
	193	return 0;
	194	}
	195
	196	int
	197	i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
	198	{
	199	int error;
00ae9a45	200
a4fc5ed6 KP	201	error = i2c_dp_aux_prepare_bus(adapter);
	202	if (error)
	203	return error;
	204	error = i2c_add_adapter(adapter);
	205	return error;
	206	}
	207	EXPORT_SYMBOL(i2c_dp_aux_add_bus);
1ffdff13 DV	208
	209	/* Helpers for DP link training */
	210	static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
	211	{
	212	return link_status[r - DP_LANE0_1_STATUS];
	213	}
	214
	215	static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
	216	int lane)
	217	{
	218	int i = DP_LANE0_1_STATUS + (lane >> 1);
	219	int s = (lane & 1) * 4;
	220	u8 l = dp_link_status(link_status, i);
	221	return (l >> s) & 0xf;
	222	}
	223
	224	bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
	225	int lane_count)
	226	{
	227	u8 lane_align;
	228	u8 lane_status;
	229	int lane;
	230
	231	lane_align = dp_link_status(link_status,
	232	DP_LANE_ALIGN_STATUS_UPDATED);
	233	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
	234	return false;
	235	for (lane = 0; lane < lane_count; lane++) {
	236	lane_status = dp_get_lane_status(link_status, lane);
	237	if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
	238	return false;
	239	}
	240	return true;
	241	}
	242	EXPORT_SYMBOL(drm_dp_channel_eq_ok);
	243
	244	bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
	245	int lane_count)
	246	{
	247	int lane;
	248	u8 lane_status;
	249
	250	for (lane = 0; lane < lane_count; lane++) {
	251	lane_status = dp_get_lane_status(link_status, lane);
	252	if ((lane_status & DP_LANE_CR_DONE) == 0)
	253	return false;
	254	}
	255	return true;
	256	}
	257	EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
0f037bde DV	258
	259	u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
	260	int lane)
	261	{
	262	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
	263	int s = ((lane & 1) ?
	264	DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
	265	DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
	266	u8 l = dp_link_status(link_status, i);
	267
	268	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
	269	}
	270	EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
	271
	272	u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
	273	int lane)
	274	{
	275	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
	276	int s = ((lane & 1) ?
	277	DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
	278	DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
	279	u8 l = dp_link_status(link_status, i);
	280
	281	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
	282	}
	283	EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
	284
1a644cd4 DV	285	void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
	286	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
	287	udelay(100);
	288	else
	289	mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
	290	}
	291	EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
	292
	293	void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
	294	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
	295	udelay(400);
	296	else
	297	mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
	298	}
	299	EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
3b5c662e DV	300
	301	u8 drm_dp_link_rate_to_bw_code(int link_rate)
	302	{
	303	switch (link_rate) {
	304	case 162000:
	305	default:
	306	return DP_LINK_BW_1_62;
	307	case 270000:
	308	return DP_LINK_BW_2_7;
	309	case 540000:
	310	return DP_LINK_BW_5_4;
	311	}
	312	}
	313	EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
	314
	315	int drm_dp_bw_code_to_link_rate(u8 link_bw)
	316	{
	317	switch (link_bw) {
	318	case DP_LINK_BW_1_62:
	319	default:
	320	return 162000;
	321	case DP_LINK_BW_2_7:
	322	return 270000;
	323	case DP_LINK_BW_5_4:
	324	return 540000;
	325	}
	326	}
	327	EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);