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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
30 | #include <linux/kernel.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
10a85120 | 32 | #include <linux/hdmi.h> |
f453ba04 | 33 | #include <linux/i2c.h> |
47819ba2 | 34 | #include <linux/module.h> |
5cb8eaa2 | 35 | #include <linux/vga_switcheroo.h> |
760285e7 DH |
36 | #include <drm/drmP.h> |
37 | #include <drm/drm_edid.h> | |
40d9b043 | 38 | #include <drm/drm_displayid.h> |
f453ba04 | 39 | |
13931579 AJ |
40 | #define version_greater(edid, maj, min) \ |
41 | (((edid)->version > (maj)) || \ | |
42 | ((edid)->version == (maj) && (edid)->revision > (min))) | |
f453ba04 | 43 | |
d1ff6409 AJ |
44 | #define EDID_EST_TIMINGS 16 |
45 | #define EDID_STD_TIMINGS 8 | |
46 | #define EDID_DETAILED_TIMINGS 4 | |
f453ba04 DA |
47 | |
48 | /* | |
49 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
50 | * them here (note that userspace may work around broken monitors first, | |
51 | * but fixes should make their way here so that the kernel "just works" | |
52 | * on as many displays as possible). | |
53 | */ | |
54 | ||
55 | /* First detailed mode wrong, use largest 60Hz mode */ | |
56 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
57 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
58 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
59 | /* Prefer the largest mode at 75 Hz */ | |
60 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
61 | /* Detail timing is in cm not mm */ | |
62 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
63 | /* Detailed timing descriptors have bogus size values, so just take the | |
64 | * maximum size and use that. | |
65 | */ | |
66 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
67 | /* Monitor forgot to set the first detailed is preferred bit. */ | |
68 | #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) | |
69 | /* use +hsync +vsync for detailed mode */ | |
70 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
bc42aabc AJ |
71 | /* Force reduced-blanking timings for detailed modes */ |
72 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) | |
49d45a31 RM |
73 | /* Force 8bpc */ |
74 | #define EDID_QUIRK_FORCE_8BPC (1 << 8) | |
bc5b9641 MK |
75 | /* Force 12bpc */ |
76 | #define EDID_QUIRK_FORCE_12BPC (1 << 9) | |
3c537889 | 77 | |
13931579 AJ |
78 | struct detailed_mode_closure { |
79 | struct drm_connector *connector; | |
80 | struct edid *edid; | |
81 | bool preferred; | |
82 | u32 quirks; | |
83 | int modes; | |
84 | }; | |
f453ba04 | 85 | |
5c61259e ZY |
86 | #define LEVEL_DMT 0 |
87 | #define LEVEL_GTF 1 | |
7a374350 AJ |
88 | #define LEVEL_GTF2 2 |
89 | #define LEVEL_CVT 3 | |
5c61259e | 90 | |
f453ba04 | 91 | static struct edid_quirk { |
c51a3fd6 | 92 | char vendor[4]; |
f453ba04 DA |
93 | int product_id; |
94 | u32 quirks; | |
95 | } edid_quirk_list[] = { | |
96 | /* Acer AL1706 */ | |
97 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | |
98 | /* Acer F51 */ | |
99 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, | |
100 | /* Unknown Acer */ | |
101 | { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
102 | ||
103 | /* Belinea 10 15 55 */ | |
104 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, | |
105 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, | |
106 | ||
107 | /* Envision Peripherals, Inc. EN-7100e */ | |
108 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, | |
ba1163de AJ |
109 | /* Envision EN2028 */ |
110 | { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, | |
f453ba04 DA |
111 | |
112 | /* Funai Electronics PM36B */ | |
113 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | | |
114 | EDID_QUIRK_DETAILED_IN_CM }, | |
115 | ||
116 | /* LG Philips LCD LP154W01-A5 */ | |
117 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
118 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
119 | ||
120 | /* Philips 107p5 CRT */ | |
121 | { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
122 | ||
123 | /* Proview AY765C */ | |
124 | { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
125 | ||
126 | /* Samsung SyncMaster 205BW. Note: irony */ | |
127 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, | |
128 | /* Samsung SyncMaster 22[5-6]BW */ | |
129 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, | |
130 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, | |
bc42aabc | 131 | |
bc5b9641 MK |
132 | /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ |
133 | { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, | |
134 | ||
bc42aabc AJ |
135 | /* ViewSonic VA2026w */ |
136 | { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, | |
118bdbd8 AD |
137 | |
138 | /* Medion MD 30217 PG */ | |
139 | { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, | |
49d45a31 RM |
140 | |
141 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ | |
142 | { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, | |
f453ba04 DA |
143 | }; |
144 | ||
a6b21831 TR |
145 | /* |
146 | * Autogenerated from the DMT spec. | |
147 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
148 | */ | |
149 | static const struct drm_display_mode drm_dmt_modes[] = { | |
24b856b1 | 150 | /* 0x01 - 640x350@85Hz */ |
a6b21831 TR |
151 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, |
152 | 736, 832, 0, 350, 382, 385, 445, 0, | |
153 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 154 | /* 0x02 - 640x400@85Hz */ |
a6b21831 TR |
155 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, |
156 | 736, 832, 0, 400, 401, 404, 445, 0, | |
157 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 158 | /* 0x03 - 720x400@85Hz */ |
a6b21831 TR |
159 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, |
160 | 828, 936, 0, 400, 401, 404, 446, 0, | |
161 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 162 | /* 0x04 - 640x480@60Hz */ |
a6b21831 | 163 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
fcf22d05 | 164 | 752, 800, 0, 480, 490, 492, 525, 0, |
a6b21831 | 165 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, |
24b856b1 | 166 | /* 0x05 - 640x480@72Hz */ |
a6b21831 TR |
167 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, |
168 | 704, 832, 0, 480, 489, 492, 520, 0, | |
169 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 170 | /* 0x06 - 640x480@75Hz */ |
a6b21831 TR |
171 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, |
172 | 720, 840, 0, 480, 481, 484, 500, 0, | |
173 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 174 | /* 0x07 - 640x480@85Hz */ |
a6b21831 TR |
175 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, |
176 | 752, 832, 0, 480, 481, 484, 509, 0, | |
177 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 178 | /* 0x08 - 800x600@56Hz */ |
a6b21831 TR |
179 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, |
180 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
181 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 182 | /* 0x09 - 800x600@60Hz */ |
a6b21831 TR |
183 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, |
184 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
185 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 186 | /* 0x0a - 800x600@72Hz */ |
a6b21831 TR |
187 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, |
188 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
189 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 190 | /* 0x0b - 800x600@75Hz */ |
a6b21831 TR |
191 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, |
192 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
193 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 194 | /* 0x0c - 800x600@85Hz */ |
a6b21831 TR |
195 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, |
196 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
197 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 198 | /* 0x0d - 800x600@120Hz RB */ |
a6b21831 TR |
199 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, |
200 | 880, 960, 0, 600, 603, 607, 636, 0, | |
201 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 202 | /* 0x0e - 848x480@60Hz */ |
a6b21831 TR |
203 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, |
204 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
205 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 206 | /* 0x0f - 1024x768@43Hz, interlace */ |
a6b21831 | 207 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, |
735b100f | 208 | 1208, 1264, 0, 768, 768, 776, 817, 0, |
a6b21831 | 209 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | |
fcf22d05 | 210 | DRM_MODE_FLAG_INTERLACE) }, |
24b856b1 | 211 | /* 0x10 - 1024x768@60Hz */ |
a6b21831 TR |
212 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, |
213 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
214 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 215 | /* 0x11 - 1024x768@70Hz */ |
a6b21831 TR |
216 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, |
217 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
218 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 219 | /* 0x12 - 1024x768@75Hz */ |
a6b21831 TR |
220 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, |
221 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
222 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 223 | /* 0x13 - 1024x768@85Hz */ |
a6b21831 TR |
224 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, |
225 | 1168, 1376, 0, 768, 769, 772, 808, 0, | |
226 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 227 | /* 0x14 - 1024x768@120Hz RB */ |
a6b21831 TR |
228 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, |
229 | 1104, 1184, 0, 768, 771, 775, 813, 0, | |
230 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 231 | /* 0x15 - 1152x864@75Hz */ |
a6b21831 TR |
232 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, |
233 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
234 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
bfcd74d2 VS |
235 | /* 0x55 - 1280x720@60Hz */ |
236 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
237 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
238 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 239 | /* 0x16 - 1280x768@60Hz RB */ |
a6b21831 TR |
240 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, |
241 | 1360, 1440, 0, 768, 771, 778, 790, 0, | |
242 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 243 | /* 0x17 - 1280x768@60Hz */ |
a6b21831 TR |
244 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, |
245 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
246 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 247 | /* 0x18 - 1280x768@75Hz */ |
a6b21831 TR |
248 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, |
249 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
fcf22d05 | 250 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 251 | /* 0x19 - 1280x768@85Hz */ |
a6b21831 TR |
252 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, |
253 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
254 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 255 | /* 0x1a - 1280x768@120Hz RB */ |
a6b21831 TR |
256 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, |
257 | 1360, 1440, 0, 768, 771, 778, 813, 0, | |
258 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 259 | /* 0x1b - 1280x800@60Hz RB */ |
a6b21831 TR |
260 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, |
261 | 1360, 1440, 0, 800, 803, 809, 823, 0, | |
262 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 263 | /* 0x1c - 1280x800@60Hz */ |
a6b21831 TR |
264 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, |
265 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
fcf22d05 | 266 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 267 | /* 0x1d - 1280x800@75Hz */ |
a6b21831 TR |
268 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, |
269 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
270 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 271 | /* 0x1e - 1280x800@85Hz */ |
a6b21831 TR |
272 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, |
273 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
274 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 275 | /* 0x1f - 1280x800@120Hz RB */ |
a6b21831 TR |
276 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, |
277 | 1360, 1440, 0, 800, 803, 809, 847, 0, | |
278 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 279 | /* 0x20 - 1280x960@60Hz */ |
a6b21831 TR |
280 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, |
281 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
282 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 283 | /* 0x21 - 1280x960@85Hz */ |
a6b21831 TR |
284 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, |
285 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
286 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 287 | /* 0x22 - 1280x960@120Hz RB */ |
a6b21831 TR |
288 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, |
289 | 1360, 1440, 0, 960, 963, 967, 1017, 0, | |
290 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 291 | /* 0x23 - 1280x1024@60Hz */ |
a6b21831 TR |
292 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, |
293 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
294 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 295 | /* 0x24 - 1280x1024@75Hz */ |
a6b21831 TR |
296 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, |
297 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
298 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 299 | /* 0x25 - 1280x1024@85Hz */ |
a6b21831 TR |
300 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, |
301 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
302 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 303 | /* 0x26 - 1280x1024@120Hz RB */ |
a6b21831 TR |
304 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, |
305 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, | |
306 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 307 | /* 0x27 - 1360x768@60Hz */ |
a6b21831 TR |
308 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, |
309 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
310 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 311 | /* 0x28 - 1360x768@120Hz RB */ |
a6b21831 TR |
312 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, |
313 | 1440, 1520, 0, 768, 771, 776, 813, 0, | |
314 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
315 | /* 0x51 - 1366x768@60Hz */ |
316 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, | |
317 | 1579, 1792, 0, 768, 771, 774, 798, 0, | |
318 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
319 | /* 0x56 - 1366x768@60Hz */ | |
320 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, | |
321 | 1436, 1500, 0, 768, 769, 772, 800, 0, | |
322 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 323 | /* 0x29 - 1400x1050@60Hz RB */ |
a6b21831 TR |
324 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, |
325 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, | |
326 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 327 | /* 0x2a - 1400x1050@60Hz */ |
a6b21831 TR |
328 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, |
329 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
330 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 331 | /* 0x2b - 1400x1050@75Hz */ |
a6b21831 TR |
332 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, |
333 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
334 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 335 | /* 0x2c - 1400x1050@85Hz */ |
a6b21831 TR |
336 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, |
337 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
338 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 339 | /* 0x2d - 1400x1050@120Hz RB */ |
a6b21831 TR |
340 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, |
341 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, | |
342 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 343 | /* 0x2e - 1440x900@60Hz RB */ |
a6b21831 TR |
344 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, |
345 | 1520, 1600, 0, 900, 903, 909, 926, 0, | |
346 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 347 | /* 0x2f - 1440x900@60Hz */ |
a6b21831 TR |
348 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, |
349 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
350 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 351 | /* 0x30 - 1440x900@75Hz */ |
a6b21831 TR |
352 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, |
353 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
354 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 355 | /* 0x31 - 1440x900@85Hz */ |
a6b21831 TR |
356 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, |
357 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
358 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 359 | /* 0x32 - 1440x900@120Hz RB */ |
a6b21831 TR |
360 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, |
361 | 1520, 1600, 0, 900, 903, 909, 953, 0, | |
362 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
363 | /* 0x53 - 1600x900@60Hz */ |
364 | { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, | |
365 | 1704, 1800, 0, 900, 901, 904, 1000, 0, | |
366 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 367 | /* 0x33 - 1600x1200@60Hz */ |
a6b21831 TR |
368 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, |
369 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
370 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 371 | /* 0x34 - 1600x1200@65Hz */ |
a6b21831 TR |
372 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, |
373 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
374 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 375 | /* 0x35 - 1600x1200@70Hz */ |
a6b21831 TR |
376 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, |
377 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
378 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 379 | /* 0x36 - 1600x1200@75Hz */ |
a6b21831 TR |
380 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, |
381 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
382 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 383 | /* 0x37 - 1600x1200@85Hz */ |
a6b21831 TR |
384 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, |
385 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
386 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 387 | /* 0x38 - 1600x1200@120Hz RB */ |
a6b21831 TR |
388 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, |
389 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, | |
390 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 391 | /* 0x39 - 1680x1050@60Hz RB */ |
a6b21831 TR |
392 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, |
393 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, | |
394 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 395 | /* 0x3a - 1680x1050@60Hz */ |
a6b21831 TR |
396 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, |
397 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
398 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 399 | /* 0x3b - 1680x1050@75Hz */ |
a6b21831 TR |
400 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, |
401 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
402 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 403 | /* 0x3c - 1680x1050@85Hz */ |
a6b21831 TR |
404 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, |
405 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
406 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 407 | /* 0x3d - 1680x1050@120Hz RB */ |
a6b21831 TR |
408 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, |
409 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, | |
410 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 411 | /* 0x3e - 1792x1344@60Hz */ |
a6b21831 TR |
412 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, |
413 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
414 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 415 | /* 0x3f - 1792x1344@75Hz */ |
a6b21831 TR |
416 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, |
417 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
418 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 419 | /* 0x40 - 1792x1344@120Hz RB */ |
a6b21831 TR |
420 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, |
421 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, | |
422 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 423 | /* 0x41 - 1856x1392@60Hz */ |
a6b21831 TR |
424 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, |
425 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
426 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 427 | /* 0x42 - 1856x1392@75Hz */ |
a6b21831 | 428 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, |
fcf22d05 | 429 | 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, |
a6b21831 | 430 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
24b856b1 | 431 | /* 0x43 - 1856x1392@120Hz RB */ |
a6b21831 TR |
432 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, |
433 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, | |
434 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
435 | /* 0x52 - 1920x1080@60Hz */ |
436 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
437 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
438 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 439 | /* 0x44 - 1920x1200@60Hz RB */ |
a6b21831 TR |
440 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, |
441 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, | |
442 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 443 | /* 0x45 - 1920x1200@60Hz */ |
a6b21831 TR |
444 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, |
445 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
446 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 447 | /* 0x46 - 1920x1200@75Hz */ |
a6b21831 TR |
448 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, |
449 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
450 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 451 | /* 0x47 - 1920x1200@85Hz */ |
a6b21831 TR |
452 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, |
453 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
454 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 455 | /* 0x48 - 1920x1200@120Hz RB */ |
a6b21831 TR |
456 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, |
457 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, | |
458 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 459 | /* 0x49 - 1920x1440@60Hz */ |
a6b21831 TR |
460 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, |
461 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
462 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 463 | /* 0x4a - 1920x1440@75Hz */ |
a6b21831 TR |
464 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, |
465 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
466 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 467 | /* 0x4b - 1920x1440@120Hz RB */ |
a6b21831 TR |
468 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, |
469 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, | |
470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
471 | /* 0x54 - 2048x1152@60Hz */ |
472 | { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, | |
473 | 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, | |
474 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 475 | /* 0x4c - 2560x1600@60Hz RB */ |
a6b21831 TR |
476 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, |
477 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, | |
478 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
24b856b1 | 479 | /* 0x4d - 2560x1600@60Hz */ |
a6b21831 TR |
480 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, |
481 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
482 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 483 | /* 0x4e - 2560x1600@75Hz */ |
a6b21831 TR |
484 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, |
485 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
486 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 487 | /* 0x4f - 2560x1600@85Hz */ |
a6b21831 TR |
488 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, |
489 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
490 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
24b856b1 | 491 | /* 0x50 - 2560x1600@120Hz RB */ |
a6b21831 TR |
492 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, |
493 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, | |
494 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
bfcd74d2 VS |
495 | /* 0x57 - 4096x2160@60Hz RB */ |
496 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, | |
497 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, | |
498 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
499 | /* 0x58 - 4096x2160@59.94Hz RB */ | |
500 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, | |
501 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, | |
502 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
a6b21831 TR |
503 | }; |
504 | ||
e7bfa5c4 VS |
505 | /* |
506 | * These more or less come from the DMT spec. The 720x400 modes are | |
507 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | |
508 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | |
509 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | |
510 | * mode. | |
511 | * | |
512 | * The DMT modes have been fact-checked; the rest are mild guesses. | |
513 | */ | |
a6b21831 TR |
514 | static const struct drm_display_mode edid_est_modes[] = { |
515 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
516 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
517 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
518 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
519 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
520 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
521 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
522 | 720, 840, 0, 480, 481, 484, 500, 0, | |
523 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
524 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
87707cfd | 525 | 704, 832, 0, 480, 489, 492, 520, 0, |
a6b21831 TR |
526 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ |
527 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
528 | 768, 864, 0, 480, 483, 486, 525, 0, | |
529 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
87707cfd | 530 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, |
a6b21831 TR |
531 | 752, 800, 0, 480, 490, 492, 525, 0, |
532 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
533 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
534 | 846, 900, 0, 400, 421, 423, 449, 0, | |
535 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
536 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
537 | 846, 900, 0, 400, 412, 414, 449, 0, | |
538 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
539 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
540 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
541 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
87707cfd | 542 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, |
a6b21831 TR |
543 | 1136, 1312, 0, 768, 769, 772, 800, 0, |
544 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
545 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
546 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
547 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
548 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
549 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
550 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
551 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
552 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
553 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
554 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
555 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
556 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
557 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
558 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
559 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
560 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
561 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
562 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
563 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
564 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
565 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
566 | }; | |
567 | ||
568 | struct minimode { | |
569 | short w; | |
570 | short h; | |
571 | short r; | |
572 | short rb; | |
573 | }; | |
574 | ||
575 | static const struct minimode est3_modes[] = { | |
576 | /* byte 6 */ | |
577 | { 640, 350, 85, 0 }, | |
578 | { 640, 400, 85, 0 }, | |
579 | { 720, 400, 85, 0 }, | |
580 | { 640, 480, 85, 0 }, | |
581 | { 848, 480, 60, 0 }, | |
582 | { 800, 600, 85, 0 }, | |
583 | { 1024, 768, 85, 0 }, | |
584 | { 1152, 864, 75, 0 }, | |
585 | /* byte 7 */ | |
586 | { 1280, 768, 60, 1 }, | |
587 | { 1280, 768, 60, 0 }, | |
588 | { 1280, 768, 75, 0 }, | |
589 | { 1280, 768, 85, 0 }, | |
590 | { 1280, 960, 60, 0 }, | |
591 | { 1280, 960, 85, 0 }, | |
592 | { 1280, 1024, 60, 0 }, | |
593 | { 1280, 1024, 85, 0 }, | |
594 | /* byte 8 */ | |
595 | { 1360, 768, 60, 0 }, | |
596 | { 1440, 900, 60, 1 }, | |
597 | { 1440, 900, 60, 0 }, | |
598 | { 1440, 900, 75, 0 }, | |
599 | { 1440, 900, 85, 0 }, | |
600 | { 1400, 1050, 60, 1 }, | |
601 | { 1400, 1050, 60, 0 }, | |
602 | { 1400, 1050, 75, 0 }, | |
603 | /* byte 9 */ | |
604 | { 1400, 1050, 85, 0 }, | |
605 | { 1680, 1050, 60, 1 }, | |
606 | { 1680, 1050, 60, 0 }, | |
607 | { 1680, 1050, 75, 0 }, | |
608 | { 1680, 1050, 85, 0 }, | |
609 | { 1600, 1200, 60, 0 }, | |
610 | { 1600, 1200, 65, 0 }, | |
611 | { 1600, 1200, 70, 0 }, | |
612 | /* byte 10 */ | |
613 | { 1600, 1200, 75, 0 }, | |
614 | { 1600, 1200, 85, 0 }, | |
615 | { 1792, 1344, 60, 0 }, | |
c068b32a | 616 | { 1792, 1344, 75, 0 }, |
a6b21831 TR |
617 | { 1856, 1392, 60, 0 }, |
618 | { 1856, 1392, 75, 0 }, | |
619 | { 1920, 1200, 60, 1 }, | |
620 | { 1920, 1200, 60, 0 }, | |
621 | /* byte 11 */ | |
622 | { 1920, 1200, 75, 0 }, | |
623 | { 1920, 1200, 85, 0 }, | |
624 | { 1920, 1440, 60, 0 }, | |
625 | { 1920, 1440, 75, 0 }, | |
626 | }; | |
627 | ||
628 | static const struct minimode extra_modes[] = { | |
629 | { 1024, 576, 60, 0 }, | |
630 | { 1366, 768, 60, 0 }, | |
631 | { 1600, 900, 60, 0 }, | |
632 | { 1680, 945, 60, 0 }, | |
633 | { 1920, 1080, 60, 0 }, | |
634 | { 2048, 1152, 60, 0 }, | |
635 | { 2048, 1536, 60, 0 }, | |
636 | }; | |
637 | ||
638 | /* | |
639 | * Probably taken from CEA-861 spec. | |
640 | * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. | |
d9278b4c JN |
641 | * |
642 | * Index using the VIC. | |
a6b21831 TR |
643 | */ |
644 | static const struct drm_display_mode edid_cea_modes[] = { | |
d9278b4c JN |
645 | /* 0 - dummy, VICs start at 1 */ |
646 | { }, | |
a6b21831 TR |
647 | /* 1 - 640x480@60Hz */ |
648 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
649 | 752, 800, 0, 480, 490, 492, 525, 0, | |
ee7925bb | 650 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 651 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
652 | /* 2 - 720x480@60Hz */ |
653 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
654 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 655 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 656 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
657 | /* 3 - 720x480@60Hz */ |
658 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
659 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 660 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 661 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
662 | /* 4 - 1280x720@60Hz */ |
663 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
664 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 665 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 666 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
667 | /* 5 - 1920x1080i@60Hz */ |
668 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
669 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
670 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 671 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 672 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
673 | /* 6 - 720(1440)x480i@60Hz */ |
674 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
675 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 676 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 677 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 678 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
679 | /* 7 - 720(1440)x480i@60Hz */ |
680 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
681 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 682 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 683 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 684 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
685 | /* 8 - 720(1440)x240@60Hz */ |
686 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
687 | 801, 858, 0, 240, 244, 247, 262, 0, | |
a6b21831 | 688 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 689 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 690 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
691 | /* 9 - 720(1440)x240@60Hz */ |
692 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, | |
693 | 801, 858, 0, 240, 244, 247, 262, 0, | |
a6b21831 | 694 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 695 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 696 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
697 | /* 10 - 2880x480i@60Hz */ |
698 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
699 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
700 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 701 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 702 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
703 | /* 11 - 2880x480i@60Hz */ |
704 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
705 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
706 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 707 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 708 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
709 | /* 12 - 2880x240@60Hz */ |
710 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
711 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 712 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 713 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
714 | /* 13 - 2880x240@60Hz */ |
715 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
716 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb | 717 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 718 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
719 | /* 14 - 1440x480@60Hz */ |
720 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
721 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 722 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 723 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
724 | /* 15 - 1440x480@60Hz */ |
725 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
726 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 727 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 728 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
729 | /* 16 - 1920x1080@60Hz */ |
730 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
731 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 732 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 733 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
734 | /* 17 - 720x576@50Hz */ |
735 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
736 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 737 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 738 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
739 | /* 18 - 720x576@50Hz */ |
740 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
741 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 742 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 743 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
744 | /* 19 - 1280x720@50Hz */ |
745 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, | |
746 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 747 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 748 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
749 | /* 20 - 1920x1080i@50Hz */ |
750 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
751 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
752 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 753 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 754 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
755 | /* 21 - 720(1440)x576i@50Hz */ |
756 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
757 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 758 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 759 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 760 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
761 | /* 22 - 720(1440)x576i@50Hz */ |
762 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
763 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 764 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 765 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 766 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
767 | /* 23 - 720(1440)x288@50Hz */ |
768 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
769 | 795, 864, 0, 288, 290, 293, 312, 0, | |
a6b21831 | 770 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 771 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 772 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
773 | /* 24 - 720(1440)x288@50Hz */ |
774 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, | |
775 | 795, 864, 0, 288, 290, 293, 312, 0, | |
a6b21831 | 776 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 777 | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 778 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
779 | /* 25 - 2880x576i@50Hz */ |
780 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
781 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
782 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 783 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 784 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
785 | /* 26 - 2880x576i@50Hz */ |
786 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
787 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
788 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 789 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 790 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
791 | /* 27 - 2880x288@50Hz */ |
792 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
793 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 794 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 795 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
796 | /* 28 - 2880x288@50Hz */ |
797 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
798 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb | 799 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 800 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
801 | /* 29 - 1440x576@50Hz */ |
802 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
803 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 804 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 805 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
806 | /* 30 - 1440x576@50Hz */ |
807 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
808 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 809 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 810 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
811 | /* 31 - 1920x1080@50Hz */ |
812 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
813 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 814 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 815 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
816 | /* 32 - 1920x1080@24Hz */ |
817 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, | |
818 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 819 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 820 | .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
821 | /* 33 - 1920x1080@25Hz */ |
822 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
823 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 824 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 825 | .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
826 | /* 34 - 1920x1080@30Hz */ |
827 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
828 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 829 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 830 | .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
831 | /* 35 - 2880x480@60Hz */ |
832 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
833 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 834 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 835 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
836 | /* 36 - 2880x480@60Hz */ |
837 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
838 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 839 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 840 | .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
841 | /* 37 - 2880x576@50Hz */ |
842 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
843 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 844 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 845 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
846 | /* 38 - 2880x576@50Hz */ |
847 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
848 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 849 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 850 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
851 | /* 39 - 1920x1080i@50Hz */ |
852 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, | |
853 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, | |
854 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb | 855 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 856 | .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
857 | /* 40 - 1920x1080i@100Hz */ |
858 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
859 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
860 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 861 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 862 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
863 | /* 41 - 1280x720@100Hz */ |
864 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, | |
865 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 866 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 867 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
868 | /* 42 - 720x576@100Hz */ |
869 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
870 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 871 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 872 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
873 | /* 43 - 720x576@100Hz */ |
874 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
875 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 876 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 877 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
878 | /* 44 - 720(1440)x576i@100Hz */ |
879 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
880 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 881 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
5a11f7f8 | 882 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 883 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
884 | /* 45 - 720(1440)x576i@100Hz */ |
885 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
886 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 887 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
5a11f7f8 | 888 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 889 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
890 | /* 46 - 1920x1080i@120Hz */ |
891 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
892 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
893 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb | 894 | DRM_MODE_FLAG_INTERLACE), |
985e5dc2 | 895 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
896 | /* 47 - 1280x720@120Hz */ |
897 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, | |
898 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 899 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 900 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
901 | /* 48 - 720x480@120Hz */ |
902 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
903 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 904 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 905 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
906 | /* 49 - 720x480@120Hz */ |
907 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
908 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 909 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 910 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
911 | /* 50 - 720(1440)x480i@120Hz */ |
912 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, | |
913 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 914 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 915 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 916 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
917 | /* 51 - 720(1440)x480i@120Hz */ |
918 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, | |
919 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 920 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 921 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 922 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
923 | /* 52 - 720x576@200Hz */ |
924 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
925 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 926 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 927 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
928 | /* 53 - 720x576@200Hz */ |
929 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
930 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb | 931 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 932 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
933 | /* 54 - 720(1440)x576i@200Hz */ |
934 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
935 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 936 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 937 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 938 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
939 | /* 55 - 720(1440)x576i@200Hz */ |
940 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
941 | 795, 864, 0, 576, 580, 586, 625, 0, | |
a6b21831 | 942 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 943 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 944 | .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
945 | /* 56 - 720x480@240Hz */ |
946 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
947 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 948 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 949 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
a6b21831 TR |
950 | /* 57 - 720x480@240Hz */ |
951 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
952 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb | 953 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
985e5dc2 | 954 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
fb01d280 CT |
955 | /* 58 - 720(1440)x480i@240 */ |
956 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, | |
957 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 958 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 959 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 960 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, |
fb01d280 CT |
961 | /* 59 - 720(1440)x480i@240 */ |
962 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, | |
963 | 801, 858, 0, 480, 488, 494, 525, 0, | |
a6b21831 | 964 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
ee7925bb | 965 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
985e5dc2 | 966 | .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
967 | /* 60 - 1280x720@24Hz */ |
968 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, | |
969 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 970 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 971 | .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
972 | /* 61 - 1280x720@25Hz */ |
973 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, | |
974 | 3740, 3960, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 975 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 976 | .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
977 | /* 62 - 1280x720@30Hz */ |
978 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, | |
979 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb | 980 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 981 | .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
982 | /* 63 - 1920x1080@120Hz */ |
983 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, | |
984 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb | 985 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 986 | .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
987 | /* 64 - 1920x1080@100Hz */ |
988 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, | |
989 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
ee7925bb | 990 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
985e5dc2 | 991 | .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, |
a6b21831 TR |
992 | }; |
993 | ||
7ebe1963 | 994 | /* |
d9278b4c | 995 | * HDMI 1.4 4k modes. Index using the VIC. |
7ebe1963 LD |
996 | */ |
997 | static const struct drm_display_mode edid_4k_modes[] = { | |
d9278b4c JN |
998 | /* 0 - dummy, VICs start at 1 */ |
999 | { }, | |
7ebe1963 LD |
1000 | /* 1 - 3840x2160@30Hz */ |
1001 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1002 | 3840, 4016, 4104, 4400, 0, | |
1003 | 2160, 2168, 2178, 2250, 0, | |
1004 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1005 | .vrefresh = 30, }, | |
1006 | /* 2 - 3840x2160@25Hz */ | |
1007 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1008 | 3840, 4896, 4984, 5280, 0, | |
1009 | 2160, 2168, 2178, 2250, 0, | |
1010 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1011 | .vrefresh = 25, }, | |
1012 | /* 3 - 3840x2160@24Hz */ | |
1013 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1014 | 3840, 5116, 5204, 5500, 0, | |
1015 | 2160, 2168, 2178, 2250, 0, | |
1016 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1017 | .vrefresh = 24, }, | |
1018 | /* 4 - 4096x2160@24Hz (SMPTE) */ | |
1019 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
1020 | 4096, 5116, 5204, 5500, 0, | |
1021 | 2160, 2168, 2178, 2250, 0, | |
1022 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
1023 | .vrefresh = 24, }, | |
1024 | }; | |
1025 | ||
61e57a8d | 1026 | /*** DDC fetch and block validation ***/ |
f453ba04 | 1027 | |
083ae056 AJ |
1028 | static const u8 edid_header[] = { |
1029 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
1030 | }; | |
f453ba04 | 1031 | |
db6cf833 TR |
1032 | /** |
1033 | * drm_edid_header_is_valid - sanity check the header of the base EDID block | |
1034 | * @raw_edid: pointer to raw base EDID block | |
1035 | * | |
1036 | * Sanity check the header of the base EDID block. | |
1037 | * | |
1038 | * Return: 8 if the header is perfect, down to 0 if it's totally wrong. | |
051963d4 TR |
1039 | */ |
1040 | int drm_edid_header_is_valid(const u8 *raw_edid) | |
1041 | { | |
1042 | int i, score = 0; | |
1043 | ||
1044 | for (i = 0; i < sizeof(edid_header); i++) | |
1045 | if (raw_edid[i] == edid_header[i]) | |
1046 | score++; | |
1047 | ||
1048 | return score; | |
1049 | } | |
1050 | EXPORT_SYMBOL(drm_edid_header_is_valid); | |
1051 | ||
47819ba2 AJ |
1052 | static int edid_fixup __read_mostly = 6; |
1053 | module_param_named(edid_fixup, edid_fixup, int, 0400); | |
1054 | MODULE_PARM_DESC(edid_fixup, | |
1055 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | |
051963d4 | 1056 | |
40d9b043 DA |
1057 | static void drm_get_displayid(struct drm_connector *connector, |
1058 | struct edid *edid); | |
da9df2f4 | 1059 | |
c465bbc8 SB |
1060 | static int drm_edid_block_checksum(const u8 *raw_edid) |
1061 | { | |
1062 | int i; | |
1063 | u8 csum = 0; | |
1064 | for (i = 0; i < EDID_LENGTH; i++) | |
1065 | csum += raw_edid[i]; | |
1066 | ||
1067 | return csum; | |
1068 | } | |
1069 | ||
d6885d65 SB |
1070 | static bool drm_edid_is_zero(const u8 *in_edid, int length) |
1071 | { | |
1072 | if (memchr_inv(in_edid, 0, length)) | |
1073 | return false; | |
1074 | ||
1075 | return true; | |
1076 | } | |
1077 | ||
db6cf833 TR |
1078 | /** |
1079 | * drm_edid_block_valid - Sanity check the EDID block (base or extension) | |
1080 | * @raw_edid: pointer to raw EDID block | |
1081 | * @block: type of block to validate (0 for base, extension otherwise) | |
1082 | * @print_bad_edid: if true, dump bad EDID blocks to the console | |
6ba2bd3d | 1083 | * @edid_corrupt: if true, the header or checksum is invalid |
db6cf833 TR |
1084 | * |
1085 | * Validate a base or extension EDID block and optionally dump bad blocks to | |
1086 | * the console. | |
1087 | * | |
1088 | * Return: True if the block is valid, false otherwise. | |
f453ba04 | 1089 | */ |
6ba2bd3d TP |
1090 | bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, |
1091 | bool *edid_corrupt) | |
f453ba04 | 1092 | { |
c465bbc8 | 1093 | u8 csum; |
61e57a8d | 1094 | struct edid *edid = (struct edid *)raw_edid; |
f453ba04 | 1095 | |
fe2ef780 SWK |
1096 | if (WARN_ON(!raw_edid)) |
1097 | return false; | |
1098 | ||
47819ba2 AJ |
1099 | if (edid_fixup > 8 || edid_fixup < 0) |
1100 | edid_fixup = 6; | |
1101 | ||
f89ec8a4 | 1102 | if (block == 0) { |
051963d4 | 1103 | int score = drm_edid_header_is_valid(raw_edid); |
6ba2bd3d TP |
1104 | if (score == 8) { |
1105 | if (edid_corrupt) | |
ac6f2e29 | 1106 | *edid_corrupt = false; |
6ba2bd3d TP |
1107 | } else if (score >= edid_fixup) { |
1108 | /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 | |
1109 | * The corrupt flag needs to be set here otherwise, the | |
1110 | * fix-up code here will correct the problem, the | |
1111 | * checksum is correct and the test fails | |
1112 | */ | |
1113 | if (edid_corrupt) | |
ac6f2e29 | 1114 | *edid_corrupt = true; |
61e57a8d AJ |
1115 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); |
1116 | memcpy(raw_edid, edid_header, sizeof(edid_header)); | |
1117 | } else { | |
6ba2bd3d | 1118 | if (edid_corrupt) |
ac6f2e29 | 1119 | *edid_corrupt = true; |
61e57a8d AJ |
1120 | goto bad; |
1121 | } | |
1122 | } | |
f453ba04 | 1123 | |
c465bbc8 | 1124 | csum = drm_edid_block_checksum(raw_edid); |
f453ba04 | 1125 | if (csum) { |
0b2443ed JG |
1126 | if (print_bad_edid) { |
1127 | DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); | |
1128 | } | |
4a638b4e | 1129 | |
6ba2bd3d | 1130 | if (edid_corrupt) |
ac6f2e29 | 1131 | *edid_corrupt = true; |
6ba2bd3d | 1132 | |
4a638b4e AJ |
1133 | /* allow CEA to slide through, switches mangle this */ |
1134 | if (raw_edid[0] != 0x02) | |
1135 | goto bad; | |
f453ba04 DA |
1136 | } |
1137 | ||
61e57a8d AJ |
1138 | /* per-block-type checks */ |
1139 | switch (raw_edid[0]) { | |
1140 | case 0: /* base */ | |
1141 | if (edid->version != 1) { | |
1142 | DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); | |
1143 | goto bad; | |
1144 | } | |
862b89c0 | 1145 | |
61e57a8d AJ |
1146 | if (edid->revision > 4) |
1147 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); | |
1148 | break; | |
862b89c0 | 1149 | |
61e57a8d AJ |
1150 | default: |
1151 | break; | |
1152 | } | |
47ee4ccf | 1153 | |
fe2ef780 | 1154 | return true; |
f453ba04 DA |
1155 | |
1156 | bad: | |
fe2ef780 | 1157 | if (print_bad_edid) { |
da4c07b7 SB |
1158 | if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { |
1159 | printk(KERN_ERR "EDID block is all zeroes\n"); | |
1160 | } else { | |
1161 | printk(KERN_ERR "Raw EDID:\n"); | |
1162 | print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, | |
0aff47f2 | 1163 | raw_edid, EDID_LENGTH, false); |
da4c07b7 | 1164 | } |
f453ba04 | 1165 | } |
fe2ef780 | 1166 | return false; |
f453ba04 | 1167 | } |
da0df92b | 1168 | EXPORT_SYMBOL(drm_edid_block_valid); |
61e57a8d AJ |
1169 | |
1170 | /** | |
1171 | * drm_edid_is_valid - sanity check EDID data | |
1172 | * @edid: EDID data | |
1173 | * | |
1174 | * Sanity-check an entire EDID record (including extensions) | |
db6cf833 TR |
1175 | * |
1176 | * Return: True if the EDID data is valid, false otherwise. | |
61e57a8d AJ |
1177 | */ |
1178 | bool drm_edid_is_valid(struct edid *edid) | |
1179 | { | |
1180 | int i; | |
1181 | u8 *raw = (u8 *)edid; | |
1182 | ||
1183 | if (!edid) | |
1184 | return false; | |
1185 | ||
1186 | for (i = 0; i <= edid->extensions; i++) | |
6ba2bd3d | 1187 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) |
61e57a8d AJ |
1188 | return false; |
1189 | ||
1190 | return true; | |
1191 | } | |
3c537889 | 1192 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 1193 | |
61e57a8d AJ |
1194 | #define DDC_SEGMENT_ADDR 0x30 |
1195 | /** | |
db6cf833 | 1196 | * drm_do_probe_ddc_edid() - get EDID information via I2C |
7c58e87e | 1197 | * @data: I2C device adapter |
fc66811c DV |
1198 | * @buf: EDID data buffer to be filled |
1199 | * @block: 128 byte EDID block to start fetching from | |
1200 | * @len: EDID data buffer length to fetch | |
1201 | * | |
db6cf833 | 1202 | * Try to fetch EDID information by calling I2C driver functions. |
61e57a8d | 1203 | * |
db6cf833 | 1204 | * Return: 0 on success or -1 on failure. |
61e57a8d AJ |
1205 | */ |
1206 | static int | |
18df89fe | 1207 | drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) |
61e57a8d | 1208 | { |
18df89fe | 1209 | struct i2c_adapter *adapter = data; |
61e57a8d | 1210 | unsigned char start = block * EDID_LENGTH; |
cd004b3f S |
1211 | unsigned char segment = block >> 1; |
1212 | unsigned char xfers = segment ? 3 : 2; | |
4819d2e4 CW |
1213 | int ret, retries = 5; |
1214 | ||
db6cf833 TR |
1215 | /* |
1216 | * The core I2C driver will automatically retry the transfer if the | |
4819d2e4 CW |
1217 | * adapter reports EAGAIN. However, we find that bit-banging transfers |
1218 | * are susceptible to errors under a heavily loaded machine and | |
1219 | * generate spurious NAKs and timeouts. Retrying the transfer | |
1220 | * of the individual block a few times seems to overcome this. | |
1221 | */ | |
1222 | do { | |
1223 | struct i2c_msg msgs[] = { | |
1224 | { | |
cd004b3f S |
1225 | .addr = DDC_SEGMENT_ADDR, |
1226 | .flags = 0, | |
1227 | .len = 1, | |
1228 | .buf = &segment, | |
1229 | }, { | |
4819d2e4 CW |
1230 | .addr = DDC_ADDR, |
1231 | .flags = 0, | |
1232 | .len = 1, | |
1233 | .buf = &start, | |
1234 | }, { | |
1235 | .addr = DDC_ADDR, | |
1236 | .flags = I2C_M_RD, | |
1237 | .len = len, | |
1238 | .buf = buf, | |
1239 | } | |
1240 | }; | |
cd004b3f | 1241 | |
db6cf833 TR |
1242 | /* |
1243 | * Avoid sending the segment addr to not upset non-compliant | |
1244 | * DDC monitors. | |
1245 | */ | |
cd004b3f S |
1246 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); |
1247 | ||
9292f37e ED |
1248 | if (ret == -ENXIO) { |
1249 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", | |
1250 | adapter->name); | |
1251 | break; | |
1252 | } | |
cd004b3f | 1253 | } while (ret != xfers && --retries); |
4819d2e4 | 1254 | |
cd004b3f | 1255 | return ret == xfers ? 0 : -1; |
61e57a8d AJ |
1256 | } |
1257 | ||
18df89fe LPC |
1258 | /** |
1259 | * drm_do_get_edid - get EDID data using a custom EDID block read function | |
1260 | * @connector: connector we're probing | |
1261 | * @get_edid_block: EDID block read function | |
1262 | * @data: private data passed to the block read function | |
1263 | * | |
1264 | * When the I2C adapter connected to the DDC bus is hidden behind a device that | |
1265 | * exposes a different interface to read EDID blocks this function can be used | |
1266 | * to get EDID data using a custom block read function. | |
1267 | * | |
1268 | * As in the general case the DDC bus is accessible by the kernel at the I2C | |
1269 | * level, drivers must make all reasonable efforts to expose it as an I2C | |
1270 | * adapter and use drm_get_edid() instead of abusing this function. | |
1271 | * | |
1272 | * Return: Pointer to valid EDID or NULL if we couldn't find any. | |
1273 | */ | |
1274 | struct edid *drm_do_get_edid(struct drm_connector *connector, | |
1275 | int (*get_edid_block)(void *data, u8 *buf, unsigned int block, | |
1276 | size_t len), | |
1277 | void *data) | |
61e57a8d | 1278 | { |
0ea75e23 | 1279 | int i, j = 0, valid_extensions = 0; |
61e57a8d | 1280 | u8 *block, *new; |
0b2443ed | 1281 | bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); |
61e57a8d AJ |
1282 | |
1283 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
1284 | return NULL; | |
1285 | ||
1286 | /* base block fetch */ | |
1287 | for (i = 0; i < 4; i++) { | |
18df89fe | 1288 | if (get_edid_block(data, block, 0, EDID_LENGTH)) |
61e57a8d | 1289 | goto out; |
6ba2bd3d TP |
1290 | if (drm_edid_block_valid(block, 0, print_bad_edid, |
1291 | &connector->edid_corrupt)) | |
61e57a8d | 1292 | break; |
4a9a8b71 DA |
1293 | if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { |
1294 | connector->null_edid_counter++; | |
1295 | goto carp; | |
1296 | } | |
61e57a8d AJ |
1297 | } |
1298 | if (i == 4) | |
1299 | goto carp; | |
1300 | ||
1301 | /* if there's no extensions, we're done */ | |
1302 | if (block[0x7e] == 0) | |
18df89fe | 1303 | return (struct edid *)block; |
61e57a8d AJ |
1304 | |
1305 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
1306 | if (!new) | |
1307 | goto out; | |
1308 | block = new; | |
1309 | ||
1310 | for (j = 1; j <= block[0x7e]; j++) { | |
1311 | for (i = 0; i < 4; i++) { | |
18df89fe | 1312 | if (get_edid_block(data, |
0ea75e23 ST |
1313 | block + (valid_extensions + 1) * EDID_LENGTH, |
1314 | j, EDID_LENGTH)) | |
61e57a8d | 1315 | goto out; |
6ba2bd3d TP |
1316 | if (drm_edid_block_valid(block + (valid_extensions + 1) |
1317 | * EDID_LENGTH, j, | |
1318 | print_bad_edid, | |
1319 | NULL)) { | |
0ea75e23 | 1320 | valid_extensions++; |
61e57a8d | 1321 | break; |
0ea75e23 | 1322 | } |
61e57a8d | 1323 | } |
f934ec8c ML |
1324 | |
1325 | if (i == 4 && print_bad_edid) { | |
0ea75e23 ST |
1326 | dev_warn(connector->dev->dev, |
1327 | "%s: Ignoring invalid EDID block %d.\n", | |
25933820 | 1328 | connector->name, j); |
f934ec8c ML |
1329 | |
1330 | connector->bad_edid_counter++; | |
1331 | } | |
0ea75e23 ST |
1332 | } |
1333 | ||
1334 | if (valid_extensions != block[0x7e]) { | |
1335 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; | |
1336 | block[0x7e] = valid_extensions; | |
1337 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1338 | if (!new) | |
1339 | goto out; | |
1340 | block = new; | |
61e57a8d AJ |
1341 | } |
1342 | ||
18df89fe | 1343 | return (struct edid *)block; |
61e57a8d AJ |
1344 | |
1345 | carp: | |
0b2443ed JG |
1346 | if (print_bad_edid) { |
1347 | dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", | |
25933820 | 1348 | connector->name, j); |
0b2443ed JG |
1349 | } |
1350 | connector->bad_edid_counter++; | |
61e57a8d AJ |
1351 | |
1352 | out: | |
1353 | kfree(block); | |
1354 | return NULL; | |
1355 | } | |
18df89fe | 1356 | EXPORT_SYMBOL_GPL(drm_do_get_edid); |
61e57a8d AJ |
1357 | |
1358 | /** | |
db6cf833 TR |
1359 | * drm_probe_ddc() - probe DDC presence |
1360 | * @adapter: I2C adapter to probe | |
fc66811c | 1361 | * |
db6cf833 | 1362 | * Return: True on success, false on failure. |
61e57a8d | 1363 | */ |
fbff4690 | 1364 | bool |
61e57a8d AJ |
1365 | drm_probe_ddc(struct i2c_adapter *adapter) |
1366 | { | |
1367 | unsigned char out; | |
1368 | ||
1369 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
1370 | } | |
fbff4690 | 1371 | EXPORT_SYMBOL(drm_probe_ddc); |
61e57a8d AJ |
1372 | |
1373 | /** | |
1374 | * drm_get_edid - get EDID data, if available | |
1375 | * @connector: connector we're probing | |
db6cf833 | 1376 | * @adapter: I2C adapter to use for DDC |
61e57a8d | 1377 | * |
db6cf833 | 1378 | * Poke the given I2C channel to grab EDID data if possible. If found, |
61e57a8d AJ |
1379 | * attach it to the connector. |
1380 | * | |
db6cf833 | 1381 | * Return: Pointer to valid EDID or NULL if we couldn't find any. |
61e57a8d AJ |
1382 | */ |
1383 | struct edid *drm_get_edid(struct drm_connector *connector, | |
1384 | struct i2c_adapter *adapter) | |
1385 | { | |
40d9b043 DA |
1386 | struct edid *edid; |
1387 | ||
18df89fe LPC |
1388 | if (!drm_probe_ddc(adapter)) |
1389 | return NULL; | |
61e57a8d | 1390 | |
40d9b043 DA |
1391 | edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); |
1392 | if (edid) | |
1393 | drm_get_displayid(connector, edid); | |
1394 | return edid; | |
61e57a8d AJ |
1395 | } |
1396 | EXPORT_SYMBOL(drm_get_edid); | |
1397 | ||
5cb8eaa2 LW |
1398 | /** |
1399 | * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output | |
1400 | * @connector: connector we're probing | |
1401 | * @adapter: I2C adapter to use for DDC | |
1402 | * | |
1403 | * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of | |
1404 | * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily | |
1405 | * switch DDC to the GPU which is retrieving EDID. | |
1406 | * | |
1407 | * Return: Pointer to valid EDID or %NULL if we couldn't find any. | |
1408 | */ | |
1409 | struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, | |
1410 | struct i2c_adapter *adapter) | |
1411 | { | |
1412 | struct pci_dev *pdev = connector->dev->pdev; | |
1413 | struct edid *edid; | |
1414 | ||
1415 | vga_switcheroo_lock_ddc(pdev); | |
1416 | edid = drm_get_edid(connector, adapter); | |
1417 | vga_switcheroo_unlock_ddc(pdev); | |
1418 | ||
1419 | return edid; | |
1420 | } | |
1421 | EXPORT_SYMBOL(drm_get_edid_switcheroo); | |
1422 | ||
51f8da59 JN |
1423 | /** |
1424 | * drm_edid_duplicate - duplicate an EDID and the extensions | |
1425 | * @edid: EDID to duplicate | |
1426 | * | |
db6cf833 | 1427 | * Return: Pointer to duplicated EDID or NULL on allocation failure. |
51f8da59 JN |
1428 | */ |
1429 | struct edid *drm_edid_duplicate(const struct edid *edid) | |
1430 | { | |
1431 | return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1432 | } | |
1433 | EXPORT_SYMBOL(drm_edid_duplicate); | |
1434 | ||
61e57a8d AJ |
1435 | /*** EDID parsing ***/ |
1436 | ||
f453ba04 DA |
1437 | /** |
1438 | * edid_vendor - match a string against EDID's obfuscated vendor field | |
1439 | * @edid: EDID to match | |
1440 | * @vendor: vendor string | |
1441 | * | |
1442 | * Returns true if @vendor is in @edid, false otherwise | |
1443 | */ | |
1444 | static bool edid_vendor(struct edid *edid, char *vendor) | |
1445 | { | |
1446 | char edid_vendor[3]; | |
1447 | ||
1448 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | |
1449 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | |
1450 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | |
16456c87 | 1451 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; |
f453ba04 DA |
1452 | |
1453 | return !strncmp(edid_vendor, vendor, 3); | |
1454 | } | |
1455 | ||
1456 | /** | |
1457 | * edid_get_quirks - return quirk flags for a given EDID | |
1458 | * @edid: EDID to process | |
1459 | * | |
1460 | * This tells subsequent routines what fixes they need to apply. | |
1461 | */ | |
1462 | static u32 edid_get_quirks(struct edid *edid) | |
1463 | { | |
1464 | struct edid_quirk *quirk; | |
1465 | int i; | |
1466 | ||
1467 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
1468 | quirk = &edid_quirk_list[i]; | |
1469 | ||
1470 | if (edid_vendor(edid, quirk->vendor) && | |
1471 | (EDID_PRODUCT_ID(edid) == quirk->product_id)) | |
1472 | return quirk->quirks; | |
1473 | } | |
1474 | ||
1475 | return 0; | |
1476 | } | |
1477 | ||
1478 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
339d202c | 1479 | #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) |
f453ba04 | 1480 | |
f453ba04 DA |
1481 | /** |
1482 | * edid_fixup_preferred - set preferred modes based on quirk list | |
1483 | * @connector: has mode list to fix up | |
1484 | * @quirks: quirks list | |
1485 | * | |
1486 | * Walk the mode list for @connector, clearing the preferred status | |
1487 | * on existing modes and setting it anew for the right mode ala @quirks. | |
1488 | */ | |
1489 | static void edid_fixup_preferred(struct drm_connector *connector, | |
1490 | u32 quirks) | |
1491 | { | |
1492 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 1493 | int target_refresh = 0; |
339d202c | 1494 | int cur_vrefresh, preferred_vrefresh; |
f453ba04 DA |
1495 | |
1496 | if (list_empty(&connector->probed_modes)) | |
1497 | return; | |
1498 | ||
1499 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
1500 | target_refresh = 60; | |
1501 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
1502 | target_refresh = 75; | |
1503 | ||
1504 | preferred_mode = list_first_entry(&connector->probed_modes, | |
1505 | struct drm_display_mode, head); | |
1506 | ||
1507 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
1508 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
1509 | ||
1510 | if (cur_mode == preferred_mode) | |
1511 | continue; | |
1512 | ||
1513 | /* Largest mode is preferred */ | |
1514 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
1515 | preferred_mode = cur_mode; | |
1516 | ||
339d202c AD |
1517 | cur_vrefresh = cur_mode->vrefresh ? |
1518 | cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); | |
1519 | preferred_vrefresh = preferred_mode->vrefresh ? | |
1520 | preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); | |
f453ba04 DA |
1521 | /* At a given size, try to get closest to target refresh */ |
1522 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
339d202c AD |
1523 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < |
1524 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { | |
f453ba04 DA |
1525 | preferred_mode = cur_mode; |
1526 | } | |
1527 | } | |
1528 | ||
1529 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
1530 | } | |
1531 | ||
f6e252ba AJ |
1532 | static bool |
1533 | mode_is_rb(const struct drm_display_mode *mode) | |
1534 | { | |
1535 | return (mode->htotal - mode->hdisplay == 160) && | |
1536 | (mode->hsync_end - mode->hdisplay == 80) && | |
1537 | (mode->hsync_end - mode->hsync_start == 32) && | |
1538 | (mode->vsync_start - mode->vdisplay == 3); | |
1539 | } | |
1540 | ||
33c7531d AJ |
1541 | /* |
1542 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | |
1543 | * @dev: Device to duplicate against | |
1544 | * @hsize: Mode width | |
1545 | * @vsize: Mode height | |
1546 | * @fresh: Mode refresh rate | |
f6e252ba | 1547 | * @rb: Mode reduced-blanking-ness |
33c7531d AJ |
1548 | * |
1549 | * Walk the DMT mode list looking for a match for the given parameters. | |
db6cf833 TR |
1550 | * |
1551 | * Return: A newly allocated copy of the mode, or NULL if not found. | |
33c7531d | 1552 | */ |
1d42bbc8 | 1553 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
f6e252ba AJ |
1554 | int hsize, int vsize, int fresh, |
1555 | bool rb) | |
559ee21d | 1556 | { |
07a5e632 | 1557 | int i; |
559ee21d | 1558 | |
a6b21831 | 1559 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
b1f559ec | 1560 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f8b46a05 AJ |
1561 | if (hsize != ptr->hdisplay) |
1562 | continue; | |
1563 | if (vsize != ptr->vdisplay) | |
1564 | continue; | |
1565 | if (fresh != drm_mode_vrefresh(ptr)) | |
1566 | continue; | |
f6e252ba AJ |
1567 | if (rb != mode_is_rb(ptr)) |
1568 | continue; | |
f8b46a05 AJ |
1569 | |
1570 | return drm_mode_duplicate(dev, ptr); | |
559ee21d | 1571 | } |
f8b46a05 AJ |
1572 | |
1573 | return NULL; | |
559ee21d | 1574 | } |
1d42bbc8 | 1575 | EXPORT_SYMBOL(drm_mode_find_dmt); |
23425cae | 1576 | |
d1ff6409 AJ |
1577 | typedef void detailed_cb(struct detailed_timing *timing, void *closure); |
1578 | ||
4d76a221 AJ |
1579 | static void |
1580 | cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1581 | { | |
1582 | int i, n = 0; | |
4966b2a9 | 1583 | u8 d = ext[0x02]; |
4d76a221 AJ |
1584 | u8 *det_base = ext + d; |
1585 | ||
4966b2a9 | 1586 | n = (127 - d) / 18; |
4d76a221 AJ |
1587 | for (i = 0; i < n; i++) |
1588 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1589 | } | |
1590 | ||
cbba98f8 AJ |
1591 | static void |
1592 | vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1593 | { | |
1594 | unsigned int i, n = min((int)ext[0x02], 6); | |
1595 | u8 *det_base = ext + 5; | |
1596 | ||
1597 | if (ext[0x01] != 1) | |
1598 | return; /* unknown version */ | |
1599 | ||
1600 | for (i = 0; i < n; i++) | |
1601 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1602 | } | |
1603 | ||
d1ff6409 AJ |
1604 | static void |
1605 | drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) | |
1606 | { | |
1607 | int i; | |
1608 | struct edid *edid = (struct edid *)raw_edid; | |
1609 | ||
1610 | if (edid == NULL) | |
1611 | return; | |
1612 | ||
1613 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) | |
1614 | cb(&(edid->detailed_timings[i]), closure); | |
1615 | ||
4d76a221 AJ |
1616 | for (i = 1; i <= raw_edid[0x7e]; i++) { |
1617 | u8 *ext = raw_edid + (i * EDID_LENGTH); | |
1618 | switch (*ext) { | |
1619 | case CEA_EXT: | |
1620 | cea_for_each_detailed_block(ext, cb, closure); | |
1621 | break; | |
cbba98f8 AJ |
1622 | case VTB_EXT: |
1623 | vtb_for_each_detailed_block(ext, cb, closure); | |
1624 | break; | |
4d76a221 AJ |
1625 | default: |
1626 | break; | |
1627 | } | |
1628 | } | |
d1ff6409 AJ |
1629 | } |
1630 | ||
1631 | static void | |
1632 | is_rb(struct detailed_timing *t, void *data) | |
1633 | { | |
1634 | u8 *r = (u8 *)t; | |
1635 | if (r[3] == EDID_DETAIL_MONITOR_RANGE) | |
1636 | if (r[15] & 0x10) | |
1637 | *(bool *)data = true; | |
1638 | } | |
1639 | ||
1640 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | |
1641 | static bool | |
1642 | drm_monitor_supports_rb(struct edid *edid) | |
1643 | { | |
1644 | if (edid->revision >= 4) { | |
b196a498 | 1645 | bool ret = false; |
d1ff6409 AJ |
1646 | drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); |
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); | |
1651 | } | |
1652 | ||
7a374350 AJ |
1653 | static void |
1654 | find_gtf2(struct detailed_timing *t, void *data) | |
1655 | { | |
1656 | u8 *r = (u8 *)t; | |
1657 | if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) | |
1658 | *(u8 **)data = r; | |
1659 | } | |
1660 | ||
1661 | /* Secondary GTF curve kicks in above some break frequency */ | |
1662 | static int | |
1663 | drm_gtf2_hbreak(struct edid *edid) | |
1664 | { | |
1665 | u8 *r = NULL; | |
1666 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1667 | return r ? (r[12] * 2) : 0; | |
1668 | } | |
1669 | ||
1670 | static int | |
1671 | drm_gtf2_2c(struct edid *edid) | |
1672 | { | |
1673 | u8 *r = NULL; | |
1674 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1675 | return r ? r[13] : 0; | |
1676 | } | |
1677 | ||
1678 | static int | |
1679 | drm_gtf2_m(struct edid *edid) | |
1680 | { | |
1681 | u8 *r = NULL; | |
1682 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1683 | return r ? (r[15] << 8) + r[14] : 0; | |
1684 | } | |
1685 | ||
1686 | static int | |
1687 | drm_gtf2_k(struct edid *edid) | |
1688 | { | |
1689 | u8 *r = NULL; | |
1690 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1691 | return r ? r[16] : 0; | |
1692 | } | |
1693 | ||
1694 | static int | |
1695 | drm_gtf2_2j(struct edid *edid) | |
1696 | { | |
1697 | u8 *r = NULL; | |
1698 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1699 | return r ? r[17] : 0; | |
1700 | } | |
1701 | ||
1702 | /** | |
1703 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | |
1704 | * @edid: EDID block to scan | |
1705 | */ | |
1706 | static int standard_timing_level(struct edid *edid) | |
1707 | { | |
1708 | if (edid->revision >= 2) { | |
1709 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
1710 | return LEVEL_CVT; | |
1711 | if (drm_gtf2_hbreak(edid)) | |
1712 | return LEVEL_GTF2; | |
1713 | return LEVEL_GTF; | |
1714 | } | |
1715 | return LEVEL_DMT; | |
1716 | } | |
1717 | ||
23425cae AJ |
1718 | /* |
1719 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
1720 | * monitors fill with ascii space (0x20) instead. | |
1721 | */ | |
1722 | static int | |
1723 | bad_std_timing(u8 a, u8 b) | |
1724 | { | |
1725 | return (a == 0x00 && b == 0x00) || | |
1726 | (a == 0x01 && b == 0x01) || | |
1727 | (a == 0x20 && b == 0x20); | |
1728 | } | |
1729 | ||
f453ba04 DA |
1730 | /** |
1731 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
fc66811c DV |
1732 | * @connector: connector of for the EDID block |
1733 | * @edid: EDID block to scan | |
f453ba04 DA |
1734 | * @t: standard timing params |
1735 | * | |
1736 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 1737 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 | 1738 | */ |
7ca6adb3 | 1739 | static struct drm_display_mode * |
7a374350 | 1740 | drm_mode_std(struct drm_connector *connector, struct edid *edid, |
464fdeca | 1741 | struct std_timing *t) |
f453ba04 | 1742 | { |
7ca6adb3 AJ |
1743 | struct drm_device *dev = connector->dev; |
1744 | struct drm_display_mode *m, *mode = NULL; | |
5c61259e ZY |
1745 | int hsize, vsize; |
1746 | int vrefresh_rate; | |
0454beab MD |
1747 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
1748 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
1749 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
1750 | >> EDID_TIMING_VFREQ_SHIFT; | |
7a374350 | 1751 | int timing_level = standard_timing_level(edid); |
5c61259e | 1752 | |
23425cae AJ |
1753 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
1754 | return NULL; | |
1755 | ||
5c61259e ZY |
1756 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
1757 | hsize = t->hsize * 8 + 248; | |
1758 | /* vrefresh_rate = vfreq + 60 */ | |
1759 | vrefresh_rate = vfreq + 60; | |
1760 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d | 1761 | if (aspect_ratio == 0) { |
464fdeca | 1762 | if (edid->revision < 3) |
f066a17d AJ |
1763 | vsize = hsize; |
1764 | else | |
1765 | vsize = (hsize * 10) / 16; | |
1766 | } else if (aspect_ratio == 1) | |
f453ba04 | 1767 | vsize = (hsize * 3) / 4; |
0454beab | 1768 | else if (aspect_ratio == 2) |
f453ba04 DA |
1769 | vsize = (hsize * 4) / 5; |
1770 | else | |
1771 | vsize = (hsize * 9) / 16; | |
a0910c8e AJ |
1772 | |
1773 | /* HDTV hack, part 1 */ | |
1774 | if (vrefresh_rate == 60 && | |
1775 | ((hsize == 1360 && vsize == 765) || | |
1776 | (hsize == 1368 && vsize == 769))) { | |
1777 | hsize = 1366; | |
1778 | vsize = 768; | |
1779 | } | |
1780 | ||
7ca6adb3 AJ |
1781 | /* |
1782 | * If this connector already has a mode for this size and refresh | |
1783 | * rate (because it came from detailed or CVT info), use that | |
1784 | * instead. This way we don't have to guess at interlace or | |
1785 | * reduced blanking. | |
1786 | */ | |
522032da | 1787 | list_for_each_entry(m, &connector->probed_modes, head) |
7ca6adb3 AJ |
1788 | if (m->hdisplay == hsize && m->vdisplay == vsize && |
1789 | drm_mode_vrefresh(m) == vrefresh_rate) | |
1790 | return NULL; | |
1791 | ||
a0910c8e AJ |
1792 | /* HDTV hack, part 2 */ |
1793 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | |
1794 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | |
d50ba256 | 1795 | false); |
559ee21d | 1796 | mode->hdisplay = 1366; |
a4967de6 AJ |
1797 | mode->hsync_start = mode->hsync_start - 1; |
1798 | mode->hsync_end = mode->hsync_end - 1; | |
559ee21d ZY |
1799 | return mode; |
1800 | } | |
a0910c8e | 1801 | |
559ee21d | 1802 | /* check whether it can be found in default mode table */ |
f6e252ba AJ |
1803 | if (drm_monitor_supports_rb(edid)) { |
1804 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | |
1805 | true); | |
1806 | if (mode) | |
1807 | return mode; | |
1808 | } | |
1809 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); | |
559ee21d ZY |
1810 | if (mode) |
1811 | return mode; | |
1812 | ||
f6e252ba | 1813 | /* okay, generate it */ |
5c61259e ZY |
1814 | switch (timing_level) { |
1815 | case LEVEL_DMT: | |
5c61259e ZY |
1816 | break; |
1817 | case LEVEL_GTF: | |
1818 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
1819 | break; | |
7a374350 AJ |
1820 | case LEVEL_GTF2: |
1821 | /* | |
1822 | * This is potentially wrong if there's ever a monitor with | |
1823 | * more than one ranges section, each claiming a different | |
1824 | * secondary GTF curve. Please don't do that. | |
1825 | */ | |
1826 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
fc48f169 TI |
1827 | if (!mode) |
1828 | return NULL; | |
7a374350 | 1829 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { |
aefd330e | 1830 | drm_mode_destroy(dev, mode); |
7a374350 AJ |
1831 | mode = drm_gtf_mode_complex(dev, hsize, vsize, |
1832 | vrefresh_rate, 0, 0, | |
1833 | drm_gtf2_m(edid), | |
1834 | drm_gtf2_2c(edid), | |
1835 | drm_gtf2_k(edid), | |
1836 | drm_gtf2_2j(edid)); | |
1837 | } | |
1838 | break; | |
5c61259e | 1839 | case LEVEL_CVT: |
d50ba256 DA |
1840 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
1841 | false); | |
5c61259e ZY |
1842 | break; |
1843 | } | |
f453ba04 DA |
1844 | return mode; |
1845 | } | |
1846 | ||
b58db2c6 AJ |
1847 | /* |
1848 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
1849 | * encoded. Our internal representation is of frame height, but some | |
1850 | * HDTV detailed timings are encoded as field height. | |
1851 | * | |
1852 | * The format list here is from CEA, in frame size. Technically we | |
1853 | * should be checking refresh rate too. Whatever. | |
1854 | */ | |
1855 | static void | |
1856 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
1857 | struct detailed_pixel_timing *pt) | |
1858 | { | |
1859 | int i; | |
1860 | static const struct { | |
1861 | int w, h; | |
1862 | } cea_interlaced[] = { | |
1863 | { 1920, 1080 }, | |
1864 | { 720, 480 }, | |
1865 | { 1440, 480 }, | |
1866 | { 2880, 480 }, | |
1867 | { 720, 576 }, | |
1868 | { 1440, 576 }, | |
1869 | { 2880, 576 }, | |
1870 | }; | |
b58db2c6 AJ |
1871 | |
1872 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
1873 | return; | |
1874 | ||
3c581411 | 1875 | for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { |
b58db2c6 AJ |
1876 | if ((mode->hdisplay == cea_interlaced[i].w) && |
1877 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
1878 | mode->vdisplay *= 2; | |
1879 | mode->vsync_start *= 2; | |
1880 | mode->vsync_end *= 2; | |
1881 | mode->vtotal *= 2; | |
1882 | mode->vtotal |= 1; | |
1883 | } | |
1884 | } | |
1885 | ||
1886 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1887 | } | |
1888 | ||
f453ba04 DA |
1889 | /** |
1890 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
1891 | * @dev: DRM device (needed to create new mode) | |
1892 | * @edid: EDID block | |
1893 | * @timing: EDID detailed timing info | |
1894 | * @quirks: quirks to apply | |
1895 | * | |
1896 | * An EDID detailed timing block contains enough info for us to create and | |
1897 | * return a new struct drm_display_mode. | |
1898 | */ | |
1899 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
1900 | struct edid *edid, | |
1901 | struct detailed_timing *timing, | |
1902 | u32 quirks) | |
1903 | { | |
1904 | struct drm_display_mode *mode; | |
1905 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | |
0454beab MD |
1906 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
1907 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
1908 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
1909 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
1910 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
1911 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
16dad1d7 | 1912 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; |
e14cbee4 | 1913 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); |
f453ba04 | 1914 | |
fc438966 | 1915 | /* ignore tiny modes */ |
0454beab | 1916 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
1917 | return NULL; |
1918 | ||
0454beab | 1919 | if (pt->misc & DRM_EDID_PT_STEREO) { |
c7d015f3 | 1920 | DRM_DEBUG_KMS("stereo mode not supported\n"); |
f453ba04 DA |
1921 | return NULL; |
1922 | } | |
0454beab | 1923 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
c7d015f3 | 1924 | DRM_DEBUG_KMS("composite sync not supported\n"); |
f453ba04 DA |
1925 | } |
1926 | ||
fcb45611 ZY |
1927 | /* it is incorrect if hsync/vsync width is zero */ |
1928 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
1929 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
1930 | "Wrong Hsync/Vsync pulse width\n"); | |
1931 | return NULL; | |
1932 | } | |
bc42aabc AJ |
1933 | |
1934 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { | |
1935 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); | |
1936 | if (!mode) | |
1937 | return NULL; | |
1938 | ||
1939 | goto set_size; | |
1940 | } | |
1941 | ||
f453ba04 DA |
1942 | mode = drm_mode_create(dev); |
1943 | if (!mode) | |
1944 | return NULL; | |
1945 | ||
f453ba04 | 1946 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) |
0454beab MD |
1947 | timing->pixel_clock = cpu_to_le16(1088); |
1948 | ||
1949 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
1950 | ||
1951 | mode->hdisplay = hactive; | |
1952 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
1953 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
1954 | mode->htotal = mode->hdisplay + hblank; | |
1955 | ||
1956 | mode->vdisplay = vactive; | |
1957 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
1958 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
1959 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 1960 | |
7064fef5 JB |
1961 | /* Some EDIDs have bogus h/vtotal values */ |
1962 | if (mode->hsync_end > mode->htotal) | |
1963 | mode->htotal = mode->hsync_end + 1; | |
1964 | if (mode->vsync_end > mode->vtotal) | |
1965 | mode->vtotal = mode->vsync_end + 1; | |
1966 | ||
b58db2c6 | 1967 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 DA |
1968 | |
1969 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { | |
0454beab | 1970 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; |
f453ba04 DA |
1971 | } |
1972 | ||
0454beab MD |
1973 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? |
1974 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
1975 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
1976 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 | 1977 | |
bc42aabc | 1978 | set_size: |
e14cbee4 MD |
1979 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
1980 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
1981 | |
1982 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
1983 | mode->width_mm *= 10; | |
1984 | mode->height_mm *= 10; | |
1985 | } | |
1986 | ||
1987 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
1988 | mode->width_mm = edid->width_cm * 10; | |
1989 | mode->height_mm = edid->height_cm * 10; | |
1990 | } | |
1991 | ||
bc42aabc | 1992 | mode->type = DRM_MODE_TYPE_DRIVER; |
c19b3b0f | 1993 | mode->vrefresh = drm_mode_vrefresh(mode); |
bc42aabc AJ |
1994 | drm_mode_set_name(mode); |
1995 | ||
f453ba04 DA |
1996 | return mode; |
1997 | } | |
1998 | ||
b17e52ef | 1999 | static bool |
b1f559ec CW |
2000 | mode_in_hsync_range(const struct drm_display_mode *mode, |
2001 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
2002 | { |
2003 | int hsync, hmin, hmax; | |
2004 | ||
2005 | hmin = t[7]; | |
2006 | if (edid->revision >= 4) | |
2007 | hmin += ((t[4] & 0x04) ? 255 : 0); | |
2008 | hmax = t[8]; | |
2009 | if (edid->revision >= 4) | |
2010 | hmax += ((t[4] & 0x08) ? 255 : 0); | |
07a5e632 | 2011 | hsync = drm_mode_hsync(mode); |
07a5e632 | 2012 | |
b17e52ef AJ |
2013 | return (hsync <= hmax && hsync >= hmin); |
2014 | } | |
2015 | ||
2016 | static bool | |
b1f559ec CW |
2017 | mode_in_vsync_range(const struct drm_display_mode *mode, |
2018 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
2019 | { |
2020 | int vsync, vmin, vmax; | |
2021 | ||
2022 | vmin = t[5]; | |
2023 | if (edid->revision >= 4) | |
2024 | vmin += ((t[4] & 0x01) ? 255 : 0); | |
2025 | vmax = t[6]; | |
2026 | if (edid->revision >= 4) | |
2027 | vmax += ((t[4] & 0x02) ? 255 : 0); | |
2028 | vsync = drm_mode_vrefresh(mode); | |
2029 | ||
2030 | return (vsync <= vmax && vsync >= vmin); | |
2031 | } | |
2032 | ||
2033 | static u32 | |
2034 | range_pixel_clock(struct edid *edid, u8 *t) | |
2035 | { | |
2036 | /* unspecified */ | |
2037 | if (t[9] == 0 || t[9] == 255) | |
2038 | return 0; | |
2039 | ||
2040 | /* 1.4 with CVT support gives us real precision, yay */ | |
2041 | if (edid->revision >= 4 && t[10] == 0x04) | |
2042 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | |
2043 | ||
2044 | /* 1.3 is pathetic, so fuzz up a bit */ | |
2045 | return t[9] * 10000 + 5001; | |
2046 | } | |
2047 | ||
b17e52ef | 2048 | static bool |
b1f559ec | 2049 | mode_in_range(const struct drm_display_mode *mode, struct edid *edid, |
b17e52ef AJ |
2050 | struct detailed_timing *timing) |
2051 | { | |
2052 | u32 max_clock; | |
2053 | u8 *t = (u8 *)timing; | |
2054 | ||
2055 | if (!mode_in_hsync_range(mode, edid, t)) | |
07a5e632 AJ |
2056 | return false; |
2057 | ||
b17e52ef | 2058 | if (!mode_in_vsync_range(mode, edid, t)) |
07a5e632 AJ |
2059 | return false; |
2060 | ||
b17e52ef | 2061 | if ((max_clock = range_pixel_clock(edid, t))) |
07a5e632 AJ |
2062 | if (mode->clock > max_clock) |
2063 | return false; | |
b17e52ef AJ |
2064 | |
2065 | /* 1.4 max horizontal check */ | |
2066 | if (edid->revision >= 4 && t[10] == 0x04) | |
2067 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | |
2068 | return false; | |
2069 | ||
2070 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | |
2071 | return false; | |
07a5e632 AJ |
2072 | |
2073 | return true; | |
2074 | } | |
2075 | ||
7b668ebe TI |
2076 | static bool valid_inferred_mode(const struct drm_connector *connector, |
2077 | const struct drm_display_mode *mode) | |
2078 | { | |
85f8fcd6 | 2079 | const struct drm_display_mode *m; |
7b668ebe TI |
2080 | bool ok = false; |
2081 | ||
2082 | list_for_each_entry(m, &connector->probed_modes, head) { | |
2083 | if (mode->hdisplay == m->hdisplay && | |
2084 | mode->vdisplay == m->vdisplay && | |
2085 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | |
2086 | return false; /* duplicated */ | |
2087 | if (mode->hdisplay <= m->hdisplay && | |
2088 | mode->vdisplay <= m->vdisplay) | |
2089 | ok = true; | |
2090 | } | |
2091 | return ok; | |
2092 | } | |
2093 | ||
b17e52ef | 2094 | static int |
cd4cd3de | 2095 | drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, |
b17e52ef | 2096 | struct detailed_timing *timing) |
07a5e632 AJ |
2097 | { |
2098 | int i, modes = 0; | |
2099 | struct drm_display_mode *newmode; | |
2100 | struct drm_device *dev = connector->dev; | |
2101 | ||
a6b21831 | 2102 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
7b668ebe TI |
2103 | if (mode_in_range(drm_dmt_modes + i, edid, timing) && |
2104 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | |
07a5e632 AJ |
2105 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); |
2106 | if (newmode) { | |
2107 | drm_mode_probed_add(connector, newmode); | |
2108 | modes++; | |
2109 | } | |
2110 | } | |
2111 | } | |
2112 | ||
2113 | return modes; | |
2114 | } | |
2115 | ||
c09dedb7 TI |
2116 | /* fix up 1366x768 mode from 1368x768; |
2117 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | |
2118 | */ | |
2119 | static void fixup_mode_1366x768(struct drm_display_mode *mode) | |
2120 | { | |
2121 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | |
2122 | mode->hdisplay = 1366; | |
2123 | mode->hsync_start--; | |
2124 | mode->hsync_end--; | |
2125 | drm_mode_set_name(mode); | |
2126 | } | |
2127 | } | |
2128 | ||
b309bd37 AJ |
2129 | static int |
2130 | drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2131 | struct detailed_timing *timing) | |
2132 | { | |
2133 | int i, modes = 0; | |
2134 | struct drm_display_mode *newmode; | |
2135 | struct drm_device *dev = connector->dev; | |
2136 | ||
a6b21831 | 2137 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2138 | const struct minimode *m = &extra_modes[i]; |
2139 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); | |
fc48f169 TI |
2140 | if (!newmode) |
2141 | return modes; | |
b309bd37 | 2142 | |
c09dedb7 | 2143 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2144 | if (!mode_in_range(newmode, edid, timing) || |
2145 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2146 | drm_mode_destroy(dev, newmode); |
2147 | continue; | |
2148 | } | |
2149 | ||
2150 | drm_mode_probed_add(connector, newmode); | |
2151 | modes++; | |
2152 | } | |
2153 | ||
2154 | return modes; | |
2155 | } | |
2156 | ||
2157 | static int | |
2158 | drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2159 | struct detailed_timing *timing) | |
2160 | { | |
2161 | int i, modes = 0; | |
2162 | struct drm_display_mode *newmode; | |
2163 | struct drm_device *dev = connector->dev; | |
2164 | bool rb = drm_monitor_supports_rb(edid); | |
2165 | ||
a6b21831 | 2166 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2167 | const struct minimode *m = &extra_modes[i]; |
2168 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); | |
fc48f169 TI |
2169 | if (!newmode) |
2170 | return modes; | |
b309bd37 | 2171 | |
c09dedb7 | 2172 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2173 | if (!mode_in_range(newmode, edid, timing) || |
2174 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2175 | drm_mode_destroy(dev, newmode); |
2176 | continue; | |
2177 | } | |
2178 | ||
2179 | drm_mode_probed_add(connector, newmode); | |
2180 | modes++; | |
2181 | } | |
2182 | ||
2183 | return modes; | |
2184 | } | |
2185 | ||
13931579 AJ |
2186 | static void |
2187 | do_inferred_modes(struct detailed_timing *timing, void *c) | |
9340d8cf | 2188 | { |
13931579 AJ |
2189 | struct detailed_mode_closure *closure = c; |
2190 | struct detailed_non_pixel *data = &timing->data.other_data; | |
b309bd37 | 2191 | struct detailed_data_monitor_range *range = &data->data.range; |
9340d8cf | 2192 | |
cb21aafe AJ |
2193 | if (data->type != EDID_DETAIL_MONITOR_RANGE) |
2194 | return; | |
2195 | ||
2196 | closure->modes += drm_dmt_modes_for_range(closure->connector, | |
2197 | closure->edid, | |
2198 | timing); | |
b309bd37 AJ |
2199 | |
2200 | if (!version_greater(closure->edid, 1, 1)) | |
2201 | return; /* GTF not defined yet */ | |
2202 | ||
2203 | switch (range->flags) { | |
2204 | case 0x02: /* secondary gtf, XXX could do more */ | |
2205 | case 0x00: /* default gtf */ | |
2206 | closure->modes += drm_gtf_modes_for_range(closure->connector, | |
2207 | closure->edid, | |
2208 | timing); | |
2209 | break; | |
2210 | case 0x04: /* cvt, only in 1.4+ */ | |
2211 | if (!version_greater(closure->edid, 1, 3)) | |
2212 | break; | |
2213 | ||
2214 | closure->modes += drm_cvt_modes_for_range(closure->connector, | |
2215 | closure->edid, | |
2216 | timing); | |
2217 | break; | |
2218 | case 0x01: /* just the ranges, no formula */ | |
2219 | default: | |
2220 | break; | |
2221 | } | |
13931579 | 2222 | } |
69da3015 | 2223 | |
13931579 AJ |
2224 | static int |
2225 | add_inferred_modes(struct drm_connector *connector, struct edid *edid) | |
2226 | { | |
2227 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2228 | .connector = connector, |
2229 | .edid = edid, | |
13931579 | 2230 | }; |
9340d8cf | 2231 | |
13931579 AJ |
2232 | if (version_greater(edid, 1, 0)) |
2233 | drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, | |
2234 | &closure); | |
9340d8cf | 2235 | |
13931579 | 2236 | return closure.modes; |
9340d8cf AJ |
2237 | } |
2238 | ||
2255be14 AJ |
2239 | static int |
2240 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | |
2241 | { | |
2242 | int i, j, m, modes = 0; | |
2243 | struct drm_display_mode *mode; | |
f3a32d74 | 2244 | u8 *est = ((u8 *)timing) + 6; |
2255be14 AJ |
2245 | |
2246 | for (i = 0; i < 6; i++) { | |
891a7469 | 2247 | for (j = 7; j >= 0; j--) { |
2255be14 | 2248 | m = (i * 8) + (7 - j); |
3c581411 | 2249 | if (m >= ARRAY_SIZE(est3_modes)) |
2255be14 AJ |
2250 | break; |
2251 | if (est[i] & (1 << j)) { | |
1d42bbc8 DA |
2252 | mode = drm_mode_find_dmt(connector->dev, |
2253 | est3_modes[m].w, | |
2254 | est3_modes[m].h, | |
f6e252ba AJ |
2255 | est3_modes[m].r, |
2256 | est3_modes[m].rb); | |
2255be14 AJ |
2257 | if (mode) { |
2258 | drm_mode_probed_add(connector, mode); | |
2259 | modes++; | |
2260 | } | |
2261 | } | |
2262 | } | |
2263 | } | |
2264 | ||
2265 | return modes; | |
2266 | } | |
2267 | ||
13931579 AJ |
2268 | static void |
2269 | do_established_modes(struct detailed_timing *timing, void *c) | |
9cf00977 | 2270 | { |
13931579 | 2271 | struct detailed_mode_closure *closure = c; |
9cf00977 | 2272 | struct detailed_non_pixel *data = &timing->data.other_data; |
9cf00977 | 2273 | |
13931579 AJ |
2274 | if (data->type == EDID_DETAIL_EST_TIMINGS) |
2275 | closure->modes += drm_est3_modes(closure->connector, timing); | |
2276 | } | |
9cf00977 | 2277 | |
13931579 AJ |
2278 | /** |
2279 | * add_established_modes - get est. modes from EDID and add them | |
db6cf833 | 2280 | * @connector: connector to add mode(s) to |
13931579 AJ |
2281 | * @edid: EDID block to scan |
2282 | * | |
2283 | * Each EDID block contains a bitmap of the supported "established modes" list | |
2284 | * (defined above). Tease them out and add them to the global modes list. | |
2285 | */ | |
2286 | static int | |
2287 | add_established_modes(struct drm_connector *connector, struct edid *edid) | |
2288 | { | |
2289 | struct drm_device *dev = connector->dev; | |
2290 | unsigned long est_bits = edid->established_timings.t1 | | |
2291 | (edid->established_timings.t2 << 8) | | |
2292 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
2293 | int i, modes = 0; | |
2294 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2295 | .connector = connector, |
2296 | .edid = edid, | |
13931579 | 2297 | }; |
9cf00977 | 2298 | |
13931579 AJ |
2299 | for (i = 0; i <= EDID_EST_TIMINGS; i++) { |
2300 | if (est_bits & (1<<i)) { | |
2301 | struct drm_display_mode *newmode; | |
2302 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | |
2303 | if (newmode) { | |
2304 | drm_mode_probed_add(connector, newmode); | |
2305 | modes++; | |
2306 | } | |
2307 | } | |
9cf00977 AJ |
2308 | } |
2309 | ||
13931579 AJ |
2310 | if (version_greater(edid, 1, 0)) |
2311 | drm_for_each_detailed_block((u8 *)edid, | |
2312 | do_established_modes, &closure); | |
2313 | ||
2314 | return modes + closure.modes; | |
2315 | } | |
2316 | ||
2317 | static void | |
2318 | do_standard_modes(struct detailed_timing *timing, void *c) | |
2319 | { | |
2320 | struct detailed_mode_closure *closure = c; | |
2321 | struct detailed_non_pixel *data = &timing->data.other_data; | |
2322 | struct drm_connector *connector = closure->connector; | |
2323 | struct edid *edid = closure->edid; | |
2324 | ||
2325 | if (data->type == EDID_DETAIL_STD_MODES) { | |
2326 | int i; | |
9cf00977 AJ |
2327 | for (i = 0; i < 6; i++) { |
2328 | struct std_timing *std; | |
2329 | struct drm_display_mode *newmode; | |
2330 | ||
2331 | std = &data->data.timings[i]; | |
464fdeca | 2332 | newmode = drm_mode_std(connector, edid, std); |
9cf00977 AJ |
2333 | if (newmode) { |
2334 | drm_mode_probed_add(connector, newmode); | |
13931579 | 2335 | closure->modes++; |
9cf00977 AJ |
2336 | } |
2337 | } | |
9cf00977 | 2338 | } |
9cf00977 AJ |
2339 | } |
2340 | ||
f453ba04 | 2341 | /** |
13931579 | 2342 | * add_standard_modes - get std. modes from EDID and add them |
db6cf833 | 2343 | * @connector: connector to add mode(s) to |
f453ba04 | 2344 | * @edid: EDID block to scan |
f453ba04 | 2345 | * |
13931579 AJ |
2346 | * Standard modes can be calculated using the appropriate standard (DMT, |
2347 | * GTF or CVT. Grab them from @edid and add them to the list. | |
f453ba04 | 2348 | */ |
13931579 AJ |
2349 | static int |
2350 | add_standard_modes(struct drm_connector *connector, struct edid *edid) | |
f453ba04 | 2351 | { |
9cf00977 | 2352 | int i, modes = 0; |
13931579 | 2353 | struct detailed_mode_closure closure = { |
d456ea2e JL |
2354 | .connector = connector, |
2355 | .edid = edid, | |
13931579 AJ |
2356 | }; |
2357 | ||
2358 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
2359 | struct drm_display_mode *newmode; | |
2360 | ||
2361 | newmode = drm_mode_std(connector, edid, | |
464fdeca | 2362 | &edid->standard_timings[i]); |
13931579 AJ |
2363 | if (newmode) { |
2364 | drm_mode_probed_add(connector, newmode); | |
2365 | modes++; | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | if (version_greater(edid, 1, 0)) | |
2370 | drm_for_each_detailed_block((u8 *)edid, do_standard_modes, | |
2371 | &closure); | |
2372 | ||
2373 | /* XXX should also look for standard codes in VTB blocks */ | |
2374 | ||
2375 | return modes + closure.modes; | |
2376 | } | |
f453ba04 | 2377 | |
13931579 AJ |
2378 | static int drm_cvt_modes(struct drm_connector *connector, |
2379 | struct detailed_timing *timing) | |
2380 | { | |
2381 | int i, j, modes = 0; | |
2382 | struct drm_display_mode *newmode; | |
2383 | struct drm_device *dev = connector->dev; | |
2384 | struct cvt_timing *cvt; | |
2385 | const int rates[] = { 60, 85, 75, 60, 50 }; | |
2386 | const u8 empty[3] = { 0, 0, 0 }; | |
a327f6b8 | 2387 | |
13931579 AJ |
2388 | for (i = 0; i < 4; i++) { |
2389 | int uninitialized_var(width), height; | |
2390 | cvt = &(timing->data.other_data.data.cvt[i]); | |
f453ba04 | 2391 | |
13931579 | 2392 | if (!memcmp(cvt->code, empty, 3)) |
9cf00977 | 2393 | continue; |
f453ba04 | 2394 | |
13931579 AJ |
2395 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
2396 | switch (cvt->code[1] & 0x0c) { | |
2397 | case 0x00: | |
2398 | width = height * 4 / 3; | |
2399 | break; | |
2400 | case 0x04: | |
2401 | width = height * 16 / 9; | |
2402 | break; | |
2403 | case 0x08: | |
2404 | width = height * 16 / 10; | |
2405 | break; | |
2406 | case 0x0c: | |
2407 | width = height * 15 / 9; | |
2408 | break; | |
2409 | } | |
2410 | ||
2411 | for (j = 1; j < 5; j++) { | |
2412 | if (cvt->code[2] & (1 << j)) { | |
2413 | newmode = drm_cvt_mode(dev, width, height, | |
2414 | rates[j], j == 0, | |
2415 | false, false); | |
2416 | if (newmode) { | |
2417 | drm_mode_probed_add(connector, newmode); | |
2418 | modes++; | |
2419 | } | |
2420 | } | |
2421 | } | |
f453ba04 DA |
2422 | } |
2423 | ||
2424 | return modes; | |
2425 | } | |
9cf00977 | 2426 | |
13931579 AJ |
2427 | static void |
2428 | do_cvt_mode(struct detailed_timing *timing, void *c) | |
882f0219 | 2429 | { |
13931579 AJ |
2430 | struct detailed_mode_closure *closure = c; |
2431 | struct detailed_non_pixel *data = &timing->data.other_data; | |
882f0219 | 2432 | |
13931579 AJ |
2433 | if (data->type == EDID_DETAIL_CVT_3BYTE) |
2434 | closure->modes += drm_cvt_modes(closure->connector, timing); | |
2435 | } | |
882f0219 | 2436 | |
13931579 AJ |
2437 | static int |
2438 | add_cvt_modes(struct drm_connector *connector, struct edid *edid) | |
2439 | { | |
2440 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2441 | .connector = connector, |
2442 | .edid = edid, | |
13931579 | 2443 | }; |
882f0219 | 2444 | |
13931579 AJ |
2445 | if (version_greater(edid, 1, 2)) |
2446 | drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); | |
882f0219 | 2447 | |
13931579 | 2448 | /* XXX should also look for CVT codes in VTB blocks */ |
882f0219 | 2449 | |
13931579 AJ |
2450 | return closure.modes; |
2451 | } | |
2452 | ||
fa3a7340 VS |
2453 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); |
2454 | ||
13931579 AJ |
2455 | static void |
2456 | do_detailed_mode(struct detailed_timing *timing, void *c) | |
2457 | { | |
2458 | struct detailed_mode_closure *closure = c; | |
2459 | struct drm_display_mode *newmode; | |
2460 | ||
2461 | if (timing->pixel_clock) { | |
2462 | newmode = drm_mode_detailed(closure->connector->dev, | |
2463 | closure->edid, timing, | |
2464 | closure->quirks); | |
2465 | if (!newmode) | |
2466 | return; | |
2467 | ||
2468 | if (closure->preferred) | |
2469 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
2470 | ||
fa3a7340 VS |
2471 | /* |
2472 | * Detailed modes are limited to 10kHz pixel clock resolution, | |
2473 | * so fix up anything that looks like CEA/HDMI mode, but the clock | |
2474 | * is just slightly off. | |
2475 | */ | |
2476 | fixup_detailed_cea_mode_clock(newmode); | |
2477 | ||
13931579 AJ |
2478 | drm_mode_probed_add(closure->connector, newmode); |
2479 | closure->modes++; | |
2480 | closure->preferred = 0; | |
882f0219 | 2481 | } |
13931579 | 2482 | } |
882f0219 | 2483 | |
13931579 AJ |
2484 | /* |
2485 | * add_detailed_modes - Add modes from detailed timings | |
2486 | * @connector: attached connector | |
2487 | * @edid: EDID block to scan | |
2488 | * @quirks: quirks to apply | |
2489 | */ | |
2490 | static int | |
2491 | add_detailed_modes(struct drm_connector *connector, struct edid *edid, | |
2492 | u32 quirks) | |
2493 | { | |
2494 | struct detailed_mode_closure closure = { | |
d456ea2e JL |
2495 | .connector = connector, |
2496 | .edid = edid, | |
2497 | .preferred = 1, | |
2498 | .quirks = quirks, | |
13931579 AJ |
2499 | }; |
2500 | ||
2501 | if (closure.preferred && !version_greater(edid, 1, 3)) | |
2502 | closure.preferred = | |
2503 | (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); | |
2504 | ||
2505 | drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); | |
2506 | ||
2507 | return closure.modes; | |
882f0219 | 2508 | } |
f453ba04 | 2509 | |
8fe9790d | 2510 | #define AUDIO_BLOCK 0x01 |
54ac76f8 | 2511 | #define VIDEO_BLOCK 0x02 |
f23c20c8 | 2512 | #define VENDOR_BLOCK 0x03 |
76adaa34 | 2513 | #define SPEAKER_BLOCK 0x04 |
b1edd6a6 | 2514 | #define VIDEO_CAPABILITY_BLOCK 0x07 |
8fe9790d | 2515 | #define EDID_BASIC_AUDIO (1 << 6) |
a988bc72 LPC |
2516 | #define EDID_CEA_YCRCB444 (1 << 5) |
2517 | #define EDID_CEA_YCRCB422 (1 << 4) | |
b1edd6a6 | 2518 | #define EDID_CEA_VCDB_QS (1 << 6) |
8fe9790d | 2519 | |
d4e4a31d | 2520 | /* |
8fe9790d | 2521 | * Search EDID for CEA extension block. |
f23c20c8 | 2522 | */ |
40d9b043 | 2523 | static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) |
f23c20c8 | 2524 | { |
8fe9790d ZW |
2525 | u8 *edid_ext = NULL; |
2526 | int i; | |
f23c20c8 ML |
2527 | |
2528 | /* No EDID or EDID extensions */ | |
2529 | if (edid == NULL || edid->extensions == 0) | |
8fe9790d | 2530 | return NULL; |
f23c20c8 | 2531 | |
f23c20c8 | 2532 | /* Find CEA extension */ |
7466f4cc | 2533 | for (i = 0; i < edid->extensions; i++) { |
8fe9790d | 2534 | edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); |
40d9b043 | 2535 | if (edid_ext[0] == ext_id) |
f23c20c8 ML |
2536 | break; |
2537 | } | |
2538 | ||
7466f4cc | 2539 | if (i == edid->extensions) |
8fe9790d ZW |
2540 | return NULL; |
2541 | ||
2542 | return edid_ext; | |
2543 | } | |
2544 | ||
40d9b043 DA |
2545 | static u8 *drm_find_cea_extension(struct edid *edid) |
2546 | { | |
2547 | return drm_find_edid_extension(edid, CEA_EXT); | |
2548 | } | |
2549 | ||
2550 | static u8 *drm_find_displayid_extension(struct edid *edid) | |
2551 | { | |
2552 | return drm_find_edid_extension(edid, DISPLAYID_EXT); | |
2553 | } | |
2554 | ||
e6e79209 VS |
2555 | /* |
2556 | * Calculate the alternate clock for the CEA mode | |
2557 | * (60Hz vs. 59.94Hz etc.) | |
2558 | */ | |
2559 | static unsigned int | |
2560 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | |
2561 | { | |
2562 | unsigned int clock = cea_mode->clock; | |
2563 | ||
2564 | if (cea_mode->vrefresh % 6 != 0) | |
2565 | return clock; | |
2566 | ||
2567 | /* | |
2568 | * edid_cea_modes contains the 59.94Hz | |
2569 | * variant for 240 and 480 line modes, | |
2570 | * and the 60Hz variant otherwise. | |
2571 | */ | |
2572 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | |
9afd808c | 2573 | clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); |
e6e79209 | 2574 | else |
9afd808c | 2575 | clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); |
e6e79209 VS |
2576 | |
2577 | return clock; | |
2578 | } | |
2579 | ||
4c6bcf44 VS |
2580 | static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, |
2581 | unsigned int clock_tolerance) | |
2582 | { | |
d9278b4c | 2583 | u8 vic; |
4c6bcf44 VS |
2584 | |
2585 | if (!to_match->clock) | |
2586 | return 0; | |
2587 | ||
d9278b4c JN |
2588 | for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { |
2589 | const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; | |
4c6bcf44 VS |
2590 | unsigned int clock1, clock2; |
2591 | ||
2592 | /* Check both 60Hz and 59.94Hz */ | |
2593 | clock1 = cea_mode->clock; | |
2594 | clock2 = cea_mode_alternate_clock(cea_mode); | |
2595 | ||
2596 | if (abs(to_match->clock - clock1) > clock_tolerance && | |
2597 | abs(to_match->clock - clock2) > clock_tolerance) | |
2598 | continue; | |
2599 | ||
2600 | if (drm_mode_equal_no_clocks(to_match, cea_mode)) | |
d9278b4c | 2601 | return vic; |
4c6bcf44 VS |
2602 | } |
2603 | ||
2604 | return 0; | |
2605 | } | |
2606 | ||
18316c8c TR |
2607 | /** |
2608 | * drm_match_cea_mode - look for a CEA mode matching given mode | |
2609 | * @to_match: display mode | |
2610 | * | |
db6cf833 | 2611 | * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 |
18316c8c | 2612 | * mode. |
a4799037 | 2613 | */ |
18316c8c | 2614 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) |
a4799037 | 2615 | { |
d9278b4c | 2616 | u8 vic; |
a4799037 | 2617 | |
a90b590e VS |
2618 | if (!to_match->clock) |
2619 | return 0; | |
2620 | ||
d9278b4c JN |
2621 | for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { |
2622 | const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; | |
a90b590e VS |
2623 | unsigned int clock1, clock2; |
2624 | ||
a90b590e | 2625 | /* Check both 60Hz and 59.94Hz */ |
e6e79209 VS |
2626 | clock1 = cea_mode->clock; |
2627 | clock2 = cea_mode_alternate_clock(cea_mode); | |
a4799037 | 2628 | |
a90b590e VS |
2629 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || |
2630 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2631 | drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) |
d9278b4c | 2632 | return vic; |
a4799037 SM |
2633 | } |
2634 | return 0; | |
2635 | } | |
2636 | EXPORT_SYMBOL(drm_match_cea_mode); | |
2637 | ||
d9278b4c JN |
2638 | static bool drm_valid_cea_vic(u8 vic) |
2639 | { | |
2640 | return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); | |
2641 | } | |
2642 | ||
0967e6a5 VK |
2643 | /** |
2644 | * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to | |
2645 | * the input VIC from the CEA mode list | |
2646 | * @video_code: ID given to each of the CEA modes | |
2647 | * | |
2648 | * Returns picture aspect ratio | |
2649 | */ | |
2650 | enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) | |
2651 | { | |
d9278b4c | 2652 | return edid_cea_modes[video_code].picture_aspect_ratio; |
0967e6a5 VK |
2653 | } |
2654 | EXPORT_SYMBOL(drm_get_cea_aspect_ratio); | |
2655 | ||
3f2f6533 LD |
2656 | /* |
2657 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | |
2658 | * specific block). | |
2659 | * | |
2660 | * It's almost like cea_mode_alternate_clock(), we just need to add an | |
2661 | * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this | |
2662 | * one. | |
2663 | */ | |
2664 | static unsigned int | |
2665 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | |
2666 | { | |
2667 | if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) | |
2668 | return hdmi_mode->clock; | |
2669 | ||
2670 | return cea_mode_alternate_clock(hdmi_mode); | |
2671 | } | |
2672 | ||
4c6bcf44 VS |
2673 | static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, |
2674 | unsigned int clock_tolerance) | |
2675 | { | |
d9278b4c | 2676 | u8 vic; |
4c6bcf44 VS |
2677 | |
2678 | if (!to_match->clock) | |
2679 | return 0; | |
2680 | ||
d9278b4c JN |
2681 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { |
2682 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | |
4c6bcf44 VS |
2683 | unsigned int clock1, clock2; |
2684 | ||
2685 | /* Make sure to also match alternate clocks */ | |
2686 | clock1 = hdmi_mode->clock; | |
2687 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
2688 | ||
2689 | if (abs(to_match->clock - clock1) > clock_tolerance && | |
2690 | abs(to_match->clock - clock2) > clock_tolerance) | |
2691 | continue; | |
2692 | ||
2693 | if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) | |
d9278b4c | 2694 | return vic; |
4c6bcf44 VS |
2695 | } |
2696 | ||
2697 | return 0; | |
2698 | } | |
2699 | ||
3f2f6533 LD |
2700 | /* |
2701 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | |
2702 | * @to_match: display mode | |
2703 | * | |
2704 | * An HDMI mode is one defined in the HDMI vendor specific block. | |
2705 | * | |
2706 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | |
2707 | */ | |
2708 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | |
2709 | { | |
d9278b4c | 2710 | u8 vic; |
3f2f6533 LD |
2711 | |
2712 | if (!to_match->clock) | |
2713 | return 0; | |
2714 | ||
d9278b4c JN |
2715 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { |
2716 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | |
3f2f6533 LD |
2717 | unsigned int clock1, clock2; |
2718 | ||
2719 | /* Make sure to also match alternate clocks */ | |
2720 | clock1 = hdmi_mode->clock; | |
2721 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
2722 | ||
2723 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || | |
2724 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2725 | drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) |
d9278b4c | 2726 | return vic; |
3f2f6533 LD |
2727 | } |
2728 | return 0; | |
2729 | } | |
2730 | ||
d9278b4c JN |
2731 | static bool drm_valid_hdmi_vic(u8 vic) |
2732 | { | |
2733 | return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); | |
2734 | } | |
2735 | ||
e6e79209 VS |
2736 | static int |
2737 | add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) | |
2738 | { | |
2739 | struct drm_device *dev = connector->dev; | |
2740 | struct drm_display_mode *mode, *tmp; | |
2741 | LIST_HEAD(list); | |
2742 | int modes = 0; | |
2743 | ||
2744 | /* Don't add CEA modes if the CEA extension block is missing */ | |
2745 | if (!drm_find_cea_extension(edid)) | |
2746 | return 0; | |
2747 | ||
2748 | /* | |
2749 | * Go through all probed modes and create a new mode | |
2750 | * with the alternate clock for certain CEA modes. | |
2751 | */ | |
2752 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
3f2f6533 | 2753 | const struct drm_display_mode *cea_mode = NULL; |
e6e79209 | 2754 | struct drm_display_mode *newmode; |
d9278b4c | 2755 | u8 vic = drm_match_cea_mode(mode); |
e6e79209 VS |
2756 | unsigned int clock1, clock2; |
2757 | ||
d9278b4c JN |
2758 | if (drm_valid_cea_vic(vic)) { |
2759 | cea_mode = &edid_cea_modes[vic]; | |
3f2f6533 LD |
2760 | clock2 = cea_mode_alternate_clock(cea_mode); |
2761 | } else { | |
d9278b4c JN |
2762 | vic = drm_match_hdmi_mode(mode); |
2763 | if (drm_valid_hdmi_vic(vic)) { | |
2764 | cea_mode = &edid_4k_modes[vic]; | |
3f2f6533 LD |
2765 | clock2 = hdmi_mode_alternate_clock(cea_mode); |
2766 | } | |
2767 | } | |
e6e79209 | 2768 | |
3f2f6533 LD |
2769 | if (!cea_mode) |
2770 | continue; | |
e6e79209 VS |
2771 | |
2772 | clock1 = cea_mode->clock; | |
e6e79209 VS |
2773 | |
2774 | if (clock1 == clock2) | |
2775 | continue; | |
2776 | ||
2777 | if (mode->clock != clock1 && mode->clock != clock2) | |
2778 | continue; | |
2779 | ||
2780 | newmode = drm_mode_duplicate(dev, cea_mode); | |
2781 | if (!newmode) | |
2782 | continue; | |
2783 | ||
27130212 DL |
2784 | /* Carry over the stereo flags */ |
2785 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; | |
2786 | ||
e6e79209 VS |
2787 | /* |
2788 | * The current mode could be either variant. Make | |
2789 | * sure to pick the "other" clock for the new mode. | |
2790 | */ | |
2791 | if (mode->clock != clock1) | |
2792 | newmode->clock = clock1; | |
2793 | else | |
2794 | newmode->clock = clock2; | |
2795 | ||
2796 | list_add_tail(&newmode->head, &list); | |
2797 | } | |
2798 | ||
2799 | list_for_each_entry_safe(mode, tmp, &list, head) { | |
2800 | list_del(&mode->head); | |
2801 | drm_mode_probed_add(connector, mode); | |
2802 | modes++; | |
2803 | } | |
2804 | ||
2805 | return modes; | |
2806 | } | |
a4799037 | 2807 | |
aff04ace TW |
2808 | static struct drm_display_mode * |
2809 | drm_display_mode_from_vic_index(struct drm_connector *connector, | |
2810 | const u8 *video_db, u8 video_len, | |
2811 | u8 video_index) | |
54ac76f8 CS |
2812 | { |
2813 | struct drm_device *dev = connector->dev; | |
aff04ace | 2814 | struct drm_display_mode *newmode; |
d9278b4c | 2815 | u8 vic; |
54ac76f8 | 2816 | |
aff04ace TW |
2817 | if (video_db == NULL || video_index >= video_len) |
2818 | return NULL; | |
2819 | ||
2820 | /* CEA modes are numbered 1..127 */ | |
d9278b4c JN |
2821 | vic = (video_db[video_index] & 127); |
2822 | if (!drm_valid_cea_vic(vic)) | |
aff04ace TW |
2823 | return NULL; |
2824 | ||
d9278b4c | 2825 | newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); |
409bbf1e DL |
2826 | if (!newmode) |
2827 | return NULL; | |
2828 | ||
aff04ace TW |
2829 | newmode->vrefresh = 0; |
2830 | ||
2831 | return newmode; | |
2832 | } | |
2833 | ||
2834 | static int | |
2835 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | |
2836 | { | |
2837 | int i, modes = 0; | |
2838 | ||
2839 | for (i = 0; i < len; i++) { | |
2840 | struct drm_display_mode *mode; | |
2841 | mode = drm_display_mode_from_vic_index(connector, db, len, i); | |
2842 | if (mode) { | |
2843 | drm_mode_probed_add(connector, mode); | |
2844 | modes++; | |
54ac76f8 CS |
2845 | } |
2846 | } | |
2847 | ||
2848 | return modes; | |
2849 | } | |
2850 | ||
c858cfca DL |
2851 | struct stereo_mandatory_mode { |
2852 | int width, height, vrefresh; | |
2853 | unsigned int flags; | |
2854 | }; | |
2855 | ||
2856 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | |
f7e121b7 DL |
2857 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2858 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
c858cfca DL |
2859 | { 1920, 1080, 50, |
2860 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
2861 | { 1920, 1080, 60, | |
2862 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
f7e121b7 DL |
2863 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2864 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
2865 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, | |
2866 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } | |
c858cfca DL |
2867 | }; |
2868 | ||
2869 | static bool | |
2870 | stereo_match_mandatory(const struct drm_display_mode *mode, | |
2871 | const struct stereo_mandatory_mode *stereo_mode) | |
2872 | { | |
2873 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
2874 | ||
2875 | return mode->hdisplay == stereo_mode->width && | |
2876 | mode->vdisplay == stereo_mode->height && | |
2877 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && | |
2878 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | |
2879 | } | |
2880 | ||
c858cfca DL |
2881 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) |
2882 | { | |
2883 | struct drm_device *dev = connector->dev; | |
2884 | const struct drm_display_mode *mode; | |
2885 | struct list_head stereo_modes; | |
f7e121b7 | 2886 | int modes = 0, i; |
c858cfca DL |
2887 | |
2888 | INIT_LIST_HEAD(&stereo_modes); | |
2889 | ||
2890 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
f7e121b7 DL |
2891 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { |
2892 | const struct stereo_mandatory_mode *mandatory; | |
c858cfca DL |
2893 | struct drm_display_mode *new_mode; |
2894 | ||
f7e121b7 DL |
2895 | if (!stereo_match_mandatory(mode, |
2896 | &stereo_mandatory_modes[i])) | |
2897 | continue; | |
c858cfca | 2898 | |
f7e121b7 | 2899 | mandatory = &stereo_mandatory_modes[i]; |
c858cfca DL |
2900 | new_mode = drm_mode_duplicate(dev, mode); |
2901 | if (!new_mode) | |
2902 | continue; | |
2903 | ||
f7e121b7 | 2904 | new_mode->flags |= mandatory->flags; |
c858cfca DL |
2905 | list_add_tail(&new_mode->head, &stereo_modes); |
2906 | modes++; | |
f7e121b7 | 2907 | } |
c858cfca DL |
2908 | } |
2909 | ||
2910 | list_splice_tail(&stereo_modes, &connector->probed_modes); | |
2911 | ||
2912 | return modes; | |
2913 | } | |
2914 | ||
1deee8d7 DL |
2915 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) |
2916 | { | |
2917 | struct drm_device *dev = connector->dev; | |
2918 | struct drm_display_mode *newmode; | |
2919 | ||
d9278b4c | 2920 | if (!drm_valid_hdmi_vic(vic)) { |
1deee8d7 DL |
2921 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic); |
2922 | return 0; | |
2923 | } | |
2924 | ||
2925 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | |
2926 | if (!newmode) | |
2927 | return 0; | |
2928 | ||
2929 | drm_mode_probed_add(connector, newmode); | |
2930 | ||
2931 | return 1; | |
2932 | } | |
2933 | ||
fbf46025 TW |
2934 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, |
2935 | const u8 *video_db, u8 video_len, u8 video_index) | |
2936 | { | |
fbf46025 TW |
2937 | struct drm_display_mode *newmode; |
2938 | int modes = 0; | |
fbf46025 TW |
2939 | |
2940 | if (structure & (1 << 0)) { | |
aff04ace TW |
2941 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2942 | video_len, | |
2943 | video_index); | |
fbf46025 TW |
2944 | if (newmode) { |
2945 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; | |
2946 | drm_mode_probed_add(connector, newmode); | |
2947 | modes++; | |
2948 | } | |
2949 | } | |
2950 | if (structure & (1 << 6)) { | |
aff04ace TW |
2951 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2952 | video_len, | |
2953 | video_index); | |
fbf46025 TW |
2954 | if (newmode) { |
2955 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
2956 | drm_mode_probed_add(connector, newmode); | |
2957 | modes++; | |
2958 | } | |
2959 | } | |
2960 | if (structure & (1 << 8)) { | |
aff04ace TW |
2961 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2962 | video_len, | |
2963 | video_index); | |
fbf46025 | 2964 | if (newmode) { |
89570eeb | 2965 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; |
fbf46025 TW |
2966 | drm_mode_probed_add(connector, newmode); |
2967 | modes++; | |
2968 | } | |
2969 | } | |
2970 | ||
2971 | return modes; | |
2972 | } | |
2973 | ||
7ebe1963 LD |
2974 | /* |
2975 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | |
2976 | * @connector: connector corresponding to the HDMI sink | |
2977 | * @db: start of the CEA vendor specific block | |
2978 | * @len: length of the CEA block payload, ie. one can access up to db[len] | |
2979 | * | |
c858cfca DL |
2980 | * Parses the HDMI VSDB looking for modes to add to @connector. This function |
2981 | * also adds the stereo 3d modes when applicable. | |
7ebe1963 LD |
2982 | */ |
2983 | static int | |
fbf46025 TW |
2984 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, |
2985 | const u8 *video_db, u8 video_len) | |
7ebe1963 | 2986 | { |
0e5083aa | 2987 | int modes = 0, offset = 0, i, multi_present = 0, multi_len; |
fbf46025 TW |
2988 | u8 vic_len, hdmi_3d_len = 0; |
2989 | u16 mask; | |
2990 | u16 structure_all; | |
7ebe1963 LD |
2991 | |
2992 | if (len < 8) | |
2993 | goto out; | |
2994 | ||
2995 | /* no HDMI_Video_Present */ | |
2996 | if (!(db[8] & (1 << 5))) | |
2997 | goto out; | |
2998 | ||
2999 | /* Latency_Fields_Present */ | |
3000 | if (db[8] & (1 << 7)) | |
3001 | offset += 2; | |
3002 | ||
3003 | /* I_Latency_Fields_Present */ | |
3004 | if (db[8] & (1 << 6)) | |
3005 | offset += 2; | |
3006 | ||
3007 | /* the declared length is not long enough for the 2 first bytes | |
3008 | * of additional video format capabilities */ | |
c858cfca | 3009 | if (len < (8 + offset + 2)) |
7ebe1963 LD |
3010 | goto out; |
3011 | ||
c858cfca DL |
3012 | /* 3D_Present */ |
3013 | offset++; | |
fbf46025 | 3014 | if (db[8 + offset] & (1 << 7)) { |
c858cfca DL |
3015 | modes += add_hdmi_mandatory_stereo_modes(connector); |
3016 | ||
fbf46025 TW |
3017 | /* 3D_Multi_present */ |
3018 | multi_present = (db[8 + offset] & 0x60) >> 5; | |
3019 | } | |
3020 | ||
c858cfca | 3021 | offset++; |
7ebe1963 | 3022 | vic_len = db[8 + offset] >> 5; |
fbf46025 | 3023 | hdmi_3d_len = db[8 + offset] & 0x1f; |
7ebe1963 LD |
3024 | |
3025 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | |
7ebe1963 LD |
3026 | u8 vic; |
3027 | ||
3028 | vic = db[9 + offset + i]; | |
1deee8d7 | 3029 | modes += add_hdmi_mode(connector, vic); |
7ebe1963 | 3030 | } |
fbf46025 TW |
3031 | offset += 1 + vic_len; |
3032 | ||
0e5083aa TW |
3033 | if (multi_present == 1) |
3034 | multi_len = 2; | |
3035 | else if (multi_present == 2) | |
3036 | multi_len = 4; | |
3037 | else | |
3038 | multi_len = 0; | |
fbf46025 | 3039 | |
0e5083aa | 3040 | if (len < (8 + offset + hdmi_3d_len - 1)) |
fbf46025 TW |
3041 | goto out; |
3042 | ||
0e5083aa | 3043 | if (hdmi_3d_len < multi_len) |
fbf46025 TW |
3044 | goto out; |
3045 | ||
0e5083aa TW |
3046 | if (multi_present == 1 || multi_present == 2) { |
3047 | /* 3D_Structure_ALL */ | |
3048 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | |
fbf46025 | 3049 | |
0e5083aa TW |
3050 | /* check if 3D_MASK is present */ |
3051 | if (multi_present == 2) | |
3052 | mask = (db[10 + offset] << 8) | db[11 + offset]; | |
3053 | else | |
3054 | mask = 0xffff; | |
3055 | ||
3056 | for (i = 0; i < 16; i++) { | |
3057 | if (mask & (1 << i)) | |
3058 | modes += add_3d_struct_modes(connector, | |
3059 | structure_all, | |
3060 | video_db, | |
3061 | video_len, i); | |
3062 | } | |
3063 | } | |
3064 | ||
3065 | offset += multi_len; | |
3066 | ||
3067 | for (i = 0; i < (hdmi_3d_len - multi_len); i++) { | |
3068 | int vic_index; | |
3069 | struct drm_display_mode *newmode = NULL; | |
3070 | unsigned int newflag = 0; | |
3071 | bool detail_present; | |
3072 | ||
3073 | detail_present = ((db[8 + offset + i] & 0x0f) > 7); | |
3074 | ||
3075 | if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) | |
3076 | break; | |
3077 | ||
3078 | /* 2D_VIC_order_X */ | |
3079 | vic_index = db[8 + offset + i] >> 4; | |
3080 | ||
3081 | /* 3D_Structure_X */ | |
3082 | switch (db[8 + offset + i] & 0x0f) { | |
3083 | case 0: | |
3084 | newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; | |
3085 | break; | |
3086 | case 6: | |
3087 | newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
3088 | break; | |
3089 | case 8: | |
3090 | /* 3D_Detail_X */ | |
3091 | if ((db[9 + offset + i] >> 4) == 1) | |
3092 | newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; | |
3093 | break; | |
3094 | } | |
3095 | ||
3096 | if (newflag != 0) { | |
3097 | newmode = drm_display_mode_from_vic_index(connector, | |
3098 | video_db, | |
3099 | video_len, | |
3100 | vic_index); | |
3101 | ||
3102 | if (newmode) { | |
3103 | newmode->flags |= newflag; | |
3104 | drm_mode_probed_add(connector, newmode); | |
3105 | modes++; | |
3106 | } | |
3107 | } | |
3108 | ||
3109 | if (detail_present) | |
3110 | i++; | |
fbf46025 | 3111 | } |
7ebe1963 LD |
3112 | |
3113 | out: | |
3114 | return modes; | |
3115 | } | |
3116 | ||
9e50b9d5 VS |
3117 | static int |
3118 | cea_db_payload_len(const u8 *db) | |
3119 | { | |
3120 | return db[0] & 0x1f; | |
3121 | } | |
3122 | ||
3123 | static int | |
3124 | cea_db_tag(const u8 *db) | |
3125 | { | |
3126 | return db[0] >> 5; | |
3127 | } | |
3128 | ||
3129 | static int | |
3130 | cea_revision(const u8 *cea) | |
3131 | { | |
3132 | return cea[1]; | |
3133 | } | |
3134 | ||
3135 | static int | |
3136 | cea_db_offsets(const u8 *cea, int *start, int *end) | |
3137 | { | |
3138 | /* Data block offset in CEA extension block */ | |
3139 | *start = 4; | |
3140 | *end = cea[2]; | |
3141 | if (*end == 0) | |
3142 | *end = 127; | |
3143 | if (*end < 4 || *end > 127) | |
3144 | return -ERANGE; | |
3145 | return 0; | |
3146 | } | |
3147 | ||
7ebe1963 LD |
3148 | static bool cea_db_is_hdmi_vsdb(const u8 *db) |
3149 | { | |
3150 | int hdmi_id; | |
3151 | ||
3152 | if (cea_db_tag(db) != VENDOR_BLOCK) | |
3153 | return false; | |
3154 | ||
3155 | if (cea_db_payload_len(db) < 5) | |
3156 | return false; | |
3157 | ||
3158 | hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); | |
3159 | ||
6cb3b7f1 | 3160 | return hdmi_id == HDMI_IEEE_OUI; |
7ebe1963 LD |
3161 | } |
3162 | ||
9e50b9d5 VS |
3163 | #define for_each_cea_db(cea, i, start, end) \ |
3164 | for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) | |
3165 | ||
54ac76f8 CS |
3166 | static int |
3167 | add_cea_modes(struct drm_connector *connector, struct edid *edid) | |
3168 | { | |
13ac3f55 | 3169 | const u8 *cea = drm_find_cea_extension(edid); |
fbf46025 TW |
3170 | const u8 *db, *hdmi = NULL, *video = NULL; |
3171 | u8 dbl, hdmi_len, video_len = 0; | |
54ac76f8 CS |
3172 | int modes = 0; |
3173 | ||
9e50b9d5 VS |
3174 | if (cea && cea_revision(cea) >= 3) { |
3175 | int i, start, end; | |
3176 | ||
3177 | if (cea_db_offsets(cea, &start, &end)) | |
3178 | return 0; | |
3179 | ||
3180 | for_each_cea_db(cea, i, start, end) { | |
3181 | db = &cea[i]; | |
3182 | dbl = cea_db_payload_len(db); | |
3183 | ||
fbf46025 TW |
3184 | if (cea_db_tag(db) == VIDEO_BLOCK) { |
3185 | video = db + 1; | |
3186 | video_len = dbl; | |
3187 | modes += do_cea_modes(connector, video, dbl); | |
3188 | } | |
c858cfca DL |
3189 | else if (cea_db_is_hdmi_vsdb(db)) { |
3190 | hdmi = db; | |
3191 | hdmi_len = dbl; | |
3192 | } | |
54ac76f8 CS |
3193 | } |
3194 | } | |
3195 | ||
c858cfca DL |
3196 | /* |
3197 | * We parse the HDMI VSDB after having added the cea modes as we will | |
3198 | * be patching their flags when the sink supports stereo 3D. | |
3199 | */ | |
3200 | if (hdmi) | |
fbf46025 TW |
3201 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, |
3202 | video_len); | |
c858cfca | 3203 | |
54ac76f8 CS |
3204 | return modes; |
3205 | } | |
3206 | ||
fa3a7340 VS |
3207 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) |
3208 | { | |
3209 | const struct drm_display_mode *cea_mode; | |
3210 | int clock1, clock2, clock; | |
d9278b4c | 3211 | u8 vic; |
fa3a7340 VS |
3212 | const char *type; |
3213 | ||
4c6bcf44 VS |
3214 | /* |
3215 | * allow 5kHz clock difference either way to account for | |
3216 | * the 10kHz clock resolution limit of detailed timings. | |
3217 | */ | |
d9278b4c JN |
3218 | vic = drm_match_cea_mode_clock_tolerance(mode, 5); |
3219 | if (drm_valid_cea_vic(vic)) { | |
fa3a7340 | 3220 | type = "CEA"; |
d9278b4c | 3221 | cea_mode = &edid_cea_modes[vic]; |
fa3a7340 VS |
3222 | clock1 = cea_mode->clock; |
3223 | clock2 = cea_mode_alternate_clock(cea_mode); | |
3224 | } else { | |
d9278b4c JN |
3225 | vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); |
3226 | if (drm_valid_hdmi_vic(vic)) { | |
fa3a7340 | 3227 | type = "HDMI"; |
d9278b4c | 3228 | cea_mode = &edid_4k_modes[vic]; |
fa3a7340 VS |
3229 | clock1 = cea_mode->clock; |
3230 | clock2 = hdmi_mode_alternate_clock(cea_mode); | |
3231 | } else { | |
3232 | return; | |
3233 | } | |
3234 | } | |
3235 | ||
3236 | /* pick whichever is closest */ | |
3237 | if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) | |
3238 | clock = clock1; | |
3239 | else | |
3240 | clock = clock2; | |
3241 | ||
3242 | if (mode->clock == clock) | |
3243 | return; | |
3244 | ||
3245 | DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", | |
d9278b4c | 3246 | type, vic, mode->clock, clock); |
fa3a7340 VS |
3247 | mode->clock = clock; |
3248 | } | |
3249 | ||
76adaa34 | 3250 | static void |
8504072a | 3251 | parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) |
76adaa34 | 3252 | { |
8504072a | 3253 | u8 len = cea_db_payload_len(db); |
76adaa34 | 3254 | |
8504072a VS |
3255 | if (len >= 6) { |
3256 | connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ | |
3257 | connector->dvi_dual = db[6] & 1; | |
3258 | } | |
3259 | if (len >= 7) | |
3260 | connector->max_tmds_clock = db[7] * 5; | |
3261 | if (len >= 8) { | |
3262 | connector->latency_present[0] = db[8] >> 7; | |
3263 | connector->latency_present[1] = (db[8] >> 6) & 1; | |
3264 | } | |
3265 | if (len >= 9) | |
3266 | connector->video_latency[0] = db[9]; | |
3267 | if (len >= 10) | |
3268 | connector->audio_latency[0] = db[10]; | |
3269 | if (len >= 11) | |
3270 | connector->video_latency[1] = db[11]; | |
3271 | if (len >= 12) | |
3272 | connector->audio_latency[1] = db[12]; | |
76adaa34 | 3273 | |
670c1ef6 | 3274 | DRM_DEBUG_KMS("HDMI: DVI dual %d, " |
76adaa34 WF |
3275 | "max TMDS clock %d, " |
3276 | "latency present %d %d, " | |
3277 | "video latency %d %d, " | |
3278 | "audio latency %d %d\n", | |
3279 | connector->dvi_dual, | |
3280 | connector->max_tmds_clock, | |
3281 | (int) connector->latency_present[0], | |
3282 | (int) connector->latency_present[1], | |
3283 | connector->video_latency[0], | |
3284 | connector->video_latency[1], | |
3285 | connector->audio_latency[0], | |
3286 | connector->audio_latency[1]); | |
3287 | } | |
3288 | ||
3289 | static void | |
3290 | monitor_name(struct detailed_timing *t, void *data) | |
3291 | { | |
3292 | if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) | |
3293 | *(u8 **)data = t->data.other_data.data.str.str; | |
14f77fdd VS |
3294 | } |
3295 | ||
59f7c0fa JB |
3296 | static int get_monitor_name(struct edid *edid, char name[13]) |
3297 | { | |
3298 | char *edid_name = NULL; | |
3299 | int mnl; | |
3300 | ||
3301 | if (!edid || !name) | |
3302 | return 0; | |
3303 | ||
3304 | drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); | |
3305 | for (mnl = 0; edid_name && mnl < 13; mnl++) { | |
3306 | if (edid_name[mnl] == 0x0a) | |
3307 | break; | |
3308 | ||
3309 | name[mnl] = edid_name[mnl]; | |
3310 | } | |
3311 | ||
3312 | return mnl; | |
3313 | } | |
3314 | ||
3315 | /** | |
3316 | * drm_edid_get_monitor_name - fetch the monitor name from the edid | |
3317 | * @edid: monitor EDID information | |
3318 | * @name: pointer to a character array to hold the name of the monitor | |
3319 | * @bufsize: The size of the name buffer (should be at least 14 chars.) | |
3320 | * | |
3321 | */ | |
3322 | void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) | |
3323 | { | |
3324 | int name_length; | |
3325 | char buf[13]; | |
3326 | ||
3327 | if (bufsize <= 0) | |
3328 | return; | |
3329 | ||
3330 | name_length = min(get_monitor_name(edid, buf), bufsize - 1); | |
3331 | memcpy(name, buf, name_length); | |
3332 | name[name_length] = '\0'; | |
3333 | } | |
3334 | EXPORT_SYMBOL(drm_edid_get_monitor_name); | |
3335 | ||
76adaa34 WF |
3336 | /** |
3337 | * drm_edid_to_eld - build ELD from EDID | |
3338 | * @connector: connector corresponding to the HDMI/DP sink | |
3339 | * @edid: EDID to parse | |
3340 | * | |
db6cf833 TR |
3341 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The |
3342 | * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to | |
3343 | * fill in. | |
76adaa34 WF |
3344 | */ |
3345 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) | |
3346 | { | |
3347 | uint8_t *eld = connector->eld; | |
3348 | u8 *cea; | |
76adaa34 | 3349 | u8 *db; |
7c018782 | 3350 | int total_sad_count = 0; |
76adaa34 WF |
3351 | int mnl; |
3352 | int dbl; | |
3353 | ||
3354 | memset(eld, 0, sizeof(connector->eld)); | |
3355 | ||
3356 | cea = drm_find_cea_extension(edid); | |
3357 | if (!cea) { | |
3358 | DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); | |
3359 | return; | |
3360 | } | |
3361 | ||
59f7c0fa JB |
3362 | mnl = get_monitor_name(edid, eld + 20); |
3363 | ||
76adaa34 WF |
3364 | eld[4] = (cea[1] << 5) | mnl; |
3365 | DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); | |
3366 | ||
3367 | eld[0] = 2 << 3; /* ELD version: 2 */ | |
3368 | ||
3369 | eld[16] = edid->mfg_id[0]; | |
3370 | eld[17] = edid->mfg_id[1]; | |
3371 | eld[18] = edid->prod_code[0]; | |
3372 | eld[19] = edid->prod_code[1]; | |
3373 | ||
9e50b9d5 VS |
3374 | if (cea_revision(cea) >= 3) { |
3375 | int i, start, end; | |
3376 | ||
3377 | if (cea_db_offsets(cea, &start, &end)) { | |
3378 | start = 0; | |
3379 | end = 0; | |
3380 | } | |
3381 | ||
3382 | for_each_cea_db(cea, i, start, end) { | |
3383 | db = &cea[i]; | |
3384 | dbl = cea_db_payload_len(db); | |
3385 | ||
3386 | switch (cea_db_tag(db)) { | |
7c018782 VS |
3387 | int sad_count; |
3388 | ||
a0ab734d CS |
3389 | case AUDIO_BLOCK: |
3390 | /* Audio Data Block, contains SADs */ | |
7c018782 VS |
3391 | sad_count = min(dbl / 3, 15 - total_sad_count); |
3392 | if (sad_count >= 1) | |
3393 | memcpy(eld + 20 + mnl + total_sad_count * 3, | |
3394 | &db[1], sad_count * 3); | |
3395 | total_sad_count += sad_count; | |
a0ab734d CS |
3396 | break; |
3397 | case SPEAKER_BLOCK: | |
9e50b9d5 VS |
3398 | /* Speaker Allocation Data Block */ |
3399 | if (dbl >= 1) | |
3400 | eld[7] = db[1]; | |
a0ab734d CS |
3401 | break; |
3402 | case VENDOR_BLOCK: | |
3403 | /* HDMI Vendor-Specific Data Block */ | |
14f77fdd | 3404 | if (cea_db_is_hdmi_vsdb(db)) |
a0ab734d CS |
3405 | parse_hdmi_vsdb(connector, db); |
3406 | break; | |
3407 | default: | |
3408 | break; | |
3409 | } | |
76adaa34 | 3410 | } |
9e50b9d5 | 3411 | } |
7c018782 | 3412 | eld[5] |= total_sad_count << 4; |
76adaa34 | 3413 | |
938fd8aa JN |
3414 | eld[DRM_ELD_BASELINE_ELD_LEN] = |
3415 | DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); | |
3416 | ||
3417 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", | |
7c018782 | 3418 | drm_eld_size(eld), total_sad_count); |
76adaa34 WF |
3419 | } |
3420 | EXPORT_SYMBOL(drm_edid_to_eld); | |
3421 | ||
fe214163 RM |
3422 | /** |
3423 | * drm_edid_to_sad - extracts SADs from EDID | |
3424 | * @edid: EDID to parse | |
3425 | * @sads: pointer that will be set to the extracted SADs | |
3426 | * | |
3427 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | |
fe214163 | 3428 | * |
db6cf833 TR |
3429 | * Note: The returned pointer needs to be freed using kfree(). |
3430 | * | |
3431 | * Return: The number of found SADs or negative number on error. | |
fe214163 RM |
3432 | */ |
3433 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) | |
3434 | { | |
3435 | int count = 0; | |
3436 | int i, start, end, dbl; | |
3437 | u8 *cea; | |
3438 | ||
3439 | cea = drm_find_cea_extension(edid); | |
3440 | if (!cea) { | |
3441 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3442 | return -ENOENT; | |
3443 | } | |
3444 | ||
3445 | if (cea_revision(cea) < 3) { | |
3446 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3447 | return -ENOTSUPP; | |
3448 | } | |
3449 | ||
3450 | if (cea_db_offsets(cea, &start, &end)) { | |
3451 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3452 | return -EPROTO; | |
3453 | } | |
3454 | ||
3455 | for_each_cea_db(cea, i, start, end) { | |
3456 | u8 *db = &cea[i]; | |
3457 | ||
3458 | if (cea_db_tag(db) == AUDIO_BLOCK) { | |
3459 | int j; | |
3460 | dbl = cea_db_payload_len(db); | |
3461 | ||
3462 | count = dbl / 3; /* SAD is 3B */ | |
3463 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); | |
3464 | if (!*sads) | |
3465 | return -ENOMEM; | |
3466 | for (j = 0; j < count; j++) { | |
3467 | u8 *sad = &db[1 + j * 3]; | |
3468 | ||
3469 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | |
3470 | (*sads)[j].channels = sad[0] & 0x7; | |
3471 | (*sads)[j].freq = sad[1] & 0x7F; | |
3472 | (*sads)[j].byte2 = sad[2]; | |
3473 | } | |
3474 | break; | |
3475 | } | |
3476 | } | |
3477 | ||
3478 | return count; | |
3479 | } | |
3480 | EXPORT_SYMBOL(drm_edid_to_sad); | |
3481 | ||
d105f476 AD |
3482 | /** |
3483 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | |
3484 | * @edid: EDID to parse | |
3485 | * @sadb: pointer to the speaker block | |
3486 | * | |
3487 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | |
d105f476 | 3488 | * |
db6cf833 TR |
3489 | * Note: The returned pointer needs to be freed using kfree(). |
3490 | * | |
3491 | * Return: The number of found Speaker Allocation Blocks or negative number on | |
3492 | * error. | |
d105f476 AD |
3493 | */ |
3494 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) | |
3495 | { | |
3496 | int count = 0; | |
3497 | int i, start, end, dbl; | |
3498 | const u8 *cea; | |
3499 | ||
3500 | cea = drm_find_cea_extension(edid); | |
3501 | if (!cea) { | |
3502 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3503 | return -ENOENT; | |
3504 | } | |
3505 | ||
3506 | if (cea_revision(cea) < 3) { | |
3507 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3508 | return -ENOTSUPP; | |
3509 | } | |
3510 | ||
3511 | if (cea_db_offsets(cea, &start, &end)) { | |
3512 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3513 | return -EPROTO; | |
3514 | } | |
3515 | ||
3516 | for_each_cea_db(cea, i, start, end) { | |
3517 | const u8 *db = &cea[i]; | |
3518 | ||
3519 | if (cea_db_tag(db) == SPEAKER_BLOCK) { | |
3520 | dbl = cea_db_payload_len(db); | |
3521 | ||
3522 | /* Speaker Allocation Data Block */ | |
3523 | if (dbl == 3) { | |
89086bca | 3524 | *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); |
618e3776 AD |
3525 | if (!*sadb) |
3526 | return -ENOMEM; | |
d105f476 AD |
3527 | count = dbl; |
3528 | break; | |
3529 | } | |
3530 | } | |
3531 | } | |
3532 | ||
3533 | return count; | |
3534 | } | |
3535 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | |
3536 | ||
76adaa34 | 3537 | /** |
db6cf833 | 3538 | * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay |
76adaa34 WF |
3539 | * @connector: connector associated with the HDMI/DP sink |
3540 | * @mode: the display mode | |
db6cf833 TR |
3541 | * |
3542 | * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if | |
3543 | * the sink doesn't support audio or video. | |
76adaa34 WF |
3544 | */ |
3545 | int drm_av_sync_delay(struct drm_connector *connector, | |
3a818d35 | 3546 | const struct drm_display_mode *mode) |
76adaa34 WF |
3547 | { |
3548 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); | |
3549 | int a, v; | |
3550 | ||
3551 | if (!connector->latency_present[0]) | |
3552 | return 0; | |
3553 | if (!connector->latency_present[1]) | |
3554 | i = 0; | |
3555 | ||
3556 | a = connector->audio_latency[i]; | |
3557 | v = connector->video_latency[i]; | |
3558 | ||
3559 | /* | |
3560 | * HDMI/DP sink doesn't support audio or video? | |
3561 | */ | |
3562 | if (a == 255 || v == 255) | |
3563 | return 0; | |
3564 | ||
3565 | /* | |
3566 | * Convert raw EDID values to millisecond. | |
3567 | * Treat unknown latency as 0ms. | |
3568 | */ | |
3569 | if (a) | |
3570 | a = min(2 * (a - 1), 500); | |
3571 | if (v) | |
3572 | v = min(2 * (v - 1), 500); | |
3573 | ||
3574 | return max(v - a, 0); | |
3575 | } | |
3576 | EXPORT_SYMBOL(drm_av_sync_delay); | |
3577 | ||
3578 | /** | |
3579 | * drm_select_eld - select one ELD from multiple HDMI/DP sinks | |
3580 | * @encoder: the encoder just changed display mode | |
76adaa34 WF |
3581 | * |
3582 | * It's possible for one encoder to be associated with multiple HDMI/DP sinks. | |
3583 | * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. | |
db6cf833 TR |
3584 | * |
3585 | * Return: The connector associated with the first HDMI/DP sink that has ELD | |
3586 | * attached to it. | |
76adaa34 | 3587 | */ |
9e5a3b52 | 3588 | struct drm_connector *drm_select_eld(struct drm_encoder *encoder) |
76adaa34 WF |
3589 | { |
3590 | struct drm_connector *connector; | |
3591 | struct drm_device *dev = encoder->dev; | |
3592 | ||
6e9f798d | 3593 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
008f4045 | 3594 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
6e9f798d | 3595 | |
9a9f5ce8 | 3596 | drm_for_each_connector(connector, dev) |
76adaa34 WF |
3597 | if (connector->encoder == encoder && connector->eld[0]) |
3598 | return connector; | |
3599 | ||
3600 | return NULL; | |
3601 | } | |
3602 | EXPORT_SYMBOL(drm_select_eld); | |
3603 | ||
8fe9790d | 3604 | /** |
db6cf833 | 3605 | * drm_detect_hdmi_monitor - detect whether monitor is HDMI |
8fe9790d ZW |
3606 | * @edid: monitor EDID information |
3607 | * | |
3608 | * Parse the CEA extension according to CEA-861-B. | |
db6cf833 TR |
3609 | * |
3610 | * Return: True if the monitor is HDMI, false if not or unknown. | |
8fe9790d ZW |
3611 | */ |
3612 | bool drm_detect_hdmi_monitor(struct edid *edid) | |
3613 | { | |
3614 | u8 *edid_ext; | |
14f77fdd | 3615 | int i; |
8fe9790d | 3616 | int start_offset, end_offset; |
8fe9790d ZW |
3617 | |
3618 | edid_ext = drm_find_cea_extension(edid); | |
3619 | if (!edid_ext) | |
14f77fdd | 3620 | return false; |
f23c20c8 | 3621 | |
9e50b9d5 | 3622 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
14f77fdd | 3623 | return false; |
f23c20c8 ML |
3624 | |
3625 | /* | |
3626 | * Because HDMI identifier is in Vendor Specific Block, | |
3627 | * search it from all data blocks of CEA extension. | |
3628 | */ | |
9e50b9d5 | 3629 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
14f77fdd VS |
3630 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) |
3631 | return true; | |
f23c20c8 ML |
3632 | } |
3633 | ||
14f77fdd | 3634 | return false; |
f23c20c8 ML |
3635 | } |
3636 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
3637 | ||
8fe9790d ZW |
3638 | /** |
3639 | * drm_detect_monitor_audio - check monitor audio capability | |
fc66811c | 3640 | * @edid: EDID block to scan |
8fe9790d ZW |
3641 | * |
3642 | * Monitor should have CEA extension block. | |
3643 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | |
3644 | * audio' only. If there is any audio extension block and supported | |
3645 | * audio format, assume at least 'basic audio' support, even if 'basic | |
3646 | * audio' is not defined in EDID. | |
3647 | * | |
db6cf833 | 3648 | * Return: True if the monitor supports audio, false otherwise. |
8fe9790d ZW |
3649 | */ |
3650 | bool drm_detect_monitor_audio(struct edid *edid) | |
3651 | { | |
3652 | u8 *edid_ext; | |
3653 | int i, j; | |
3654 | bool has_audio = false; | |
3655 | int start_offset, end_offset; | |
3656 | ||
3657 | edid_ext = drm_find_cea_extension(edid); | |
3658 | if (!edid_ext) | |
3659 | goto end; | |
3660 | ||
3661 | has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); | |
3662 | ||
3663 | if (has_audio) { | |
3664 | DRM_DEBUG_KMS("Monitor has basic audio support\n"); | |
3665 | goto end; | |
3666 | } | |
3667 | ||
9e50b9d5 VS |
3668 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
3669 | goto end; | |
8fe9790d | 3670 | |
9e50b9d5 VS |
3671 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
3672 | if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { | |
8fe9790d | 3673 | has_audio = true; |
9e50b9d5 | 3674 | for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) |
8fe9790d ZW |
3675 | DRM_DEBUG_KMS("CEA audio format %d\n", |
3676 | (edid_ext[i + j] >> 3) & 0xf); | |
3677 | goto end; | |
3678 | } | |
3679 | } | |
3680 | end: | |
3681 | return has_audio; | |
3682 | } | |
3683 | EXPORT_SYMBOL(drm_detect_monitor_audio); | |
3684 | ||
b1edd6a6 VS |
3685 | /** |
3686 | * drm_rgb_quant_range_selectable - is RGB quantization range selectable? | |
fc66811c | 3687 | * @edid: EDID block to scan |
b1edd6a6 VS |
3688 | * |
3689 | * Check whether the monitor reports the RGB quantization range selection | |
3690 | * as supported. The AVI infoframe can then be used to inform the monitor | |
3691 | * which quantization range (full or limited) is used. | |
db6cf833 TR |
3692 | * |
3693 | * Return: True if the RGB quantization range is selectable, false otherwise. | |
b1edd6a6 VS |
3694 | */ |
3695 | bool drm_rgb_quant_range_selectable(struct edid *edid) | |
3696 | { | |
3697 | u8 *edid_ext; | |
3698 | int i, start, end; | |
3699 | ||
3700 | edid_ext = drm_find_cea_extension(edid); | |
3701 | if (!edid_ext) | |
3702 | return false; | |
3703 | ||
3704 | if (cea_db_offsets(edid_ext, &start, &end)) | |
3705 | return false; | |
3706 | ||
3707 | for_each_cea_db(edid_ext, i, start, end) { | |
3708 | if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && | |
3709 | cea_db_payload_len(&edid_ext[i]) == 2) { | |
3710 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); | |
3711 | return edid_ext[i + 2] & EDID_CEA_VCDB_QS; | |
3712 | } | |
3713 | } | |
3714 | ||
3715 | return false; | |
3716 | } | |
3717 | EXPORT_SYMBOL(drm_rgb_quant_range_selectable); | |
3718 | ||
d0c94692 MK |
3719 | /** |
3720 | * drm_assign_hdmi_deep_color_info - detect whether monitor supports | |
3721 | * hdmi deep color modes and update drm_display_info if so. | |
d0c94692 MK |
3722 | * @edid: monitor EDID information |
3723 | * @info: Updated with maximum supported deep color bpc and color format | |
3724 | * if deep color supported. | |
295ee853 | 3725 | * @connector: DRM connector, used only for debug output |
d0c94692 MK |
3726 | * |
3727 | * Parse the CEA extension according to CEA-861-B. | |
3728 | * Return true if HDMI deep color supported, false if not or unknown. | |
3729 | */ | |
3730 | static bool drm_assign_hdmi_deep_color_info(struct edid *edid, | |
3731 | struct drm_display_info *info, | |
3732 | struct drm_connector *connector) | |
3733 | { | |
3734 | u8 *edid_ext, *hdmi; | |
3735 | int i; | |
3736 | int start_offset, end_offset; | |
3737 | unsigned int dc_bpc = 0; | |
3738 | ||
3739 | edid_ext = drm_find_cea_extension(edid); | |
3740 | if (!edid_ext) | |
3741 | return false; | |
3742 | ||
3743 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) | |
3744 | return false; | |
3745 | ||
3746 | /* | |
3747 | * Because HDMI identifier is in Vendor Specific Block, | |
3748 | * search it from all data blocks of CEA extension. | |
3749 | */ | |
3750 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { | |
3751 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { | |
3752 | /* HDMI supports at least 8 bpc */ | |
3753 | info->bpc = 8; | |
3754 | ||
3755 | hdmi = &edid_ext[i]; | |
3756 | if (cea_db_payload_len(hdmi) < 6) | |
3757 | return false; | |
3758 | ||
3759 | if (hdmi[6] & DRM_EDID_HDMI_DC_30) { | |
3760 | dc_bpc = 10; | |
5d02626d | 3761 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; |
d0c94692 | 3762 | DRM_DEBUG("%s: HDMI sink does deep color 30.\n", |
25933820 | 3763 | connector->name); |
d0c94692 MK |
3764 | } |
3765 | ||
3766 | if (hdmi[6] & DRM_EDID_HDMI_DC_36) { | |
3767 | dc_bpc = 12; | |
5d02626d | 3768 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; |
d0c94692 | 3769 | DRM_DEBUG("%s: HDMI sink does deep color 36.\n", |
25933820 | 3770 | connector->name); |
d0c94692 MK |
3771 | } |
3772 | ||
3773 | if (hdmi[6] & DRM_EDID_HDMI_DC_48) { | |
3774 | dc_bpc = 16; | |
5d02626d | 3775 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; |
d0c94692 | 3776 | DRM_DEBUG("%s: HDMI sink does deep color 48.\n", |
25933820 | 3777 | connector->name); |
d0c94692 MK |
3778 | } |
3779 | ||
3780 | if (dc_bpc > 0) { | |
3781 | DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", | |
25933820 | 3782 | connector->name, dc_bpc); |
d0c94692 MK |
3783 | info->bpc = dc_bpc; |
3784 | ||
3785 | /* | |
3786 | * Deep color support mandates RGB444 support for all video | |
3787 | * modes and forbids YCRCB422 support for all video modes per | |
3788 | * HDMI 1.3 spec. | |
3789 | */ | |
3790 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
3791 | ||
3792 | /* YCRCB444 is optional according to spec. */ | |
3793 | if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { | |
3794 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3795 | DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", | |
25933820 | 3796 | connector->name); |
d0c94692 MK |
3797 | } |
3798 | ||
3799 | /* | |
3800 | * Spec says that if any deep color mode is supported at all, | |
3801 | * then deep color 36 bit must be supported. | |
3802 | */ | |
3803 | if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { | |
3804 | DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", | |
25933820 | 3805 | connector->name); |
d0c94692 MK |
3806 | } |
3807 | ||
3808 | return true; | |
3809 | } | |
3810 | else { | |
3811 | DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", | |
25933820 | 3812 | connector->name); |
d0c94692 MK |
3813 | } |
3814 | } | |
3815 | } | |
3816 | ||
3817 | return false; | |
3818 | } | |
3819 | ||
3b11228b JB |
3820 | /** |
3821 | * drm_add_display_info - pull display info out if present | |
3822 | * @edid: EDID data | |
3823 | * @info: display info (attached to connector) | |
d0c94692 | 3824 | * @connector: connector whose edid is used to build display info |
3b11228b JB |
3825 | * |
3826 | * Grab any available display info and stuff it into the drm_display_info | |
3827 | * structure that's part of the connector. Useful for tracking bpp and | |
3828 | * color spaces. | |
3829 | */ | |
3830 | static void drm_add_display_info(struct edid *edid, | |
d0c94692 MK |
3831 | struct drm_display_info *info, |
3832 | struct drm_connector *connector) | |
3b11228b | 3833 | { |
ebec9a7b JB |
3834 | u8 *edid_ext; |
3835 | ||
3b11228b JB |
3836 | info->width_mm = edid->width_cm * 10; |
3837 | info->height_mm = edid->height_cm * 10; | |
3838 | ||
3839 | /* driver figures it out in this case */ | |
3840 | info->bpc = 0; | |
da05a5a7 | 3841 | info->color_formats = 0; |
3b11228b | 3842 | |
a988bc72 | 3843 | if (edid->revision < 3) |
3b11228b JB |
3844 | return; |
3845 | ||
3846 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) | |
3847 | return; | |
3848 | ||
a988bc72 LPC |
3849 | /* Get data from CEA blocks if present */ |
3850 | edid_ext = drm_find_cea_extension(edid); | |
3851 | if (edid_ext) { | |
3852 | info->cea_rev = edid_ext[1]; | |
3853 | ||
3854 | /* The existence of a CEA block should imply RGB support */ | |
3855 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
3856 | if (edid_ext[3] & EDID_CEA_YCRCB444) | |
3857 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3858 | if (edid_ext[3] & EDID_CEA_YCRCB422) | |
3859 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3860 | } | |
3861 | ||
d0c94692 MK |
3862 | /* HDMI deep color modes supported? Assign to info, if so */ |
3863 | drm_assign_hdmi_deep_color_info(edid, info, connector); | |
3864 | ||
a988bc72 LPC |
3865 | /* Only defined for 1.4 with digital displays */ |
3866 | if (edid->revision < 4) | |
3867 | return; | |
3868 | ||
3b11228b JB |
3869 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { |
3870 | case DRM_EDID_DIGITAL_DEPTH_6: | |
3871 | info->bpc = 6; | |
3872 | break; | |
3873 | case DRM_EDID_DIGITAL_DEPTH_8: | |
3874 | info->bpc = 8; | |
3875 | break; | |
3876 | case DRM_EDID_DIGITAL_DEPTH_10: | |
3877 | info->bpc = 10; | |
3878 | break; | |
3879 | case DRM_EDID_DIGITAL_DEPTH_12: | |
3880 | info->bpc = 12; | |
3881 | break; | |
3882 | case DRM_EDID_DIGITAL_DEPTH_14: | |
3883 | info->bpc = 14; | |
3884 | break; | |
3885 | case DRM_EDID_DIGITAL_DEPTH_16: | |
3886 | info->bpc = 16; | |
3887 | break; | |
3888 | case DRM_EDID_DIGITAL_DEPTH_UNDEF: | |
3889 | default: | |
3890 | info->bpc = 0; | |
3891 | break; | |
3892 | } | |
da05a5a7 | 3893 | |
d0c94692 | 3894 | DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", |
25933820 | 3895 | connector->name, info->bpc); |
d0c94692 | 3896 | |
a988bc72 | 3897 | info->color_formats |= DRM_COLOR_FORMAT_RGB444; |
ee58808d LPC |
3898 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) |
3899 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3900 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) | |
3901 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3b11228b JB |
3902 | } |
3903 | ||
c9729177 DA |
3904 | static int validate_displayid(u8 *displayid, int length, int idx) |
3905 | { | |
3906 | int i; | |
3907 | u8 csum = 0; | |
3908 | struct displayid_hdr *base; | |
3909 | ||
3910 | base = (struct displayid_hdr *)&displayid[idx]; | |
3911 | ||
3912 | DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", | |
3913 | base->rev, base->bytes, base->prod_id, base->ext_count); | |
3914 | ||
3915 | if (base->bytes + 5 > length - idx) | |
3916 | return -EINVAL; | |
3917 | for (i = idx; i <= base->bytes + 5; i++) { | |
3918 | csum += displayid[i]; | |
3919 | } | |
3920 | if (csum) { | |
3921 | DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); | |
3922 | return -EINVAL; | |
3923 | } | |
3924 | return 0; | |
3925 | } | |
3926 | ||
a39ed680 DA |
3927 | static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, |
3928 | struct displayid_detailed_timings_1 *timings) | |
3929 | { | |
3930 | struct drm_display_mode *mode; | |
3931 | unsigned pixel_clock = (timings->pixel_clock[0] | | |
3932 | (timings->pixel_clock[1] << 8) | | |
3933 | (timings->pixel_clock[2] << 16)); | |
3934 | unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; | |
3935 | unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; | |
3936 | unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; | |
3937 | unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; | |
3938 | unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; | |
3939 | unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; | |
3940 | unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; | |
3941 | unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; | |
3942 | bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; | |
3943 | bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; | |
3944 | mode = drm_mode_create(dev); | |
3945 | if (!mode) | |
3946 | return NULL; | |
3947 | ||
3948 | mode->clock = pixel_clock * 10; | |
3949 | mode->hdisplay = hactive; | |
3950 | mode->hsync_start = mode->hdisplay + hsync; | |
3951 | mode->hsync_end = mode->hsync_start + hsync_width; | |
3952 | mode->htotal = mode->hdisplay + hblank; | |
3953 | ||
3954 | mode->vdisplay = vactive; | |
3955 | mode->vsync_start = mode->vdisplay + vsync; | |
3956 | mode->vsync_end = mode->vsync_start + vsync_width; | |
3957 | mode->vtotal = mode->vdisplay + vblank; | |
3958 | ||
3959 | mode->flags = 0; | |
3960 | mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
3961 | mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
3962 | mode->type = DRM_MODE_TYPE_DRIVER; | |
3963 | ||
3964 | if (timings->flags & 0x80) | |
3965 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3966 | mode->vrefresh = drm_mode_vrefresh(mode); | |
3967 | drm_mode_set_name(mode); | |
3968 | ||
3969 | return mode; | |
3970 | } | |
3971 | ||
3972 | static int add_displayid_detailed_1_modes(struct drm_connector *connector, | |
3973 | struct displayid_block *block) | |
3974 | { | |
3975 | struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; | |
3976 | int i; | |
3977 | int num_timings; | |
3978 | struct drm_display_mode *newmode; | |
3979 | int num_modes = 0; | |
3980 | /* blocks must be multiple of 20 bytes length */ | |
3981 | if (block->num_bytes % 20) | |
3982 | return 0; | |
3983 | ||
3984 | num_timings = block->num_bytes / 20; | |
3985 | for (i = 0; i < num_timings; i++) { | |
3986 | struct displayid_detailed_timings_1 *timings = &det->timings[i]; | |
3987 | ||
3988 | newmode = drm_mode_displayid_detailed(connector->dev, timings); | |
3989 | if (!newmode) | |
3990 | continue; | |
3991 | ||
3992 | drm_mode_probed_add(connector, newmode); | |
3993 | num_modes++; | |
3994 | } | |
3995 | return num_modes; | |
3996 | } | |
3997 | ||
3998 | static int add_displayid_detailed_modes(struct drm_connector *connector, | |
3999 | struct edid *edid) | |
4000 | { | |
4001 | u8 *displayid; | |
4002 | int ret; | |
4003 | int idx = 1; | |
4004 | int length = EDID_LENGTH; | |
4005 | struct displayid_block *block; | |
4006 | int num_modes = 0; | |
4007 | ||
4008 | displayid = drm_find_displayid_extension(edid); | |
4009 | if (!displayid) | |
4010 | return 0; | |
4011 | ||
4012 | ret = validate_displayid(displayid, length, idx); | |
4013 | if (ret) | |
4014 | return 0; | |
4015 | ||
4016 | idx += sizeof(struct displayid_hdr); | |
4017 | while (block = (struct displayid_block *)&displayid[idx], | |
4018 | idx + sizeof(struct displayid_block) <= length && | |
4019 | idx + sizeof(struct displayid_block) + block->num_bytes <= length && | |
4020 | block->num_bytes > 0) { | |
4021 | idx += block->num_bytes + sizeof(struct displayid_block); | |
4022 | switch (block->tag) { | |
4023 | case DATA_BLOCK_TYPE_1_DETAILED_TIMING: | |
4024 | num_modes += add_displayid_detailed_1_modes(connector, block); | |
4025 | break; | |
4026 | } | |
4027 | } | |
4028 | return num_modes; | |
4029 | } | |
4030 | ||
f453ba04 DA |
4031 | /** |
4032 | * drm_add_edid_modes - add modes from EDID data, if available | |
4033 | * @connector: connector we're probing | |
db6cf833 | 4034 | * @edid: EDID data |
f453ba04 DA |
4035 | * |
4036 | * Add the specified modes to the connector's mode list. | |
4037 | * | |
db6cf833 | 4038 | * Return: The number of modes added or 0 if we couldn't find any. |
f453ba04 DA |
4039 | */ |
4040 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
4041 | { | |
4042 | int num_modes = 0; | |
4043 | u32 quirks; | |
4044 | ||
4045 | if (edid == NULL) { | |
4046 | return 0; | |
4047 | } | |
3c537889 | 4048 | if (!drm_edid_is_valid(edid)) { |
dcdb1674 | 4049 | dev_warn(connector->dev->dev, "%s: EDID invalid.\n", |
25933820 | 4050 | connector->name); |
f453ba04 DA |
4051 | return 0; |
4052 | } | |
4053 | ||
4054 | quirks = edid_get_quirks(edid); | |
4055 | ||
c867df70 AJ |
4056 | /* |
4057 | * EDID spec says modes should be preferred in this order: | |
4058 | * - preferred detailed mode | |
4059 | * - other detailed modes from base block | |
4060 | * - detailed modes from extension blocks | |
4061 | * - CVT 3-byte code modes | |
4062 | * - standard timing codes | |
4063 | * - established timing codes | |
4064 | * - modes inferred from GTF or CVT range information | |
4065 | * | |
13931579 | 4066 | * We get this pretty much right. |
c867df70 AJ |
4067 | * |
4068 | * XXX order for additional mode types in extension blocks? | |
4069 | */ | |
13931579 AJ |
4070 | num_modes += add_detailed_modes(connector, edid, quirks); |
4071 | num_modes += add_cvt_modes(connector, edid); | |
c867df70 AJ |
4072 | num_modes += add_standard_modes(connector, edid); |
4073 | num_modes += add_established_modes(connector, edid); | |
54ac76f8 | 4074 | num_modes += add_cea_modes(connector, edid); |
e6e79209 | 4075 | num_modes += add_alternate_cea_modes(connector, edid); |
a39ed680 | 4076 | num_modes += add_displayid_detailed_modes(connector, edid); |
4d53dc0c VS |
4077 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) |
4078 | num_modes += add_inferred_modes(connector, edid); | |
f453ba04 DA |
4079 | |
4080 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
4081 | edid_fixup_preferred(connector, quirks); | |
4082 | ||
d0c94692 | 4083 | drm_add_display_info(edid, &connector->display_info, connector); |
f453ba04 | 4084 | |
49d45a31 RM |
4085 | if (quirks & EDID_QUIRK_FORCE_8BPC) |
4086 | connector->display_info.bpc = 8; | |
4087 | ||
bc5b9641 MK |
4088 | if (quirks & EDID_QUIRK_FORCE_12BPC) |
4089 | connector->display_info.bpc = 12; | |
4090 | ||
f453ba04 DA |
4091 | return num_modes; |
4092 | } | |
4093 | EXPORT_SYMBOL(drm_add_edid_modes); | |
f0fda0a4 ZY |
4094 | |
4095 | /** | |
4096 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
4097 | * @connector: connector we're probing | |
4098 | * @hdisplay: the horizontal display limit | |
4099 | * @vdisplay: the vertical display limit | |
4100 | * | |
4101 | * Add the specified modes to the connector's mode list. Only when the | |
4102 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
4103 | * | |
db6cf833 | 4104 | * Return: The number of modes added or 0 if we couldn't find any. |
f0fda0a4 ZY |
4105 | */ |
4106 | int drm_add_modes_noedid(struct drm_connector *connector, | |
4107 | int hdisplay, int vdisplay) | |
4108 | { | |
4109 | int i, count, num_modes = 0; | |
b1f559ec | 4110 | struct drm_display_mode *mode; |
f0fda0a4 ZY |
4111 | struct drm_device *dev = connector->dev; |
4112 | ||
fbb40b28 | 4113 | count = ARRAY_SIZE(drm_dmt_modes); |
f0fda0a4 ZY |
4114 | if (hdisplay < 0) |
4115 | hdisplay = 0; | |
4116 | if (vdisplay < 0) | |
4117 | vdisplay = 0; | |
4118 | ||
4119 | for (i = 0; i < count; i++) { | |
b1f559ec | 4120 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f0fda0a4 ZY |
4121 | if (hdisplay && vdisplay) { |
4122 | /* | |
4123 | * Only when two are valid, they will be used to check | |
4124 | * whether the mode should be added to the mode list of | |
4125 | * the connector. | |
4126 | */ | |
4127 | if (ptr->hdisplay > hdisplay || | |
4128 | ptr->vdisplay > vdisplay) | |
4129 | continue; | |
4130 | } | |
f985dedb AJ |
4131 | if (drm_mode_vrefresh(ptr) > 61) |
4132 | continue; | |
f0fda0a4 ZY |
4133 | mode = drm_mode_duplicate(dev, ptr); |
4134 | if (mode) { | |
4135 | drm_mode_probed_add(connector, mode); | |
4136 | num_modes++; | |
4137 | } | |
4138 | } | |
4139 | return num_modes; | |
4140 | } | |
4141 | EXPORT_SYMBOL(drm_add_modes_noedid); | |
10a85120 | 4142 | |
db6cf833 TR |
4143 | /** |
4144 | * drm_set_preferred_mode - Sets the preferred mode of a connector | |
4145 | * @connector: connector whose mode list should be processed | |
4146 | * @hpref: horizontal resolution of preferred mode | |
4147 | * @vpref: vertical resolution of preferred mode | |
4148 | * | |
4149 | * Marks a mode as preferred if it matches the resolution specified by @hpref | |
4150 | * and @vpref. | |
4151 | */ | |
3cf70daf GH |
4152 | void drm_set_preferred_mode(struct drm_connector *connector, |
4153 | int hpref, int vpref) | |
4154 | { | |
4155 | struct drm_display_mode *mode; | |
4156 | ||
4157 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
db6cf833 | 4158 | if (mode->hdisplay == hpref && |
9d3de138 | 4159 | mode->vdisplay == vpref) |
3cf70daf GH |
4160 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
4161 | } | |
4162 | } | |
4163 | EXPORT_SYMBOL(drm_set_preferred_mode); | |
4164 | ||
10a85120 TR |
4165 | /** |
4166 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | |
4167 | * data from a DRM display mode | |
4168 | * @frame: HDMI AVI infoframe | |
4169 | * @mode: DRM display mode | |
4170 | * | |
db6cf833 | 4171 | * Return: 0 on success or a negative error code on failure. |
10a85120 TR |
4172 | */ |
4173 | int | |
4174 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | |
4175 | const struct drm_display_mode *mode) | |
4176 | { | |
4177 | int err; | |
4178 | ||
4179 | if (!frame || !mode) | |
4180 | return -EINVAL; | |
4181 | ||
4182 | err = hdmi_avi_infoframe_init(frame); | |
4183 | if (err < 0) | |
4184 | return err; | |
4185 | ||
bf02db99 DL |
4186 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
4187 | frame->pixel_repeat = 1; | |
4188 | ||
10a85120 | 4189 | frame->video_code = drm_match_cea_mode(mode); |
10a85120 TR |
4190 | |
4191 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | |
0967e6a5 | 4192 | |
69ab6d35 VK |
4193 | /* |
4194 | * Populate picture aspect ratio from either | |
4195 | * user input (if specified) or from the CEA mode list. | |
4196 | */ | |
4197 | if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || | |
4198 | mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) | |
4199 | frame->picture_aspect = mode->picture_aspect_ratio; | |
4200 | else if (frame->video_code > 0) | |
0967e6a5 VK |
4201 | frame->picture_aspect = drm_get_cea_aspect_ratio( |
4202 | frame->video_code); | |
4203 | ||
10a85120 | 4204 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; |
24d01805 | 4205 | frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; |
10a85120 TR |
4206 | |
4207 | return 0; | |
4208 | } | |
4209 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | |
83dd0008 | 4210 | |
4eed4a0a DL |
4211 | static enum hdmi_3d_structure |
4212 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | |
4213 | { | |
4214 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; | |
4215 | ||
4216 | switch (layout) { | |
4217 | case DRM_MODE_FLAG_3D_FRAME_PACKING: | |
4218 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | |
4219 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: | |
4220 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | |
4221 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: | |
4222 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | |
4223 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: | |
4224 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | |
4225 | case DRM_MODE_FLAG_3D_L_DEPTH: | |
4226 | return HDMI_3D_STRUCTURE_L_DEPTH; | |
4227 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: | |
4228 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | |
4229 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: | |
4230 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | |
4231 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: | |
4232 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | |
4233 | default: | |
4234 | return HDMI_3D_STRUCTURE_INVALID; | |
4235 | } | |
4236 | } | |
4237 | ||
83dd0008 LD |
4238 | /** |
4239 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | |
4240 | * data from a DRM display mode | |
4241 | * @frame: HDMI vendor infoframe | |
4242 | * @mode: DRM display mode | |
4243 | * | |
4244 | * Note that there's is a need to send HDMI vendor infoframes only when using a | |
4245 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | |
4246 | * function will return -EINVAL, error that can be safely ignored. | |
4247 | * | |
db6cf833 | 4248 | * Return: 0 on success or a negative error code on failure. |
83dd0008 LD |
4249 | */ |
4250 | int | |
4251 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | |
4252 | const struct drm_display_mode *mode) | |
4253 | { | |
4254 | int err; | |
4eed4a0a | 4255 | u32 s3d_flags; |
83dd0008 LD |
4256 | u8 vic; |
4257 | ||
4258 | if (!frame || !mode) | |
4259 | return -EINVAL; | |
4260 | ||
4261 | vic = drm_match_hdmi_mode(mode); | |
4eed4a0a DL |
4262 | s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; |
4263 | ||
4264 | if (!vic && !s3d_flags) | |
4265 | return -EINVAL; | |
4266 | ||
4267 | if (vic && s3d_flags) | |
83dd0008 LD |
4268 | return -EINVAL; |
4269 | ||
4270 | err = hdmi_vendor_infoframe_init(frame); | |
4271 | if (err < 0) | |
4272 | return err; | |
4273 | ||
4eed4a0a DL |
4274 | if (vic) |
4275 | frame->vic = vic; | |
4276 | else | |
4277 | frame->s3d_struct = s3d_structure_from_display_mode(mode); | |
83dd0008 LD |
4278 | |
4279 | return 0; | |
4280 | } | |
4281 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); | |
40d9b043 | 4282 | |
5e546cd5 DA |
4283 | static int drm_parse_tiled_block(struct drm_connector *connector, |
4284 | struct displayid_block *block) | |
4285 | { | |
4286 | struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; | |
4287 | u16 w, h; | |
4288 | u8 tile_v_loc, tile_h_loc; | |
4289 | u8 num_v_tile, num_h_tile; | |
4290 | struct drm_tile_group *tg; | |
4291 | ||
4292 | w = tile->tile_size[0] | tile->tile_size[1] << 8; | |
4293 | h = tile->tile_size[2] | tile->tile_size[3] << 8; | |
4294 | ||
4295 | num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); | |
4296 | num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); | |
4297 | tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); | |
4298 | tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); | |
4299 | ||
4300 | connector->has_tile = true; | |
4301 | if (tile->tile_cap & 0x80) | |
4302 | connector->tile_is_single_monitor = true; | |
4303 | ||
4304 | connector->num_h_tile = num_h_tile + 1; | |
4305 | connector->num_v_tile = num_v_tile + 1; | |
4306 | connector->tile_h_loc = tile_h_loc; | |
4307 | connector->tile_v_loc = tile_v_loc; | |
4308 | connector->tile_h_size = w + 1; | |
4309 | connector->tile_v_size = h + 1; | |
4310 | ||
4311 | DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); | |
4312 | DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); | |
4313 | DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", | |
4314 | num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); | |
4315 | DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); | |
4316 | ||
4317 | tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); | |
4318 | if (!tg) { | |
4319 | tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); | |
4320 | } | |
4321 | if (!tg) | |
4322 | return -ENOMEM; | |
4323 | ||
4324 | if (connector->tile_group != tg) { | |
4325 | /* if we haven't got a pointer, | |
4326 | take the reference, drop ref to old tile group */ | |
4327 | if (connector->tile_group) { | |
4328 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | |
4329 | } | |
4330 | connector->tile_group = tg; | |
4331 | } else | |
4332 | /* if same tile group, then release the ref we just took. */ | |
4333 | drm_mode_put_tile_group(connector->dev, tg); | |
4334 | return 0; | |
4335 | } | |
4336 | ||
40d9b043 DA |
4337 | static int drm_parse_display_id(struct drm_connector *connector, |
4338 | u8 *displayid, int length, | |
4339 | bool is_edid_extension) | |
4340 | { | |
4341 | /* if this is an EDID extension the first byte will be 0x70 */ | |
4342 | int idx = 0; | |
40d9b043 | 4343 | struct displayid_block *block; |
5e546cd5 | 4344 | int ret; |
40d9b043 DA |
4345 | |
4346 | if (is_edid_extension) | |
4347 | idx = 1; | |
4348 | ||
c9729177 DA |
4349 | ret = validate_displayid(displayid, length, idx); |
4350 | if (ret) | |
4351 | return ret; | |
40d9b043 | 4352 | |
3a4a2ea3 TB |
4353 | idx += sizeof(struct displayid_hdr); |
4354 | while (block = (struct displayid_block *)&displayid[idx], | |
4355 | idx + sizeof(struct displayid_block) <= length && | |
4356 | idx + sizeof(struct displayid_block) + block->num_bytes <= length && | |
4357 | block->num_bytes > 0) { | |
4358 | idx += block->num_bytes + sizeof(struct displayid_block); | |
4359 | DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", | |
4360 | block->tag, block->rev, block->num_bytes); | |
4361 | ||
4362 | switch (block->tag) { | |
4363 | case DATA_BLOCK_TILED_DISPLAY: | |
4364 | ret = drm_parse_tiled_block(connector, block); | |
4365 | if (ret) | |
4366 | return ret; | |
4367 | break; | |
a39ed680 DA |
4368 | case DATA_BLOCK_TYPE_1_DETAILED_TIMING: |
4369 | /* handled in mode gathering code. */ | |
4370 | break; | |
3a4a2ea3 TB |
4371 | default: |
4372 | DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); | |
4373 | break; | |
4374 | } | |
40d9b043 DA |
4375 | } |
4376 | return 0; | |
4377 | } | |
4378 | ||
4379 | static void drm_get_displayid(struct drm_connector *connector, | |
4380 | struct edid *edid) | |
4381 | { | |
4382 | void *displayid = NULL; | |
4383 | int ret; | |
4384 | connector->has_tile = false; | |
4385 | displayid = drm_find_displayid_extension(edid); | |
4386 | if (!displayid) { | |
4387 | /* drop reference to any tile group we had */ | |
4388 | goto out_drop_ref; | |
4389 | } | |
4390 | ||
4391 | ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); | |
4392 | if (ret < 0) | |
4393 | goto out_drop_ref; | |
4394 | if (!connector->has_tile) | |
4395 | goto out_drop_ref; | |
4396 | return; | |
4397 | out_drop_ref: | |
4398 | if (connector->tile_group) { | |
4399 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | |
4400 | connector->tile_group = NULL; | |
4401 | } | |
4402 | return; | |
4403 | } |