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drm/edid: Rewrite mode parse to use the generic detailed block walk
[deliverable/linux.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
f453ba04
DA		 32#include <linux/i2c.h>
33#include <linux/i2c-algo-bit.h>
34#include "drmP.h"
35#include "drm_edid.h"
36
13931579
AJ		 37#define version_greater(edid, maj, min) \
38 (((edid)->version > (maj)) || \
39 ((edid)->version == (maj) && (edid)->revision > (min)))
40
d1ff6409
AJ		 41#define EDID_EST_TIMINGS 16
42#define EDID_STD_TIMINGS 8
43#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 44
45/*
46 * EDID blocks out in the wild have a variety of bugs, try to collect
47 * them here (note that userspace may work around broken monitors first,
48 * but fixes should make their way here so that the kernel "just works"
49 * on as many displays as possible).
50 */
51
52/* First detailed mode wrong, use largest 60Hz mode */
53#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
54/* Reported 135MHz pixel clock is too high, needs adjustment */
55#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
56/* Prefer the largest mode at 75 Hz */
57#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
58/* Detail timing is in cm not mm */
59#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
60/* Detailed timing descriptors have bogus size values, so just take the
61 * maximum size and use that.
62 */
63#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
64/* Monitor forgot to set the first detailed is preferred bit. */
65#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
66/* use +hsync +vsync for detailed mode */
67#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3c537889 68
13931579
AJ		 69struct detailed_mode_closure {
70 struct drm_connector *connector;
71 struct edid *edid;
72 bool preferred;
73 u32 quirks;
74 int modes;
75};
f453ba04 76
5c61259e
ZY		 77#define LEVEL_DMT 0
78#define LEVEL_GTF 1
7a374350
AJ		 79#define LEVEL_GTF2 2
80#define LEVEL_CVT 3
5c61259e 81
f453ba04
DA		 82static struct edid_quirk {
83 char *vendor;
84 int product_id;
85 u32 quirks;
86} edid_quirk_list[] = {
87 /* Acer AL1706 */
88 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
89 /* Acer F51 */
90 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
91 /* Unknown Acer */
92 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
93
94 /* Belinea 10 15 55 */
95 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
96 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
97
98 /* Envision Peripherals, Inc. EN-7100e */
99 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 100 /* Envision EN2028 */
101 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 102
103 /* Funai Electronics PM36B */
104 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
105 EDID_QUIRK_DETAILED_IN_CM },
106
107 /* LG Philips LCD LP154W01-A5 */
108 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
109 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
110
111 /* Philips 107p5 CRT */
112 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113
114 /* Proview AY765C */
115 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
116
117 /* Samsung SyncMaster 205BW. Note: irony */
118 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
119 /* Samsung SyncMaster 22[5-6]BW */
120 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
121 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
122};
123
61e57a8d 124/*** DDC fetch and block validation ***/
f453ba04 125
083ae056
AJ		 126static const u8 edid_header[] = {
127 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
128};
f453ba04 129
61e57a8d
AJ		 130/*
131 * Sanity check the EDID block (base or extension). Return 0 if the block
132 * doesn't check out, or 1 if it's valid.
f453ba04 133 */
61e57a8d
AJ		 134static bool
135drm_edid_block_valid(u8 *raw_edid)
f453ba04 136{
61e57a8d 137 int i;
f453ba04 138 u8 csum = 0;
61e57a8d 139 struct edid *edid = (struct edid *)raw_edid;
f453ba04 140
61e57a8d
AJ		 141 if (raw_edid[0] == 0x00) {
142 int score = 0;
862b89c0 143
61e57a8d
AJ		 144 for (i = 0; i < sizeof(edid_header); i++)
145 if (raw_edid[i] == edid_header[i])
146 score++;
147
148 if (score == 8) ;
149 else if (score >= 6) {
150 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
151 memcpy(raw_edid, edid_header, sizeof(edid_header));
152 } else {
153 goto bad;
154 }
155 }
f453ba04
DA		 156
157 for (i = 0; i < EDID_LENGTH; i++)
158 csum += raw_edid[i];
159 if (csum) {
160 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
4a638b4e
AJ		 161
162 /* allow CEA to slide through, switches mangle this */
163 if (raw_edid[0] != 0x02)
164 goto bad;
f453ba04
DA		 165 }
166
61e57a8d
AJ		 167 /* per-block-type checks */
168 switch (raw_edid[0]) {
169 case 0: /* base */
170 if (edid->version != 1) {
171 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
172 goto bad;
173 }
862b89c0 174
61e57a8d
AJ		 175 if (edid->revision > 4)
176 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
177 break;
862b89c0 178
61e57a8d
AJ		 179 default:
180 break;
181 }
47ee4ccf 182
f453ba04
DA		 183 return 1;
184
185bad:
186 if (raw_edid) {
187 DRM_ERROR("Raw EDID:\n");
188 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);
189 printk("\n");
190 }
191 return 0;
192}
61e57a8d
AJ		 193
194/**
195 * drm_edid_is_valid - sanity check EDID data
196 * @edid: EDID data
197 *
198 * Sanity-check an entire EDID record (including extensions)
199 */
200bool drm_edid_is_valid(struct edid *edid)
201{
202 int i;
203 u8 *raw = (u8 *)edid;
204
205 if (!edid)
206 return false;
207
208 for (i = 0; i <= edid->extensions; i++)
209 if (!drm_edid_block_valid(raw + i * EDID_LENGTH))
210 return false;
211
212 return true;
213}
3c537889 214EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 215
61e57a8d
AJ		 216#define DDC_ADDR 0x50
217#define DDC_SEGMENT_ADDR 0x30
218/**
219 * Get EDID information via I2C.
220 *
221 * \param adapter : i2c device adaptor
222 * \param buf : EDID data buffer to be filled
223 * \param len : EDID data buffer length
224 * \return 0 on success or -1 on failure.
225 *
226 * Try to fetch EDID information by calling i2c driver function.
227 */
228static int
229drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
230 int block, int len)
231{
232 unsigned char start = block * EDID_LENGTH;
233 struct i2c_msg msgs[] = {
234 {
235 .addr = DDC_ADDR,
236 .flags = 0,
237 .len = 1,
238 .buf = &start,
239 }, {
240 .addr = DDC_ADDR,
241 .flags = I2C_M_RD,
242 .len = len,
243 .buf = buf + start,
244 }
245 };
246
247 if (i2c_transfer(adapter, msgs, 2) == 2)
248 return 0;
249
250 return -1;
251}
252
253static u8 *
254drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
255{
256 int i, j = 0;
257 u8 *block, *new;
258
259 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
260 return NULL;
261
262 /* base block fetch */
263 for (i = 0; i < 4; i++) {
264 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
265 goto out;
266 if (drm_edid_block_valid(block))
267 break;
268 }
269 if (i == 4)
270 goto carp;
271
272 /* if there's no extensions, we're done */
273 if (block[0x7e] == 0)
274 return block;
275
276 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
277 if (!new)
278 goto out;
279 block = new;
280
281 for (j = 1; j <= block[0x7e]; j++) {
282 for (i = 0; i < 4; i++) {
283 if (drm_do_probe_ddc_edid(adapter, block, j,
284 EDID_LENGTH))
285 goto out;
286 if (drm_edid_block_valid(block + j * EDID_LENGTH))
287 break;
288 }
289 if (i == 4)
290 goto carp;
291 }
292
293 return block;
294
295carp:
dcdb1674 296 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
61e57a8d
AJ		 297 drm_get_connector_name(connector), j);
298
299out:
300 kfree(block);
301 return NULL;
302}
303
304/**
305 * Probe DDC presence.
306 *
307 * \param adapter : i2c device adaptor
308 * \return 1 on success
309 */
310static bool
311drm_probe_ddc(struct i2c_adapter *adapter)
312{
313 unsigned char out;
314
315 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
316}
317
318/**
319 * drm_get_edid - get EDID data, if available
320 * @connector: connector we're probing
321 * @adapter: i2c adapter to use for DDC
322 *
323 * Poke the given i2c channel to grab EDID data if possible. If found,
324 * attach it to the connector.
325 *
326 * Return edid data or NULL if we couldn't find any.
327 */
328struct edid *drm_get_edid(struct drm_connector *connector,
329 struct i2c_adapter *adapter)
330{
331 struct edid *edid = NULL;
332
333 if (drm_probe_ddc(adapter))
334 edid = (struct edid *)drm_do_get_edid(connector, adapter);
335
336 connector->display_info.raw_edid = (char *)edid;
337
338 return edid;
339
340}
341EXPORT_SYMBOL(drm_get_edid);
342
343/*** EDID parsing ***/
344
f453ba04
DA		 345/**
346 * edid_vendor - match a string against EDID's obfuscated vendor field
347 * @edid: EDID to match
348 * @vendor: vendor string
349 *
350 * Returns true if @vendor is in @edid, false otherwise
351 */
352static bool edid_vendor(struct edid *edid, char *vendor)
353{
354 char edid_vendor[3];
355
356 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
357 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
358 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 359 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 360
361 return !strncmp(edid_vendor, vendor, 3);
362}
363
364/**
365 * edid_get_quirks - return quirk flags for a given EDID
366 * @edid: EDID to process
367 *
368 * This tells subsequent routines what fixes they need to apply.
369 */
370static u32 edid_get_quirks(struct edid *edid)
371{
372 struct edid_quirk *quirk;
373 int i;
374
375 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
376 quirk = &edid_quirk_list[i];
377
378 if (edid_vendor(edid, quirk->vendor) &&
379 (EDID_PRODUCT_ID(edid) == quirk->product_id))
380 return quirk->quirks;
381 }
382
383 return 0;
384}
385
386#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
387#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
388
389
390/**
391 * edid_fixup_preferred - set preferred modes based on quirk list
392 * @connector: has mode list to fix up
393 * @quirks: quirks list
394 *
395 * Walk the mode list for @connector, clearing the preferred status
396 * on existing modes and setting it anew for the right mode ala @quirks.
397 */
398static void edid_fixup_preferred(struct drm_connector *connector,
399 u32 quirks)
400{
401 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 402 int target_refresh = 0;
f453ba04
DA		 403
404 if (list_empty(&connector->probed_modes))
405 return;
406
407 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
408 target_refresh = 60;
409 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
410 target_refresh = 75;
411
412 preferred_mode = list_first_entry(&connector->probed_modes,
413 struct drm_display_mode, head);
414
415 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
416 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
417
418 if (cur_mode == preferred_mode)
419 continue;
420
421 /* Largest mode is preferred */
422 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
423 preferred_mode = cur_mode;
424
425 /* At a given size, try to get closest to target refresh */
426 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
427 MODE_REFRESH_DIFF(cur_mode, target_refresh) <
428 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
429 preferred_mode = cur_mode;
430 }
431 }
432
433 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
434}
435
aa9eaa1f
ZY		 436/*
437 * Add the Autogenerated from the DMT spec.
438 * This table is copied from xfree86/modes/xf86EdidModes.c.
439 * But the mode with Reduced blank feature is deleted.
440 */
441static struct drm_display_mode drm_dmt_modes[] = {
442 /* 640x350@85Hz */
443 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
444 736, 832, 0, 350, 382, 385, 445, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 640x400@85Hz */
447 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
448 736, 832, 0, 400, 401, 404, 445, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 720x400@85Hz */
451 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
452 828, 936, 0, 400, 401, 404, 446, 0,
453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 640x480@60Hz */
455 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
456 752, 800, 0, 480, 489, 492, 525, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
458 /* 640x480@72Hz */
459 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
460 704, 832, 0, 480, 489, 492, 520, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
462 /* 640x480@75Hz */
463 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
464 720, 840, 0, 480, 481, 484, 500, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 640x480@85Hz */
467 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
468 752, 832, 0, 480, 481, 484, 509, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 800x600@56Hz */
471 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
472 896, 1024, 0, 600, 601, 603, 625, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 800x600@60Hz */
475 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
476 968, 1056, 0, 600, 601, 605, 628, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 800x600@72Hz */
479 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
480 976, 1040, 0, 600, 637, 643, 666, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 800x600@75Hz */
483 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
484 896, 1056, 0, 600, 601, 604, 625, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 800x600@85Hz */
487 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
488 896, 1048, 0, 600, 601, 604, 631, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 848x480@60Hz */
491 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
492 976, 1088, 0, 480, 486, 494, 517, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 1024x768@43Hz, interlace */
495 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
496 1208, 1264, 0, 768, 768, 772, 817, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
498 DRM_MODE_FLAG_INTERLACE) },
499 /* 1024x768@60Hz */
500 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
501 1184, 1344, 0, 768, 771, 777, 806, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 1024x768@70Hz */
504 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
505 1184, 1328, 0, 768, 771, 777, 806, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 1024x768@75Hz */
508 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
509 1136, 1312, 0, 768, 769, 772, 800, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
511 /* 1024x768@85Hz */
512 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
61dd98fa 513 1168, 1376, 0, 768, 769, 772, 808, 0,
aa9eaa1f
ZY		 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 1152x864@75Hz */
516 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
517 1344, 1600, 0, 864, 865, 868, 900, 0,
518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 1280x768@60Hz */
520 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
521 1472, 1664, 0, 768, 771, 778, 798, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 1280x768@75Hz */
524 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
525 1488, 1696, 0, 768, 771, 778, 805, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 1280x768@85Hz */
528 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
529 1496, 1712, 0, 768, 771, 778, 809, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
531 /* 1280x800@60Hz */
532 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
533 1480, 1680, 0, 800, 803, 809, 831, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
535 /* 1280x800@75Hz */
536 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
537 1488, 1696, 0, 800, 803, 809, 838, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
539 /* 1280x800@85Hz */
540 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
541 1496, 1712, 0, 800, 803, 809, 843, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 1280x960@60Hz */
544 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
545 1488, 1800, 0, 960, 961, 964, 1000, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
547 /* 1280x960@85Hz */
548 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
549 1504, 1728, 0, 960, 961, 964, 1011, 0,
550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
551 /* 1280x1024@60Hz */
552 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
553 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 1280x1024@75Hz */
556 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
557 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
559 /* 1280x1024@85Hz */
560 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
561 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
563 /* 1360x768@60Hz */
564 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
565 1536, 1792, 0, 768, 771, 777, 795, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
567 /* 1440x1050@60Hz */
568 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
569 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
571 /* 1440x1050@75Hz */
572 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
573 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
575 /* 1440x1050@85Hz */
576 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
577 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
579 /* 1440x900@60Hz */
580 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
581 1672, 1904, 0, 900, 903, 909, 934, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
583 /* 1440x900@75Hz */
584 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
585 1688, 1936, 0, 900, 903, 909, 942, 0,
586 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
587 /* 1440x900@85Hz */
588 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
589 1696, 1952, 0, 900, 903, 909, 948, 0,
590 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
591 /* 1600x1200@60Hz */
592 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
593 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
595 /* 1600x1200@65Hz */
596 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
597 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
599 /* 1600x1200@70Hz */
600 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
601 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
603 /* 1600x1200@75Hz */
c43ae476 604 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
aa9eaa1f
ZY		 605 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
607 /* 1600x1200@85Hz */
608 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
609 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
611 /* 1680x1050@60Hz */
612 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
613 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
615 /* 1680x1050@75Hz */
616 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
617 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
619 /* 1680x1050@85Hz */
620 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
621 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
623 /* 1792x1344@60Hz */
624 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
625 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
627 /* 1729x1344@75Hz */
628 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
629 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
631 /* 1853x1392@60Hz */
632 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
633 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
635 /* 1856x1392@75Hz */
636 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
637 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
639 /* 1920x1200@60Hz */
640 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
641 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
643 /* 1920x1200@75Hz */
644 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
645 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
647 /* 1920x1200@85Hz */
648 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
649 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
651 /* 1920x1440@60Hz */
652 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
653 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
654 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
655 /* 1920x1440@75Hz */
656 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
657 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
659 /* 2560x1600@60Hz */
660 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
661 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
663 /* 2560x1600@75HZ */
664 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
665 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
666 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
667 /* 2560x1600@85HZ */
668 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
669 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
670 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
671};
07a5e632
AJ		 672static const int drm_num_dmt_modes =
673 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
aa9eaa1f 674
1d42bbc8
DA		 675struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
676 int hsize, int vsize, int fresh)
559ee21d 677{
07a5e632 678 int i;
559ee21d
ZY		 679 struct drm_display_mode *ptr, *mode;
680
559ee21d 681 mode = NULL;
07a5e632 682 for (i = 0; i < drm_num_dmt_modes; i++) {
559ee21d
ZY		 683 ptr = &drm_dmt_modes[i];
684 if (hsize == ptr->hdisplay &&
685 vsize == ptr->vdisplay &&
686 fresh == drm_mode_vrefresh(ptr)) {
687 /* get the expected default mode */
688 mode = drm_mode_duplicate(dev, ptr);
689 break;
690 }
691 }
692 return mode;
693}
1d42bbc8 694EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 695
d1ff6409
AJ		 696typedef void detailed_cb(struct detailed_timing *timing, void *closure);
697
4d76a221
AJ		 698static void
699cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
700{
701 int i, n = 0;
702 u8 rev = ext[0x01], d = ext[0x02];
703 u8 *det_base = ext + d;
704
705 switch (rev) {
706 case 0:
707 /* can't happen */
708 return;
709 case 1:
710 /* have to infer how many blocks we have, check pixel clock */
711 for (i = 0; i < 6; i++)
712 if (det_base[18*i] || det_base[18*i+1])
713 n++;
714 break;
715 default:
716 /* explicit count */
717 n = min(ext[0x03] & 0x0f, 6);
718 break;
719 }
720
721 for (i = 0; i < n; i++)
722 cb((struct detailed_timing *)(det_base + 18 * i), closure);
723}
724
cbba98f8
AJ		 725static void
726vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
727{
728 unsigned int i, n = min((int)ext[0x02], 6);
729 u8 *det_base = ext + 5;
730
731 if (ext[0x01] != 1)
732 return; /* unknown version */
733
734 for (i = 0; i < n; i++)
735 cb((struct detailed_timing *)(det_base + 18 * i), closure);
736}
737
d1ff6409
AJ		 738static void
739drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
740{
741 int i;
742 struct edid *edid = (struct edid *)raw_edid;
743
744 if (edid == NULL)
745 return;
746
747 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
748 cb(&(edid->detailed_timings[i]), closure);
749
4d76a221
AJ		 750 for (i = 1; i <= raw_edid[0x7e]; i++) {
751 u8 *ext = raw_edid + (i * EDID_LENGTH);
752 switch (*ext) {
753 case CEA_EXT:
754 cea_for_each_detailed_block(ext, cb, closure);
755 break;
cbba98f8
AJ		 756 case VTB_EXT:
757 vtb_for_each_detailed_block(ext, cb, closure);
758 break;
4d76a221
AJ		 759 default:
760 break;
761 }
762 }
d1ff6409
AJ		 763}
764
765static void
766is_rb(struct detailed_timing *t, void *data)
767{
768 u8 *r = (u8 *)t;
769 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
770 if (r[15] & 0x10)
771 *(bool *)data = true;
772}
773
774/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
775static bool
776drm_monitor_supports_rb(struct edid *edid)
777{
778 if (edid->revision >= 4) {
779 bool ret;
780 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
781 return ret;
782 }
783
784 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
785}
786
7a374350
AJ		 787static void
788find_gtf2(struct detailed_timing *t, void *data)
789{
790 u8 *r = (u8 *)t;
791 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
792 *(u8 **)data = r;
793}
794
795/* Secondary GTF curve kicks in above some break frequency */
796static int
797drm_gtf2_hbreak(struct edid *edid)
798{
799 u8 *r = NULL;
800 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
801 return r ? (r[12] * 2) : 0;
802}
803
804static int
805drm_gtf2_2c(struct edid *edid)
806{
807 u8 *r = NULL;
808 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
809 return r ? r[13] : 0;
810}
811
812static int
813drm_gtf2_m(struct edid *edid)
814{
815 u8 *r = NULL;
816 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
817 return r ? (r[15] << 8) + r[14] : 0;
818}
819
820static int
821drm_gtf2_k(struct edid *edid)
822{
823 u8 *r = NULL;
824 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
825 return r ? r[16] : 0;
826}
827
828static int
829drm_gtf2_2j(struct edid *edid)
830{
831 u8 *r = NULL;
832 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
833 return r ? r[17] : 0;
834}
835
836/**
837 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
838 * @edid: EDID block to scan
839 */
840static int standard_timing_level(struct edid *edid)
841{
842 if (edid->revision >= 2) {
843 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
844 return LEVEL_CVT;
845 if (drm_gtf2_hbreak(edid))
846 return LEVEL_GTF2;
847 return LEVEL_GTF;
848 }
849 return LEVEL_DMT;
850}
851
23425cae
AJ		 852/*
853 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
854 * monitors fill with ascii space (0x20) instead.
855 */
856static int
857bad_std_timing(u8 a, u8 b)
858{
859 return (a == 0x00 && b == 0x00) ||
860 (a == 0x01 && b == 0x01) ||
861 (a == 0x20 && b == 0x20);
862}
863
f453ba04
DA		 864/**
865 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
866 * @t: standard timing params
5c61259e 867 * @timing_level: standard timing level
f453ba04
DA		 868 *
869 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 870 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 871 */
7ca6adb3 872static struct drm_display_mode *
7a374350
AJ		 873drm_mode_std(struct drm_connector *connector, struct edid *edid,
874 struct std_timing *t, int revision)
f453ba04 875{
7ca6adb3
AJ		 876 struct drm_device *dev = connector->dev;
877 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 878 int hsize, vsize;
879 int vrefresh_rate;
0454beab
MD		 880 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
881 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 882 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
883 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 884 int timing_level = standard_timing_level(edid);
5c61259e 885
23425cae
AJ		 886 if (bad_std_timing(t->hsize, t->vfreq_aspect))
887 return NULL;
888
5c61259e
ZY		 889 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
890 hsize = t->hsize * 8 + 248;
891 /* vrefresh_rate = vfreq + 60 */
892 vrefresh_rate = vfreq + 60;
893 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ		 894 if (aspect_ratio == 0) {
895 if (revision < 3)
896 vsize = hsize;
897 else
898 vsize = (hsize * 10) / 16;
899 } else if (aspect_ratio == 1)
f453ba04 900 vsize = (hsize * 3) / 4;
0454beab 901 else if (aspect_ratio == 2)
f453ba04
DA		 902 vsize = (hsize * 4) / 5;
903 else
904 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 905
906 /* HDTV hack, part 1 */
907 if (vrefresh_rate == 60 &&
908 ((hsize == 1360 && vsize == 765) ||
909 (hsize == 1368 && vsize == 769))) {
910 hsize = 1366;
911 vsize = 768;
912 }
913
7ca6adb3
AJ		 914 /*
915 * If this connector already has a mode for this size and refresh
916 * rate (because it came from detailed or CVT info), use that
917 * instead. This way we don't have to guess at interlace or
918 * reduced blanking.
919 */
522032da 920 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 921 if (m->hdisplay == hsize && m->vdisplay == vsize &&
922 drm_mode_vrefresh(m) == vrefresh_rate)
923 return NULL;
924
a0910c8e
AJ		 925 /* HDTV hack, part 2 */
926 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
927 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 928 false);
559ee21d 929 mode->hdisplay = 1366;
a4967de6
AJ		 930 mode->hsync_start = mode->hsync_start - 1;
931 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 932 return mode;
933 }
a0910c8e 934
559ee21d 935 /* check whether it can be found in default mode table */
1d42bbc8 936 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate);
559ee21d
ZY		 937 if (mode)
938 return mode;
939
5c61259e
ZY		 940 switch (timing_level) {
941 case LEVEL_DMT:
5c61259e
ZY		 942 break;
943 case LEVEL_GTF:
944 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
945 break;
7a374350
AJ		 946 case LEVEL_GTF2:
947 /*
948 * This is potentially wrong if there's ever a monitor with
949 * more than one ranges section, each claiming a different
950 * secondary GTF curve. Please don't do that.
951 */
952 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
953 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
954 kfree(mode);
955 mode = drm_gtf_mode_complex(dev, hsize, vsize,
956 vrefresh_rate, 0, 0,
957 drm_gtf2_m(edid),
958 drm_gtf2_2c(edid),
959 drm_gtf2_k(edid),
960 drm_gtf2_2j(edid));
961 }
962 break;
5c61259e 963 case LEVEL_CVT:
d50ba256
DA		 964 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
965 false);
5c61259e
ZY		 966 break;
967 }
f453ba04
DA		 968 return mode;
969}
970
b58db2c6
AJ		 971/*
972 * EDID is delightfully ambiguous about how interlaced modes are to be
973 * encoded. Our internal representation is of frame height, but some
974 * HDTV detailed timings are encoded as field height.
975 *
976 * The format list here is from CEA, in frame size. Technically we
977 * should be checking refresh rate too. Whatever.
978 */
979static void
980drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
981 struct detailed_pixel_timing *pt)
982{
983 int i;
984 static const struct {
985 int w, h;
986 } cea_interlaced[] = {
987 { 1920, 1080 },
988 { 720, 480 },
989 { 1440, 480 },
990 { 2880, 480 },
991 { 720, 576 },
992 { 1440, 576 },
993 { 2880, 576 },
994 };
995 static const int n_sizes =
996 sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
997
998 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
999 return;
1000
1001 for (i = 0; i < n_sizes; i++) {
1002 if ((mode->hdisplay == cea_interlaced[i].w) &&
1003 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1004 mode->vdisplay *= 2;
1005 mode->vsync_start *= 2;
1006 mode->vsync_end *= 2;
1007 mode->vtotal *= 2;
1008 mode->vtotal |= 1;
1009 }
1010 }
1011
1012 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1013}
1014
f453ba04
DA		 1015/**
1016 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1017 * @dev: DRM device (needed to create new mode)
1018 * @edid: EDID block
1019 * @timing: EDID detailed timing info
1020 * @quirks: quirks to apply
1021 *
1022 * An EDID detailed timing block contains enough info for us to create and
1023 * return a new struct drm_display_mode.
1024 */
1025static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1026 struct edid *edid,
1027 struct detailed_timing *timing,
1028 u32 quirks)
1029{
1030 struct drm_display_mode *mode;
1031 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 1032 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1033 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1034 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1035 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 1036 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1037 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1038 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
1039 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 1040
fc438966 1041 /* ignore tiny modes */
0454beab 1042 if (hactive < 64 || vactive < 64)
fc438966
AJ		 1043 return NULL;
1044
0454beab 1045 if (pt->misc & DRM_EDID_PT_STEREO) {
f453ba04
DA		 1046 printk(KERN_WARNING "stereo mode not supported\n");
1047 return NULL;
1048 }
0454beab 1049 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
79b7dcb2 1050 printk(KERN_WARNING "composite sync not supported\n");
f453ba04
DA		 1051 }
1052
fcb45611
ZY		 1053 /* it is incorrect if hsync/vsync width is zero */
1054 if (!hsync_pulse_width || !vsync_pulse_width) {
1055 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1056 "Wrong Hsync/Vsync pulse width\n");
1057 return NULL;
1058 }
f453ba04
DA		 1059 mode = drm_mode_create(dev);
1060 if (!mode)
1061 return NULL;
1062
1063 mode->type = DRM_MODE_TYPE_DRIVER;
1064
1065 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1066 timing->pixel_clock = cpu_to_le16(1088);
1067
1068 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1069
1070 mode->hdisplay = hactive;
1071 mode->hsync_start = mode->hdisplay + hsync_offset;
1072 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1073 mode->htotal = mode->hdisplay + hblank;
1074
1075 mode->vdisplay = vactive;
1076 mode->vsync_start = mode->vdisplay + vsync_offset;
1077 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1078 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1079
7064fef5
JB		 1080 /* Some EDIDs have bogus h/vtotal values */
1081 if (mode->hsync_end > mode->htotal)
1082 mode->htotal = mode->hsync_end + 1;
1083 if (mode->vsync_end > mode->vtotal)
1084 mode->vtotal = mode->vsync_end + 1;
1085
b58db2c6 1086 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 1087
171fdd89
AJ		 1088 drm_mode_set_name(mode);
1089
f453ba04 1090 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1091 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1092 }
1093
0454beab
MD		 1094 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1095 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1096 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1097 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1098
e14cbee4
MD		 1099 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1100 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1101
1102 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1103 mode->width_mm *= 10;
1104 mode->height_mm *= 10;
1105 }
1106
1107 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1108 mode->width_mm = edid->width_cm * 10;
1109 mode->height_mm = edid->height_cm * 10;
1110 }
1111
1112 return mode;
1113}
1114
07a5e632 1115static bool
b17e52ef 1116mode_is_rb(struct drm_display_mode *mode)
07a5e632 1117{
b17e52ef
AJ		 1118 return (mode->htotal - mode->hdisplay == 160) &&
1119 (mode->hsync_end - mode->hdisplay == 80) &&
1120 (mode->hsync_end - mode->hsync_start == 32) &&
1121 (mode->vsync_start - mode->vdisplay == 3);
1122}
07a5e632 1123
b17e52ef
AJ		 1124static bool
1125mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1126{
1127 int hsync, hmin, hmax;
1128
1129 hmin = t[7];
1130 if (edid->revision >= 4)
1131 hmin += ((t[4] & 0x04) ? 255 : 0);
1132 hmax = t[8];
1133 if (edid->revision >= 4)
1134 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1135 hsync = drm_mode_hsync(mode);
07a5e632 1136
b17e52ef
AJ		 1137 return (hsync <= hmax && hsync >= hmin);
1138}
1139
1140static bool
1141mode_in_vsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1142{
1143 int vsync, vmin, vmax;
1144
1145 vmin = t[5];
1146 if (edid->revision >= 4)
1147 vmin += ((t[4] & 0x01) ? 255 : 0);
1148 vmax = t[6];
1149 if (edid->revision >= 4)
1150 vmax += ((t[4] & 0x02) ? 255 : 0);
1151 vsync = drm_mode_vrefresh(mode);
1152
1153 return (vsync <= vmax && vsync >= vmin);
1154}
1155
1156static u32
1157range_pixel_clock(struct edid *edid, u8 *t)
1158{
1159 /* unspecified */
1160 if (t[9] == 0 || t[9] == 255)
1161 return 0;
1162
1163 /* 1.4 with CVT support gives us real precision, yay */
1164 if (edid->revision >= 4 && t[10] == 0x04)
1165 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1166
1167 /* 1.3 is pathetic, so fuzz up a bit */
1168 return t[9] * 10000 + 5001;
1169}
1170
b17e52ef
AJ		 1171static bool
1172mode_in_range(struct drm_display_mode *mode, struct edid *edid,
1173 struct detailed_timing *timing)
1174{
1175 u32 max_clock;
1176 u8 *t = (u8 *)timing;
1177
1178 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1179 return false;
1180
b17e52ef 1181 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1182 return false;
1183
b17e52ef 1184 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1185 if (mode->clock > max_clock)
1186 return false;
b17e52ef
AJ		 1187
1188 /* 1.4 max horizontal check */
1189 if (edid->revision >= 4 && t[10] == 0x04)
1190 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1191 return false;
1192
1193 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1194 return false;
07a5e632
AJ		 1195
1196 return true;
1197}
1198
1199/*
1200 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
1201 * need to account for them.
1202 */
b17e52ef
AJ		 1203static int
1204drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1205 struct detailed_timing *timing)
07a5e632
AJ		 1206{
1207 int i, modes = 0;
1208 struct drm_display_mode *newmode;
1209 struct drm_device *dev = connector->dev;
1210
1211 for (i = 0; i < drm_num_dmt_modes; i++) {
b17e52ef 1212 if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
07a5e632
AJ		 1213 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1214 if (newmode) {
1215 drm_mode_probed_add(connector, newmode);
1216 modes++;
1217 }
1218 }
1219 }
1220
1221 return modes;
1222}
1223
13931579
AJ		 1224static void
1225do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 1226{
13931579
AJ		 1227 struct detailed_mode_closure *closure = c;
1228 struct detailed_non_pixel *data = &timing->data.other_data;
1229 int gtf = (closure->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
9340d8cf 1230
13931579
AJ		 1231 if (gtf && data->type == EDID_DETAIL_MONITOR_RANGE)
1232 closure->modes += drm_gtf_modes_for_range(closure->connector,
1233 closure->edid,
1234 timing);
1235}
69da3015 1236
13931579
AJ		 1237static int
1238add_inferred_modes(struct drm_connector *connector, struct edid *edid)
1239{
1240 struct detailed_mode_closure closure = {
1241 connector, edid, 0, 0, 0
1242 };
9340d8cf 1243
13931579
AJ		 1244 if (version_greater(edid, 1, 0))
1245 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
1246 &closure);
9340d8cf 1247
13931579 1248 return closure.modes;
9340d8cf
AJ		 1249}
1250
13931579
AJ		 1251static struct drm_display_mode edid_est_modes[] = {
1252 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1253 968, 1056, 0, 600, 601, 605, 628, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
1255 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
1256 896, 1024, 0, 600, 601, 603, 625, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
1258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
1259 720, 840, 0, 480, 481, 484, 500, 0,
1260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
1261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
1262 704, 832, 0, 480, 489, 491, 520, 0,
1263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
1264 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
1265 768, 864, 0, 480, 483, 486, 525, 0,
1266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
1267 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
1268 752, 800, 0, 480, 490, 492, 525, 0,
1269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
1270 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
1271 846, 900, 0, 400, 421, 423, 449, 0,
1272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
1273 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
1274 846, 900, 0, 400, 412, 414, 449, 0,
1275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
1276 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1277 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
1279 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
1280 1136, 1312, 0, 768, 769, 772, 800, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
1282 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1283 1184, 1328, 0, 768, 771, 777, 806, 0,
1284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
1285 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1286 1184, 1344, 0, 768, 771, 777, 806, 0,
1287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
1288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1289 1208, 1264, 0, 768, 768, 776, 817, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1291 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
1292 928, 1152, 0, 624, 625, 628, 667, 0,
1293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
1294 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
1295 896, 1056, 0, 600, 601, 604, 625, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
1297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
1298 976, 1040, 0, 600, 637, 643, 666, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
1300 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1301 1344, 1600, 0, 864, 865, 868, 900, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
1303};
1304
2255be14
AJ		 1305static const struct {
1306 short w;
1307 short h;
1308 short r;
1309 short rb;
1310} est3_modes[] = {
1311 /* byte 6 */
1312 { 640, 350, 85, 0 },
1313 { 640, 400, 85, 0 },
1314 { 720, 400, 85, 0 },
1315 { 640, 480, 85, 0 },
1316 { 848, 480, 60, 0 },
1317 { 800, 600, 85, 0 },
1318 { 1024, 768, 85, 0 },
1319 { 1152, 864, 75, 0 },
1320 /* byte 7 */
1321 { 1280, 768, 60, 1 },
1322 { 1280, 768, 60, 0 },
1323 { 1280, 768, 75, 0 },
1324 { 1280, 768, 85, 0 },
1325 { 1280, 960, 60, 0 },
1326 { 1280, 960, 85, 0 },
1327 { 1280, 1024, 60, 0 },
1328 { 1280, 1024, 85, 0 },
1329 /* byte 8 */
1330 { 1360, 768, 60, 0 },
1331 { 1440, 900, 60, 1 },
1332 { 1440, 900, 60, 0 },
1333 { 1440, 900, 75, 0 },
1334 { 1440, 900, 85, 0 },
1335 { 1400, 1050, 60, 1 },
1336 { 1400, 1050, 60, 0 },
1337 { 1400, 1050, 75, 0 },
1338 /* byte 9 */
1339 { 1400, 1050, 85, 0 },
1340 { 1680, 1050, 60, 1 },
1341 { 1680, 1050, 60, 0 },
1342 { 1680, 1050, 75, 0 },
1343 { 1680, 1050, 85, 0 },
1344 { 1600, 1200, 60, 0 },
1345 { 1600, 1200, 65, 0 },
1346 { 1600, 1200, 70, 0 },
1347 /* byte 10 */
1348 { 1600, 1200, 75, 0 },
1349 { 1600, 1200, 85, 0 },
1350 { 1792, 1344, 60, 0 },
1351 { 1792, 1344, 85, 0 },
1352 { 1856, 1392, 60, 0 },
1353 { 1856, 1392, 75, 0 },
1354 { 1920, 1200, 60, 1 },
1355 { 1920, 1200, 60, 0 },
1356 /* byte 11 */
1357 { 1920, 1200, 75, 0 },
1358 { 1920, 1200, 85, 0 },
1359 { 1920, 1440, 60, 0 },
1360 { 1920, 1440, 75, 0 },
1361};
1362static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
1363
1364static int
1365drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1366{
1367 int i, j, m, modes = 0;
1368 struct drm_display_mode *mode;
1369 u8 *est = ((u8 *)timing) + 5;
1370
1371 for (i = 0; i < 6; i++) {
1372 for (j = 7; j > 0; j--) {
1373 m = (i * 8) + (7 - j);
0ddfa7d5 1374 if (m >= num_est3_modes)
2255be14
AJ		 1375 break;
1376 if (est[i] & (1 << j)) {
1d42bbc8
DA		 1377 mode = drm_mode_find_dmt(connector->dev,
1378 est3_modes[m].w,
1379 est3_modes[m].h,
1380 est3_modes[m].r
1381 /*, est3_modes[m].rb */);
2255be14
AJ		 1382 if (mode) {
1383 drm_mode_probed_add(connector, mode);
1384 modes++;
1385 }
1386 }
1387 }
1388 }
1389
1390 return modes;
1391}
1392
13931579
AJ		 1393static void
1394do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 1395{
13931579 1396 struct detailed_mode_closure *closure = c;
9cf00977 1397 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 1398
13931579
AJ		 1399 if (data->type == EDID_DETAIL_EST_TIMINGS)
1400 closure->modes += drm_est3_modes(closure->connector, timing);
1401}
9cf00977 1402
13931579
AJ		 1403/**
1404 * add_established_modes - get est. modes from EDID and add them
1405 * @edid: EDID block to scan
1406 *
1407 * Each EDID block contains a bitmap of the supported "established modes" list
1408 * (defined above). Tease them out and add them to the global modes list.
1409 */
1410static int
1411add_established_modes(struct drm_connector *connector, struct edid *edid)
1412{
1413 struct drm_device *dev = connector->dev;
1414 unsigned long est_bits = edid->established_timings.t1 |
1415 (edid->established_timings.t2 << 8) |
1416 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1417 int i, modes = 0;
1418 struct detailed_mode_closure closure = {
1419 connector, edid, 0, 0, 0
1420 };
9cf00977 1421
13931579
AJ		 1422 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1423 if (est_bits & (1<<i)) {
1424 struct drm_display_mode *newmode;
1425 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1426 if (newmode) {
1427 drm_mode_probed_add(connector, newmode);
1428 modes++;
1429 }
1430 }
9cf00977
AJ		 1431 }
1432
13931579
AJ		 1433 if (version_greater(edid, 1, 0))
1434 drm_for_each_detailed_block((u8 *)edid,
1435 do_established_modes, &closure);
1436
1437 return modes + closure.modes;
1438}
1439
1440static void
1441do_standard_modes(struct detailed_timing *timing, void *c)
1442{
1443 struct detailed_mode_closure *closure = c;
1444 struct detailed_non_pixel *data = &timing->data.other_data;
1445 struct drm_connector *connector = closure->connector;
1446 struct edid *edid = closure->edid;
1447
1448 if (data->type == EDID_DETAIL_STD_MODES) {
1449 int i;
9cf00977
AJ		 1450 for (i = 0; i < 6; i++) {
1451 struct std_timing *std;
1452 struct drm_display_mode *newmode;
1453
1454 std = &data->data.timings[i];
7a374350
AJ		 1455 newmode = drm_mode_std(connector, edid, std,
1456 edid->revision);
9cf00977
AJ		 1457 if (newmode) {
1458 drm_mode_probed_add(connector, newmode);
13931579 1459 closure->modes++;
9cf00977
AJ		 1460 }
1461 }
9cf00977 1462 }
9cf00977
AJ		 1463}
1464
f453ba04 1465/**
13931579 1466 * add_standard_modes - get std. modes from EDID and add them
f453ba04 1467 * @edid: EDID block to scan
f453ba04 1468 *
13931579
AJ		 1469 * Standard modes can be calculated using the appropriate standard (DMT,
1470 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 1471 */
13931579
AJ		 1472static int
1473add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 1474{
9cf00977 1475 int i, modes = 0;
13931579
AJ		 1476 struct detailed_mode_closure closure = {
1477 connector, edid, 0, 0, 0
1478 };
1479
1480 for (i = 0; i < EDID_STD_TIMINGS; i++) {
1481 struct drm_display_mode *newmode;
1482
1483 newmode = drm_mode_std(connector, edid,
1484 &edid->standard_timings[i],
1485 edid->revision);
1486 if (newmode) {
1487 drm_mode_probed_add(connector, newmode);
1488 modes++;
1489 }
1490 }
1491
1492 if (version_greater(edid, 1, 0))
1493 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
1494 &closure);
1495
1496 /* XXX should also look for standard codes in VTB blocks */
1497
1498 return modes + closure.modes;
1499}
f453ba04 1500
13931579
AJ		 1501static int drm_cvt_modes(struct drm_connector *connector,
1502 struct detailed_timing *timing)
1503{
1504 int i, j, modes = 0;
1505 struct drm_display_mode *newmode;
1506 struct drm_device *dev = connector->dev;
1507 struct cvt_timing *cvt;
1508 const int rates[] = { 60, 85, 75, 60, 50 };
1509 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 1510
13931579
AJ		 1511 for (i = 0; i < 4; i++) {
1512 int uninitialized_var(width), height;
1513 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 1514
13931579 1515 if (!memcmp(cvt->code, empty, 3))
9cf00977 1516 continue;
f453ba04 1517
13931579
AJ		 1518 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1519 switch (cvt->code[1] & 0x0c) {
1520 case 0x00:
1521 width = height * 4 / 3;
1522 break;
1523 case 0x04:
1524 width = height * 16 / 9;
1525 break;
1526 case 0x08:
1527 width = height * 16 / 10;
1528 break;
1529 case 0x0c:
1530 width = height * 15 / 9;
1531 break;
1532 }
1533
1534 for (j = 1; j < 5; j++) {
1535 if (cvt->code[2] & (1 << j)) {
1536 newmode = drm_cvt_mode(dev, width, height,
1537 rates[j], j == 0,
1538 false, false);
1539 if (newmode) {
1540 drm_mode_probed_add(connector, newmode);
1541 modes++;
1542 }
1543 }
1544 }
f453ba04
DA		 1545 }
1546
1547 return modes;
1548}
9cf00977 1549
13931579
AJ		 1550static void
1551do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 1552{
13931579
AJ		 1553 struct detailed_mode_closure *closure = c;
1554 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 1555
13931579
AJ		 1556 if (data->type == EDID_DETAIL_CVT_3BYTE)
1557 closure->modes += drm_cvt_modes(closure->connector, timing);
1558}
882f0219 1559
13931579
AJ		 1560static int
1561add_cvt_modes(struct drm_connector *connector, struct edid *edid)
1562{
1563 struct detailed_mode_closure closure = {
1564 connector, edid, 0, 0, 0
1565 };
882f0219 1566
13931579
AJ		 1567 if (version_greater(edid, 1, 2))
1568 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 1569
13931579 1570 /* XXX should also look for CVT codes in VTB blocks */
882f0219 1571
13931579
AJ		 1572 return closure.modes;
1573}
1574
1575static void
1576do_detailed_mode(struct detailed_timing *timing, void *c)
1577{
1578 struct detailed_mode_closure *closure = c;
1579 struct drm_display_mode *newmode;
1580
1581 if (timing->pixel_clock) {
1582 newmode = drm_mode_detailed(closure->connector->dev,
1583 closure->edid, timing,
1584 closure->quirks);
1585 if (!newmode)
1586 return;
1587
1588 if (closure->preferred)
1589 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1590
1591 drm_mode_probed_add(closure->connector, newmode);
1592 closure->modes++;
1593 closure->preferred = 0;
882f0219 1594 }
13931579 1595}
882f0219 1596
13931579
AJ		 1597/*
1598 * add_detailed_modes - Add modes from detailed timings
1599 * @connector: attached connector
1600 * @edid: EDID block to scan
1601 * @quirks: quirks to apply
1602 */
1603static int
1604add_detailed_modes(struct drm_connector *connector, struct edid *edid,
1605 u32 quirks)
1606{
1607 struct detailed_mode_closure closure = {
1608 connector,
1609 edid,
1610 1,
1611 quirks,
1612 0
1613 };
1614
1615 if (closure.preferred && !version_greater(edid, 1, 3))
1616 closure.preferred =
1617 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
1618
1619 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
1620
1621 return closure.modes;
882f0219 1622}
f453ba04 1623
f23c20c8
ML		 1624#define HDMI_IDENTIFIER 0x000C03
1625#define VENDOR_BLOCK 0x03
1626/**
1627 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
1628 * @edid: monitor EDID information
1629 *
1630 * Parse the CEA extension according to CEA-861-B.
1631 * Return true if HDMI, false if not or unknown.
1632 */
1633bool drm_detect_hdmi_monitor(struct edid *edid)
1634{
1635 char *edid_ext = NULL;
7466f4cc 1636 int i, hdmi_id;
f23c20c8
ML		 1637 int start_offset, end_offset;
1638 bool is_hdmi = false;
1639
1640 /* No EDID or EDID extensions */
1641 if (edid == NULL || edid->extensions == 0)
1642 goto end;
1643
f23c20c8 1644 /* Find CEA extension */
7466f4cc 1645 for (i = 0; i < edid->extensions; i++) {
f23c20c8
ML		 1646 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
1647 /* This block is CEA extension */
1648 if (edid_ext[0] == 0x02)
1649 break;
1650 }
1651
7466f4cc 1652 if (i == edid->extensions)
f23c20c8
ML		 1653 goto end;
1654
1655 /* Data block offset in CEA extension block */
1656 start_offset = 4;
1657 end_offset = edid_ext[2];
1658
1659 /*
1660 * Because HDMI identifier is in Vendor Specific Block,
1661 * search it from all data blocks of CEA extension.
1662 */
1663 for (i = start_offset; i < end_offset;
1664 /* Increased by data block len */
1665 i += ((edid_ext[i] & 0x1f) + 1)) {
1666 /* Find vendor specific block */
1667 if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1668 hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1669 edid_ext[i + 3] << 16;
1670 /* Find HDMI identifier */
1671 if (hdmi_id == HDMI_IDENTIFIER)
1672 is_hdmi = true;
1673 break;
1674 }
1675 }
1676
1677end:
1678 return is_hdmi;
1679}
1680EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1681
f453ba04
DA		 1682/**
1683 * drm_add_edid_modes - add modes from EDID data, if available
1684 * @connector: connector we're probing
1685 * @edid: edid data
1686 *
1687 * Add the specified modes to the connector's mode list.
1688 *
1689 * Return number of modes added or 0 if we couldn't find any.
1690 */
1691int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1692{
1693 int num_modes = 0;
1694 u32 quirks;
1695
1696 if (edid == NULL) {
1697 return 0;
1698 }
3c537889 1699 if (!drm_edid_is_valid(edid)) {
dcdb1674 1700 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
f453ba04
DA		 1701 drm_get_connector_name(connector));
1702 return 0;
1703 }
1704
1705 quirks = edid_get_quirks(edid);
1706
c867df70
AJ		 1707 /*
1708 * EDID spec says modes should be preferred in this order:
1709 * - preferred detailed mode
1710 * - other detailed modes from base block
1711 * - detailed modes from extension blocks
1712 * - CVT 3-byte code modes
1713 * - standard timing codes
1714 * - established timing codes
1715 * - modes inferred from GTF or CVT range information
1716 *
13931579 1717 * We get this pretty much right.
c867df70
AJ		 1718 *
1719 * XXX order for additional mode types in extension blocks?
1720 */
13931579
AJ		 1721 num_modes += add_detailed_modes(connector, edid, quirks);
1722 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 1723 num_modes += add_standard_modes(connector, edid);
1724 num_modes += add_established_modes(connector, edid);
13931579 1725 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 1726
1727 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1728 edid_fixup_preferred(connector, quirks);
1729
f453ba04
DA		 1730 connector->display_info.width_mm = edid->width_cm * 10;
1731 connector->display_info.height_mm = edid->height_cm * 10;
f453ba04
DA		 1732
1733 return num_modes;
1734}
1735EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 1736
1737/**
1738 * drm_add_modes_noedid - add modes for the connectors without EDID
1739 * @connector: connector we're probing
1740 * @hdisplay: the horizontal display limit
1741 * @vdisplay: the vertical display limit
1742 *
1743 * Add the specified modes to the connector's mode list. Only when the
1744 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1745 *
1746 * Return number of modes added or 0 if we couldn't find any.
1747 */
1748int drm_add_modes_noedid(struct drm_connector *connector,
1749 int hdisplay, int vdisplay)
1750{
1751 int i, count, num_modes = 0;
1752 struct drm_display_mode *mode, *ptr;
1753 struct drm_device *dev = connector->dev;
1754
1755 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1756 if (hdisplay < 0)
1757 hdisplay = 0;
1758 if (vdisplay < 0)
1759 vdisplay = 0;
1760
1761 for (i = 0; i < count; i++) {
1762 ptr = &drm_dmt_modes[i];
1763 if (hdisplay && vdisplay) {
1764 /*
1765 * Only when two are valid, they will be used to check
1766 * whether the mode should be added to the mode list of
1767 * the connector.
1768 */
1769 if (ptr->hdisplay > hdisplay ||
1770 ptr->vdisplay > vdisplay)
1771 continue;
1772 }
f985dedb
AJ		 1773 if (drm_mode_vrefresh(ptr) > 61)
1774 continue;
f0fda0a4
ZY		 1775 mode = drm_mode_duplicate(dev, ptr);
1776 if (mode) {
1777 drm_mode_probed_add(connector, mode);
1778 num_modes++;
1779 }
1780 }
1781 return num_modes;
1782}
1783EXPORT_SYMBOL(drm_add_modes_noedid);
Linux kernel - Deliverables
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