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drm/connector: store tile information from displayid (v3)
[deliverable/linux.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
760285e7
DH		 35#include <drm/drmP.h>
36#include <drm/drm_edid.h>
40d9b043 37#include <drm/drm_displayid.h>
f453ba04 38
13931579
AJ		 39#define version_greater(edid, maj, min) \
40 (((edid)->version > (maj)) || \
41 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 42
d1ff6409
AJ		 43#define EDID_EST_TIMINGS 16
44#define EDID_STD_TIMINGS 8
45#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 46
47/*
48 * EDID blocks out in the wild have a variety of bugs, try to collect
49 * them here (note that userspace may work around broken monitors first,
50 * but fixes should make their way here so that the kernel "just works"
51 * on as many displays as possible).
52 */
53
54/* First detailed mode wrong, use largest 60Hz mode */
55#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
56/* Reported 135MHz pixel clock is too high, needs adjustment */
57#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
58/* Prefer the largest mode at 75 Hz */
59#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
60/* Detail timing is in cm not mm */
61#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
62/* Detailed timing descriptors have bogus size values, so just take the
63 * maximum size and use that.
64 */
65#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
66/* Monitor forgot to set the first detailed is preferred bit. */
67#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
68/* use +hsync +vsync for detailed mode */
69#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 70/* Force reduced-blanking timings for detailed modes */
71#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 72/* Force 8bpc */
73#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 74/* Force 12bpc */
75#define EDID_QUIRK_FORCE_12BPC (1 << 9)
3c537889 76
13931579
AJ		 77struct detailed_mode_closure {
78 struct drm_connector *connector;
79 struct edid *edid;
80 bool preferred;
81 u32 quirks;
82 int modes;
83};
f453ba04 84
5c61259e
ZY		 85#define LEVEL_DMT 0
86#define LEVEL_GTF 1
7a374350
AJ		 87#define LEVEL_GTF2 2
88#define LEVEL_CVT 3
5c61259e 89
f453ba04 90static struct edid_quirk {
c51a3fd6 91 char vendor[4];
f453ba04
DA		 92 int product_id;
93 u32 quirks;
94} edid_quirk_list[] = {
95 /* Acer AL1706 */
96 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
97 /* Acer F51 */
98 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
99 /* Unknown Acer */
100 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
101
102 /* Belinea 10 15 55 */
103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
105
106 /* Envision Peripherals, Inc. EN-7100e */
107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 108 /* Envision EN2028 */
109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 110
111 /* Funai Electronics PM36B */
112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
113 EDID_QUIRK_DETAILED_IN_CM },
114
115 /* LG Philips LCD LP154W01-A5 */
116 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
117 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
118
119 /* Philips 107p5 CRT */
120 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
121
122 /* Proview AY765C */
123 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
124
125 /* Samsung SyncMaster 205BW. Note: irony */
126 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
127 /* Samsung SyncMaster 22[5-6]BW */
128 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
129 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 130
bc5b9641
MK		 131 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
132 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
133
bc42aabc
AJ		 134 /* ViewSonic VA2026w */
135 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 136
137 /* Medion MD 30217 PG */
138 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 139
140 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
141 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
f453ba04
DA		 142};
143
a6b21831
TR		 144/*
145 * Autogenerated from the DMT spec.
146 * This table is copied from xfree86/modes/xf86EdidModes.c.
147 */
148static const struct drm_display_mode drm_dmt_modes[] = {
149 /* 640x350@85Hz */
150 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
151 736, 832, 0, 350, 382, 385, 445, 0,
152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
153 /* 640x400@85Hz */
154 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
155 736, 832, 0, 400, 401, 404, 445, 0,
156 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
157 /* 720x400@85Hz */
158 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
159 828, 936, 0, 400, 401, 404, 446, 0,
160 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
161 /* 640x480@60Hz */
162 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
163 752, 800, 0, 480, 489, 492, 525, 0,
164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
165 /* 640x480@72Hz */
166 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
167 704, 832, 0, 480, 489, 492, 520, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
169 /* 640x480@75Hz */
170 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
171 720, 840, 0, 480, 481, 484, 500, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
173 /* 640x480@85Hz */
174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
175 752, 832, 0, 480, 481, 484, 509, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
177 /* 800x600@56Hz */
178 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
179 896, 1024, 0, 600, 601, 603, 625, 0,
180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
181 /* 800x600@60Hz */
182 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
183 968, 1056, 0, 600, 601, 605, 628, 0,
184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
185 /* 800x600@72Hz */
186 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
187 976, 1040, 0, 600, 637, 643, 666, 0,
188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
189 /* 800x600@75Hz */
190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
191 896, 1056, 0, 600, 601, 604, 625, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 800x600@85Hz */
194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
195 896, 1048, 0, 600, 601, 604, 631, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 800x600@120Hz RB */
198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
199 880, 960, 0, 600, 603, 607, 636, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
201 /* 848x480@60Hz */
202 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
203 976, 1088, 0, 480, 486, 494, 517, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 1024x768@43Hz, interlace */
206 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
207 1208, 1264, 0, 768, 768, 772, 817, 0,
208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
209 DRM_MODE_FLAG_INTERLACE) },
210 /* 1024x768@60Hz */
211 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
212 1184, 1344, 0, 768, 771, 777, 806, 0,
213 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
214 /* 1024x768@70Hz */
215 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
216 1184, 1328, 0, 768, 771, 777, 806, 0,
217 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
218 /* 1024x768@75Hz */
219 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
220 1136, 1312, 0, 768, 769, 772, 800, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
222 /* 1024x768@85Hz */
223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
224 1168, 1376, 0, 768, 769, 772, 808, 0,
225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
226 /* 1024x768@120Hz RB */
227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
228 1104, 1184, 0, 768, 771, 775, 813, 0,
229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
230 /* 1152x864@75Hz */
231 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
232 1344, 1600, 0, 864, 865, 868, 900, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
234 /* 1280x768@60Hz RB */
235 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
236 1360, 1440, 0, 768, 771, 778, 790, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
238 /* 1280x768@60Hz */
239 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
240 1472, 1664, 0, 768, 771, 778, 798, 0,
241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
242 /* 1280x768@75Hz */
243 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
244 1488, 1696, 0, 768, 771, 778, 805, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
246 /* 1280x768@85Hz */
247 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
248 1496, 1712, 0, 768, 771, 778, 809, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 1280x768@120Hz RB */
251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
252 1360, 1440, 0, 768, 771, 778, 813, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
254 /* 1280x800@60Hz RB */
255 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
256 1360, 1440, 0, 800, 803, 809, 823, 0,
257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 1280x800@60Hz */
259 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
260 1480, 1680, 0, 800, 803, 809, 831, 0,
261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 1280x800@75Hz */
263 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
264 1488, 1696, 0, 800, 803, 809, 838, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 1280x800@85Hz */
267 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
268 1496, 1712, 0, 800, 803, 809, 843, 0,
269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 1280x800@120Hz RB */
271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
272 1360, 1440, 0, 800, 803, 809, 847, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
274 /* 1280x960@60Hz */
275 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
276 1488, 1800, 0, 960, 961, 964, 1000, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 1280x960@85Hz */
279 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
280 1504, 1728, 0, 960, 961, 964, 1011, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 1280x960@120Hz RB */
283 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
284 1360, 1440, 0, 960, 963, 967, 1017, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
286 /* 1280x1024@60Hz */
287 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
288 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 1280x1024@75Hz */
291 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
292 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 1280x1024@85Hz */
295 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
296 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 1280x1024@120Hz RB */
299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
300 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 1360x768@60Hz */
303 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
304 1536, 1792, 0, 768, 771, 777, 795, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 1360x768@120Hz RB */
307 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
308 1440, 1520, 0, 768, 771, 776, 813, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 1400x1050@60Hz RB */
311 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
312 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 1400x1050@60Hz */
315 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
316 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 1400x1050@75Hz */
319 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
320 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 1400x1050@85Hz */
323 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
324 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 1400x1050@120Hz RB */
327 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
328 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
330 /* 1440x900@60Hz RB */
331 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
332 1520, 1600, 0, 900, 903, 909, 926, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 1440x900@60Hz */
335 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
336 1672, 1904, 0, 900, 903, 909, 934, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 1440x900@75Hz */
339 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
340 1688, 1936, 0, 900, 903, 909, 942, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 1440x900@85Hz */
343 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
344 1696, 1952, 0, 900, 903, 909, 948, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 1440x900@120Hz RB */
347 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
348 1520, 1600, 0, 900, 903, 909, 953, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 1600x1200@60Hz */
351 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
352 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 1600x1200@65Hz */
355 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
356 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 1600x1200@70Hz */
359 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
360 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 1600x1200@75Hz */
363 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
364 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 1600x1200@85Hz */
367 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
368 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 1600x1200@120Hz RB */
371 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
372 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 1680x1050@60Hz RB */
375 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
376 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
378 /* 1680x1050@60Hz */
379 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
380 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 1680x1050@75Hz */
383 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
384 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 1680x1050@85Hz */
387 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
388 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
389 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 1680x1050@120Hz RB */
391 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
392 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
394 /* 1792x1344@60Hz */
395 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
396 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 1792x1344@75Hz */
399 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
400 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 1792x1344@120Hz RB */
403 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
404 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 1856x1392@60Hz */
407 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
408 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 1856x1392@75Hz */
411 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
412 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 1856x1392@120Hz RB */
415 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
416 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 1920x1200@60Hz RB */
419 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
420 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 1920x1200@60Hz */
423 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
424 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 1920x1200@75Hz */
427 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
428 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 1920x1200@85Hz */
431 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
432 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 1920x1200@120Hz RB */
435 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
436 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 1920x1440@60Hz */
439 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
440 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 1920x1440@75Hz */
443 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
444 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 1920x1440@120Hz RB */
447 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
448 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 2560x1600@60Hz RB */
451 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
452 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 2560x1600@60Hz */
455 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
456 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 2560x1600@75HZ */
459 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
460 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 2560x1600@85HZ */
463 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
464 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 2560x1600@120Hz RB */
467 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
468 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470};
471
e7bfa5c4
VS		 472/*
473 * These more or less come from the DMT spec. The 720x400 modes are
474 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
475 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
476 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
477 * mode.
478 *
479 * The DMT modes have been fact-checked; the rest are mild guesses.
480 */
a6b21831
TR		 481static const struct drm_display_mode edid_est_modes[] = {
482 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
483 968, 1056, 0, 600, 601, 605, 628, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
485 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
486 896, 1024, 0, 600, 601, 603, 625, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
488 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
489 720, 840, 0, 480, 481, 484, 500, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
492 704, 832, 0, 480, 489, 491, 520, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
494 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
495 768, 864, 0, 480, 483, 486, 525, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
497 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
498 752, 800, 0, 480, 490, 492, 525, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
500 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
501 846, 900, 0, 400, 421, 423, 449, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
503 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
504 846, 900, 0, 400, 412, 414, 449, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
506 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
507 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
509 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
510 1136, 1312, 0, 768, 769, 772, 800, 0,
511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
512 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
513 1184, 1328, 0, 768, 771, 777, 806, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
515 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
516 1184, 1344, 0, 768, 771, 777, 806, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
518 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
519 1208, 1264, 0, 768, 768, 776, 817, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
521 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
522 928, 1152, 0, 624, 625, 628, 667, 0,
523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
524 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
525 896, 1056, 0, 600, 601, 604, 625, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
527 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
528 976, 1040, 0, 600, 637, 643, 666, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
530 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
531 1344, 1600, 0, 864, 865, 868, 900, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
533};
534
535struct minimode {
536 short w;
537 short h;
538 short r;
539 short rb;
540};
541
542static const struct minimode est3_modes[] = {
543 /* byte 6 */
544 { 640, 350, 85, 0 },
545 { 640, 400, 85, 0 },
546 { 720, 400, 85, 0 },
547 { 640, 480, 85, 0 },
548 { 848, 480, 60, 0 },
549 { 800, 600, 85, 0 },
550 { 1024, 768, 85, 0 },
551 { 1152, 864, 75, 0 },
552 /* byte 7 */
553 { 1280, 768, 60, 1 },
554 { 1280, 768, 60, 0 },
555 { 1280, 768, 75, 0 },
556 { 1280, 768, 85, 0 },
557 { 1280, 960, 60, 0 },
558 { 1280, 960, 85, 0 },
559 { 1280, 1024, 60, 0 },
560 { 1280, 1024, 85, 0 },
561 /* byte 8 */
562 { 1360, 768, 60, 0 },
563 { 1440, 900, 60, 1 },
564 { 1440, 900, 60, 0 },
565 { 1440, 900, 75, 0 },
566 { 1440, 900, 85, 0 },
567 { 1400, 1050, 60, 1 },
568 { 1400, 1050, 60, 0 },
569 { 1400, 1050, 75, 0 },
570 /* byte 9 */
571 { 1400, 1050, 85, 0 },
572 { 1680, 1050, 60, 1 },
573 { 1680, 1050, 60, 0 },
574 { 1680, 1050, 75, 0 },
575 { 1680, 1050, 85, 0 },
576 { 1600, 1200, 60, 0 },
577 { 1600, 1200, 65, 0 },
578 { 1600, 1200, 70, 0 },
579 /* byte 10 */
580 { 1600, 1200, 75, 0 },
581 { 1600, 1200, 85, 0 },
582 { 1792, 1344, 60, 0 },
c068b32a 583 { 1792, 1344, 75, 0 },
a6b21831
TR		 584 { 1856, 1392, 60, 0 },
585 { 1856, 1392, 75, 0 },
586 { 1920, 1200, 60, 1 },
587 { 1920, 1200, 60, 0 },
588 /* byte 11 */
589 { 1920, 1200, 75, 0 },
590 { 1920, 1200, 85, 0 },
591 { 1920, 1440, 60, 0 },
592 { 1920, 1440, 75, 0 },
593};
594
595static const struct minimode extra_modes[] = {
596 { 1024, 576, 60, 0 },
597 { 1366, 768, 60, 0 },
598 { 1600, 900, 60, 0 },
599 { 1680, 945, 60, 0 },
600 { 1920, 1080, 60, 0 },
601 { 2048, 1152, 60, 0 },
602 { 2048, 1536, 60, 0 },
603};
604
605/*
606 * Probably taken from CEA-861 spec.
607 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
608 */
609static const struct drm_display_mode edid_cea_modes[] = {
610 /* 1 - 640x480@60Hz */
611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
612 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 614 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 615 /* 2 - 720x480@60Hz */
616 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
617 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 619 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 620 /* 3 - 720x480@60Hz */
621 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
622 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 624 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 625 /* 4 - 1280x720@60Hz */
626 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
627 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 629 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 630 /* 5 - 1920x1080i@60Hz */
631 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
632 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 634 DRM_MODE_FLAG_INTERLACE),
985e5dc2 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 636 /* 6 - 720(1440)x480i@60Hz */
637 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
638 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 640 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 641 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 642 /* 7 - 720(1440)x480i@60Hz */
643 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
644 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 646 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 647 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 648 /* 8 - 720(1440)x240@60Hz */
649 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
650 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 652 DRM_MODE_FLAG_DBLCLK),
985e5dc2 653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 654 /* 9 - 720(1440)x240@60Hz */
655 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
656 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 658 DRM_MODE_FLAG_DBLCLK),
985e5dc2 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 660 /* 10 - 2880x480i@60Hz */
661 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
662 3204, 3432, 0, 480, 488, 494, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 664 DRM_MODE_FLAG_INTERLACE),
985e5dc2 665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 666 /* 11 - 2880x480i@60Hz */
667 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
668 3204, 3432, 0, 480, 488, 494, 525, 0,
669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 670 DRM_MODE_FLAG_INTERLACE),
985e5dc2 671 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 672 /* 12 - 2880x240@60Hz */
673 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
674 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 677 /* 13 - 2880x240@60Hz */
678 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
679 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 682 /* 14 - 1440x480@60Hz */
683 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
684 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 687 /* 15 - 1440x480@60Hz */
688 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
689 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 692 /* 16 - 1920x1080@60Hz */
693 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
694 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 697 /* 17 - 720x576@50Hz */
698 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
699 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 701 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 702 /* 18 - 720x576@50Hz */
703 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
704 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 706 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 707 /* 19 - 1280x720@50Hz */
708 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
709 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 711 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 712 /* 20 - 1920x1080i@50Hz */
713 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
714 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
715 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 716 DRM_MODE_FLAG_INTERLACE),
985e5dc2 717 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 718 /* 21 - 720(1440)x576i@50Hz */
719 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
720 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 722 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 723 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 724 /* 22 - 720(1440)x576i@50Hz */
725 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
726 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 728 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 729 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 730 /* 23 - 720(1440)x288@50Hz */
731 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
732 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 734 DRM_MODE_FLAG_DBLCLK),
985e5dc2 735 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 736 /* 24 - 720(1440)x288@50Hz */
737 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
738 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 740 DRM_MODE_FLAG_DBLCLK),
985e5dc2 741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 742 /* 25 - 2880x576i@50Hz */
743 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
744 3180, 3456, 0, 576, 580, 586, 625, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 746 DRM_MODE_FLAG_INTERLACE),
985e5dc2 747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 748 /* 26 - 2880x576i@50Hz */
749 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
750 3180, 3456, 0, 576, 580, 586, 625, 0,
751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 752 DRM_MODE_FLAG_INTERLACE),
985e5dc2 753 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 754 /* 27 - 2880x288@50Hz */
755 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
756 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 757 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 758 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 759 /* 28 - 2880x288@50Hz */
760 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
761 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 763 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 764 /* 29 - 1440x576@50Hz */
765 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
766 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 769 /* 30 - 1440x576@50Hz */
770 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
771 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 774 /* 31 - 1920x1080@50Hz */
775 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
776 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 779 /* 32 - 1920x1080@24Hz */
780 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
781 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 782 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 783 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 784 /* 33 - 1920x1080@25Hz */
785 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
786 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 788 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 789 /* 34 - 1920x1080@30Hz */
790 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
791 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 792 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 793 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 794 /* 35 - 2880x480@60Hz */
795 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
796 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 798 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 799 /* 36 - 2880x480@60Hz */
800 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
801 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 803 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 804 /* 37 - 2880x576@50Hz */
805 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
806 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 809 /* 38 - 2880x576@50Hz */
810 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
811 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 814 /* 39 - 1920x1080i@50Hz */
815 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
816 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 818 DRM_MODE_FLAG_INTERLACE),
985e5dc2 819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 820 /* 40 - 1920x1080i@100Hz */
821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 824 DRM_MODE_FLAG_INTERLACE),
985e5dc2 825 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 826 /* 41 - 1280x720@100Hz */
827 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
828 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 830 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 831 /* 42 - 720x576@100Hz */
832 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
833 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 835 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 836 /* 43 - 720x576@100Hz */
837 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
838 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 840 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 841 /* 44 - 720(1440)x576i@100Hz */
842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 846 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 847 /* 45 - 720(1440)x576i@100Hz */
848 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
849 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 851 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 852 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 853 /* 46 - 1920x1080i@120Hz */
854 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
855 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 857 DRM_MODE_FLAG_INTERLACE),
985e5dc2 858 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 859 /* 47 - 1280x720@120Hz */
860 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
861 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 863 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 864 /* 48 - 720x480@120Hz */
865 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
866 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 868 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 869 /* 49 - 720x480@120Hz */
870 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
871 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 873 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 874 /* 50 - 720(1440)x480i@120Hz */
875 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
876 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 878 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 879 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 880 /* 51 - 720(1440)x480i@120Hz */
881 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
882 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 884 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 885 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 886 /* 52 - 720x576@200Hz */
887 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
888 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 890 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 891 /* 53 - 720x576@200Hz */
892 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
893 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 895 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 896 /* 54 - 720(1440)x576i@200Hz */
897 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
898 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 901 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 902 /* 55 - 720(1440)x576i@200Hz */
903 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
904 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 906 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 907 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 908 /* 56 - 720x480@240Hz */
909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
910 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 912 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 913 /* 57 - 720x480@240Hz */
914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
915 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 917 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 918 /* 58 - 720(1440)x480i@240 */
919 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
920 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 923 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 924 /* 59 - 720(1440)x480i@240 */
925 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
926 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 928 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 929 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 930 /* 60 - 1280x720@24Hz */
931 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
932 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 934 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 935 /* 61 - 1280x720@25Hz */
936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
937 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 939 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 940 /* 62 - 1280x720@30Hz */
941 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
942 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 944 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 945 /* 63 - 1920x1080@120Hz */
946 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
947 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 949 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 950 /* 64 - 1920x1080@100Hz */
951 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
952 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
ee7925bb 953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 955};
956
7ebe1963
LD		 957/*
958 * HDMI 1.4 4k modes.
959 */
960static const struct drm_display_mode edid_4k_modes[] = {
961 /* 1 - 3840x2160@30Hz */
962 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
963 3840, 4016, 4104, 4400, 0,
964 2160, 2168, 2178, 2250, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
966 .vrefresh = 30, },
967 /* 2 - 3840x2160@25Hz */
968 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
969 3840, 4896, 4984, 5280, 0,
970 2160, 2168, 2178, 2250, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .vrefresh = 25, },
973 /* 3 - 3840x2160@24Hz */
974 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
975 3840, 5116, 5204, 5500, 0,
976 2160, 2168, 2178, 2250, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 24, },
979 /* 4 - 4096x2160@24Hz (SMPTE) */
980 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
981 4096, 5116, 5204, 5500, 0,
982 2160, 2168, 2178, 2250, 0,
983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
984 .vrefresh = 24, },
985};
986
61e57a8d 987/*** DDC fetch and block validation ***/
f453ba04 988
083ae056
AJ		 989static const u8 edid_header[] = {
990 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
991};
f453ba04 992
db6cf833
TR		 993/**
994 * drm_edid_header_is_valid - sanity check the header of the base EDID block
995 * @raw_edid: pointer to raw base EDID block
996 *
997 * Sanity check the header of the base EDID block.
998 *
999 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1000 */
1001int drm_edid_header_is_valid(const u8 *raw_edid)
1002{
1003 int i, score = 0;
1004
1005 for (i = 0; i < sizeof(edid_header); i++)
1006 if (raw_edid[i] == edid_header[i])
1007 score++;
1008
1009 return score;
1010}
1011EXPORT_SYMBOL(drm_edid_header_is_valid);
1012
47819ba2
AJ		 1013static int edid_fixup __read_mostly = 6;
1014module_param_named(edid_fixup, edid_fixup, int, 0400);
1015MODULE_PARM_DESC(edid_fixup,
1016 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1017
40d9b043
DA		 1018static void drm_get_displayid(struct drm_connector *connector,
1019 struct edid *edid);
db6cf833
TR		 1020/**
1021 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1022 * @raw_edid: pointer to raw EDID block
1023 * @block: type of block to validate (0 for base, extension otherwise)
1024 * @print_bad_edid: if true, dump bad EDID blocks to the console
1025 *
1026 * Validate a base or extension EDID block and optionally dump bad blocks to
1027 * the console.
1028 *
1029 * Return: True if the block is valid, false otherwise.
f453ba04 1030 */
0b2443ed 1031bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
f453ba04 1032{
61e57a8d 1033 int i;
f453ba04 1034 u8 csum = 0;
61e57a8d 1035 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1036
fe2ef780
SWK		 1037 if (WARN_ON(!raw_edid))
1038 return false;
1039
47819ba2
AJ		 1040 if (edid_fixup > 8 || edid_fixup < 0)
1041 edid_fixup = 6;
1042
f89ec8a4 1043 if (block == 0) {
051963d4 1044 int score = drm_edid_header_is_valid(raw_edid);
61e57a8d 1045 if (score == 8) ;
47819ba2 1046 else if (score >= edid_fixup) {
61e57a8d
AJ		 1047 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1048 memcpy(raw_edid, edid_header, sizeof(edid_header));
1049 } else {
1050 goto bad;
1051 }
1052 }
f453ba04
DA		 1053
1054 for (i = 0; i < EDID_LENGTH; i++)
1055 csum += raw_edid[i];
1056 if (csum) {
0b2443ed
JG		 1057 if (print_bad_edid) {
1058 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1059 }
4a638b4e
AJ		 1060
1061 /* allow CEA to slide through, switches mangle this */
1062 if (raw_edid[0] != 0x02)
1063 goto bad;
f453ba04
DA		 1064 }
1065
61e57a8d
AJ		 1066 /* per-block-type checks */
1067 switch (raw_edid[0]) {
1068 case 0: /* base */
1069 if (edid->version != 1) {
1070 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1071 goto bad;
1072 }
862b89c0 1073
61e57a8d
AJ		 1074 if (edid->revision > 4)
1075 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1076 break;
862b89c0 1077
61e57a8d
AJ		 1078 default:
1079 break;
1080 }
47ee4ccf 1081
fe2ef780 1082 return true;
f453ba04
DA		 1083
1084bad:
fe2ef780 1085 if (print_bad_edid) {
f49dadb8 1086 printk(KERN_ERR "Raw EDID:\n");
0aff47f2
TV		 1087 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1088 raw_edid, EDID_LENGTH, false);
f453ba04 1089 }
fe2ef780 1090 return false;
f453ba04 1091}
da0df92b 1092EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1093
1094/**
1095 * drm_edid_is_valid - sanity check EDID data
1096 * @edid: EDID data
1097 *
1098 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1099 *
1100 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1101 */
1102bool drm_edid_is_valid(struct edid *edid)
1103{
1104 int i;
1105 u8 *raw = (u8 *)edid;
1106
1107 if (!edid)
1108 return false;
1109
1110 for (i = 0; i <= edid->extensions; i++)
0b2443ed 1111 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true))
61e57a8d
AJ		 1112 return false;
1113
1114 return true;
1115}
3c537889 1116EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1117
61e57a8d
AJ		 1118#define DDC_SEGMENT_ADDR 0x30
1119/**
db6cf833
TR		 1120 * drm_do_probe_ddc_edid() - get EDID information via I2C
1121 * @adapter: I2C device adaptor
fc66811c
DV		 1122 * @buf: EDID data buffer to be filled
1123 * @block: 128 byte EDID block to start fetching from
1124 * @len: EDID data buffer length to fetch
1125 *
db6cf833 1126 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1127 *
db6cf833 1128 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1129 */
1130static int
18df89fe 1131drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1132{
18df89fe 1133 struct i2c_adapter *adapter = data;
61e57a8d 1134 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1135 unsigned char segment = block >> 1;
1136 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1137 int ret, retries = 5;
1138
db6cf833
TR		 1139 /*
1140 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1141 * adapter reports EAGAIN. However, we find that bit-banging transfers
1142 * are susceptible to errors under a heavily loaded machine and
1143 * generate spurious NAKs and timeouts. Retrying the transfer
1144 * of the individual block a few times seems to overcome this.
1145 */
1146 do {
1147 struct i2c_msg msgs[] = {
1148 {
cd004b3f
S		 1149 .addr = DDC_SEGMENT_ADDR,
1150 .flags = 0,
1151 .len = 1,
1152 .buf = &segment,
1153 }, {
4819d2e4
CW		 1154 .addr = DDC_ADDR,
1155 .flags = 0,
1156 .len = 1,
1157 .buf = &start,
1158 }, {
1159 .addr = DDC_ADDR,
1160 .flags = I2C_M_RD,
1161 .len = len,
1162 .buf = buf,
1163 }
1164 };
cd004b3f 1165
db6cf833
TR		 1166 /*
1167 * Avoid sending the segment addr to not upset non-compliant
1168 * DDC monitors.
1169 */
cd004b3f
S		 1170 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1171
9292f37e
ED		 1172 if (ret == -ENXIO) {
1173 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1174 adapter->name);
1175 break;
1176 }
cd004b3f 1177 } while (ret != xfers && --retries);
4819d2e4 1178
cd004b3f 1179 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1180}
1181
4a9a8b71
DA		 1182static bool drm_edid_is_zero(u8 *in_edid, int length)
1183{
6311803b
AM		 1184 if (memchr_inv(in_edid, 0, length))
1185 return false;
4a9a8b71 1186
4a9a8b71
DA		 1187 return true;
1188}
1189
18df89fe
LPC		 1190/**
1191 * drm_do_get_edid - get EDID data using a custom EDID block read function
1192 * @connector: connector we're probing
1193 * @get_edid_block: EDID block read function
1194 * @data: private data passed to the block read function
1195 *
1196 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1197 * exposes a different interface to read EDID blocks this function can be used
1198 * to get EDID data using a custom block read function.
1199 *
1200 * As in the general case the DDC bus is accessible by the kernel at the I2C
1201 * level, drivers must make all reasonable efforts to expose it as an I2C
1202 * adapter and use drm_get_edid() instead of abusing this function.
1203 *
1204 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1205 */
1206struct edid *drm_do_get_edid(struct drm_connector *connector,
1207 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1208 size_t len),
1209 void *data)
61e57a8d 1210{
0ea75e23 1211 int i, j = 0, valid_extensions = 0;
61e57a8d 1212 u8 *block, *new;
0b2443ed 1213 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
61e57a8d
AJ		 1214
1215 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1216 return NULL;
1217
1218 /* base block fetch */
1219 for (i = 0; i < 4; i++) {
18df89fe 1220 if (get_edid_block(data, block, 0, EDID_LENGTH))
61e57a8d 1221 goto out;
0b2443ed 1222 if (drm_edid_block_valid(block, 0, print_bad_edid))
61e57a8d 1223 break;
4a9a8b71
DA		 1224 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1225 connector->null_edid_counter++;
1226 goto carp;
1227 }
61e57a8d
AJ		 1228 }
1229 if (i == 4)
1230 goto carp;
1231
1232 /* if there's no extensions, we're done */
1233 if (block[0x7e] == 0)
18df89fe 1234 return (struct edid *)block;
61e57a8d
AJ		 1235
1236 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1237 if (!new)
1238 goto out;
1239 block = new;
1240
1241 for (j = 1; j <= block[0x7e]; j++) {
1242 for (i = 0; i < 4; i++) {
18df89fe 1243 if (get_edid_block(data,
0ea75e23
ST		 1244 block + (valid_extensions + 1) * EDID_LENGTH,
1245 j, EDID_LENGTH))
61e57a8d 1246 goto out;
0b2443ed 1247 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) {
0ea75e23 1248 valid_extensions++;
61e57a8d 1249 break;
0ea75e23 1250 }
61e57a8d 1251 }
f934ec8c
ML		 1252
1253 if (i == 4 && print_bad_edid) {
0ea75e23
ST		 1254 dev_warn(connector->dev->dev,
1255 "%s: Ignoring invalid EDID block %d.\n",
25933820 1256 connector->name, j);
f934ec8c
ML		 1257
1258 connector->bad_edid_counter++;
1259 }
0ea75e23
ST		 1260 }
1261
1262 if (valid_extensions != block[0x7e]) {
1263 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1264 block[0x7e] = valid_extensions;
1265 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1266 if (!new)
1267 goto out;
1268 block = new;
61e57a8d
AJ		 1269 }
1270
18df89fe 1271 return (struct edid *)block;
61e57a8d
AJ		 1272
1273carp:
0b2443ed
JG		 1274 if (print_bad_edid) {
1275 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
25933820 1276 connector->name, j);
0b2443ed
JG		 1277 }
1278 connector->bad_edid_counter++;
61e57a8d
AJ		 1279
1280out:
1281 kfree(block);
1282 return NULL;
1283}
18df89fe 1284EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1285
1286/**
db6cf833
TR		 1287 * drm_probe_ddc() - probe DDC presence
1288 * @adapter: I2C adapter to probe
fc66811c 1289 *
db6cf833 1290 * Return: True on success, false on failure.
61e57a8d 1291 */
fbff4690 1292bool
61e57a8d
AJ		 1293drm_probe_ddc(struct i2c_adapter *adapter)
1294{
1295 unsigned char out;
1296
1297 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1298}
fbff4690 1299EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1300
1301/**
1302 * drm_get_edid - get EDID data, if available
1303 * @connector: connector we're probing
db6cf833 1304 * @adapter: I2C adapter to use for DDC
61e57a8d 1305 *
db6cf833 1306 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1307 * attach it to the connector.
1308 *
db6cf833 1309 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1310 */
1311struct edid *drm_get_edid(struct drm_connector *connector,
1312 struct i2c_adapter *adapter)
1313{
40d9b043
DA		 1314 struct edid *edid;
1315
18df89fe
LPC		 1316 if (!drm_probe_ddc(adapter))
1317 return NULL;
61e57a8d 1318
40d9b043
DA		 1319 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1320 if (edid)
1321 drm_get_displayid(connector, edid);
1322 return edid;
61e57a8d
AJ		 1323}
1324EXPORT_SYMBOL(drm_get_edid);
1325
51f8da59
JN		 1326/**
1327 * drm_edid_duplicate - duplicate an EDID and the extensions
1328 * @edid: EDID to duplicate
1329 *
db6cf833 1330 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1331 */
1332struct edid *drm_edid_duplicate(const struct edid *edid)
1333{
1334 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1335}
1336EXPORT_SYMBOL(drm_edid_duplicate);
1337
61e57a8d
AJ		 1338/*** EDID parsing ***/
1339
f453ba04
DA		 1340/**
1341 * edid_vendor - match a string against EDID's obfuscated vendor field
1342 * @edid: EDID to match
1343 * @vendor: vendor string
1344 *
1345 * Returns true if @vendor is in @edid, false otherwise
1346 */
1347static bool edid_vendor(struct edid *edid, char *vendor)
1348{
1349 char edid_vendor[3];
1350
1351 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1352 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1353 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1354 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1355
1356 return !strncmp(edid_vendor, vendor, 3);
1357}
1358
1359/**
1360 * edid_get_quirks - return quirk flags for a given EDID
1361 * @edid: EDID to process
1362 *
1363 * This tells subsequent routines what fixes they need to apply.
1364 */
1365static u32 edid_get_quirks(struct edid *edid)
1366{
1367 struct edid_quirk *quirk;
1368 int i;
1369
1370 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1371 quirk = &edid_quirk_list[i];
1372
1373 if (edid_vendor(edid, quirk->vendor) &&
1374 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1375 return quirk->quirks;
1376 }
1377
1378 return 0;
1379}
1380
1381#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1382#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1383
f453ba04
DA		 1384/**
1385 * edid_fixup_preferred - set preferred modes based on quirk list
1386 * @connector: has mode list to fix up
1387 * @quirks: quirks list
1388 *
1389 * Walk the mode list for @connector, clearing the preferred status
1390 * on existing modes and setting it anew for the right mode ala @quirks.
1391 */
1392static void edid_fixup_preferred(struct drm_connector *connector,
1393 u32 quirks)
1394{
1395 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1396 int target_refresh = 0;
339d202c 1397 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1398
1399 if (list_empty(&connector->probed_modes))
1400 return;
1401
1402 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1403 target_refresh = 60;
1404 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1405 target_refresh = 75;
1406
1407 preferred_mode = list_first_entry(&connector->probed_modes,
1408 struct drm_display_mode, head);
1409
1410 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1411 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1412
1413 if (cur_mode == preferred_mode)
1414 continue;
1415
1416 /* Largest mode is preferred */
1417 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1418 preferred_mode = cur_mode;
1419
339d202c
AD		 1420 cur_vrefresh = cur_mode->vrefresh ?
1421 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1422 preferred_vrefresh = preferred_mode->vrefresh ?
1423 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1424 /* At a given size, try to get closest to target refresh */
1425 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1426 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1427 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1428 preferred_mode = cur_mode;
1429 }
1430 }
1431
1432 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1433}
1434
f6e252ba
AJ		 1435static bool
1436mode_is_rb(const struct drm_display_mode *mode)
1437{
1438 return (mode->htotal - mode->hdisplay == 160) &&
1439 (mode->hsync_end - mode->hdisplay == 80) &&
1440 (mode->hsync_end - mode->hsync_start == 32) &&
1441 (mode->vsync_start - mode->vdisplay == 3);
1442}
1443
33c7531d
AJ		 1444/*
1445 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1446 * @dev: Device to duplicate against
1447 * @hsize: Mode width
1448 * @vsize: Mode height
1449 * @fresh: Mode refresh rate
f6e252ba 1450 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1451 *
1452 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1453 *
1454 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1455 */
1d42bbc8 1456struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1457 int hsize, int vsize, int fresh,
1458 bool rb)
559ee21d 1459{
07a5e632 1460 int i;
559ee21d 1461
a6b21831 1462 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1463 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1464 if (hsize != ptr->hdisplay)
1465 continue;
1466 if (vsize != ptr->vdisplay)
1467 continue;
1468 if (fresh != drm_mode_vrefresh(ptr))
1469 continue;
f6e252ba
AJ		 1470 if (rb != mode_is_rb(ptr))
1471 continue;
f8b46a05
AJ		 1472
1473 return drm_mode_duplicate(dev, ptr);
559ee21d 1474 }
f8b46a05
AJ		 1475
1476 return NULL;
559ee21d 1477}
1d42bbc8 1478EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1479
d1ff6409
AJ		 1480typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1481
4d76a221
AJ		 1482static void
1483cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1484{
1485 int i, n = 0;
4966b2a9 1486 u8 d = ext[0x02];
4d76a221
AJ		 1487 u8 *det_base = ext + d;
1488
4966b2a9 1489 n = (127 - d) / 18;
4d76a221
AJ		 1490 for (i = 0; i < n; i++)
1491 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1492}
1493
cbba98f8
AJ		 1494static void
1495vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1496{
1497 unsigned int i, n = min((int)ext[0x02], 6);
1498 u8 *det_base = ext + 5;
1499
1500 if (ext[0x01] != 1)
1501 return; /* unknown version */
1502
1503 for (i = 0; i < n; i++)
1504 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1505}
1506
d1ff6409
AJ		 1507static void
1508drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1509{
1510 int i;
1511 struct edid *edid = (struct edid *)raw_edid;
1512
1513 if (edid == NULL)
1514 return;
1515
1516 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1517 cb(&(edid->detailed_timings[i]), closure);
1518
4d76a221
AJ		 1519 for (i = 1; i <= raw_edid[0x7e]; i++) {
1520 u8 *ext = raw_edid + (i * EDID_LENGTH);
1521 switch (*ext) {
1522 case CEA_EXT:
1523 cea_for_each_detailed_block(ext, cb, closure);
1524 break;
cbba98f8
AJ		 1525 case VTB_EXT:
1526 vtb_for_each_detailed_block(ext, cb, closure);
1527 break;
4d76a221
AJ		 1528 default:
1529 break;
1530 }
1531 }
d1ff6409
AJ		 1532}
1533
1534static void
1535is_rb(struct detailed_timing *t, void *data)
1536{
1537 u8 *r = (u8 *)t;
1538 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1539 if (r[15] & 0x10)
1540 *(bool *)data = true;
1541}
1542
1543/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1544static bool
1545drm_monitor_supports_rb(struct edid *edid)
1546{
1547 if (edid->revision >= 4) {
b196a498 1548 bool ret = false;
d1ff6409
AJ		 1549 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1550 return ret;
1551 }
1552
1553 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1554}
1555
7a374350
AJ		 1556static void
1557find_gtf2(struct detailed_timing *t, void *data)
1558{
1559 u8 *r = (u8 *)t;
1560 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1561 *(u8 **)data = r;
1562}
1563
1564/* Secondary GTF curve kicks in above some break frequency */
1565static int
1566drm_gtf2_hbreak(struct edid *edid)
1567{
1568 u8 *r = NULL;
1569 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1570 return r ? (r[12] * 2) : 0;
1571}
1572
1573static int
1574drm_gtf2_2c(struct edid *edid)
1575{
1576 u8 *r = NULL;
1577 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1578 return r ? r[13] : 0;
1579}
1580
1581static int
1582drm_gtf2_m(struct edid *edid)
1583{
1584 u8 *r = NULL;
1585 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1586 return r ? (r[15] << 8) + r[14] : 0;
1587}
1588
1589static int
1590drm_gtf2_k(struct edid *edid)
1591{
1592 u8 *r = NULL;
1593 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1594 return r ? r[16] : 0;
1595}
1596
1597static int
1598drm_gtf2_2j(struct edid *edid)
1599{
1600 u8 *r = NULL;
1601 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1602 return r ? r[17] : 0;
1603}
1604
1605/**
1606 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1607 * @edid: EDID block to scan
1608 */
1609static int standard_timing_level(struct edid *edid)
1610{
1611 if (edid->revision >= 2) {
1612 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1613 return LEVEL_CVT;
1614 if (drm_gtf2_hbreak(edid))
1615 return LEVEL_GTF2;
1616 return LEVEL_GTF;
1617 }
1618 return LEVEL_DMT;
1619}
1620
23425cae
AJ		 1621/*
1622 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1623 * monitors fill with ascii space (0x20) instead.
1624 */
1625static int
1626bad_std_timing(u8 a, u8 b)
1627{
1628 return (a == 0x00 && b == 0x00) ||
1629 (a == 0x01 && b == 0x01) ||
1630 (a == 0x20 && b == 0x20);
1631}
1632
f453ba04
DA		 1633/**
1634 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 1635 * @connector: connector of for the EDID block
1636 * @edid: EDID block to scan
f453ba04
DA		 1637 * @t: standard timing params
1638 *
1639 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 1640 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 1641 */
7ca6adb3 1642static struct drm_display_mode *
7a374350 1643drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 1644 struct std_timing *t)
f453ba04 1645{
7ca6adb3
AJ		 1646 struct drm_device *dev = connector->dev;
1647 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 1648 int hsize, vsize;
1649 int vrefresh_rate;
0454beab
MD		 1650 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1651 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 1652 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1653 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 1654 int timing_level = standard_timing_level(edid);
5c61259e 1655
23425cae
AJ		 1656 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1657 return NULL;
1658
5c61259e
ZY		 1659 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1660 hsize = t->hsize * 8 + 248;
1661 /* vrefresh_rate = vfreq + 60 */
1662 vrefresh_rate = vfreq + 60;
1663 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 1664 if (aspect_ratio == 0) {
464fdeca 1665 if (edid->revision < 3)
f066a17d
AJ		 1666 vsize = hsize;
1667 else
1668 vsize = (hsize * 10) / 16;
1669 } else if (aspect_ratio == 1)
f453ba04 1670 vsize = (hsize * 3) / 4;
0454beab 1671 else if (aspect_ratio == 2)
f453ba04
DA		 1672 vsize = (hsize * 4) / 5;
1673 else
1674 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 1675
1676 /* HDTV hack, part 1 */
1677 if (vrefresh_rate == 60 &&
1678 ((hsize == 1360 && vsize == 765) ||
1679 (hsize == 1368 && vsize == 769))) {
1680 hsize = 1366;
1681 vsize = 768;
1682 }
1683
7ca6adb3
AJ		 1684 /*
1685 * If this connector already has a mode for this size and refresh
1686 * rate (because it came from detailed or CVT info), use that
1687 * instead. This way we don't have to guess at interlace or
1688 * reduced blanking.
1689 */
522032da 1690 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 1691 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1692 drm_mode_vrefresh(m) == vrefresh_rate)
1693 return NULL;
1694
a0910c8e
AJ		 1695 /* HDTV hack, part 2 */
1696 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1697 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 1698 false);
559ee21d 1699 mode->hdisplay = 1366;
a4967de6
AJ		 1700 mode->hsync_start = mode->hsync_start - 1;
1701 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 1702 return mode;
1703 }
a0910c8e 1704
559ee21d 1705 /* check whether it can be found in default mode table */
f6e252ba
AJ		 1706 if (drm_monitor_supports_rb(edid)) {
1707 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1708 true);
1709 if (mode)
1710 return mode;
1711 }
1712 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 1713 if (mode)
1714 return mode;
1715
f6e252ba 1716 /* okay, generate it */
5c61259e
ZY		 1717 switch (timing_level) {
1718 case LEVEL_DMT:
5c61259e
ZY		 1719 break;
1720 case LEVEL_GTF:
1721 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1722 break;
7a374350
AJ		 1723 case LEVEL_GTF2:
1724 /*
1725 * This is potentially wrong if there's ever a monitor with
1726 * more than one ranges section, each claiming a different
1727 * secondary GTF curve. Please don't do that.
1728 */
1729 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 1730 if (!mode)
1731 return NULL;
7a374350 1732 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 1733 drm_mode_destroy(dev, mode);
7a374350
AJ		 1734 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1735 vrefresh_rate, 0, 0,
1736 drm_gtf2_m(edid),
1737 drm_gtf2_2c(edid),
1738 drm_gtf2_k(edid),
1739 drm_gtf2_2j(edid));
1740 }
1741 break;
5c61259e 1742 case LEVEL_CVT:
d50ba256
DA		 1743 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1744 false);
5c61259e
ZY		 1745 break;
1746 }
f453ba04
DA		 1747 return mode;
1748}
1749
b58db2c6
AJ		 1750/*
1751 * EDID is delightfully ambiguous about how interlaced modes are to be
1752 * encoded. Our internal representation is of frame height, but some
1753 * HDTV detailed timings are encoded as field height.
1754 *
1755 * The format list here is from CEA, in frame size. Technically we
1756 * should be checking refresh rate too. Whatever.
1757 */
1758static void
1759drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1760 struct detailed_pixel_timing *pt)
1761{
1762 int i;
1763 static const struct {
1764 int w, h;
1765 } cea_interlaced[] = {
1766 { 1920, 1080 },
1767 { 720, 480 },
1768 { 1440, 480 },
1769 { 2880, 480 },
1770 { 720, 576 },
1771 { 1440, 576 },
1772 { 2880, 576 },
1773 };
b58db2c6
AJ		 1774
1775 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1776 return;
1777
3c581411 1778 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 1779 if ((mode->hdisplay == cea_interlaced[i].w) &&
1780 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1781 mode->vdisplay *= 2;
1782 mode->vsync_start *= 2;
1783 mode->vsync_end *= 2;
1784 mode->vtotal *= 2;
1785 mode->vtotal |= 1;
1786 }
1787 }
1788
1789 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1790}
1791
f453ba04
DA		 1792/**
1793 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1794 * @dev: DRM device (needed to create new mode)
1795 * @edid: EDID block
1796 * @timing: EDID detailed timing info
1797 * @quirks: quirks to apply
1798 *
1799 * An EDID detailed timing block contains enough info for us to create and
1800 * return a new struct drm_display_mode.
1801 */
1802static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1803 struct edid *edid,
1804 struct detailed_timing *timing,
1805 u32 quirks)
1806{
1807 struct drm_display_mode *mode;
1808 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 1809 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1810 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1811 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1812 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 1813 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1814 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 1815 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 1816 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 1817
fc438966 1818 /* ignore tiny modes */
0454beab 1819 if (hactive < 64 || vactive < 64)
fc438966
AJ		 1820 return NULL;
1821
0454beab 1822 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 1823 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 1824 return NULL;
1825 }
0454beab 1826 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 1827 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 1828 }
1829
fcb45611
ZY		 1830 /* it is incorrect if hsync/vsync width is zero */
1831 if (!hsync_pulse_width || !vsync_pulse_width) {
1832 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1833 "Wrong Hsync/Vsync pulse width\n");
1834 return NULL;
1835 }
bc42aabc
AJ		 1836
1837 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1838 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1839 if (!mode)
1840 return NULL;
1841
1842 goto set_size;
1843 }
1844
f453ba04
DA		 1845 mode = drm_mode_create(dev);
1846 if (!mode)
1847 return NULL;
1848
f453ba04 1849 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1850 timing->pixel_clock = cpu_to_le16(1088);
1851
1852 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1853
1854 mode->hdisplay = hactive;
1855 mode->hsync_start = mode->hdisplay + hsync_offset;
1856 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1857 mode->htotal = mode->hdisplay + hblank;
1858
1859 mode->vdisplay = vactive;
1860 mode->vsync_start = mode->vdisplay + vsync_offset;
1861 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1862 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1863
7064fef5
JB		 1864 /* Some EDIDs have bogus h/vtotal values */
1865 if (mode->hsync_end > mode->htotal)
1866 mode->htotal = mode->hsync_end + 1;
1867 if (mode->vsync_end > mode->vtotal)
1868 mode->vtotal = mode->vsync_end + 1;
1869
b58db2c6 1870 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 1871
1872 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1873 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1874 }
1875
0454beab
MD		 1876 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1877 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1878 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1879 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1880
bc42aabc 1881set_size:
e14cbee4
MD		 1882 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1883 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1884
1885 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1886 mode->width_mm *= 10;
1887 mode->height_mm *= 10;
1888 }
1889
1890 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1891 mode->width_mm = edid->width_cm * 10;
1892 mode->height_mm = edid->height_cm * 10;
1893 }
1894
bc42aabc 1895 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 1896 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 1897 drm_mode_set_name(mode);
1898
f453ba04
DA		 1899 return mode;
1900}
1901
b17e52ef 1902static bool
b1f559ec
CW		 1903mode_in_hsync_range(const struct drm_display_mode *mode,
1904 struct edid *edid, u8 *t)
b17e52ef
AJ		 1905{
1906 int hsync, hmin, hmax;
1907
1908 hmin = t[7];
1909 if (edid->revision >= 4)
1910 hmin += ((t[4] & 0x04) ? 255 : 0);
1911 hmax = t[8];
1912 if (edid->revision >= 4)
1913 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1914 hsync = drm_mode_hsync(mode);
07a5e632 1915
b17e52ef
AJ		 1916 return (hsync <= hmax && hsync >= hmin);
1917}
1918
1919static bool
b1f559ec
CW		 1920mode_in_vsync_range(const struct drm_display_mode *mode,
1921 struct edid *edid, u8 *t)
b17e52ef
AJ		 1922{
1923 int vsync, vmin, vmax;
1924
1925 vmin = t[5];
1926 if (edid->revision >= 4)
1927 vmin += ((t[4] & 0x01) ? 255 : 0);
1928 vmax = t[6];
1929 if (edid->revision >= 4)
1930 vmax += ((t[4] & 0x02) ? 255 : 0);
1931 vsync = drm_mode_vrefresh(mode);
1932
1933 return (vsync <= vmax && vsync >= vmin);
1934}
1935
1936static u32
1937range_pixel_clock(struct edid *edid, u8 *t)
1938{
1939 /* unspecified */
1940 if (t[9] == 0 || t[9] == 255)
1941 return 0;
1942
1943 /* 1.4 with CVT support gives us real precision, yay */
1944 if (edid->revision >= 4 && t[10] == 0x04)
1945 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1946
1947 /* 1.3 is pathetic, so fuzz up a bit */
1948 return t[9] * 10000 + 5001;
1949}
1950
b17e52ef 1951static bool
b1f559ec 1952mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 1953 struct detailed_timing *timing)
1954{
1955 u32 max_clock;
1956 u8 *t = (u8 *)timing;
1957
1958 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1959 return false;
1960
b17e52ef 1961 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1962 return false;
1963
b17e52ef 1964 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1965 if (mode->clock > max_clock)
1966 return false;
b17e52ef
AJ		 1967
1968 /* 1.4 max horizontal check */
1969 if (edid->revision >= 4 && t[10] == 0x04)
1970 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1971 return false;
1972
1973 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1974 return false;
07a5e632
AJ		 1975
1976 return true;
1977}
1978
7b668ebe
TI		 1979static bool valid_inferred_mode(const struct drm_connector *connector,
1980 const struct drm_display_mode *mode)
1981{
1982 struct drm_display_mode *m;
1983 bool ok = false;
1984
1985 list_for_each_entry(m, &connector->probed_modes, head) {
1986 if (mode->hdisplay == m->hdisplay &&
1987 mode->vdisplay == m->vdisplay &&
1988 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
1989 return false; /* duplicated */
1990 if (mode->hdisplay <= m->hdisplay &&
1991 mode->vdisplay <= m->vdisplay)
1992 ok = true;
1993 }
1994 return ok;
1995}
1996
b17e52ef 1997static int
cd4cd3de 1998drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 1999 struct detailed_timing *timing)
07a5e632
AJ		 2000{
2001 int i, modes = 0;
2002 struct drm_display_mode *newmode;
2003 struct drm_device *dev = connector->dev;
2004
a6b21831 2005 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2006 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2007 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2008 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2009 if (newmode) {
2010 drm_mode_probed_add(connector, newmode);
2011 modes++;
2012 }
2013 }
2014 }
2015
2016 return modes;
2017}
2018
c09dedb7
TI		 2019/* fix up 1366x768 mode from 1368x768;
2020 * GFT/CVT can't express 1366 width which isn't dividable by 8
2021 */
2022static void fixup_mode_1366x768(struct drm_display_mode *mode)
2023{
2024 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2025 mode->hdisplay = 1366;
2026 mode->hsync_start--;
2027 mode->hsync_end--;
2028 drm_mode_set_name(mode);
2029 }
2030}
2031
b309bd37
AJ		 2032static int
2033drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2034 struct detailed_timing *timing)
2035{
2036 int i, modes = 0;
2037 struct drm_display_mode *newmode;
2038 struct drm_device *dev = connector->dev;
2039
a6b21831 2040 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2041 const struct minimode *m = &extra_modes[i];
2042 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2043 if (!newmode)
2044 return modes;
b309bd37 2045
c09dedb7 2046 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2047 if (!mode_in_range(newmode, edid, timing) ||
2048 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2049 drm_mode_destroy(dev, newmode);
2050 continue;
2051 }
2052
2053 drm_mode_probed_add(connector, newmode);
2054 modes++;
2055 }
2056
2057 return modes;
2058}
2059
2060static int
2061drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2062 struct detailed_timing *timing)
2063{
2064 int i, modes = 0;
2065 struct drm_display_mode *newmode;
2066 struct drm_device *dev = connector->dev;
2067 bool rb = drm_monitor_supports_rb(edid);
2068
a6b21831 2069 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2070 const struct minimode *m = &extra_modes[i];
2071 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2072 if (!newmode)
2073 return modes;
b309bd37 2074
c09dedb7 2075 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2076 if (!mode_in_range(newmode, edid, timing) ||
2077 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2078 drm_mode_destroy(dev, newmode);
2079 continue;
2080 }
2081
2082 drm_mode_probed_add(connector, newmode);
2083 modes++;
2084 }
2085
2086 return modes;
2087}
2088
13931579
AJ		 2089static void
2090do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2091{
13931579
AJ		 2092 struct detailed_mode_closure *closure = c;
2093 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2094 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2095
cb21aafe
AJ		 2096 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2097 return;
2098
2099 closure->modes += drm_dmt_modes_for_range(closure->connector,
2100 closure->edid,
2101 timing);
b309bd37
AJ		 2102
2103 if (!version_greater(closure->edid, 1, 1))
2104 return; /* GTF not defined yet */
2105
2106 switch (range->flags) {
2107 case 0x02: /* secondary gtf, XXX could do more */
2108 case 0x00: /* default gtf */
2109 closure->modes += drm_gtf_modes_for_range(closure->connector,
2110 closure->edid,
2111 timing);
2112 break;
2113 case 0x04: /* cvt, only in 1.4+ */
2114 if (!version_greater(closure->edid, 1, 3))
2115 break;
2116
2117 closure->modes += drm_cvt_modes_for_range(closure->connector,
2118 closure->edid,
2119 timing);
2120 break;
2121 case 0x01: /* just the ranges, no formula */
2122 default:
2123 break;
2124 }
13931579 2125}
69da3015 2126
13931579
AJ		 2127static int
2128add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2129{
2130 struct detailed_mode_closure closure = {
d456ea2e
JL		 2131 .connector = connector,
2132 .edid = edid,
13931579 2133 };
9340d8cf 2134
13931579
AJ		 2135 if (version_greater(edid, 1, 0))
2136 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2137 &closure);
9340d8cf 2138
13931579 2139 return closure.modes;
9340d8cf
AJ		 2140}
2141
2255be14
AJ		 2142static int
2143drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2144{
2145 int i, j, m, modes = 0;
2146 struct drm_display_mode *mode;
2147 u8 *est = ((u8 *)timing) + 5;
2148
2149 for (i = 0; i < 6; i++) {
891a7469 2150 for (j = 7; j >= 0; j--) {
2255be14 2151 m = (i * 8) + (7 - j);
3c581411 2152 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2153 break;
2154 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2155 mode = drm_mode_find_dmt(connector->dev,
2156 est3_modes[m].w,
2157 est3_modes[m].h,
f6e252ba
AJ		 2158 est3_modes[m].r,
2159 est3_modes[m].rb);
2255be14
AJ		 2160 if (mode) {
2161 drm_mode_probed_add(connector, mode);
2162 modes++;
2163 }
2164 }
2165 }
2166 }
2167
2168 return modes;
2169}
2170
13931579
AJ		 2171static void
2172do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2173{
13931579 2174 struct detailed_mode_closure *closure = c;
9cf00977 2175 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2176
13931579
AJ		 2177 if (data->type == EDID_DETAIL_EST_TIMINGS)
2178 closure->modes += drm_est3_modes(closure->connector, timing);
2179}
9cf00977 2180
13931579
AJ		 2181/**
2182 * add_established_modes - get est. modes from EDID and add them
db6cf833 2183 * @connector: connector to add mode(s) to
13931579
AJ		 2184 * @edid: EDID block to scan
2185 *
2186 * Each EDID block contains a bitmap of the supported "established modes" list
2187 * (defined above). Tease them out and add them to the global modes list.
2188 */
2189static int
2190add_established_modes(struct drm_connector *connector, struct edid *edid)
2191{
2192 struct drm_device *dev = connector->dev;
2193 unsigned long est_bits = edid->established_timings.t1 |
2194 (edid->established_timings.t2 << 8) |
2195 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2196 int i, modes = 0;
2197 struct detailed_mode_closure closure = {
d456ea2e
JL		 2198 .connector = connector,
2199 .edid = edid,
13931579 2200 };
9cf00977 2201
13931579
AJ		 2202 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2203 if (est_bits & (1<<i)) {
2204 struct drm_display_mode *newmode;
2205 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2206 if (newmode) {
2207 drm_mode_probed_add(connector, newmode);
2208 modes++;
2209 }
2210 }
9cf00977
AJ		 2211 }
2212
13931579
AJ		 2213 if (version_greater(edid, 1, 0))
2214 drm_for_each_detailed_block((u8 *)edid,
2215 do_established_modes, &closure);
2216
2217 return modes + closure.modes;
2218}
2219
2220static void
2221do_standard_modes(struct detailed_timing *timing, void *c)
2222{
2223 struct detailed_mode_closure *closure = c;
2224 struct detailed_non_pixel *data = &timing->data.other_data;
2225 struct drm_connector *connector = closure->connector;
2226 struct edid *edid = closure->edid;
2227
2228 if (data->type == EDID_DETAIL_STD_MODES) {
2229 int i;
9cf00977
AJ		 2230 for (i = 0; i < 6; i++) {
2231 struct std_timing *std;
2232 struct drm_display_mode *newmode;
2233
2234 std = &data->data.timings[i];
464fdeca 2235 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2236 if (newmode) {
2237 drm_mode_probed_add(connector, newmode);
13931579 2238 closure->modes++;
9cf00977
AJ		 2239 }
2240 }
9cf00977 2241 }
9cf00977
AJ		 2242}
2243
f453ba04 2244/**
13931579 2245 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2246 * @connector: connector to add mode(s) to
f453ba04 2247 * @edid: EDID block to scan
f453ba04 2248 *
13931579
AJ		 2249 * Standard modes can be calculated using the appropriate standard (DMT,
2250 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2251 */
13931579
AJ		 2252static int
2253add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2254{
9cf00977 2255 int i, modes = 0;
13931579 2256 struct detailed_mode_closure closure = {
d456ea2e
JL		 2257 .connector = connector,
2258 .edid = edid,
13931579
AJ		 2259 };
2260
2261 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2262 struct drm_display_mode *newmode;
2263
2264 newmode = drm_mode_std(connector, edid,
464fdeca 2265 &edid->standard_timings[i]);
13931579
AJ		 2266 if (newmode) {
2267 drm_mode_probed_add(connector, newmode);
2268 modes++;
2269 }
2270 }
2271
2272 if (version_greater(edid, 1, 0))
2273 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2274 &closure);
2275
2276 /* XXX should also look for standard codes in VTB blocks */
2277
2278 return modes + closure.modes;
2279}
f453ba04 2280
13931579
AJ		 2281static int drm_cvt_modes(struct drm_connector *connector,
2282 struct detailed_timing *timing)
2283{
2284 int i, j, modes = 0;
2285 struct drm_display_mode *newmode;
2286 struct drm_device *dev = connector->dev;
2287 struct cvt_timing *cvt;
2288 const int rates[] = { 60, 85, 75, 60, 50 };
2289 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2290
13931579
AJ		 2291 for (i = 0; i < 4; i++) {
2292 int uninitialized_var(width), height;
2293 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2294
13931579 2295 if (!memcmp(cvt->code, empty, 3))
9cf00977 2296 continue;
f453ba04 2297
13931579
AJ		 2298 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2299 switch (cvt->code[1] & 0x0c) {
2300 case 0x00:
2301 width = height * 4 / 3;
2302 break;
2303 case 0x04:
2304 width = height * 16 / 9;
2305 break;
2306 case 0x08:
2307 width = height * 16 / 10;
2308 break;
2309 case 0x0c:
2310 width = height * 15 / 9;
2311 break;
2312 }
2313
2314 for (j = 1; j < 5; j++) {
2315 if (cvt->code[2] & (1 << j)) {
2316 newmode = drm_cvt_mode(dev, width, height,
2317 rates[j], j == 0,
2318 false, false);
2319 if (newmode) {
2320 drm_mode_probed_add(connector, newmode);
2321 modes++;
2322 }
2323 }
2324 }
f453ba04
DA		 2325 }
2326
2327 return modes;
2328}
9cf00977 2329
13931579
AJ		 2330static void
2331do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2332{
13931579
AJ		 2333 struct detailed_mode_closure *closure = c;
2334 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2335
13931579
AJ		 2336 if (data->type == EDID_DETAIL_CVT_3BYTE)
2337 closure->modes += drm_cvt_modes(closure->connector, timing);
2338}
882f0219 2339
13931579
AJ		 2340static int
2341add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2342{
2343 struct detailed_mode_closure closure = {
d456ea2e
JL		 2344 .connector = connector,
2345 .edid = edid,
13931579 2346 };
882f0219 2347
13931579
AJ		 2348 if (version_greater(edid, 1, 2))
2349 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2350
13931579 2351 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2352
13931579
AJ		 2353 return closure.modes;
2354}
2355
2356static void
2357do_detailed_mode(struct detailed_timing *timing, void *c)
2358{
2359 struct detailed_mode_closure *closure = c;
2360 struct drm_display_mode *newmode;
2361
2362 if (timing->pixel_clock) {
2363 newmode = drm_mode_detailed(closure->connector->dev,
2364 closure->edid, timing,
2365 closure->quirks);
2366 if (!newmode)
2367 return;
2368
2369 if (closure->preferred)
2370 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2371
2372 drm_mode_probed_add(closure->connector, newmode);
2373 closure->modes++;
2374 closure->preferred = 0;
882f0219 2375 }
13931579 2376}
882f0219 2377
13931579
AJ		 2378/*
2379 * add_detailed_modes - Add modes from detailed timings
2380 * @connector: attached connector
2381 * @edid: EDID block to scan
2382 * @quirks: quirks to apply
2383 */
2384static int
2385add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2386 u32 quirks)
2387{
2388 struct detailed_mode_closure closure = {
d456ea2e
JL		 2389 .connector = connector,
2390 .edid = edid,
2391 .preferred = 1,
2392 .quirks = quirks,
13931579
AJ		 2393 };
2394
2395 if (closure.preferred && !version_greater(edid, 1, 3))
2396 closure.preferred =
2397 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2398
2399 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2400
2401 return closure.modes;
882f0219 2402}
f453ba04 2403
8fe9790d 2404#define AUDIO_BLOCK 0x01
54ac76f8 2405#define VIDEO_BLOCK 0x02
f23c20c8 2406#define VENDOR_BLOCK 0x03
76adaa34 2407#define SPEAKER_BLOCK 0x04
b1edd6a6 2408#define VIDEO_CAPABILITY_BLOCK 0x07
8fe9790d 2409#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2410#define EDID_CEA_YCRCB444 (1 << 5)
2411#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2412#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2413
d4e4a31d 2414/*
8fe9790d 2415 * Search EDID for CEA extension block.
f23c20c8 2416 */
40d9b043 2417static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
f23c20c8 2418{
8fe9790d
ZW		 2419 u8 *edid_ext = NULL;
2420 int i;
f23c20c8
ML		 2421
2422 /* No EDID or EDID extensions */
2423 if (edid == NULL || edid->extensions == 0)
8fe9790d 2424 return NULL;
f23c20c8 2425
f23c20c8 2426 /* Find CEA extension */
7466f4cc 2427 for (i = 0; i < edid->extensions; i++) {
8fe9790d 2428 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 2429 if (edid_ext[0] == ext_id)
f23c20c8
ML		 2430 break;
2431 }
2432
7466f4cc 2433 if (i == edid->extensions)
8fe9790d
ZW		 2434 return NULL;
2435
2436 return edid_ext;
2437}
2438
40d9b043
DA		 2439static u8 *drm_find_cea_extension(struct edid *edid)
2440{
2441 return drm_find_edid_extension(edid, CEA_EXT);
2442}
2443
2444static u8 *drm_find_displayid_extension(struct edid *edid)
2445{
2446 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2447}
2448
e6e79209
VS		 2449/*
2450 * Calculate the alternate clock for the CEA mode
2451 * (60Hz vs. 59.94Hz etc.)
2452 */
2453static unsigned int
2454cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2455{
2456 unsigned int clock = cea_mode->clock;
2457
2458 if (cea_mode->vrefresh % 6 != 0)
2459 return clock;
2460
2461 /*
2462 * edid_cea_modes contains the 59.94Hz
2463 * variant for 240 and 480 line modes,
2464 * and the 60Hz variant otherwise.
2465 */
2466 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2467 clock = clock * 1001 / 1000;
2468 else
2469 clock = DIV_ROUND_UP(clock * 1000, 1001);
2470
2471 return clock;
2472}
2473
18316c8c
TR		 2474/**
2475 * drm_match_cea_mode - look for a CEA mode matching given mode
2476 * @to_match: display mode
2477 *
db6cf833 2478 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2479 * mode.
a4799037 2480 */
18316c8c 2481u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2482{
a4799037
SM		 2483 u8 mode;
2484
a90b590e
VS		 2485 if (!to_match->clock)
2486 return 0;
2487
a6b21831 2488 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
a90b590e
VS		 2489 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
2490 unsigned int clock1, clock2;
2491
a90b590e 2492 /* Check both 60Hz and 59.94Hz */
e6e79209
VS		 2493 clock1 = cea_mode->clock;
2494 clock2 = cea_mode_alternate_clock(cea_mode);
a4799037 2495
a90b590e
VS		 2496 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2497 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2498 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
a4799037
SM		 2499 return mode + 1;
2500 }
2501 return 0;
2502}
2503EXPORT_SYMBOL(drm_match_cea_mode);
2504
0967e6a5
VK		 2505/**
2506 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2507 * the input VIC from the CEA mode list
2508 * @video_code: ID given to each of the CEA modes
2509 *
2510 * Returns picture aspect ratio
2511 */
2512enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2513{
2514 /* return picture aspect ratio for video_code - 1 to access the
2515 * right array element
2516 */
2517 return edid_cea_modes[video_code-1].picture_aspect_ratio;
2518}
2519EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2520
3f2f6533
LD		 2521/*
2522 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2523 * specific block).
2524 *
2525 * It's almost like cea_mode_alternate_clock(), we just need to add an
2526 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2527 * one.
2528 */
2529static unsigned int
2530hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2531{
2532 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2533 return hdmi_mode->clock;
2534
2535 return cea_mode_alternate_clock(hdmi_mode);
2536}
2537
2538/*
2539 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2540 * @to_match: display mode
2541 *
2542 * An HDMI mode is one defined in the HDMI vendor specific block.
2543 *
2544 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2545 */
2546static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2547{
2548 u8 mode;
2549
2550 if (!to_match->clock)
2551 return 0;
2552
2553 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
2554 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
2555 unsigned int clock1, clock2;
2556
2557 /* Make sure to also match alternate clocks */
2558 clock1 = hdmi_mode->clock;
2559 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2560
2561 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2562 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2563 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3f2f6533
LD		 2564 return mode + 1;
2565 }
2566 return 0;
2567}
2568
e6e79209
VS		 2569static int
2570add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2571{
2572 struct drm_device *dev = connector->dev;
2573 struct drm_display_mode *mode, *tmp;
2574 LIST_HEAD(list);
2575 int modes = 0;
2576
2577 /* Don't add CEA modes if the CEA extension block is missing */
2578 if (!drm_find_cea_extension(edid))
2579 return 0;
2580
2581 /*
2582 * Go through all probed modes and create a new mode
2583 * with the alternate clock for certain CEA modes.
2584 */
2585 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 2586 const struct drm_display_mode *cea_mode = NULL;
e6e79209 2587 struct drm_display_mode *newmode;
3f2f6533 2588 u8 mode_idx = drm_match_cea_mode(mode) - 1;
e6e79209
VS		 2589 unsigned int clock1, clock2;
2590
3f2f6533
LD		 2591 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
2592 cea_mode = &edid_cea_modes[mode_idx];
2593 clock2 = cea_mode_alternate_clock(cea_mode);
2594 } else {
2595 mode_idx = drm_match_hdmi_mode(mode) - 1;
2596 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
2597 cea_mode = &edid_4k_modes[mode_idx];
2598 clock2 = hdmi_mode_alternate_clock(cea_mode);
2599 }
2600 }
e6e79209 2601
3f2f6533
LD		 2602 if (!cea_mode)
2603 continue;
e6e79209
VS		 2604
2605 clock1 = cea_mode->clock;
e6e79209
VS		 2606
2607 if (clock1 == clock2)
2608 continue;
2609
2610 if (mode->clock != clock1 && mode->clock != clock2)
2611 continue;
2612
2613 newmode = drm_mode_duplicate(dev, cea_mode);
2614 if (!newmode)
2615 continue;
2616
27130212
DL		 2617 /* Carry over the stereo flags */
2618 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2619
e6e79209
VS		 2620 /*
2621 * The current mode could be either variant. Make
2622 * sure to pick the "other" clock for the new mode.
2623 */
2624 if (mode->clock != clock1)
2625 newmode->clock = clock1;
2626 else
2627 newmode->clock = clock2;
2628
2629 list_add_tail(&newmode->head, &list);
2630 }
2631
2632 list_for_each_entry_safe(mode, tmp, &list, head) {
2633 list_del(&mode->head);
2634 drm_mode_probed_add(connector, mode);
2635 modes++;
2636 }
2637
2638 return modes;
2639}
a4799037 2640
aff04ace
TW		 2641static struct drm_display_mode *
2642drm_display_mode_from_vic_index(struct drm_connector *connector,
2643 const u8 *video_db, u8 video_len,
2644 u8 video_index)
54ac76f8
CS		 2645{
2646 struct drm_device *dev = connector->dev;
aff04ace 2647 struct drm_display_mode *newmode;
13ac3f55 2648 u8 cea_mode;
54ac76f8 2649
aff04ace
TW		 2650 if (video_db == NULL || video_index >= video_len)
2651 return NULL;
2652
2653 /* CEA modes are numbered 1..127 */
2654 cea_mode = (video_db[video_index] & 127) - 1;
2655 if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
2656 return NULL;
2657
2658 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
409bbf1e
DL		 2659 if (!newmode)
2660 return NULL;
2661
aff04ace
TW		 2662 newmode->vrefresh = 0;
2663
2664 return newmode;
2665}
2666
2667static int
2668do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2669{
2670 int i, modes = 0;
2671
2672 for (i = 0; i < len; i++) {
2673 struct drm_display_mode *mode;
2674 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2675 if (mode) {
2676 drm_mode_probed_add(connector, mode);
2677 modes++;
54ac76f8
CS		 2678 }
2679 }
2680
2681 return modes;
2682}
2683
c858cfca
DL		 2684struct stereo_mandatory_mode {
2685 int width, height, vrefresh;
2686 unsigned int flags;
2687};
2688
2689static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 2690 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2691 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 2692 { 1920, 1080, 50,
2693 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2694 { 1920, 1080, 60,
2695 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 2696 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2697 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2698 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2699 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 2700};
2701
2702static bool
2703stereo_match_mandatory(const struct drm_display_mode *mode,
2704 const struct stereo_mandatory_mode *stereo_mode)
2705{
2706 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2707
2708 return mode->hdisplay == stereo_mode->width &&
2709 mode->vdisplay == stereo_mode->height &&
2710 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2711 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2712}
2713
c858cfca
DL		 2714static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2715{
2716 struct drm_device *dev = connector->dev;
2717 const struct drm_display_mode *mode;
2718 struct list_head stereo_modes;
f7e121b7 2719 int modes = 0, i;
c858cfca
DL		 2720
2721 INIT_LIST_HEAD(&stereo_modes);
2722
2723 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 2724 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2725 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 2726 struct drm_display_mode *new_mode;
2727
f7e121b7
DL		 2728 if (!stereo_match_mandatory(mode,
2729 &stereo_mandatory_modes[i]))
2730 continue;
c858cfca 2731
f7e121b7 2732 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 2733 new_mode = drm_mode_duplicate(dev, mode);
2734 if (!new_mode)
2735 continue;
2736
f7e121b7 2737 new_mode->flags |= mandatory->flags;
c858cfca
DL		 2738 list_add_tail(&new_mode->head, &stereo_modes);
2739 modes++;
f7e121b7 2740 }
c858cfca
DL		 2741 }
2742
2743 list_splice_tail(&stereo_modes, &connector->probed_modes);
2744
2745 return modes;
2746}
2747
1deee8d7
DL		 2748static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2749{
2750 struct drm_device *dev = connector->dev;
2751 struct drm_display_mode *newmode;
2752
2753 vic--; /* VICs start at 1 */
2754 if (vic >= ARRAY_SIZE(edid_4k_modes)) {
2755 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2756 return 0;
2757 }
2758
2759 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2760 if (!newmode)
2761 return 0;
2762
2763 drm_mode_probed_add(connector, newmode);
2764
2765 return 1;
2766}
2767
fbf46025
TW		 2768static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2769 const u8 *video_db, u8 video_len, u8 video_index)
2770{
fbf46025
TW		 2771 struct drm_display_mode *newmode;
2772 int modes = 0;
fbf46025
TW		 2773
2774 if (structure & (1 << 0)) {
aff04ace
TW		 2775 newmode = drm_display_mode_from_vic_index(connector, video_db,
2776 video_len,
2777 video_index);
fbf46025
TW		 2778 if (newmode) {
2779 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2780 drm_mode_probed_add(connector, newmode);
2781 modes++;
2782 }
2783 }
2784 if (structure & (1 << 6)) {
aff04ace
TW		 2785 newmode = drm_display_mode_from_vic_index(connector, video_db,
2786 video_len,
2787 video_index);
fbf46025
TW		 2788 if (newmode) {
2789 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2790 drm_mode_probed_add(connector, newmode);
2791 modes++;
2792 }
2793 }
2794 if (structure & (1 << 8)) {
aff04ace
TW		 2795 newmode = drm_display_mode_from_vic_index(connector, video_db,
2796 video_len,
2797 video_index);
fbf46025 2798 if (newmode) {
89570eeb 2799 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 2800 drm_mode_probed_add(connector, newmode);
2801 modes++;
2802 }
2803 }
2804
2805 return modes;
2806}
2807
7ebe1963
LD		 2808/*
2809 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2810 * @connector: connector corresponding to the HDMI sink
2811 * @db: start of the CEA vendor specific block
2812 * @len: length of the CEA block payload, ie. one can access up to db[len]
2813 *
c858cfca
DL		 2814 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2815 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 2816 */
2817static int
fbf46025
TW		 2818do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2819 const u8 *video_db, u8 video_len)
7ebe1963 2820{
0e5083aa 2821 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 2822 u8 vic_len, hdmi_3d_len = 0;
2823 u16 mask;
2824 u16 structure_all;
7ebe1963
LD		 2825
2826 if (len < 8)
2827 goto out;
2828
2829 /* no HDMI_Video_Present */
2830 if (!(db[8] & (1 << 5)))
2831 goto out;
2832
2833 /* Latency_Fields_Present */
2834 if (db[8] & (1 << 7))
2835 offset += 2;
2836
2837 /* I_Latency_Fields_Present */
2838 if (db[8] & (1 << 6))
2839 offset += 2;
2840
2841 /* the declared length is not long enough for the 2 first bytes
2842 * of additional video format capabilities */
c858cfca 2843 if (len < (8 + offset + 2))
7ebe1963
LD		 2844 goto out;
2845
c858cfca
DL		 2846 /* 3D_Present */
2847 offset++;
fbf46025 2848 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 2849 modes += add_hdmi_mandatory_stereo_modes(connector);
2850
fbf46025
TW		 2851 /* 3D_Multi_present */
2852 multi_present = (db[8 + offset] & 0x60) >> 5;
2853 }
2854
c858cfca 2855 offset++;
7ebe1963 2856 vic_len = db[8 + offset] >> 5;
fbf46025 2857 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 2858
2859 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 2860 u8 vic;
2861
2862 vic = db[9 + offset + i];
1deee8d7 2863 modes += add_hdmi_mode(connector, vic);
7ebe1963 2864 }
fbf46025
TW		 2865 offset += 1 + vic_len;
2866
0e5083aa
TW		 2867 if (multi_present == 1)
2868 multi_len = 2;
2869 else if (multi_present == 2)
2870 multi_len = 4;
2871 else
2872 multi_len = 0;
fbf46025 2873
0e5083aa 2874 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 2875 goto out;
2876
0e5083aa 2877 if (hdmi_3d_len < multi_len)
fbf46025
TW		 2878 goto out;
2879
0e5083aa
TW		 2880 if (multi_present == 1 || multi_present == 2) {
2881 /* 3D_Structure_ALL */
2882 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 2883
0e5083aa
TW		 2884 /* check if 3D_MASK is present */
2885 if (multi_present == 2)
2886 mask = (db[10 + offset] << 8) | db[11 + offset];
2887 else
2888 mask = 0xffff;
2889
2890 for (i = 0; i < 16; i++) {
2891 if (mask & (1 << i))
2892 modes += add_3d_struct_modes(connector,
2893 structure_all,
2894 video_db,
2895 video_len, i);
2896 }
2897 }
2898
2899 offset += multi_len;
2900
2901 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
2902 int vic_index;
2903 struct drm_display_mode *newmode = NULL;
2904 unsigned int newflag = 0;
2905 bool detail_present;
2906
2907 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
2908
2909 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
2910 break;
2911
2912 /* 2D_VIC_order_X */
2913 vic_index = db[8 + offset + i] >> 4;
2914
2915 /* 3D_Structure_X */
2916 switch (db[8 + offset + i] & 0x0f) {
2917 case 0:
2918 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
2919 break;
2920 case 6:
2921 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2922 break;
2923 case 8:
2924 /* 3D_Detail_X */
2925 if ((db[9 + offset + i] >> 4) == 1)
2926 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2927 break;
2928 }
2929
2930 if (newflag != 0) {
2931 newmode = drm_display_mode_from_vic_index(connector,
2932 video_db,
2933 video_len,
2934 vic_index);
2935
2936 if (newmode) {
2937 newmode->flags |= newflag;
2938 drm_mode_probed_add(connector, newmode);
2939 modes++;
2940 }
2941 }
2942
2943 if (detail_present)
2944 i++;
fbf46025 2945 }
7ebe1963
LD		 2946
2947out:
2948 return modes;
2949}
2950
9e50b9d5
VS		 2951static int
2952cea_db_payload_len(const u8 *db)
2953{
2954 return db[0] & 0x1f;
2955}
2956
2957static int
2958cea_db_tag(const u8 *db)
2959{
2960 return db[0] >> 5;
2961}
2962
2963static int
2964cea_revision(const u8 *cea)
2965{
2966 return cea[1];
2967}
2968
2969static int
2970cea_db_offsets(const u8 *cea, int *start, int *end)
2971{
2972 /* Data block offset in CEA extension block */
2973 *start = 4;
2974 *end = cea[2];
2975 if (*end == 0)
2976 *end = 127;
2977 if (*end < 4 || *end > 127)
2978 return -ERANGE;
2979 return 0;
2980}
2981
7ebe1963
LD		 2982static bool cea_db_is_hdmi_vsdb(const u8 *db)
2983{
2984 int hdmi_id;
2985
2986 if (cea_db_tag(db) != VENDOR_BLOCK)
2987 return false;
2988
2989 if (cea_db_payload_len(db) < 5)
2990 return false;
2991
2992 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
2993
6cb3b7f1 2994 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 2995}
2996
9e50b9d5
VS		 2997#define for_each_cea_db(cea, i, start, end) \
2998 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
2999
54ac76f8
CS		 3000static int
3001add_cea_modes(struct drm_connector *connector, struct edid *edid)
3002{
13ac3f55 3003 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 3004 const u8 *db, *hdmi = NULL, *video = NULL;
3005 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 3006 int modes = 0;
3007
9e50b9d5
VS		 3008 if (cea && cea_revision(cea) >= 3) {
3009 int i, start, end;
3010
3011 if (cea_db_offsets(cea, &start, &end))
3012 return 0;
3013
3014 for_each_cea_db(cea, i, start, end) {
3015 db = &cea[i];
3016 dbl = cea_db_payload_len(db);
3017
fbf46025
TW		 3018 if (cea_db_tag(db) == VIDEO_BLOCK) {
3019 video = db + 1;
3020 video_len = dbl;
3021 modes += do_cea_modes(connector, video, dbl);
3022 }
c858cfca
DL		 3023 else if (cea_db_is_hdmi_vsdb(db)) {
3024 hdmi = db;
3025 hdmi_len = dbl;
3026 }
54ac76f8
CS		 3027 }
3028 }
3029
c858cfca
DL		 3030 /*
3031 * We parse the HDMI VSDB after having added the cea modes as we will
3032 * be patching their flags when the sink supports stereo 3D.
3033 */
3034 if (hdmi)
fbf46025
TW		 3035 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3036 video_len);
c858cfca 3037
54ac76f8
CS		 3038 return modes;
3039}
3040
76adaa34 3041static void
8504072a 3042parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
76adaa34 3043{
8504072a 3044 u8 len = cea_db_payload_len(db);
76adaa34 3045
8504072a
VS		 3046 if (len >= 6) {
3047 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3048 connector->dvi_dual = db[6] & 1;
3049 }
3050 if (len >= 7)
3051 connector->max_tmds_clock = db[7] * 5;
3052 if (len >= 8) {
3053 connector->latency_present[0] = db[8] >> 7;
3054 connector->latency_present[1] = (db[8] >> 6) & 1;
3055 }
3056 if (len >= 9)
3057 connector->video_latency[0] = db[9];
3058 if (len >= 10)
3059 connector->audio_latency[0] = db[10];
3060 if (len >= 11)
3061 connector->video_latency[1] = db[11];
3062 if (len >= 12)
3063 connector->audio_latency[1] = db[12];
76adaa34 3064
670c1ef6 3065 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
76adaa34
WF		 3066 "max TMDS clock %d, "
3067 "latency present %d %d, "
3068 "video latency %d %d, "
3069 "audio latency %d %d\n",
3070 connector->dvi_dual,
3071 connector->max_tmds_clock,
3072 (int) connector->latency_present[0],
3073 (int) connector->latency_present[1],
3074 connector->video_latency[0],
3075 connector->video_latency[1],
3076 connector->audio_latency[0],
3077 connector->audio_latency[1]);
3078}
3079
3080static void
3081monitor_name(struct detailed_timing *t, void *data)
3082{
3083 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3084 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3085}
3086
76adaa34
WF		 3087/**
3088 * drm_edid_to_eld - build ELD from EDID
3089 * @connector: connector corresponding to the HDMI/DP sink
3090 * @edid: EDID to parse
3091 *
db6cf833
TR		 3092 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3093 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3094 * fill in.
76adaa34
WF		 3095 */
3096void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3097{
3098 uint8_t *eld = connector->eld;
3099 u8 *cea;
3100 u8 *name;
3101 u8 *db;
3102 int sad_count = 0;
3103 int mnl;
3104 int dbl;
3105
3106 memset(eld, 0, sizeof(connector->eld));
3107
3108 cea = drm_find_cea_extension(edid);
3109 if (!cea) {
3110 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3111 return;
3112 }
3113
3114 name = NULL;
3115 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3116 for (mnl = 0; name && mnl < 13; mnl++) {
3117 if (name[mnl] == 0x0a)
3118 break;
3119 eld[20 + mnl] = name[mnl];
3120 }
3121 eld[4] = (cea[1] << 5) | mnl;
3122 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3123
3124 eld[0] = 2 << 3; /* ELD version: 2 */
3125
3126 eld[16] = edid->mfg_id[0];
3127 eld[17] = edid->mfg_id[1];
3128 eld[18] = edid->prod_code[0];
3129 eld[19] = edid->prod_code[1];
3130
9e50b9d5
VS		 3131 if (cea_revision(cea) >= 3) {
3132 int i, start, end;
3133
3134 if (cea_db_offsets(cea, &start, &end)) {
3135 start = 0;
3136 end = 0;
3137 }
3138
3139 for_each_cea_db(cea, i, start, end) {
3140 db = &cea[i];
3141 dbl = cea_db_payload_len(db);
3142
3143 switch (cea_db_tag(db)) {
a0ab734d
CS		 3144 case AUDIO_BLOCK:
3145 /* Audio Data Block, contains SADs */
3146 sad_count = dbl / 3;
9e50b9d5
VS		 3147 if (dbl >= 1)
3148 memcpy(eld + 20 + mnl, &db[1], dbl);
a0ab734d
CS		 3149 break;
3150 case SPEAKER_BLOCK:
9e50b9d5
VS		 3151 /* Speaker Allocation Data Block */
3152 if (dbl >= 1)
3153 eld[7] = db[1];
a0ab734d
CS		 3154 break;
3155 case VENDOR_BLOCK:
3156 /* HDMI Vendor-Specific Data Block */
14f77fdd 3157 if (cea_db_is_hdmi_vsdb(db))
a0ab734d
CS		 3158 parse_hdmi_vsdb(connector, db);
3159 break;
3160 default:
3161 break;
3162 }
76adaa34 3163 }
9e50b9d5 3164 }
76adaa34 3165 eld[5] |= sad_count << 4;
76adaa34 3166
938fd8aa
JN		 3167 eld[DRM_ELD_BASELINE_ELD_LEN] =
3168 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3169
3170 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3171 drm_eld_size(eld), sad_count);
76adaa34
WF		 3172}
3173EXPORT_SYMBOL(drm_edid_to_eld);
3174
fe214163
RM		 3175/**
3176 * drm_edid_to_sad - extracts SADs from EDID
3177 * @edid: EDID to parse
3178 * @sads: pointer that will be set to the extracted SADs
3179 *
3180 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3181 *
db6cf833
TR		 3182 * Note: The returned pointer needs to be freed using kfree().
3183 *
3184 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3185 */
3186int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3187{
3188 int count = 0;
3189 int i, start, end, dbl;
3190 u8 *cea;
3191
3192 cea = drm_find_cea_extension(edid);
3193 if (!cea) {
3194 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3195 return -ENOENT;
3196 }
3197
3198 if (cea_revision(cea) < 3) {
3199 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3200 return -ENOTSUPP;
3201 }
3202
3203 if (cea_db_offsets(cea, &start, &end)) {
3204 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3205 return -EPROTO;
3206 }
3207
3208 for_each_cea_db(cea, i, start, end) {
3209 u8 *db = &cea[i];
3210
3211 if (cea_db_tag(db) == AUDIO_BLOCK) {
3212 int j;
3213 dbl = cea_db_payload_len(db);
3214
3215 count = dbl / 3; /* SAD is 3B */
3216 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3217 if (!*sads)
3218 return -ENOMEM;
3219 for (j = 0; j < count; j++) {
3220 u8 *sad = &db[1 + j * 3];
3221
3222 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3223 (*sads)[j].channels = sad[0] & 0x7;
3224 (*sads)[j].freq = sad[1] & 0x7F;
3225 (*sads)[j].byte2 = sad[2];
3226 }
3227 break;
3228 }
3229 }
3230
3231 return count;
3232}
3233EXPORT_SYMBOL(drm_edid_to_sad);
3234
d105f476
AD		 3235/**
3236 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3237 * @edid: EDID to parse
3238 * @sadb: pointer to the speaker block
3239 *
3240 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 3241 *
db6cf833
TR		 3242 * Note: The returned pointer needs to be freed using kfree().
3243 *
3244 * Return: The number of found Speaker Allocation Blocks or negative number on
3245 * error.
d105f476
AD		 3246 */
3247int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3248{
3249 int count = 0;
3250 int i, start, end, dbl;
3251 const u8 *cea;
3252
3253 cea = drm_find_cea_extension(edid);
3254 if (!cea) {
3255 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3256 return -ENOENT;
3257 }
3258
3259 if (cea_revision(cea) < 3) {
3260 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3261 return -ENOTSUPP;
3262 }
3263
3264 if (cea_db_offsets(cea, &start, &end)) {
3265 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3266 return -EPROTO;
3267 }
3268
3269 for_each_cea_db(cea, i, start, end) {
3270 const u8 *db = &cea[i];
3271
3272 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3273 dbl = cea_db_payload_len(db);
3274
3275 /* Speaker Allocation Data Block */
3276 if (dbl == 3) {
89086bca 3277 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 3278 if (!*sadb)
3279 return -ENOMEM;
d105f476
AD		 3280 count = dbl;
3281 break;
3282 }
3283 }
3284 }
3285
3286 return count;
3287}
3288EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3289
76adaa34 3290/**
db6cf833 3291 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 3292 * @connector: connector associated with the HDMI/DP sink
3293 * @mode: the display mode
db6cf833
TR		 3294 *
3295 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3296 * the sink doesn't support audio or video.
76adaa34
WF		 3297 */
3298int drm_av_sync_delay(struct drm_connector *connector,
3299 struct drm_display_mode *mode)
3300{
3301 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3302 int a, v;
3303
3304 if (!connector->latency_present[0])
3305 return 0;
3306 if (!connector->latency_present[1])
3307 i = 0;
3308
3309 a = connector->audio_latency[i];
3310 v = connector->video_latency[i];
3311
3312 /*
3313 * HDMI/DP sink doesn't support audio or video?
3314 */
3315 if (a == 255 || v == 255)
3316 return 0;
3317
3318 /*
3319 * Convert raw EDID values to millisecond.
3320 * Treat unknown latency as 0ms.
3321 */
3322 if (a)
3323 a = min(2 * (a - 1), 500);
3324 if (v)
3325 v = min(2 * (v - 1), 500);
3326
3327 return max(v - a, 0);
3328}
3329EXPORT_SYMBOL(drm_av_sync_delay);
3330
3331/**
3332 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3333 * @encoder: the encoder just changed display mode
3334 * @mode: the adjusted display mode
3335 *
3336 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3337 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
db6cf833
TR		 3338 *
3339 * Return: The connector associated with the first HDMI/DP sink that has ELD
3340 * attached to it.
76adaa34
WF		 3341 */
3342struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
3343 struct drm_display_mode *mode)
3344{
3345 struct drm_connector *connector;
3346 struct drm_device *dev = encoder->dev;
3347
6e9f798d 3348 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
008f4045 3349 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
6e9f798d 3350
76adaa34
WF		 3351 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
3352 if (connector->encoder == encoder && connector->eld[0])
3353 return connector;
3354
3355 return NULL;
3356}
3357EXPORT_SYMBOL(drm_select_eld);
3358
8fe9790d 3359/**
db6cf833 3360 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 3361 * @edid: monitor EDID information
3362 *
3363 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 3364 *
3365 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 3366 */
3367bool drm_detect_hdmi_monitor(struct edid *edid)
3368{
3369 u8 *edid_ext;
14f77fdd 3370 int i;
8fe9790d 3371 int start_offset, end_offset;
8fe9790d
ZW		 3372
3373 edid_ext = drm_find_cea_extension(edid);
3374 if (!edid_ext)
14f77fdd 3375 return false;
f23c20c8 3376
9e50b9d5 3377 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 3378 return false;
f23c20c8
ML		 3379
3380 /*
3381 * Because HDMI identifier is in Vendor Specific Block,
3382 * search it from all data blocks of CEA extension.
3383 */
9e50b9d5 3384 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 3385 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3386 return true;
f23c20c8
ML		 3387 }
3388
14f77fdd 3389 return false;
f23c20c8
ML		 3390}
3391EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3392
8fe9790d
ZW		 3393/**
3394 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 3395 * @edid: EDID block to scan
8fe9790d
ZW		 3396 *
3397 * Monitor should have CEA extension block.
3398 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3399 * audio' only. If there is any audio extension block and supported
3400 * audio format, assume at least 'basic audio' support, even if 'basic
3401 * audio' is not defined in EDID.
3402 *
db6cf833 3403 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 3404 */
3405bool drm_detect_monitor_audio(struct edid *edid)
3406{
3407 u8 *edid_ext;
3408 int i, j;
3409 bool has_audio = false;
3410 int start_offset, end_offset;
3411
3412 edid_ext = drm_find_cea_extension(edid);
3413 if (!edid_ext)
3414 goto end;
3415
3416 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3417
3418 if (has_audio) {
3419 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3420 goto end;
3421 }
3422
9e50b9d5
VS		 3423 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3424 goto end;
8fe9790d 3425
9e50b9d5
VS		 3426 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3427 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 3428 has_audio = true;
9e50b9d5 3429 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 3430 DRM_DEBUG_KMS("CEA audio format %d\n",
3431 (edid_ext[i + j] >> 3) & 0xf);
3432 goto end;
3433 }
3434 }
3435end:
3436 return has_audio;
3437}
3438EXPORT_SYMBOL(drm_detect_monitor_audio);
3439
b1edd6a6
VS		 3440/**
3441 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 3442 * @edid: EDID block to scan
b1edd6a6
VS		 3443 *
3444 * Check whether the monitor reports the RGB quantization range selection
3445 * as supported. The AVI infoframe can then be used to inform the monitor
3446 * which quantization range (full or limited) is used.
db6cf833
TR		 3447 *
3448 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 3449 */
3450bool drm_rgb_quant_range_selectable(struct edid *edid)
3451{
3452 u8 *edid_ext;
3453 int i, start, end;
3454
3455 edid_ext = drm_find_cea_extension(edid);
3456 if (!edid_ext)
3457 return false;
3458
3459 if (cea_db_offsets(edid_ext, &start, &end))
3460 return false;
3461
3462 for_each_cea_db(edid_ext, i, start, end) {
3463 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3464 cea_db_payload_len(&edid_ext[i]) == 2) {
3465 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3466 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3467 }
3468 }
3469
3470 return false;
3471}
3472EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3473
d0c94692
MK		 3474/**
3475 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3476 * hdmi deep color modes and update drm_display_info if so.
d0c94692
MK		 3477 * @edid: monitor EDID information
3478 * @info: Updated with maximum supported deep color bpc and color format
3479 * if deep color supported.
295ee853 3480 * @connector: DRM connector, used only for debug output
d0c94692
MK		 3481 *
3482 * Parse the CEA extension according to CEA-861-B.
3483 * Return true if HDMI deep color supported, false if not or unknown.
3484 */
3485static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3486 struct drm_display_info *info,
3487 struct drm_connector *connector)
3488{
3489 u8 *edid_ext, *hdmi;
3490 int i;
3491 int start_offset, end_offset;
3492 unsigned int dc_bpc = 0;
3493
3494 edid_ext = drm_find_cea_extension(edid);
3495 if (!edid_ext)
3496 return false;
3497
3498 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3499 return false;
3500
3501 /*
3502 * Because HDMI identifier is in Vendor Specific Block,
3503 * search it from all data blocks of CEA extension.
3504 */
3505 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3506 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3507 /* HDMI supports at least 8 bpc */
3508 info->bpc = 8;
3509
3510 hdmi = &edid_ext[i];
3511 if (cea_db_payload_len(hdmi) < 6)
3512 return false;
3513
3514 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3515 dc_bpc = 10;
5d02626d 3516 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
d0c94692 3517 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
25933820 3518 connector->name);
d0c94692
MK		 3519 }
3520
3521 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3522 dc_bpc = 12;
5d02626d 3523 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
d0c94692 3524 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
25933820 3525 connector->name);
d0c94692
MK		 3526 }
3527
3528 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3529 dc_bpc = 16;
5d02626d 3530 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
d0c94692 3531 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
25933820 3532 connector->name);
d0c94692
MK		 3533 }
3534
3535 if (dc_bpc > 0) {
3536 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
25933820 3537 connector->name, dc_bpc);
d0c94692
MK		 3538 info->bpc = dc_bpc;
3539
3540 /*
3541 * Deep color support mandates RGB444 support for all video
3542 * modes and forbids YCRCB422 support for all video modes per
3543 * HDMI 1.3 spec.
3544 */
3545 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3546
3547 /* YCRCB444 is optional according to spec. */
3548 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3549 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3550 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
25933820 3551 connector->name);
d0c94692
MK		 3552 }
3553
3554 /*
3555 * Spec says that if any deep color mode is supported at all,
3556 * then deep color 36 bit must be supported.
3557 */
3558 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3559 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
25933820 3560 connector->name);
d0c94692
MK		 3561 }
3562
3563 return true;
3564 }
3565 else {
3566 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
25933820 3567 connector->name);
d0c94692
MK		 3568 }
3569 }
3570 }
3571
3572 return false;
3573}
3574
3b11228b
JB		 3575/**
3576 * drm_add_display_info - pull display info out if present
3577 * @edid: EDID data
3578 * @info: display info (attached to connector)
d0c94692 3579 * @connector: connector whose edid is used to build display info
3b11228b
JB		 3580 *
3581 * Grab any available display info and stuff it into the drm_display_info
3582 * structure that's part of the connector. Useful for tracking bpp and
3583 * color spaces.
3584 */
3585static void drm_add_display_info(struct edid *edid,
d0c94692
MK		 3586 struct drm_display_info *info,
3587 struct drm_connector *connector)
3b11228b 3588{
ebec9a7b
JB		 3589 u8 *edid_ext;
3590
3b11228b
JB		 3591 info->width_mm = edid->width_cm * 10;
3592 info->height_mm = edid->height_cm * 10;
3593
3594 /* driver figures it out in this case */
3595 info->bpc = 0;
da05a5a7 3596 info->color_formats = 0;
3b11228b 3597
a988bc72 3598 if (edid->revision < 3)
3b11228b
JB		 3599 return;
3600
3601 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3602 return;
3603
a988bc72
LPC		 3604 /* Get data from CEA blocks if present */
3605 edid_ext = drm_find_cea_extension(edid);
3606 if (edid_ext) {
3607 info->cea_rev = edid_ext[1];
3608
3609 /* The existence of a CEA block should imply RGB support */
3610 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3611 if (edid_ext[3] & EDID_CEA_YCRCB444)
3612 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3613 if (edid_ext[3] & EDID_CEA_YCRCB422)
3614 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3615 }
3616
d0c94692
MK		 3617 /* HDMI deep color modes supported? Assign to info, if so */
3618 drm_assign_hdmi_deep_color_info(edid, info, connector);
3619
a988bc72
LPC		 3620 /* Only defined for 1.4 with digital displays */
3621 if (edid->revision < 4)
3622 return;
3623
3b11228b
JB		 3624 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3625 case DRM_EDID_DIGITAL_DEPTH_6:
3626 info->bpc = 6;
3627 break;
3628 case DRM_EDID_DIGITAL_DEPTH_8:
3629 info->bpc = 8;
3630 break;
3631 case DRM_EDID_DIGITAL_DEPTH_10:
3632 info->bpc = 10;
3633 break;
3634 case DRM_EDID_DIGITAL_DEPTH_12:
3635 info->bpc = 12;
3636 break;
3637 case DRM_EDID_DIGITAL_DEPTH_14:
3638 info->bpc = 14;
3639 break;
3640 case DRM_EDID_DIGITAL_DEPTH_16:
3641 info->bpc = 16;
3642 break;
3643 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3644 default:
3645 info->bpc = 0;
3646 break;
3647 }
da05a5a7 3648
d0c94692 3649 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 3650 connector->name, info->bpc);
d0c94692 3651
a988bc72 3652 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 3653 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3654 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3655 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3656 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3b11228b
JB		 3657}
3658
f453ba04
DA		 3659/**
3660 * drm_add_edid_modes - add modes from EDID data, if available
3661 * @connector: connector we're probing
db6cf833 3662 * @edid: EDID data
f453ba04
DA		 3663 *
3664 * Add the specified modes to the connector's mode list.
3665 *
db6cf833 3666 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 3667 */
3668int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3669{
3670 int num_modes = 0;
3671 u32 quirks;
3672
3673 if (edid == NULL) {
3674 return 0;
3675 }
3c537889 3676 if (!drm_edid_is_valid(edid)) {
dcdb1674 3677 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 3678 connector->name);
f453ba04
DA		 3679 return 0;
3680 }
3681
3682 quirks = edid_get_quirks(edid);
3683
c867df70
AJ		 3684 /*
3685 * EDID spec says modes should be preferred in this order:
3686 * - preferred detailed mode
3687 * - other detailed modes from base block
3688 * - detailed modes from extension blocks
3689 * - CVT 3-byte code modes
3690 * - standard timing codes
3691 * - established timing codes
3692 * - modes inferred from GTF or CVT range information
3693 *
13931579 3694 * We get this pretty much right.
c867df70
AJ		 3695 *
3696 * XXX order for additional mode types in extension blocks?
3697 */
13931579
AJ		 3698 num_modes += add_detailed_modes(connector, edid, quirks);
3699 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 3700 num_modes += add_standard_modes(connector, edid);
3701 num_modes += add_established_modes(connector, edid);
196e077d
PZ		 3702 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3703 num_modes += add_inferred_modes(connector, edid);
54ac76f8 3704 num_modes += add_cea_modes(connector, edid);
e6e79209 3705 num_modes += add_alternate_cea_modes(connector, edid);
f453ba04
DA		 3706
3707 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3708 edid_fixup_preferred(connector, quirks);
3709
d0c94692 3710 drm_add_display_info(edid, &connector->display_info, connector);
f453ba04 3711
49d45a31
RM		 3712 if (quirks & EDID_QUIRK_FORCE_8BPC)
3713 connector->display_info.bpc = 8;
3714
bc5b9641
MK		 3715 if (quirks & EDID_QUIRK_FORCE_12BPC)
3716 connector->display_info.bpc = 12;
3717
f453ba04
DA		 3718 return num_modes;
3719}
3720EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 3721
3722/**
3723 * drm_add_modes_noedid - add modes for the connectors without EDID
3724 * @connector: connector we're probing
3725 * @hdisplay: the horizontal display limit
3726 * @vdisplay: the vertical display limit
3727 *
3728 * Add the specified modes to the connector's mode list. Only when the
3729 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3730 *
db6cf833 3731 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 3732 */
3733int drm_add_modes_noedid(struct drm_connector *connector,
3734 int hdisplay, int vdisplay)
3735{
3736 int i, count, num_modes = 0;
b1f559ec 3737 struct drm_display_mode *mode;
f0fda0a4
ZY		 3738 struct drm_device *dev = connector->dev;
3739
3740 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
3741 if (hdisplay < 0)
3742 hdisplay = 0;
3743 if (vdisplay < 0)
3744 vdisplay = 0;
3745
3746 for (i = 0; i < count; i++) {
b1f559ec 3747 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 3748 if (hdisplay && vdisplay) {
3749 /*
3750 * Only when two are valid, they will be used to check
3751 * whether the mode should be added to the mode list of
3752 * the connector.
3753 */
3754 if (ptr->hdisplay > hdisplay ||
3755 ptr->vdisplay > vdisplay)
3756 continue;
3757 }
f985dedb
AJ		 3758 if (drm_mode_vrefresh(ptr) > 61)
3759 continue;
f0fda0a4
ZY		 3760 mode = drm_mode_duplicate(dev, ptr);
3761 if (mode) {
3762 drm_mode_probed_add(connector, mode);
3763 num_modes++;
3764 }
3765 }
3766 return num_modes;
3767}
3768EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 3769
db6cf833
TR		 3770/**
3771 * drm_set_preferred_mode - Sets the preferred mode of a connector
3772 * @connector: connector whose mode list should be processed
3773 * @hpref: horizontal resolution of preferred mode
3774 * @vpref: vertical resolution of preferred mode
3775 *
3776 * Marks a mode as preferred if it matches the resolution specified by @hpref
3777 * and @vpref.
3778 */
3cf70daf
GH		 3779void drm_set_preferred_mode(struct drm_connector *connector,
3780 int hpref, int vpref)
3781{
3782 struct drm_display_mode *mode;
3783
3784 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 3785 if (mode->hdisplay == hpref &&
9d3de138 3786 mode->vdisplay == vpref)
3cf70daf
GH		 3787 mode->type |= DRM_MODE_TYPE_PREFERRED;
3788 }
3789}
3790EXPORT_SYMBOL(drm_set_preferred_mode);
3791
10a85120
TR		 3792/**
3793 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
3794 * data from a DRM display mode
3795 * @frame: HDMI AVI infoframe
3796 * @mode: DRM display mode
3797 *
db6cf833 3798 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 3799 */
3800int
3801drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
3802 const struct drm_display_mode *mode)
3803{
3804 int err;
3805
3806 if (!frame || !mode)
3807 return -EINVAL;
3808
3809 err = hdmi_avi_infoframe_init(frame);
3810 if (err < 0)
3811 return err;
3812
bf02db99
DL		 3813 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
3814 frame->pixel_repeat = 1;
3815
10a85120 3816 frame->video_code = drm_match_cea_mode(mode);
10a85120
TR		 3817
3818 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3819
69ab6d35
VK		 3820 /*
3821 * Populate picture aspect ratio from either
3822 * user input (if specified) or from the CEA mode list.
3823 */
3824 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
3825 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
3826 frame->picture_aspect = mode->picture_aspect_ratio;
3827 else if (frame->video_code > 0)
0967e6a5
VK		 3828 frame->picture_aspect = drm_get_cea_aspect_ratio(
3829 frame->video_code);
3830
10a85120 3831 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 3832 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 3833
3834 return 0;
3835}
3836EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 3837
4eed4a0a
DL		 3838static enum hdmi_3d_structure
3839s3d_structure_from_display_mode(const struct drm_display_mode *mode)
3840{
3841 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
3842
3843 switch (layout) {
3844 case DRM_MODE_FLAG_3D_FRAME_PACKING:
3845 return HDMI_3D_STRUCTURE_FRAME_PACKING;
3846 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
3847 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
3848 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
3849 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
3850 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
3851 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
3852 case DRM_MODE_FLAG_3D_L_DEPTH:
3853 return HDMI_3D_STRUCTURE_L_DEPTH;
3854 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
3855 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
3856 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
3857 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
3858 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
3859 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
3860 default:
3861 return HDMI_3D_STRUCTURE_INVALID;
3862 }
3863}
3864
83dd0008
LD		 3865/**
3866 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
3867 * data from a DRM display mode
3868 * @frame: HDMI vendor infoframe
3869 * @mode: DRM display mode
3870 *
3871 * Note that there's is a need to send HDMI vendor infoframes only when using a
3872 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
3873 * function will return -EINVAL, error that can be safely ignored.
3874 *
db6cf833 3875 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 3876 */
3877int
3878drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
3879 const struct drm_display_mode *mode)
3880{
3881 int err;
4eed4a0a 3882 u32 s3d_flags;
83dd0008
LD		 3883 u8 vic;
3884
3885 if (!frame || !mode)
3886 return -EINVAL;
3887
3888 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 3889 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
3890
3891 if (!vic && !s3d_flags)
3892 return -EINVAL;
3893
3894 if (vic && s3d_flags)
83dd0008
LD		 3895 return -EINVAL;
3896
3897 err = hdmi_vendor_infoframe_init(frame);
3898 if (err < 0)
3899 return err;
3900
4eed4a0a
DL		 3901 if (vic)
3902 frame->vic = vic;
3903 else
3904 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 3905
3906 return 0;
3907}
3908EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043
DA		 3909
3910static int drm_parse_display_id(struct drm_connector *connector,
3911 u8 *displayid, int length,
3912 bool is_edid_extension)
3913{
3914 /* if this is an EDID extension the first byte will be 0x70 */
3915 int idx = 0;
3916 struct displayid_hdr *base;
3917 struct displayid_block *block;
3918 u8 csum = 0;
3919 int i;
3920
3921 if (is_edid_extension)
3922 idx = 1;
3923
3924 base = (struct displayid_hdr *)&displayid[idx];
3925
3926 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
3927 base->rev, base->bytes, base->prod_id, base->ext_count);
3928
3929 if (base->bytes + 5 > length - idx)
3930 return -EINVAL;
3931
3932 for (i = idx; i <= base->bytes + 5; i++) {
3933 csum += displayid[i];
3934 }
3935 if (csum) {
3936 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
3937 return -EINVAL;
3938 }
3939
3940 block = (struct displayid_block *)&displayid[idx + 4];
3941 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
3942 block->tag, block->rev, block->num_bytes);
3943
3944 switch (block->tag) {
3945 case DATA_BLOCK_TILED_DISPLAY: {
3946 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
3947
3948 u16 w, h;
3949 u8 tile_v_loc, tile_h_loc;
3950 u8 num_v_tile, num_h_tile;
3951 struct drm_tile_group *tg;
3952
3953 w = tile->tile_size[0] | tile->tile_size[1] << 8;
3954 h = tile->tile_size[2] | tile->tile_size[3] << 8;
3955
3956 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
3957 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
3958 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
3959 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
3960
3961 connector->has_tile = true;
3962 if (tile->tile_cap & 0x80)
3963 connector->tile_is_single_monitor = true;
3964
3965 connector->num_h_tile = num_h_tile + 1;
3966 connector->num_v_tile = num_v_tile + 1;
3967 connector->tile_h_loc = tile_h_loc;
3968 connector->tile_v_loc = tile_v_loc;
3969 connector->tile_h_size = w + 1;
3970 connector->tile_v_size = h + 1;
3971
3972 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
3973 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
3974 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
3975 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
3976 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
3977
3978 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
3979 if (!tg) {
3980 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
3981 }
3982 if (!tg)
3983 return -ENOMEM;
3984
3985 if (connector->tile_group != tg) {
3986 /* if we haven't got a pointer,
3987 take the reference, drop ref to old tile group */
3988 if (connector->tile_group) {
3989 drm_mode_put_tile_group(connector->dev, connector->tile_group);
3990 }
3991 connector->tile_group = tg;
3992 } else
3993 /* if same tile group, then release the ref we just took. */
3994 drm_mode_put_tile_group(connector->dev, tg);
3995 }
3996 break;
3997 default:
3998 printk("unknown displayid tag %d\n", block->tag);
3999 break;
4000 }
4001 return 0;
4002}
4003
4004static void drm_get_displayid(struct drm_connector *connector,
4005 struct edid *edid)
4006{
4007 void *displayid = NULL;
4008 int ret;
4009 connector->has_tile = false;
4010 displayid = drm_find_displayid_extension(edid);
4011 if (!displayid) {
4012 /* drop reference to any tile group we had */
4013 goto out_drop_ref;
4014 }
4015
4016 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4017 if (ret < 0)
4018 goto out_drop_ref;
4019 if (!connector->has_tile)
4020 goto out_drop_ref;
4021 return;
4022out_drop_ref:
4023 if (connector->tile_group) {
4024 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4025 connector->tile_group = NULL;
4026 }
4027 return;
4028}
Linux kernel - Deliverables
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