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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/i2c.h> | |
32 | #include <linux/i2c-algo-bit.h> | |
33 | #include "drmP.h" | |
34 | #include "drm_edid.h" | |
35 | ||
f453ba04 DA |
36 | /* |
37 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
38 | * them here (note that userspace may work around broken monitors first, | |
39 | * but fixes should make their way here so that the kernel "just works" | |
40 | * on as many displays as possible). | |
41 | */ | |
42 | ||
43 | /* First detailed mode wrong, use largest 60Hz mode */ | |
44 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
45 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
46 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
47 | /* Prefer the largest mode at 75 Hz */ | |
48 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
49 | /* Detail timing is in cm not mm */ | |
50 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
51 | /* Detailed timing descriptors have bogus size values, so just take the | |
52 | * maximum size and use that. | |
53 | */ | |
54 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
55 | /* Monitor forgot to set the first detailed is preferred bit. */ | |
56 | #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) | |
57 | /* use +hsync +vsync for detailed mode */ | |
58 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
3c537889 | 59 | |
f453ba04 | 60 | |
5c61259e ZY |
61 | #define LEVEL_DMT 0 |
62 | #define LEVEL_GTF 1 | |
63 | #define LEVEL_CVT 2 | |
64 | ||
f453ba04 DA |
65 | static struct edid_quirk { |
66 | char *vendor; | |
67 | int product_id; | |
68 | u32 quirks; | |
69 | } edid_quirk_list[] = { | |
70 | /* Acer AL1706 */ | |
71 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | |
72 | /* Acer F51 */ | |
73 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, | |
74 | /* Unknown Acer */ | |
75 | { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
76 | ||
77 | /* Belinea 10 15 55 */ | |
78 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, | |
79 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, | |
80 | ||
81 | /* Envision Peripherals, Inc. EN-7100e */ | |
82 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, | |
83 | ||
84 | /* Funai Electronics PM36B */ | |
85 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | | |
86 | EDID_QUIRK_DETAILED_IN_CM }, | |
87 | ||
88 | /* LG Philips LCD LP154W01-A5 */ | |
89 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
90 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
91 | ||
92 | /* Philips 107p5 CRT */ | |
93 | { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
94 | ||
95 | /* Proview AY765C */ | |
96 | { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
97 | ||
98 | /* Samsung SyncMaster 205BW. Note: irony */ | |
99 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, | |
100 | /* Samsung SyncMaster 22[5-6]BW */ | |
101 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, | |
102 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, | |
103 | }; | |
104 | ||
61e57a8d | 105 | /*** DDC fetch and block validation ***/ |
f453ba04 | 106 | |
083ae056 AJ |
107 | static const u8 edid_header[] = { |
108 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
109 | }; | |
f453ba04 | 110 | |
61e57a8d AJ |
111 | /* |
112 | * Sanity check the EDID block (base or extension). Return 0 if the block | |
113 | * doesn't check out, or 1 if it's valid. | |
f453ba04 | 114 | */ |
61e57a8d AJ |
115 | static bool |
116 | drm_edid_block_valid(u8 *raw_edid) | |
f453ba04 | 117 | { |
61e57a8d | 118 | int i; |
f453ba04 | 119 | u8 csum = 0; |
61e57a8d | 120 | struct edid *edid = (struct edid *)raw_edid; |
f453ba04 | 121 | |
61e57a8d AJ |
122 | if (raw_edid[0] == 0x00) { |
123 | int score = 0; | |
862b89c0 | 124 | |
61e57a8d AJ |
125 | for (i = 0; i < sizeof(edid_header); i++) |
126 | if (raw_edid[i] == edid_header[i]) | |
127 | score++; | |
128 | ||
129 | if (score == 8) ; | |
130 | else if (score >= 6) { | |
131 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); | |
132 | memcpy(raw_edid, edid_header, sizeof(edid_header)); | |
133 | } else { | |
134 | goto bad; | |
135 | } | |
136 | } | |
f453ba04 DA |
137 | |
138 | for (i = 0; i < EDID_LENGTH; i++) | |
139 | csum += raw_edid[i]; | |
140 | if (csum) { | |
141 | DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); | |
142 | goto bad; | |
143 | } | |
144 | ||
61e57a8d AJ |
145 | /* per-block-type checks */ |
146 | switch (raw_edid[0]) { | |
147 | case 0: /* base */ | |
148 | if (edid->version != 1) { | |
149 | DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); | |
150 | goto bad; | |
151 | } | |
862b89c0 | 152 | |
61e57a8d AJ |
153 | if (edid->revision > 4) |
154 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); | |
155 | break; | |
156 | ||
157 | default: | |
158 | break; | |
159 | } | |
47ee4ccf | 160 | |
f453ba04 DA |
161 | return 1; |
162 | ||
163 | bad: | |
164 | if (raw_edid) { | |
165 | DRM_ERROR("Raw EDID:\n"); | |
166 | print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH); | |
167 | printk("\n"); | |
168 | } | |
169 | return 0; | |
170 | } | |
61e57a8d AJ |
171 | |
172 | /** | |
173 | * drm_edid_is_valid - sanity check EDID data | |
174 | * @edid: EDID data | |
175 | * | |
176 | * Sanity-check an entire EDID record (including extensions) | |
177 | */ | |
178 | bool drm_edid_is_valid(struct edid *edid) | |
179 | { | |
180 | int i; | |
181 | u8 *raw = (u8 *)edid; | |
182 | ||
183 | if (!edid) | |
184 | return false; | |
185 | ||
186 | for (i = 0; i <= edid->extensions; i++) | |
187 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH)) | |
188 | return false; | |
189 | ||
190 | return true; | |
191 | } | |
3c537889 | 192 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 193 | |
61e57a8d AJ |
194 | #define DDC_ADDR 0x50 |
195 | #define DDC_SEGMENT_ADDR 0x30 | |
196 | /** | |
197 | * Get EDID information via I2C. | |
198 | * | |
199 | * \param adapter : i2c device adaptor | |
200 | * \param buf : EDID data buffer to be filled | |
201 | * \param len : EDID data buffer length | |
202 | * \return 0 on success or -1 on failure. | |
203 | * | |
204 | * Try to fetch EDID information by calling i2c driver function. | |
205 | */ | |
206 | static int | |
207 | drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, | |
208 | int block, int len) | |
209 | { | |
210 | unsigned char start = block * EDID_LENGTH; | |
211 | struct i2c_msg msgs[] = { | |
212 | { | |
213 | .addr = DDC_ADDR, | |
214 | .flags = 0, | |
215 | .len = 1, | |
216 | .buf = &start, | |
217 | }, { | |
218 | .addr = DDC_ADDR, | |
219 | .flags = I2C_M_RD, | |
220 | .len = len, | |
221 | .buf = buf + start, | |
222 | } | |
223 | }; | |
224 | ||
225 | if (i2c_transfer(adapter, msgs, 2) == 2) | |
226 | return 0; | |
227 | ||
228 | return -1; | |
229 | } | |
230 | ||
231 | static u8 * | |
232 | drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
233 | { | |
234 | int i, j = 0; | |
235 | u8 *block, *new; | |
236 | ||
237 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
238 | return NULL; | |
239 | ||
240 | /* base block fetch */ | |
241 | for (i = 0; i < 4; i++) { | |
242 | if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) | |
243 | goto out; | |
244 | if (drm_edid_block_valid(block)) | |
245 | break; | |
246 | } | |
247 | if (i == 4) | |
248 | goto carp; | |
249 | ||
250 | /* if there's no extensions, we're done */ | |
251 | if (block[0x7e] == 0) | |
252 | return block; | |
253 | ||
254 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
255 | if (!new) | |
256 | goto out; | |
257 | block = new; | |
258 | ||
259 | for (j = 1; j <= block[0x7e]; j++) { | |
260 | for (i = 0; i < 4; i++) { | |
261 | if (drm_do_probe_ddc_edid(adapter, block, j, | |
262 | EDID_LENGTH)) | |
263 | goto out; | |
264 | if (drm_edid_block_valid(block + j * EDID_LENGTH)) | |
265 | break; | |
266 | } | |
267 | if (i == 4) | |
268 | goto carp; | |
269 | } | |
270 | ||
271 | return block; | |
272 | ||
273 | carp: | |
274 | dev_warn(&connector->dev->pdev->dev, "%s: EDID block %d invalid.\n", | |
275 | drm_get_connector_name(connector), j); | |
276 | ||
277 | out: | |
278 | kfree(block); | |
279 | return NULL; | |
280 | } | |
281 | ||
282 | /** | |
283 | * Probe DDC presence. | |
284 | * | |
285 | * \param adapter : i2c device adaptor | |
286 | * \return 1 on success | |
287 | */ | |
288 | static bool | |
289 | drm_probe_ddc(struct i2c_adapter *adapter) | |
290 | { | |
291 | unsigned char out; | |
292 | ||
293 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
294 | } | |
295 | ||
296 | /** | |
297 | * drm_get_edid - get EDID data, if available | |
298 | * @connector: connector we're probing | |
299 | * @adapter: i2c adapter to use for DDC | |
300 | * | |
301 | * Poke the given i2c channel to grab EDID data if possible. If found, | |
302 | * attach it to the connector. | |
303 | * | |
304 | * Return edid data or NULL if we couldn't find any. | |
305 | */ | |
306 | struct edid *drm_get_edid(struct drm_connector *connector, | |
307 | struct i2c_adapter *adapter) | |
308 | { | |
309 | struct edid *edid = NULL; | |
310 | ||
311 | if (drm_probe_ddc(adapter)) | |
312 | edid = (struct edid *)drm_do_get_edid(connector, adapter); | |
313 | ||
314 | connector->display_info.raw_edid = (char *)edid; | |
315 | ||
316 | return edid; | |
317 | ||
318 | } | |
319 | EXPORT_SYMBOL(drm_get_edid); | |
320 | ||
321 | /*** EDID parsing ***/ | |
322 | ||
f453ba04 DA |
323 | /** |
324 | * edid_vendor - match a string against EDID's obfuscated vendor field | |
325 | * @edid: EDID to match | |
326 | * @vendor: vendor string | |
327 | * | |
328 | * Returns true if @vendor is in @edid, false otherwise | |
329 | */ | |
330 | static bool edid_vendor(struct edid *edid, char *vendor) | |
331 | { | |
332 | char edid_vendor[3]; | |
333 | ||
334 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | |
335 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | |
336 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | |
16456c87 | 337 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; |
f453ba04 DA |
338 | |
339 | return !strncmp(edid_vendor, vendor, 3); | |
340 | } | |
341 | ||
342 | /** | |
343 | * edid_get_quirks - return quirk flags for a given EDID | |
344 | * @edid: EDID to process | |
345 | * | |
346 | * This tells subsequent routines what fixes they need to apply. | |
347 | */ | |
348 | static u32 edid_get_quirks(struct edid *edid) | |
349 | { | |
350 | struct edid_quirk *quirk; | |
351 | int i; | |
352 | ||
353 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
354 | quirk = &edid_quirk_list[i]; | |
355 | ||
356 | if (edid_vendor(edid, quirk->vendor) && | |
357 | (EDID_PRODUCT_ID(edid) == quirk->product_id)) | |
358 | return quirk->quirks; | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
365 | #define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh)) | |
366 | ||
367 | ||
368 | /** | |
369 | * edid_fixup_preferred - set preferred modes based on quirk list | |
370 | * @connector: has mode list to fix up | |
371 | * @quirks: quirks list | |
372 | * | |
373 | * Walk the mode list for @connector, clearing the preferred status | |
374 | * on existing modes and setting it anew for the right mode ala @quirks. | |
375 | */ | |
376 | static void edid_fixup_preferred(struct drm_connector *connector, | |
377 | u32 quirks) | |
378 | { | |
379 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 380 | int target_refresh = 0; |
f453ba04 DA |
381 | |
382 | if (list_empty(&connector->probed_modes)) | |
383 | return; | |
384 | ||
385 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
386 | target_refresh = 60; | |
387 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
388 | target_refresh = 75; | |
389 | ||
390 | preferred_mode = list_first_entry(&connector->probed_modes, | |
391 | struct drm_display_mode, head); | |
392 | ||
393 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
394 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
395 | ||
396 | if (cur_mode == preferred_mode) | |
397 | continue; | |
398 | ||
399 | /* Largest mode is preferred */ | |
400 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
401 | preferred_mode = cur_mode; | |
402 | ||
403 | /* At a given size, try to get closest to target refresh */ | |
404 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
405 | MODE_REFRESH_DIFF(cur_mode, target_refresh) < | |
406 | MODE_REFRESH_DIFF(preferred_mode, target_refresh)) { | |
407 | preferred_mode = cur_mode; | |
408 | } | |
409 | } | |
410 | ||
411 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
412 | } | |
413 | ||
aa9eaa1f ZY |
414 | /* |
415 | * Add the Autogenerated from the DMT spec. | |
416 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
417 | * But the mode with Reduced blank feature is deleted. | |
418 | */ | |
419 | static struct drm_display_mode drm_dmt_modes[] = { | |
420 | /* 640x350@85Hz */ | |
421 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
422 | 736, 832, 0, 350, 382, 385, 445, 0, | |
423 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
424 | /* 640x400@85Hz */ | |
425 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
426 | 736, 832, 0, 400, 401, 404, 445, 0, | |
427 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
428 | /* 720x400@85Hz */ | |
429 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, | |
430 | 828, 936, 0, 400, 401, 404, 446, 0, | |
431 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
432 | /* 640x480@60Hz */ | |
433 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
434 | 752, 800, 0, 480, 489, 492, 525, 0, | |
435 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
436 | /* 640x480@72Hz */ | |
437 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
438 | 704, 832, 0, 480, 489, 492, 520, 0, | |
439 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
440 | /* 640x480@75Hz */ | |
441 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
442 | 720, 840, 0, 480, 481, 484, 500, 0, | |
443 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
444 | /* 640x480@85Hz */ | |
445 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, | |
446 | 752, 832, 0, 480, 481, 484, 509, 0, | |
447 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
448 | /* 800x600@56Hz */ | |
449 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
450 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
451 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
452 | /* 800x600@60Hz */ | |
453 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
454 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
455 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
456 | /* 800x600@72Hz */ | |
457 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
458 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
459 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
460 | /* 800x600@75Hz */ | |
461 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
462 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
463 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
464 | /* 800x600@85Hz */ | |
465 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, | |
466 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
467 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
468 | /* 848x480@60Hz */ | |
469 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, | |
470 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
471 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
472 | /* 1024x768@43Hz, interlace */ | |
473 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, | |
474 | 1208, 1264, 0, 768, 768, 772, 817, 0, | |
475 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
476 | DRM_MODE_FLAG_INTERLACE) }, | |
477 | /* 1024x768@60Hz */ | |
478 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
479 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
480 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
481 | /* 1024x768@70Hz */ | |
482 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
483 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
484 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
485 | /* 1024x768@75Hz */ | |
486 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, | |
487 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
488 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
489 | /* 1024x768@85Hz */ | |
490 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, | |
491 | 1072, 1376, 0, 768, 769, 772, 808, 0, | |
492 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
493 | /* 1152x864@75Hz */ | |
494 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
495 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
496 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
497 | /* 1280x768@60Hz */ | |
498 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, | |
499 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
500 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
501 | /* 1280x768@75Hz */ | |
502 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, | |
503 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
504 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
505 | /* 1280x768@85Hz */ | |
506 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, | |
507 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
508 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
509 | /* 1280x800@60Hz */ | |
510 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, | |
511 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
512 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
513 | /* 1280x800@75Hz */ | |
514 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, | |
515 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
516 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
517 | /* 1280x800@85Hz */ | |
518 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, | |
519 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
520 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
521 | /* 1280x960@60Hz */ | |
522 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, | |
523 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
524 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
525 | /* 1280x960@85Hz */ | |
526 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, | |
527 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
528 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
529 | /* 1280x1024@60Hz */ | |
530 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, | |
531 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
532 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
533 | /* 1280x1024@75Hz */ | |
534 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
535 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
536 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
537 | /* 1280x1024@85Hz */ | |
538 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, | |
539 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
540 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
541 | /* 1360x768@60Hz */ | |
542 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, | |
543 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
544 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
545 | /* 1440x1050@60Hz */ | |
546 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, | |
547 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
548 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
549 | /* 1440x1050@75Hz */ | |
550 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, | |
551 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
552 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
553 | /* 1440x1050@85Hz */ | |
554 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, | |
555 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
556 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
557 | /* 1440x900@60Hz */ | |
558 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, | |
559 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
560 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
561 | /* 1440x900@75Hz */ | |
562 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, | |
563 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
564 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
565 | /* 1440x900@85Hz */ | |
566 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, | |
567 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
568 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
569 | /* 1600x1200@60Hz */ | |
570 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, | |
571 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
572 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
573 | /* 1600x1200@65Hz */ | |
574 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, | |
575 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
576 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
577 | /* 1600x1200@70Hz */ | |
578 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, | |
579 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
580 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
581 | /* 1600x1200@75Hz */ | |
582 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664, | |
583 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
584 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
585 | /* 1600x1200@85Hz */ | |
586 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, | |
587 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
588 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
589 | /* 1680x1050@60Hz */ | |
590 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, | |
591 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
592 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
593 | /* 1680x1050@75Hz */ | |
594 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, | |
595 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
596 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
597 | /* 1680x1050@85Hz */ | |
598 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, | |
599 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
600 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
601 | /* 1792x1344@60Hz */ | |
602 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, | |
603 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
604 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
605 | /* 1729x1344@75Hz */ | |
606 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, | |
607 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
608 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
609 | /* 1853x1392@60Hz */ | |
610 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, | |
611 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
612 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
613 | /* 1856x1392@75Hz */ | |
614 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, | |
615 | 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, | |
616 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
617 | /* 1920x1200@60Hz */ | |
618 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, | |
619 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
620 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
621 | /* 1920x1200@75Hz */ | |
622 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, | |
623 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
624 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
625 | /* 1920x1200@85Hz */ | |
626 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, | |
627 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
628 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
629 | /* 1920x1440@60Hz */ | |
630 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, | |
631 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
632 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
633 | /* 1920x1440@75Hz */ | |
634 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, | |
635 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
636 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
637 | /* 2560x1600@60Hz */ | |
638 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, | |
639 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
640 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
641 | /* 2560x1600@75HZ */ | |
642 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, | |
643 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
644 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
645 | /* 2560x1600@85HZ */ | |
646 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, | |
647 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
648 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
649 | }; | |
07a5e632 AJ |
650 | static const int drm_num_dmt_modes = |
651 | sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); | |
aa9eaa1f | 652 | |
559ee21d ZY |
653 | static struct drm_display_mode *drm_find_dmt(struct drm_device *dev, |
654 | int hsize, int vsize, int fresh) | |
655 | { | |
07a5e632 | 656 | int i; |
559ee21d ZY |
657 | struct drm_display_mode *ptr, *mode; |
658 | ||
559ee21d | 659 | mode = NULL; |
07a5e632 | 660 | for (i = 0; i < drm_num_dmt_modes; i++) { |
559ee21d ZY |
661 | ptr = &drm_dmt_modes[i]; |
662 | if (hsize == ptr->hdisplay && | |
663 | vsize == ptr->vdisplay && | |
664 | fresh == drm_mode_vrefresh(ptr)) { | |
665 | /* get the expected default mode */ | |
666 | mode = drm_mode_duplicate(dev, ptr); | |
667 | break; | |
668 | } | |
669 | } | |
670 | return mode; | |
671 | } | |
23425cae AJ |
672 | |
673 | /* | |
674 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
675 | * monitors fill with ascii space (0x20) instead. | |
676 | */ | |
677 | static int | |
678 | bad_std_timing(u8 a, u8 b) | |
679 | { | |
680 | return (a == 0x00 && b == 0x00) || | |
681 | (a == 0x01 && b == 0x01) || | |
682 | (a == 0x20 && b == 0x20); | |
683 | } | |
684 | ||
f453ba04 DA |
685 | /** |
686 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
687 | * @t: standard timing params | |
5c61259e | 688 | * @timing_level: standard timing level |
f453ba04 DA |
689 | * |
690 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 691 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 DA |
692 | */ |
693 | struct drm_display_mode *drm_mode_std(struct drm_device *dev, | |
5c61259e | 694 | struct std_timing *t, |
f066a17d | 695 | int revision, |
5c61259e | 696 | int timing_level) |
f453ba04 DA |
697 | { |
698 | struct drm_display_mode *mode; | |
5c61259e ZY |
699 | int hsize, vsize; |
700 | int vrefresh_rate; | |
0454beab MD |
701 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
702 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
703 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
704 | >> EDID_TIMING_VFREQ_SHIFT; | |
705 | ||
23425cae AJ |
706 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
707 | return NULL; | |
708 | ||
5c61259e ZY |
709 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
710 | hsize = t->hsize * 8 + 248; | |
711 | /* vrefresh_rate = vfreq + 60 */ | |
712 | vrefresh_rate = vfreq + 60; | |
713 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d AJ |
714 | if (aspect_ratio == 0) { |
715 | if (revision < 3) | |
716 | vsize = hsize; | |
717 | else | |
718 | vsize = (hsize * 10) / 16; | |
719 | } else if (aspect_ratio == 1) | |
f453ba04 | 720 | vsize = (hsize * 3) / 4; |
0454beab | 721 | else if (aspect_ratio == 2) |
f453ba04 DA |
722 | vsize = (hsize * 4) / 5; |
723 | else | |
724 | vsize = (hsize * 9) / 16; | |
559ee21d ZY |
725 | /* HDTV hack */ |
726 | if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { | |
d50ba256 DA |
727 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
728 | false); | |
559ee21d ZY |
729 | mode->hdisplay = 1366; |
730 | mode->vsync_start = mode->vsync_start - 1; | |
731 | mode->vsync_end = mode->vsync_end - 1; | |
732 | return mode; | |
733 | } | |
5c61259e | 734 | mode = NULL; |
559ee21d ZY |
735 | /* check whether it can be found in default mode table */ |
736 | mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate); | |
737 | if (mode) | |
738 | return mode; | |
739 | ||
5c61259e ZY |
740 | switch (timing_level) { |
741 | case LEVEL_DMT: | |
5c61259e ZY |
742 | break; |
743 | case LEVEL_GTF: | |
744 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
745 | break; | |
746 | case LEVEL_CVT: | |
d50ba256 DA |
747 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
748 | false); | |
5c61259e ZY |
749 | break; |
750 | } | |
f453ba04 DA |
751 | return mode; |
752 | } | |
753 | ||
b58db2c6 AJ |
754 | /* |
755 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
756 | * encoded. Our internal representation is of frame height, but some | |
757 | * HDTV detailed timings are encoded as field height. | |
758 | * | |
759 | * The format list here is from CEA, in frame size. Technically we | |
760 | * should be checking refresh rate too. Whatever. | |
761 | */ | |
762 | static void | |
763 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
764 | struct detailed_pixel_timing *pt) | |
765 | { | |
766 | int i; | |
767 | static const struct { | |
768 | int w, h; | |
769 | } cea_interlaced[] = { | |
770 | { 1920, 1080 }, | |
771 | { 720, 480 }, | |
772 | { 1440, 480 }, | |
773 | { 2880, 480 }, | |
774 | { 720, 576 }, | |
775 | { 1440, 576 }, | |
776 | { 2880, 576 }, | |
777 | }; | |
778 | static const int n_sizes = | |
779 | sizeof(cea_interlaced)/sizeof(cea_interlaced[0]); | |
780 | ||
781 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
782 | return; | |
783 | ||
784 | for (i = 0; i < n_sizes; i++) { | |
785 | if ((mode->hdisplay == cea_interlaced[i].w) && | |
786 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
787 | mode->vdisplay *= 2; | |
788 | mode->vsync_start *= 2; | |
789 | mode->vsync_end *= 2; | |
790 | mode->vtotal *= 2; | |
791 | mode->vtotal |= 1; | |
792 | } | |
793 | } | |
794 | ||
795 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
796 | } | |
797 | ||
f453ba04 DA |
798 | /** |
799 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
800 | * @dev: DRM device (needed to create new mode) | |
801 | * @edid: EDID block | |
802 | * @timing: EDID detailed timing info | |
803 | * @quirks: quirks to apply | |
804 | * | |
805 | * An EDID detailed timing block contains enough info for us to create and | |
806 | * return a new struct drm_display_mode. | |
807 | */ | |
808 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
809 | struct edid *edid, | |
810 | struct detailed_timing *timing, | |
811 | u32 quirks) | |
812 | { | |
813 | struct drm_display_mode *mode; | |
814 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | |
0454beab MD |
815 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
816 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
817 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
818 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
819 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
820 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
821 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4; | |
822 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); | |
f453ba04 | 823 | |
fc438966 | 824 | /* ignore tiny modes */ |
0454beab | 825 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
826 | return NULL; |
827 | ||
0454beab | 828 | if (pt->misc & DRM_EDID_PT_STEREO) { |
f453ba04 DA |
829 | printk(KERN_WARNING "stereo mode not supported\n"); |
830 | return NULL; | |
831 | } | |
0454beab | 832 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
79b7dcb2 | 833 | printk(KERN_WARNING "composite sync not supported\n"); |
f453ba04 DA |
834 | } |
835 | ||
fcb45611 ZY |
836 | /* it is incorrect if hsync/vsync width is zero */ |
837 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
838 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
839 | "Wrong Hsync/Vsync pulse width\n"); | |
840 | return NULL; | |
841 | } | |
f453ba04 DA |
842 | mode = drm_mode_create(dev); |
843 | if (!mode) | |
844 | return NULL; | |
845 | ||
846 | mode->type = DRM_MODE_TYPE_DRIVER; | |
847 | ||
848 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) | |
0454beab MD |
849 | timing->pixel_clock = cpu_to_le16(1088); |
850 | ||
851 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
852 | ||
853 | mode->hdisplay = hactive; | |
854 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
855 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
856 | mode->htotal = mode->hdisplay + hblank; | |
857 | ||
858 | mode->vdisplay = vactive; | |
859 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
860 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
861 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 862 | |
7064fef5 JB |
863 | /* Some EDIDs have bogus h/vtotal values */ |
864 | if (mode->hsync_end > mode->htotal) | |
865 | mode->htotal = mode->hsync_end + 1; | |
866 | if (mode->vsync_end > mode->vtotal) | |
867 | mode->vtotal = mode->vsync_end + 1; | |
868 | ||
f453ba04 DA |
869 | drm_mode_set_name(mode); |
870 | ||
b58db2c6 | 871 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 DA |
872 | |
873 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { | |
0454beab | 874 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; |
f453ba04 DA |
875 | } |
876 | ||
0454beab MD |
877 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? |
878 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
879 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
880 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 | 881 | |
e14cbee4 MD |
882 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
883 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
884 | |
885 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
886 | mode->width_mm *= 10; | |
887 | mode->height_mm *= 10; | |
888 | } | |
889 | ||
890 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
891 | mode->width_mm = edid->width_cm * 10; | |
892 | mode->height_mm = edid->height_cm * 10; | |
893 | } | |
894 | ||
895 | return mode; | |
896 | } | |
897 | ||
898 | /* | |
899 | * Detailed mode info for the EDID "established modes" data to use. | |
900 | */ | |
901 | static struct drm_display_mode edid_est_modes[] = { | |
902 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
903 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
904 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
905 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
906 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
907 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
908 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
909 | 720, 840, 0, 480, 481, 484, 500, 0, | |
910 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
911 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
912 | 704, 832, 0, 480, 489, 491, 520, 0, | |
913 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ | |
914 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
915 | 768, 864, 0, 480, 483, 486, 525, 0, | |
916 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
917 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, | |
918 | 752, 800, 0, 480, 490, 492, 525, 0, | |
919 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
920 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
921 | 846, 900, 0, 400, 421, 423, 449, 0, | |
922 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
923 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
924 | 846, 900, 0, 400, 412, 414, 449, 0, | |
925 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
926 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
927 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
928 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
929 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, | |
930 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
931 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
932 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
933 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
934 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
935 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
936 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
937 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
938 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
939 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
940 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
941 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
942 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
943 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
944 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
945 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
946 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
947 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
948 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
949 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
950 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
951 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
952 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
953 | }; | |
954 | ||
955 | #define EDID_EST_TIMINGS 16 | |
956 | #define EDID_STD_TIMINGS 8 | |
957 | #define EDID_DETAILED_TIMINGS 4 | |
958 | ||
959 | /** | |
960 | * add_established_modes - get est. modes from EDID and add them | |
961 | * @edid: EDID block to scan | |
962 | * | |
963 | * Each EDID block contains a bitmap of the supported "established modes" list | |
964 | * (defined above). Tease them out and add them to the global modes list. | |
965 | */ | |
966 | static int add_established_modes(struct drm_connector *connector, struct edid *edid) | |
967 | { | |
968 | struct drm_device *dev = connector->dev; | |
969 | unsigned long est_bits = edid->established_timings.t1 | | |
970 | (edid->established_timings.t2 << 8) | | |
971 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
972 | int i, modes = 0; | |
973 | ||
974 | for (i = 0; i <= EDID_EST_TIMINGS; i++) | |
975 | if (est_bits & (1<<i)) { | |
976 | struct drm_display_mode *newmode; | |
977 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | |
978 | if (newmode) { | |
979 | drm_mode_probed_add(connector, newmode); | |
980 | modes++; | |
981 | } | |
982 | } | |
983 | ||
984 | return modes; | |
985 | } | |
5c61259e ZY |
986 | /** |
987 | * stanard_timing_level - get std. timing level(CVT/GTF/DMT) | |
988 | * @edid: EDID block to scan | |
989 | */ | |
990 | static int standard_timing_level(struct edid *edid) | |
991 | { | |
992 | if (edid->revision >= 2) { | |
993 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
994 | return LEVEL_CVT; | |
995 | return LEVEL_GTF; | |
996 | } | |
997 | return LEVEL_DMT; | |
998 | } | |
f453ba04 DA |
999 | |
1000 | /** | |
1001 | * add_standard_modes - get std. modes from EDID and add them | |
1002 | * @edid: EDID block to scan | |
1003 | * | |
1004 | * Standard modes can be calculated using the CVT standard. Grab them from | |
1005 | * @edid, calculate them, and add them to the list. | |
1006 | */ | |
1007 | static int add_standard_modes(struct drm_connector *connector, struct edid *edid) | |
1008 | { | |
1009 | struct drm_device *dev = connector->dev; | |
1010 | int i, modes = 0; | |
5c61259e ZY |
1011 | int timing_level; |
1012 | ||
1013 | timing_level = standard_timing_level(edid); | |
f453ba04 DA |
1014 | |
1015 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
1016 | struct std_timing *t = &edid->standard_timings[i]; | |
1017 | struct drm_display_mode *newmode; | |
1018 | ||
5c61259e | 1019 | newmode = drm_mode_std(dev, &edid->standard_timings[i], |
f066a17d | 1020 | edid->revision, timing_level); |
f453ba04 DA |
1021 | if (newmode) { |
1022 | drm_mode_probed_add(connector, newmode); | |
1023 | modes++; | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | return modes; | |
1028 | } | |
1029 | ||
07a5e632 AJ |
1030 | /* |
1031 | * XXX fix this for: | |
1032 | * - GTF secondary curve formula | |
1033 | * - EDID 1.4 range offsets | |
1034 | * - CVT extended bits | |
1035 | */ | |
1036 | static bool | |
1037 | mode_in_range(struct drm_display_mode *mode, struct detailed_timing *timing) | |
1038 | { | |
1039 | struct detailed_data_monitor_range *range; | |
1040 | int hsync, vrefresh; | |
1041 | ||
1042 | range = &timing->data.other_data.data.range; | |
1043 | ||
1044 | hsync = drm_mode_hsync(mode); | |
1045 | vrefresh = drm_mode_vrefresh(mode); | |
1046 | ||
1047 | if (hsync < range->min_hfreq_khz || hsync > range->max_hfreq_khz) | |
1048 | return false; | |
1049 | ||
1050 | if (vrefresh < range->min_vfreq || vrefresh > range->max_vfreq) | |
1051 | return false; | |
1052 | ||
1053 | if (range->pixel_clock_mhz && range->pixel_clock_mhz != 0xff) { | |
1054 | /* be forgiving since it's in units of 10MHz */ | |
1055 | int max_clock = range->pixel_clock_mhz * 10 + 9; | |
1056 | max_clock *= 1000; | |
1057 | if (mode->clock > max_clock) | |
1058 | return false; | |
1059 | } | |
1060 | ||
1061 | return true; | |
1062 | } | |
1063 | ||
1064 | /* | |
1065 | * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will | |
1066 | * need to account for them. | |
1067 | */ | |
1068 | static int drm_gtf_modes_for_range(struct drm_connector *connector, | |
1069 | struct detailed_timing *timing) | |
1070 | { | |
1071 | int i, modes = 0; | |
1072 | struct drm_display_mode *newmode; | |
1073 | struct drm_device *dev = connector->dev; | |
1074 | ||
1075 | for (i = 0; i < drm_num_dmt_modes; i++) { | |
1076 | if (mode_in_range(drm_dmt_modes + i, timing)) { | |
1077 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); | |
1078 | if (newmode) { | |
1079 | drm_mode_probed_add(connector, newmode); | |
1080 | modes++; | |
1081 | } | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | return modes; | |
1086 | } | |
1087 | ||
9340d8cf AJ |
1088 | static int drm_cvt_modes(struct drm_connector *connector, |
1089 | struct detailed_timing *timing) | |
1090 | { | |
1091 | int i, j, modes = 0; | |
1092 | struct drm_display_mode *newmode; | |
1093 | struct drm_device *dev = connector->dev; | |
1094 | struct cvt_timing *cvt; | |
1095 | const int rates[] = { 60, 85, 75, 60, 50 }; | |
69da3015 | 1096 | const u8 empty[3] = { 0, 0, 0 }; |
9340d8cf AJ |
1097 | |
1098 | for (i = 0; i < 4; i++) { | |
29ebdf92 | 1099 | int uninitialized_var(width), height; |
9340d8cf AJ |
1100 | cvt = &(timing->data.other_data.data.cvt[i]); |
1101 | ||
69da3015 AJ |
1102 | if (!memcmp(cvt->code, empty, 3)) |
1103 | continue; | |
1104 | ||
8e10ee9a AJ |
1105 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
1106 | switch (cvt->code[1] & 0x0c) { | |
9340d8cf AJ |
1107 | case 0x00: |
1108 | width = height * 4 / 3; | |
1109 | break; | |
8e10ee9a | 1110 | case 0x04: |
9340d8cf AJ |
1111 | width = height * 16 / 9; |
1112 | break; | |
8e10ee9a | 1113 | case 0x08: |
9340d8cf AJ |
1114 | width = height * 16 / 10; |
1115 | break; | |
8e10ee9a | 1116 | case 0x0c: |
9340d8cf AJ |
1117 | width = height * 15 / 9; |
1118 | break; | |
1119 | } | |
1120 | ||
1121 | for (j = 1; j < 5; j++) { | |
1122 | if (cvt->code[2] & (1 << j)) { | |
1123 | newmode = drm_cvt_mode(dev, width, height, | |
1124 | rates[j], j == 0, | |
1125 | false, false); | |
1126 | if (newmode) { | |
1127 | drm_mode_probed_add(connector, newmode); | |
1128 | modes++; | |
1129 | } | |
1130 | } | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | return modes; | |
1135 | } | |
1136 | ||
2255be14 AJ |
1137 | static const struct { |
1138 | short w; | |
1139 | short h; | |
1140 | short r; | |
1141 | short rb; | |
1142 | } est3_modes[] = { | |
1143 | /* byte 6 */ | |
1144 | { 640, 350, 85, 0 }, | |
1145 | { 640, 400, 85, 0 }, | |
1146 | { 720, 400, 85, 0 }, | |
1147 | { 640, 480, 85, 0 }, | |
1148 | { 848, 480, 60, 0 }, | |
1149 | { 800, 600, 85, 0 }, | |
1150 | { 1024, 768, 85, 0 }, | |
1151 | { 1152, 864, 75, 0 }, | |
1152 | /* byte 7 */ | |
1153 | { 1280, 768, 60, 1 }, | |
1154 | { 1280, 768, 60, 0 }, | |
1155 | { 1280, 768, 75, 0 }, | |
1156 | { 1280, 768, 85, 0 }, | |
1157 | { 1280, 960, 60, 0 }, | |
1158 | { 1280, 960, 85, 0 }, | |
1159 | { 1280, 1024, 60, 0 }, | |
1160 | { 1280, 1024, 85, 0 }, | |
1161 | /* byte 8 */ | |
1162 | { 1360, 768, 60, 0 }, | |
1163 | { 1440, 900, 60, 1 }, | |
1164 | { 1440, 900, 60, 0 }, | |
1165 | { 1440, 900, 75, 0 }, | |
1166 | { 1440, 900, 85, 0 }, | |
1167 | { 1400, 1050, 60, 1 }, | |
1168 | { 1400, 1050, 60, 0 }, | |
1169 | { 1400, 1050, 75, 0 }, | |
1170 | /* byte 9 */ | |
1171 | { 1400, 1050, 85, 0 }, | |
1172 | { 1680, 1050, 60, 1 }, | |
1173 | { 1680, 1050, 60, 0 }, | |
1174 | { 1680, 1050, 75, 0 }, | |
1175 | { 1680, 1050, 85, 0 }, | |
1176 | { 1600, 1200, 60, 0 }, | |
1177 | { 1600, 1200, 65, 0 }, | |
1178 | { 1600, 1200, 70, 0 }, | |
1179 | /* byte 10 */ | |
1180 | { 1600, 1200, 75, 0 }, | |
1181 | { 1600, 1200, 85, 0 }, | |
1182 | { 1792, 1344, 60, 0 }, | |
1183 | { 1792, 1344, 85, 0 }, | |
1184 | { 1856, 1392, 60, 0 }, | |
1185 | { 1856, 1392, 75, 0 }, | |
1186 | { 1920, 1200, 60, 1 }, | |
1187 | { 1920, 1200, 60, 0 }, | |
1188 | /* byte 11 */ | |
1189 | { 1920, 1200, 75, 0 }, | |
1190 | { 1920, 1200, 85, 0 }, | |
1191 | { 1920, 1440, 60, 0 }, | |
1192 | { 1920, 1440, 75, 0 }, | |
1193 | }; | |
1194 | static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]); | |
1195 | ||
1196 | static int | |
1197 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | |
1198 | { | |
1199 | int i, j, m, modes = 0; | |
1200 | struct drm_display_mode *mode; | |
1201 | u8 *est = ((u8 *)timing) + 5; | |
1202 | ||
1203 | for (i = 0; i < 6; i++) { | |
1204 | for (j = 7; j > 0; j--) { | |
1205 | m = (i * 8) + (7 - j); | |
1206 | if (m > num_est3_modes) | |
1207 | break; | |
1208 | if (est[i] & (1 << j)) { | |
1209 | mode = drm_find_dmt(connector->dev, | |
1210 | est3_modes[m].w, | |
1211 | est3_modes[m].h, | |
1212 | est3_modes[m].r | |
1213 | /*, est3_modes[m].rb */); | |
1214 | if (mode) { | |
1215 | drm_mode_probed_add(connector, mode); | |
1216 | modes++; | |
1217 | } | |
1218 | } | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | return modes; | |
1223 | } | |
1224 | ||
9cf00977 AJ |
1225 | static int add_detailed_modes(struct drm_connector *connector, |
1226 | struct detailed_timing *timing, | |
1227 | struct edid *edid, u32 quirks, int preferred) | |
1228 | { | |
1229 | int i, modes = 0; | |
1230 | struct detailed_non_pixel *data = &timing->data.other_data; | |
1231 | int timing_level = standard_timing_level(edid); | |
07a5e632 | 1232 | int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF); |
9cf00977 AJ |
1233 | struct drm_display_mode *newmode; |
1234 | struct drm_device *dev = connector->dev; | |
1235 | ||
1236 | if (timing->pixel_clock) { | |
1237 | newmode = drm_mode_detailed(dev, edid, timing, quirks); | |
1238 | if (!newmode) | |
1239 | return 0; | |
1240 | ||
1241 | if (preferred) | |
1242 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
1243 | ||
1244 | drm_mode_probed_add(connector, newmode); | |
1245 | return 1; | |
1246 | } | |
1247 | ||
1248 | /* other timing types */ | |
1249 | switch (data->type) { | |
1250 | case EDID_DETAIL_MONITOR_RANGE: | |
07a5e632 AJ |
1251 | if (gtf) |
1252 | modes += drm_gtf_modes_for_range(connector, timing); | |
9cf00977 AJ |
1253 | break; |
1254 | case EDID_DETAIL_STD_MODES: | |
1255 | /* Six modes per detailed section */ | |
1256 | for (i = 0; i < 6; i++) { | |
1257 | struct std_timing *std; | |
1258 | struct drm_display_mode *newmode; | |
1259 | ||
1260 | std = &data->data.timings[i]; | |
1261 | newmode = drm_mode_std(dev, std, edid->revision, | |
1262 | timing_level); | |
1263 | if (newmode) { | |
1264 | drm_mode_probed_add(connector, newmode); | |
1265 | modes++; | |
1266 | } | |
1267 | } | |
1268 | break; | |
9340d8cf AJ |
1269 | case EDID_DETAIL_CVT_3BYTE: |
1270 | modes += drm_cvt_modes(connector, timing); | |
1271 | break; | |
2255be14 AJ |
1272 | case EDID_DETAIL_EST_TIMINGS: |
1273 | modes += drm_est3_modes(connector, timing); | |
1274 | break; | |
9cf00977 AJ |
1275 | default: |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | return modes; | |
1280 | } | |
1281 | ||
f453ba04 | 1282 | /** |
9cf00977 | 1283 | * add_detailed_info - get detailed mode info from EDID data |
f453ba04 DA |
1284 | * @connector: attached connector |
1285 | * @edid: EDID block to scan | |
1286 | * @quirks: quirks to apply | |
1287 | * | |
1288 | * Some of the detailed timing sections may contain mode information. Grab | |
1289 | * it and add it to the list. | |
1290 | */ | |
1291 | static int add_detailed_info(struct drm_connector *connector, | |
1292 | struct edid *edid, u32 quirks) | |
1293 | { | |
9cf00977 | 1294 | int i, modes = 0; |
f453ba04 DA |
1295 | |
1296 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { | |
1297 | struct detailed_timing *timing = &edid->detailed_timings[i]; | |
9cf00977 | 1298 | int preferred = (i == 0) && (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); |
f453ba04 | 1299 | |
9cf00977 AJ |
1300 | /* In 1.0, only timings are allowed */ |
1301 | if (!timing->pixel_clock && edid->version == 1 && | |
1302 | edid->revision == 0) | |
1303 | continue; | |
f453ba04 | 1304 | |
9cf00977 AJ |
1305 | modes += add_detailed_modes(connector, timing, edid, quirks, |
1306 | preferred); | |
f453ba04 DA |
1307 | } |
1308 | ||
1309 | return modes; | |
1310 | } | |
9cf00977 | 1311 | |
882f0219 ZY |
1312 | /** |
1313 | * add_detailed_mode_eedid - get detailed mode info from addtional timing | |
1314 | * EDID block | |
1315 | * @connector: attached connector | |
1316 | * @edid: EDID block to scan(It is only to get addtional timing EDID block) | |
1317 | * @quirks: quirks to apply | |
1318 | * | |
1319 | * Some of the detailed timing sections may contain mode information. Grab | |
1320 | * it and add it to the list. | |
1321 | */ | |
1322 | static int add_detailed_info_eedid(struct drm_connector *connector, | |
1323 | struct edid *edid, u32 quirks) | |
1324 | { | |
9cf00977 | 1325 | int i, modes = 0; |
882f0219 ZY |
1326 | char *edid_ext = NULL; |
1327 | struct detailed_timing *timing; | |
882f0219 ZY |
1328 | int start_offset, end_offset; |
1329 | int timing_level; | |
1330 | ||
1331 | if (edid->version == 1 && edid->revision < 3) { | |
1332 | /* If the EDID version is less than 1.3, there is no | |
1333 | * extension EDID. | |
1334 | */ | |
1335 | return 0; | |
1336 | } | |
1337 | if (!edid->extensions) { | |
1338 | /* if there is no extension EDID, it is unnecessary to | |
1339 | * parse the E-EDID to get detailed info | |
1340 | */ | |
1341 | return 0; | |
1342 | } | |
1343 | ||
882f0219 | 1344 | /* Find CEA extension */ |
7466f4cc | 1345 | for (i = 0; i < edid->extensions; i++) { |
882f0219 ZY |
1346 | edid_ext = (char *)edid + EDID_LENGTH * (i + 1); |
1347 | /* This block is CEA extension */ | |
1348 | if (edid_ext[0] == 0x02) | |
1349 | break; | |
1350 | } | |
1351 | ||
7466f4cc | 1352 | if (i == edid->extensions) { |
882f0219 ZY |
1353 | /* if there is no additional timing EDID block, return */ |
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | /* Get the start offset of detailed timing block */ | |
1358 | start_offset = edid_ext[2]; | |
1359 | if (start_offset == 0) { | |
1360 | /* If the start_offset is zero, it means that neither detailed | |
1361 | * info nor data block exist. In such case it is also | |
1362 | * unnecessary to parse the detailed timing info. | |
1363 | */ | |
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | timing_level = standard_timing_level(edid); | |
1368 | end_offset = EDID_LENGTH; | |
1369 | end_offset -= sizeof(struct detailed_timing); | |
1370 | for (i = start_offset; i < end_offset; | |
1371 | i += sizeof(struct detailed_timing)) { | |
1372 | timing = (struct detailed_timing *)(edid_ext + i); | |
9cf00977 | 1373 | modes += add_detailed_modes(connector, timing, edid, quirks, 0); |
882f0219 ZY |
1374 | } |
1375 | ||
1376 | return modes; | |
1377 | } | |
f453ba04 | 1378 | |
f23c20c8 ML |
1379 | #define HDMI_IDENTIFIER 0x000C03 |
1380 | #define VENDOR_BLOCK 0x03 | |
1381 | /** | |
1382 | * drm_detect_hdmi_monitor - detect whether monitor is hdmi. | |
1383 | * @edid: monitor EDID information | |
1384 | * | |
1385 | * Parse the CEA extension according to CEA-861-B. | |
1386 | * Return true if HDMI, false if not or unknown. | |
1387 | */ | |
1388 | bool drm_detect_hdmi_monitor(struct edid *edid) | |
1389 | { | |
1390 | char *edid_ext = NULL; | |
7466f4cc | 1391 | int i, hdmi_id; |
f23c20c8 ML |
1392 | int start_offset, end_offset; |
1393 | bool is_hdmi = false; | |
1394 | ||
1395 | /* No EDID or EDID extensions */ | |
1396 | if (edid == NULL || edid->extensions == 0) | |
1397 | goto end; | |
1398 | ||
f23c20c8 | 1399 | /* Find CEA extension */ |
7466f4cc | 1400 | for (i = 0; i < edid->extensions; i++) { |
f23c20c8 ML |
1401 | edid_ext = (char *)edid + EDID_LENGTH * (i + 1); |
1402 | /* This block is CEA extension */ | |
1403 | if (edid_ext[0] == 0x02) | |
1404 | break; | |
1405 | } | |
1406 | ||
7466f4cc | 1407 | if (i == edid->extensions) |
f23c20c8 ML |
1408 | goto end; |
1409 | ||
1410 | /* Data block offset in CEA extension block */ | |
1411 | start_offset = 4; | |
1412 | end_offset = edid_ext[2]; | |
1413 | ||
1414 | /* | |
1415 | * Because HDMI identifier is in Vendor Specific Block, | |
1416 | * search it from all data blocks of CEA extension. | |
1417 | */ | |
1418 | for (i = start_offset; i < end_offset; | |
1419 | /* Increased by data block len */ | |
1420 | i += ((edid_ext[i] & 0x1f) + 1)) { | |
1421 | /* Find vendor specific block */ | |
1422 | if ((edid_ext[i] >> 5) == VENDOR_BLOCK) { | |
1423 | hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) | | |
1424 | edid_ext[i + 3] << 16; | |
1425 | /* Find HDMI identifier */ | |
1426 | if (hdmi_id == HDMI_IDENTIFIER) | |
1427 | is_hdmi = true; | |
1428 | break; | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | end: | |
1433 | return is_hdmi; | |
1434 | } | |
1435 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
1436 | ||
f453ba04 DA |
1437 | /** |
1438 | * drm_add_edid_modes - add modes from EDID data, if available | |
1439 | * @connector: connector we're probing | |
1440 | * @edid: edid data | |
1441 | * | |
1442 | * Add the specified modes to the connector's mode list. | |
1443 | * | |
1444 | * Return number of modes added or 0 if we couldn't find any. | |
1445 | */ | |
1446 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
1447 | { | |
1448 | int num_modes = 0; | |
1449 | u32 quirks; | |
1450 | ||
1451 | if (edid == NULL) { | |
1452 | return 0; | |
1453 | } | |
3c537889 | 1454 | if (!drm_edid_is_valid(edid)) { |
f453ba04 DA |
1455 | dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n", |
1456 | drm_get_connector_name(connector)); | |
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | quirks = edid_get_quirks(edid); | |
1461 | ||
c867df70 AJ |
1462 | /* |
1463 | * EDID spec says modes should be preferred in this order: | |
1464 | * - preferred detailed mode | |
1465 | * - other detailed modes from base block | |
1466 | * - detailed modes from extension blocks | |
1467 | * - CVT 3-byte code modes | |
1468 | * - standard timing codes | |
1469 | * - established timing codes | |
1470 | * - modes inferred from GTF or CVT range information | |
1471 | * | |
1472 | * We don't quite implement this yet, but we're close. | |
1473 | * | |
1474 | * XXX order for additional mode types in extension blocks? | |
1475 | */ | |
f453ba04 | 1476 | num_modes += add_detailed_info(connector, edid, quirks); |
882f0219 | 1477 | num_modes += add_detailed_info_eedid(connector, edid, quirks); |
c867df70 AJ |
1478 | num_modes += add_standard_modes(connector, edid); |
1479 | num_modes += add_established_modes(connector, edid); | |
f453ba04 DA |
1480 | |
1481 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
1482 | edid_fixup_preferred(connector, quirks); | |
1483 | ||
0454beab MD |
1484 | connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0; |
1485 | connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0; | |
1486 | connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0; | |
1487 | connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0; | |
1488 | connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0; | |
1489 | connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5; | |
1490 | connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0; | |
f453ba04 DA |
1491 | connector->display_info.width_mm = edid->width_cm * 10; |
1492 | connector->display_info.height_mm = edid->height_cm * 10; | |
1493 | connector->display_info.gamma = edid->gamma; | |
0454beab MD |
1494 | connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0; |
1495 | connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0; | |
1496 | connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3; | |
1497 | connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0; | |
1498 | connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0; | |
1499 | connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0; | |
f453ba04 DA |
1500 | connector->display_info.gamma = edid->gamma; |
1501 | ||
1502 | return num_modes; | |
1503 | } | |
1504 | EXPORT_SYMBOL(drm_add_edid_modes); | |
f0fda0a4 ZY |
1505 | |
1506 | /** | |
1507 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
1508 | * @connector: connector we're probing | |
1509 | * @hdisplay: the horizontal display limit | |
1510 | * @vdisplay: the vertical display limit | |
1511 | * | |
1512 | * Add the specified modes to the connector's mode list. Only when the | |
1513 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
1514 | * | |
1515 | * Return number of modes added or 0 if we couldn't find any. | |
1516 | */ | |
1517 | int drm_add_modes_noedid(struct drm_connector *connector, | |
1518 | int hdisplay, int vdisplay) | |
1519 | { | |
1520 | int i, count, num_modes = 0; | |
1521 | struct drm_display_mode *mode, *ptr; | |
1522 | struct drm_device *dev = connector->dev; | |
1523 | ||
1524 | count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); | |
1525 | if (hdisplay < 0) | |
1526 | hdisplay = 0; | |
1527 | if (vdisplay < 0) | |
1528 | vdisplay = 0; | |
1529 | ||
1530 | for (i = 0; i < count; i++) { | |
1531 | ptr = &drm_dmt_modes[i]; | |
1532 | if (hdisplay && vdisplay) { | |
1533 | /* | |
1534 | * Only when two are valid, they will be used to check | |
1535 | * whether the mode should be added to the mode list of | |
1536 | * the connector. | |
1537 | */ | |
1538 | if (ptr->hdisplay > hdisplay || | |
1539 | ptr->vdisplay > vdisplay) | |
1540 | continue; | |
1541 | } | |
f985dedb AJ |
1542 | if (drm_mode_vrefresh(ptr) > 61) |
1543 | continue; | |
f0fda0a4 ZY |
1544 | mode = drm_mode_duplicate(dev, ptr); |
1545 | if (mode) { | |
1546 | drm_mode_probed_add(connector, mode); | |
1547 | num_modes++; | |
1548 | } | |
1549 | } | |
1550 | return num_modes; | |
1551 | } | |
1552 | EXPORT_SYMBOL(drm_add_modes_noedid); |