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c8466a91 JS |
1 | /* drivers/gpu/drm/exynos5433_drm_decon.c |
2 | * | |
3 | * Copyright (C) 2015 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Hyungwon Hwang <human.hwang@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundationr | |
11 | */ | |
12 | ||
13 | #include <linux/platform_device.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/component.h> | |
b8182832 | 16 | #include <linux/of_device.h> |
c8466a91 JS |
17 | #include <linux/of_gpio.h> |
18 | #include <linux/pm_runtime.h> | |
19 | ||
20 | #include <video/exynos5433_decon.h> | |
21 | ||
22 | #include "exynos_drm_drv.h" | |
23 | #include "exynos_drm_crtc.h" | |
0488f50e | 24 | #include "exynos_drm_fb.h" |
c8466a91 JS |
25 | #include "exynos_drm_plane.h" |
26 | #include "exynos_drm_iommu.h" | |
27 | ||
28 | #define WINDOWS_NR 3 | |
29 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 | |
30 | ||
9ac26de8 ID |
31 | #define IFTYPE_I80 (1 << 0) |
32 | #define I80_HW_TRG (1 << 1) | |
33 | #define IFTYPE_HDMI (1 << 2) | |
34 | ||
4f54f21c AH |
35 | static const char * const decon_clks_name[] = { |
36 | "pclk", | |
37 | "aclk_decon", | |
38 | "aclk_smmu_decon0x", | |
39 | "aclk_xiu_decon0x", | |
40 | "pclk_smmu_decon0x", | |
41 | "sclk_decon_vclk", | |
42 | "sclk_decon_eclk", | |
43 | }; | |
44 | ||
7b6bb6ed AH |
45 | enum decon_flag_bits { |
46 | BIT_CLKS_ENABLED, | |
47 | BIT_IRQS_ENABLED, | |
48 | BIT_WIN_UPDATED, | |
49 | BIT_SUSPENDED | |
50 | }; | |
51 | ||
c8466a91 JS |
52 | struct decon_context { |
53 | struct device *dev; | |
54 | struct drm_device *drm_dev; | |
55 | struct exynos_drm_crtc *crtc; | |
56 | struct exynos_drm_plane planes[WINDOWS_NR]; | |
fd2d2fc2 | 57 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
c8466a91 | 58 | void __iomem *addr; |
4f54f21c | 59 | struct clk *clks[ARRAY_SIZE(decon_clks_name)]; |
c8466a91 | 60 | int pipe; |
7b6bb6ed | 61 | unsigned long flags; |
9ac26de8 | 62 | unsigned long out_type; |
b8182832 | 63 | int first_win; |
c8466a91 JS |
64 | }; |
65 | ||
fbbb1e1a MS |
66 | static const uint32_t decon_formats[] = { |
67 | DRM_FORMAT_XRGB1555, | |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_ARGB8888, | |
71 | }; | |
72 | ||
fd2d2fc2 MS |
73 | static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { |
74 | DRM_PLANE_TYPE_PRIMARY, | |
75 | DRM_PLANE_TYPE_OVERLAY, | |
76 | DRM_PLANE_TYPE_CURSOR, | |
77 | }; | |
78 | ||
b2192073 AH |
79 | static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, |
80 | u32 val) | |
81 | { | |
82 | val = (val & mask) | (readl(ctx->addr + reg) & ~mask); | |
83 | writel(val, ctx->addr + reg); | |
84 | } | |
85 | ||
c8466a91 JS |
86 | static int decon_enable_vblank(struct exynos_drm_crtc *crtc) |
87 | { | |
88 | struct decon_context *ctx = crtc->ctx; | |
89 | u32 val; | |
90 | ||
7b6bb6ed | 91 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
92 | return -EPERM; |
93 | ||
f3fb3d82 | 94 | if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) { |
c8466a91 | 95 | val = VIDINTCON0_INTEN; |
9ac26de8 | 96 | if (ctx->out_type & IFTYPE_I80) |
c8466a91 JS |
97 | val |= VIDINTCON0_FRAMEDONE; |
98 | else | |
99 | val |= VIDINTCON0_INTFRMEN; | |
100 | ||
101 | writel(val, ctx->addr + DECON_VIDINTCON0); | |
102 | } | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | static void decon_disable_vblank(struct exynos_drm_crtc *crtc) | |
108 | { | |
109 | struct decon_context *ctx = crtc->ctx; | |
110 | ||
7b6bb6ed | 111 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
112 | return; |
113 | ||
7b6bb6ed | 114 | if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) |
c8466a91 JS |
115 | writel(0, ctx->addr + DECON_VIDINTCON0); |
116 | } | |
117 | ||
118 | static void decon_setup_trigger(struct decon_context *ctx) | |
119 | { | |
9ac26de8 | 120 | u32 val = !(ctx->out_type & I80_HW_TRG) |
b8182832 AH |
121 | ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | |
122 | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN | |
123 | : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | | |
b5bf0f1e | 124 | TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN; |
c8466a91 JS |
125 | writel(val, ctx->addr + DECON_TRIGCON); |
126 | } | |
127 | ||
128 | static void decon_commit(struct exynos_drm_crtc *crtc) | |
129 | { | |
130 | struct decon_context *ctx = crtc->ctx; | |
85de275a | 131 | struct drm_display_mode *m = &crtc->base.mode; |
c8466a91 JS |
132 | u32 val; |
133 | ||
7b6bb6ed | 134 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
135 | return; |
136 | ||
9ac26de8 | 137 | if (ctx->out_type & IFTYPE_HDMI) { |
b8182832 AH |
138 | m->crtc_hsync_start = m->crtc_hdisplay + 10; |
139 | m->crtc_hsync_end = m->crtc_htotal - 92; | |
140 | m->crtc_vsync_start = m->crtc_vdisplay + 1; | |
141 | m->crtc_vsync_end = m->crtc_vsync_start + 1; | |
142 | } | |
143 | ||
144 | decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0); | |
145 | ||
c8466a91 JS |
146 | /* enable clock gate */ |
147 | val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; | |
148 | writel(val, ctx->addr + DECON_CMU); | |
149 | ||
dd65a686 AH |
150 | if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)) |
151 | decon_setup_trigger(ctx); | |
152 | ||
c8466a91 JS |
153 | /* lcd on and use command if */ |
154 | val = VIDOUT_LCD_ON; | |
9ac26de8 | 155 | if (ctx->out_type & IFTYPE_I80) { |
c8466a91 | 156 | val |= VIDOUT_COMMAND_IF; |
9ac26de8 | 157 | } else { |
c8466a91 | 158 | val |= VIDOUT_RGB_IF; |
9ac26de8 ID |
159 | } |
160 | ||
c8466a91 JS |
161 | writel(val, ctx->addr + DECON_VIDOUTCON0); |
162 | ||
85de275a AH |
163 | val = VIDTCON2_LINEVAL(m->vdisplay - 1) | |
164 | VIDTCON2_HOZVAL(m->hdisplay - 1); | |
c8466a91 JS |
165 | writel(val, ctx->addr + DECON_VIDTCON2); |
166 | ||
9ac26de8 | 167 | if (!(ctx->out_type & IFTYPE_I80)) { |
c8466a91 | 168 | val = VIDTCON00_VBPD_F( |
85de275a | 169 | m->crtc_vtotal - m->crtc_vsync_end - 1) | |
c8466a91 | 170 | VIDTCON00_VFPD_F( |
85de275a | 171 | m->crtc_vsync_start - m->crtc_vdisplay - 1); |
c8466a91 JS |
172 | writel(val, ctx->addr + DECON_VIDTCON00); |
173 | ||
174 | val = VIDTCON01_VSPW_F( | |
85de275a | 175 | m->crtc_vsync_end - m->crtc_vsync_start - 1); |
c8466a91 JS |
176 | writel(val, ctx->addr + DECON_VIDTCON01); |
177 | ||
178 | val = VIDTCON10_HBPD_F( | |
85de275a | 179 | m->crtc_htotal - m->crtc_hsync_end - 1) | |
c8466a91 | 180 | VIDTCON10_HFPD_F( |
85de275a | 181 | m->crtc_hsync_start - m->crtc_hdisplay - 1); |
c8466a91 JS |
182 | writel(val, ctx->addr + DECON_VIDTCON10); |
183 | ||
184 | val = VIDTCON11_HSPW_F( | |
85de275a | 185 | m->crtc_hsync_end - m->crtc_hsync_start - 1); |
c8466a91 JS |
186 | writel(val, ctx->addr + DECON_VIDTCON11); |
187 | } | |
188 | ||
c8466a91 | 189 | /* enable output and display signal */ |
b8182832 | 190 | decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); |
92ead494 AH |
191 | |
192 | decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); | |
c8466a91 JS |
193 | } |
194 | ||
2eeb2e5e GP |
195 | static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, |
196 | struct drm_framebuffer *fb) | |
c8466a91 | 197 | { |
c8466a91 JS |
198 | unsigned long val; |
199 | ||
200 | val = readl(ctx->addr + DECON_WINCONx(win)); | |
201 | val &= ~WINCONx_BPPMODE_MASK; | |
202 | ||
2eeb2e5e | 203 | switch (fb->pixel_format) { |
c8466a91 JS |
204 | case DRM_FORMAT_XRGB1555: |
205 | val |= WINCONx_BPPMODE_16BPP_I1555; | |
206 | val |= WINCONx_HAWSWP_F; | |
207 | val |= WINCONx_BURSTLEN_16WORD; | |
208 | break; | |
209 | case DRM_FORMAT_RGB565: | |
210 | val |= WINCONx_BPPMODE_16BPP_565; | |
211 | val |= WINCONx_HAWSWP_F; | |
212 | val |= WINCONx_BURSTLEN_16WORD; | |
213 | break; | |
214 | case DRM_FORMAT_XRGB8888: | |
215 | val |= WINCONx_BPPMODE_24BPP_888; | |
216 | val |= WINCONx_WSWP_F; | |
217 | val |= WINCONx_BURSTLEN_16WORD; | |
218 | break; | |
219 | case DRM_FORMAT_ARGB8888: | |
220 | val |= WINCONx_BPPMODE_32BPP_A8888; | |
221 | val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; | |
222 | val |= WINCONx_BURSTLEN_16WORD; | |
223 | break; | |
224 | default: | |
225 | DRM_ERROR("Proper pixel format is not set\n"); | |
226 | return; | |
227 | } | |
228 | ||
2eeb2e5e | 229 | DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel); |
c8466a91 JS |
230 | |
231 | /* | |
232 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
233 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
234 | * switching which is based on plane size is not recommended as | |
235 | * plane size varies a lot towards the end of the screen and rapid | |
236 | * movement causes unstable DMA which results into iommu crash/tear. | |
237 | */ | |
238 | ||
2eeb2e5e | 239 | if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
c8466a91 JS |
240 | val &= ~WINCONx_BURSTLEN_MASK; |
241 | val |= WINCONx_BURSTLEN_8WORD; | |
242 | } | |
243 | ||
244 | writel(val, ctx->addr + DECON_WINCONx(win)); | |
245 | } | |
246 | ||
247 | static void decon_shadow_protect_win(struct decon_context *ctx, int win, | |
248 | bool protect) | |
249 | { | |
b2192073 AH |
250 | decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win), |
251 | protect ? ~0 : 0); | |
c8466a91 JS |
252 | } |
253 | ||
d29c2c14 | 254 | static void decon_atomic_begin(struct exynos_drm_crtc *crtc) |
cc5a7b35 HH |
255 | { |
256 | struct decon_context *ctx = crtc->ctx; | |
d29c2c14 | 257 | int i; |
cc5a7b35 | 258 | |
7b6bb6ed | 259 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
cc5a7b35 HH |
260 | return; |
261 | ||
d29c2c14 MS |
262 | for (i = ctx->first_win; i < WINDOWS_NR; i++) |
263 | decon_shadow_protect_win(ctx, i, true); | |
cc5a7b35 HH |
264 | } |
265 | ||
b8182832 AH |
266 | #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) |
267 | #define COORDINATE_X(x) BIT_VAL((x), 23, 12) | |
268 | #define COORDINATE_Y(x) BIT_VAL((x), 11, 0) | |
269 | ||
1e1d1393 GP |
270 | static void decon_update_plane(struct exynos_drm_crtc *crtc, |
271 | struct exynos_drm_plane *plane) | |
c8466a91 | 272 | { |
0114f404 MS |
273 | struct exynos_drm_plane_state *state = |
274 | to_exynos_plane_state(plane->base.state); | |
c8466a91 | 275 | struct decon_context *ctx = crtc->ctx; |
0114f404 | 276 | struct drm_framebuffer *fb = state->base.fb; |
40bdfb0a | 277 | unsigned int win = plane->index; |
0488f50e MS |
278 | unsigned int bpp = fb->bits_per_pixel >> 3; |
279 | unsigned int pitch = fb->pitches[0]; | |
280 | dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); | |
c8466a91 JS |
281 | u32 val; |
282 | ||
7b6bb6ed | 283 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
284 | return; |
285 | ||
0114f404 | 286 | val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); |
c8466a91 JS |
287 | writel(val, ctx->addr + DECON_VIDOSDxA(win)); |
288 | ||
0114f404 MS |
289 | val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | |
290 | COORDINATE_Y(state->crtc.y + state->crtc.h - 1); | |
c8466a91 JS |
291 | writel(val, ctx->addr + DECON_VIDOSDxB(win)); |
292 | ||
293 | val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | | |
294 | VIDOSD_Wx_ALPHA_B_F(0x0); | |
295 | writel(val, ctx->addr + DECON_VIDOSDxC(win)); | |
296 | ||
297 | val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | | |
298 | VIDOSD_Wx_ALPHA_B_F(0x0); | |
299 | writel(val, ctx->addr + DECON_VIDOSDxD(win)); | |
300 | ||
0488f50e | 301 | writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); |
c8466a91 | 302 | |
0114f404 | 303 | val = dma_addr + pitch * state->src.h; |
c8466a91 JS |
304 | writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); |
305 | ||
9ac26de8 | 306 | if (!(ctx->out_type & IFTYPE_HDMI)) |
0114f404 MS |
307 | val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14) |
308 | | BIT_VAL(state->crtc.w * bpp, 13, 0); | |
b8182832 | 309 | else |
0114f404 MS |
310 | val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15) |
311 | | BIT_VAL(state->crtc.w * bpp, 14, 0); | |
c8466a91 JS |
312 | writel(val, ctx->addr + DECON_VIDW0xADD2(win)); |
313 | ||
0488f50e | 314 | decon_win_set_pixfmt(ctx, win, fb); |
c8466a91 JS |
315 | |
316 | /* window enable */ | |
b2192073 | 317 | decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); |
c8466a91 JS |
318 | } |
319 | ||
1e1d1393 GP |
320 | static void decon_disable_plane(struct exynos_drm_crtc *crtc, |
321 | struct exynos_drm_plane *plane) | |
c8466a91 JS |
322 | { |
323 | struct decon_context *ctx = crtc->ctx; | |
40bdfb0a | 324 | unsigned int win = plane->index; |
c8466a91 | 325 | |
7b6bb6ed | 326 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
327 | return; |
328 | ||
b2192073 | 329 | decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); |
c8466a91 JS |
330 | } |
331 | ||
d29c2c14 | 332 | static void decon_atomic_flush(struct exynos_drm_crtc *crtc) |
cc5a7b35 HH |
333 | { |
334 | struct decon_context *ctx = crtc->ctx; | |
d29c2c14 | 335 | int i; |
cc5a7b35 | 336 | |
7b6bb6ed | 337 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
cc5a7b35 HH |
338 | return; |
339 | ||
d29c2c14 MS |
340 | for (i = ctx->first_win; i < WINDOWS_NR; i++) |
341 | decon_shadow_protect_win(ctx, i, false); | |
cc5a7b35 | 342 | |
92ead494 AH |
343 | /* standalone update */ |
344 | decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); | |
345 | ||
9ac26de8 | 346 | if (ctx->out_type & IFTYPE_I80) |
7b6bb6ed | 347 | set_bit(BIT_WIN_UPDATED, &ctx->flags); |
cc5a7b35 HH |
348 | } |
349 | ||
c8466a91 JS |
350 | static void decon_swreset(struct decon_context *ctx) |
351 | { | |
352 | unsigned int tries; | |
353 | ||
354 | writel(0, ctx->addr + DECON_VIDCON0); | |
355 | for (tries = 2000; tries; --tries) { | |
356 | if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS) | |
357 | break; | |
358 | udelay(10); | |
359 | } | |
360 | ||
361 | WARN(tries == 0, "failed to disable DECON\n"); | |
362 | ||
363 | writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); | |
364 | for (tries = 2000; tries; --tries) { | |
365 | if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) | |
366 | break; | |
367 | udelay(10); | |
368 | } | |
369 | ||
370 | WARN(tries == 0, "failed to software reset DECON\n"); | |
b8182832 | 371 | |
9ac26de8 | 372 | if (!(ctx->out_type & IFTYPE_HDMI)) |
b8182832 AH |
373 | return; |
374 | ||
375 | writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); | |
376 | decon_set_bits(ctx, DECON_CMU, | |
377 | CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); | |
378 | writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); | |
379 | writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, | |
380 | ctx->addr + DECON_CRCCTRL); | |
c8466a91 JS |
381 | } |
382 | ||
383 | static void decon_enable(struct exynos_drm_crtc *crtc) | |
384 | { | |
385 | struct decon_context *ctx = crtc->ctx; | |
c8466a91 | 386 | |
7b6bb6ed | 387 | if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
388 | return; |
389 | ||
c8466a91 JS |
390 | pm_runtime_get_sync(ctx->dev); |
391 | ||
c60230eb AH |
392 | exynos_drm_pipe_clk_enable(crtc, true); |
393 | ||
7b6bb6ed | 394 | set_bit(BIT_CLKS_ENABLED, &ctx->flags); |
c8466a91 | 395 | |
e87b3c62 AH |
396 | decon_swreset(ctx); |
397 | ||
c8466a91 | 398 | /* if vblank was enabled status, enable it again. */ |
7b6bb6ed | 399 | if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) |
c8466a91 JS |
400 | decon_enable_vblank(ctx->crtc); |
401 | ||
402 | decon_commit(ctx->crtc); | |
c8466a91 JS |
403 | } |
404 | ||
405 | static void decon_disable(struct exynos_drm_crtc *crtc) | |
406 | { | |
407 | struct decon_context *ctx = crtc->ctx; | |
408 | int i; | |
409 | ||
7b6bb6ed | 410 | if (test_bit(BIT_SUSPENDED, &ctx->flags)) |
c8466a91 JS |
411 | return; |
412 | ||
413 | /* | |
414 | * We need to make sure that all windows are disabled before we | |
415 | * suspend that connector. Otherwise we might try to scan from | |
416 | * a destroyed buffer later. | |
417 | */ | |
b8182832 | 418 | for (i = ctx->first_win; i < WINDOWS_NR; i++) |
1e1d1393 | 419 | decon_disable_plane(crtc, &ctx->planes[i]); |
c8466a91 JS |
420 | |
421 | decon_swreset(ctx); | |
422 | ||
7b6bb6ed | 423 | clear_bit(BIT_CLKS_ENABLED, &ctx->flags); |
c8466a91 | 424 | |
c60230eb AH |
425 | exynos_drm_pipe_clk_enable(crtc, false); |
426 | ||
c8466a91 JS |
427 | pm_runtime_put_sync(ctx->dev); |
428 | ||
7b6bb6ed | 429 | set_bit(BIT_SUSPENDED, &ctx->flags); |
c8466a91 JS |
430 | } |
431 | ||
9844d6eb | 432 | static void decon_te_irq_handler(struct exynos_drm_crtc *crtc) |
c8466a91 JS |
433 | { |
434 | struct decon_context *ctx = crtc->ctx; | |
c8466a91 | 435 | |
3f4c8e5c AH |
436 | if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) || |
437 | (ctx->out_type & I80_HW_TRG)) | |
c8466a91 JS |
438 | return; |
439 | ||
7b6bb6ed | 440 | if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) |
b2192073 | 441 | decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); |
c8466a91 JS |
442 | } |
443 | ||
444 | static void decon_clear_channels(struct exynos_drm_crtc *crtc) | |
445 | { | |
446 | struct decon_context *ctx = crtc->ctx; | |
447 | int win, i, ret; | |
c8466a91 JS |
448 | |
449 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
450 | ||
451 | for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { | |
452 | ret = clk_prepare_enable(ctx->clks[i]); | |
453 | if (ret < 0) | |
454 | goto err; | |
455 | } | |
456 | ||
457 | for (win = 0; win < WINDOWS_NR; win++) { | |
b2192073 AH |
458 | decon_shadow_protect_win(ctx, win, true); |
459 | decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); | |
460 | decon_shadow_protect_win(ctx, win, false); | |
c8466a91 | 461 | } |
92ead494 AH |
462 | |
463 | decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); | |
464 | ||
c8466a91 JS |
465 | /* TODO: wait for possible vsync */ |
466 | msleep(50); | |
467 | ||
468 | err: | |
469 | while (--i >= 0) | |
470 | clk_disable_unprepare(ctx->clks[i]); | |
471 | } | |
472 | ||
473 | static struct exynos_drm_crtc_ops decon_crtc_ops = { | |
474 | .enable = decon_enable, | |
475 | .disable = decon_disable, | |
c8466a91 JS |
476 | .enable_vblank = decon_enable_vblank, |
477 | .disable_vblank = decon_disable_vblank, | |
cc5a7b35 | 478 | .atomic_begin = decon_atomic_begin, |
9cc7610a GP |
479 | .update_plane = decon_update_plane, |
480 | .disable_plane = decon_disable_plane, | |
cc5a7b35 | 481 | .atomic_flush = decon_atomic_flush, |
c8466a91 | 482 | .te_handler = decon_te_irq_handler, |
c8466a91 JS |
483 | }; |
484 | ||
485 | static int decon_bind(struct device *dev, struct device *master, void *data) | |
486 | { | |
487 | struct decon_context *ctx = dev_get_drvdata(dev); | |
488 | struct drm_device *drm_dev = data; | |
489 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
490 | struct exynos_drm_plane *exynos_plane; | |
b8182832 | 491 | enum exynos_drm_output_type out_type; |
b8182832 | 492 | unsigned int win; |
c8466a91 JS |
493 | int ret; |
494 | ||
495 | ctx->drm_dev = drm_dev; | |
496 | ctx->pipe = priv->pipe++; | |
497 | ||
b8182832 AH |
498 | for (win = ctx->first_win; win < WINDOWS_NR; win++) { |
499 | int tmp = (win == ctx->first_win) ? 0 : win; | |
500 | ||
fd2d2fc2 MS |
501 | ctx->configs[win].pixel_formats = decon_formats; |
502 | ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); | |
503 | ctx->configs[win].zpos = win; | |
504 | ctx->configs[win].type = decon_win_types[tmp]; | |
505 | ||
40bdfb0a | 506 | ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, |
fd2d2fc2 | 507 | 1 << ctx->pipe, &ctx->configs[win]); |
c8466a91 JS |
508 | if (ret) |
509 | return ret; | |
510 | } | |
511 | ||
b8182832 | 512 | exynos_plane = &ctx->planes[ctx->first_win]; |
9ac26de8 | 513 | out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI |
b8182832 | 514 | : EXYNOS_DISPLAY_TYPE_LCD; |
c8466a91 | 515 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
b8182832 | 516 | ctx->pipe, out_type, |
c8466a91 JS |
517 | &decon_crtc_ops, ctx); |
518 | if (IS_ERR(ctx->crtc)) { | |
519 | ret = PTR_ERR(ctx->crtc); | |
520 | goto err; | |
521 | } | |
522 | ||
eb7a3fc7 JS |
523 | decon_clear_channels(ctx->crtc); |
524 | ||
525 | ret = drm_iommu_attach_device(drm_dev, dev); | |
c8466a91 JS |
526 | if (ret) |
527 | goto err; | |
528 | ||
529 | return ret; | |
530 | err: | |
531 | priv->pipe--; | |
532 | return ret; | |
533 | } | |
534 | ||
535 | static void decon_unbind(struct device *dev, struct device *master, void *data) | |
536 | { | |
537 | struct decon_context *ctx = dev_get_drvdata(dev); | |
538 | ||
539 | decon_disable(ctx->crtc); | |
540 | ||
541 | /* detach this sub driver from iommu mapping if supported. */ | |
bf56608a | 542 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
c8466a91 JS |
543 | } |
544 | ||
545 | static const struct component_ops decon_component_ops = { | |
546 | .bind = decon_bind, | |
547 | .unbind = decon_unbind, | |
548 | }; | |
549 | ||
b8182832 | 550 | static irqreturn_t decon_irq_handler(int irq, void *dev_id) |
c8466a91 JS |
551 | { |
552 | struct decon_context *ctx = dev_id; | |
553 | u32 val; | |
822f6dfd | 554 | int win; |
c8466a91 | 555 | |
7b6bb6ed | 556 | if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) |
c8466a91 JS |
557 | goto out; |
558 | ||
559 | val = readl(ctx->addr + DECON_VIDINTCON1); | |
b8182832 AH |
560 | val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; |
561 | ||
562 | if (val) { | |
563 | for (win = ctx->first_win; win < WINDOWS_NR ; win++) { | |
822f6dfd GP |
564 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
565 | ||
566 | if (!plane->pending_fb) | |
567 | continue; | |
568 | ||
569 | exynos_drm_crtc_finish_update(ctx->crtc, plane); | |
570 | } | |
c8466a91 JS |
571 | |
572 | /* clear */ | |
b8182832 | 573 | writel(val, ctx->addr + DECON_VIDINTCON1); |
b0bb3d07 | 574 | drm_crtc_handle_vblank(&ctx->crtc->base); |
c8466a91 JS |
575 | } |
576 | ||
577 | out: | |
578 | return IRQ_HANDLED; | |
579 | } | |
580 | ||
ebf3fd40 GP |
581 | #ifdef CONFIG_PM |
582 | static int exynos5433_decon_suspend(struct device *dev) | |
583 | { | |
584 | struct decon_context *ctx = dev_get_drvdata(dev); | |
92c96ff8 | 585 | int i = ARRAY_SIZE(decon_clks_name); |
ebf3fd40 | 586 | |
92c96ff8 | 587 | while (--i >= 0) |
ebf3fd40 GP |
588 | clk_disable_unprepare(ctx->clks[i]); |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
593 | static int exynos5433_decon_resume(struct device *dev) | |
594 | { | |
595 | struct decon_context *ctx = dev_get_drvdata(dev); | |
596 | int i, ret; | |
597 | ||
598 | for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { | |
599 | ret = clk_prepare_enable(ctx->clks[i]); | |
600 | if (ret < 0) | |
601 | goto err; | |
602 | } | |
603 | ||
604 | return 0; | |
605 | ||
606 | err: | |
607 | while (--i >= 0) | |
608 | clk_disable_unprepare(ctx->clks[i]); | |
609 | ||
610 | return ret; | |
611 | } | |
612 | #endif | |
613 | ||
614 | static const struct dev_pm_ops exynos5433_decon_pm_ops = { | |
615 | SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume, | |
616 | NULL) | |
617 | }; | |
618 | ||
b8182832 AH |
619 | static const struct of_device_id exynos5433_decon_driver_dt_match[] = { |
620 | { | |
621 | .compatible = "samsung,exynos5433-decon", | |
9ac26de8 | 622 | .data = (void *)I80_HW_TRG |
b8182832 AH |
623 | }, |
624 | { | |
625 | .compatible = "samsung,exynos5433-decon-tv", | |
9ac26de8 | 626 | .data = (void *)(I80_HW_TRG | IFTYPE_HDMI) |
b8182832 AH |
627 | }, |
628 | {}, | |
629 | }; | |
630 | MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); | |
631 | ||
c8466a91 JS |
632 | static int exynos5433_decon_probe(struct platform_device *pdev) |
633 | { | |
634 | struct device *dev = &pdev->dev; | |
635 | struct decon_context *ctx; | |
636 | struct resource *res; | |
637 | int ret; | |
638 | int i; | |
639 | ||
640 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
641 | if (!ctx) | |
642 | return -ENOMEM; | |
643 | ||
7b6bb6ed | 644 | __set_bit(BIT_SUSPENDED, &ctx->flags); |
c8466a91 | 645 | ctx->dev = dev; |
9ac26de8 | 646 | ctx->out_type = (unsigned long)of_device_get_match_data(dev); |
b8182832 | 647 | |
9ac26de8 | 648 | if (ctx->out_type & IFTYPE_HDMI) { |
b8182832 | 649 | ctx->first_win = 1; |
9ac26de8 | 650 | } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) { |
dd65a686 | 651 | ctx->out_type |= IFTYPE_I80; |
9ac26de8 | 652 | } |
c8466a91 JS |
653 | |
654 | for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { | |
655 | struct clk *clk; | |
656 | ||
657 | clk = devm_clk_get(ctx->dev, decon_clks_name[i]); | |
658 | if (IS_ERR(clk)) | |
659 | return PTR_ERR(clk); | |
660 | ||
661 | ctx->clks[i] = clk; | |
662 | } | |
663 | ||
664 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
665 | if (!res) { | |
666 | dev_err(dev, "cannot find IO resource\n"); | |
667 | return -ENXIO; | |
668 | } | |
669 | ||
670 | ctx->addr = devm_ioremap_resource(dev, res); | |
671 | if (IS_ERR(ctx->addr)) { | |
672 | dev_err(dev, "ioremap failed\n"); | |
673 | return PTR_ERR(ctx->addr); | |
674 | } | |
675 | ||
676 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
9ac26de8 | 677 | (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync"); |
c8466a91 JS |
678 | if (!res) { |
679 | dev_err(dev, "cannot find IRQ resource\n"); | |
680 | return -ENXIO; | |
681 | } | |
682 | ||
b8182832 AH |
683 | ret = devm_request_irq(dev, res->start, decon_irq_handler, 0, |
684 | "drm_decon", ctx); | |
c8466a91 JS |
685 | if (ret < 0) { |
686 | dev_err(dev, "lcd_sys irq request failed\n"); | |
687 | return ret; | |
688 | } | |
689 | ||
690 | platform_set_drvdata(pdev, ctx); | |
691 | ||
692 | pm_runtime_enable(dev); | |
693 | ||
694 | ret = component_add(dev, &decon_component_ops); | |
695 | if (ret) | |
696 | goto err_disable_pm_runtime; | |
697 | ||
698 | return 0; | |
699 | ||
700 | err_disable_pm_runtime: | |
701 | pm_runtime_disable(dev); | |
702 | ||
703 | return ret; | |
704 | } | |
705 | ||
706 | static int exynos5433_decon_remove(struct platform_device *pdev) | |
707 | { | |
708 | pm_runtime_disable(&pdev->dev); | |
709 | ||
710 | component_del(&pdev->dev, &decon_component_ops); | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
c8466a91 JS |
715 | struct platform_driver exynos5433_decon_driver = { |
716 | .probe = exynos5433_decon_probe, | |
717 | .remove = exynos5433_decon_remove, | |
718 | .driver = { | |
719 | .name = "exynos5433-decon", | |
ebf3fd40 | 720 | .pm = &exynos5433_decon_pm_ops, |
c8466a91 JS |
721 | .of_match_table = exynos5433_decon_driver_dt_match, |
722 | }, | |
723 | }; |