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96976c3d AK |
1 | /* drivers/gpu/drm/exynos/exynos7_drm_decon.c |
2 | * | |
3 | * Copyright (C) 2014 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Akshu Agarwal <akshua@gmail.com> | |
6 | * Ajay Kumar <ajaykumar.rs@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | #include <drm/drmP.h> | |
15 | #include <drm/exynos_drm.h> | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/component.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | ||
26 | #include <video/of_display_timing.h> | |
27 | #include <video/of_videomode.h> | |
28 | #include <video/exynos7_decon.h> | |
29 | ||
30 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 31 | #include "exynos_drm_plane.h" |
96976c3d AK |
32 | #include "exynos_drm_drv.h" |
33 | #include "exynos_drm_fbdev.h" | |
34 | #include "exynos_drm_iommu.h" | |
35 | ||
36 | /* | |
37 | * DECON stands for Display and Enhancement controller. | |
38 | */ | |
39 | ||
40 | #define DECON_DEFAULT_FRAMERATE 60 | |
41 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 | |
42 | ||
43 | #define WINDOWS_NR 2 | |
44 | ||
96976c3d AK |
45 | struct decon_context { |
46 | struct device *dev; | |
47 | struct drm_device *drm_dev; | |
48 | struct exynos_drm_crtc *crtc; | |
7ee14cdc | 49 | struct exynos_drm_plane planes[WINDOWS_NR]; |
96976c3d AK |
50 | struct clk *pclk; |
51 | struct clk *aclk; | |
52 | struct clk *eclk; | |
53 | struct clk *vclk; | |
54 | void __iomem *regs; | |
96976c3d AK |
55 | unsigned int default_win; |
56 | unsigned long irq_flags; | |
57 | bool i80_if; | |
58 | bool suspended; | |
59 | int pipe; | |
60 | wait_queue_head_t wait_vsync_queue; | |
61 | atomic_t wait_vsync_event; | |
62 | ||
63 | struct exynos_drm_panel_info panel; | |
64 | struct exynos_drm_display *display; | |
65 | }; | |
66 | ||
67 | static const struct of_device_id decon_driver_dt_match[] = { | |
68 | {.compatible = "samsung,exynos7-decon"}, | |
69 | {}, | |
70 | }; | |
71 | MODULE_DEVICE_TABLE(of, decon_driver_dt_match); | |
72 | ||
73 | static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) | |
74 | { | |
75 | struct decon_context *ctx = crtc->ctx; | |
76 | ||
77 | if (ctx->suspended) | |
78 | return; | |
79 | ||
80 | atomic_set(&ctx->wait_vsync_event, 1); | |
81 | ||
82 | /* | |
83 | * wait for DECON to signal VSYNC interrupt or return after | |
84 | * timeout which is set to 50ms (refresh rate of 20). | |
85 | */ | |
86 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
87 | !atomic_read(&ctx->wait_vsync_event), | |
88 | HZ/20)) | |
89 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
90 | } | |
91 | ||
92 | static void decon_clear_channel(struct decon_context *ctx) | |
93 | { | |
5b1d5bc6 | 94 | unsigned int win, ch_enabled = 0; |
96976c3d AK |
95 | |
96 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
97 | ||
98 | /* Check if any channel is enabled. */ | |
99 | for (win = 0; win < WINDOWS_NR; win++) { | |
100 | u32 val = readl(ctx->regs + WINCON(win)); | |
101 | ||
102 | if (val & WINCONx_ENWIN) { | |
103 | val &= ~WINCONx_ENWIN; | |
104 | writel(val, ctx->regs + WINCON(win)); | |
105 | ch_enabled = 1; | |
106 | } | |
107 | } | |
108 | ||
109 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
110 | if (ch_enabled) { | |
111 | unsigned int state = ctx->suspended; | |
112 | ||
113 | ctx->suspended = 0; | |
114 | decon_wait_for_vblank(ctx->crtc); | |
115 | ctx->suspended = state; | |
116 | } | |
117 | } | |
118 | ||
119 | static int decon_ctx_initialize(struct decon_context *ctx, | |
120 | struct drm_device *drm_dev) | |
121 | { | |
122 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
123 | ||
124 | ctx->drm_dev = drm_dev; | |
125 | ctx->pipe = priv->pipe++; | |
126 | ||
127 | /* attach this sub driver to iommu mapping if supported. */ | |
128 | if (is_drm_iommu_supported(ctx->drm_dev)) { | |
129 | int ret; | |
130 | ||
131 | /* | |
132 | * If any channel is already active, iommu will throw | |
133 | * a PAGE FAULT when enabled. So clear any channel if enabled. | |
134 | */ | |
135 | decon_clear_channel(ctx); | |
136 | ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev); | |
137 | if (ret) { | |
138 | DRM_ERROR("drm_iommu_attach failed.\n"); | |
139 | return ret; | |
140 | } | |
141 | } | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | static void decon_ctx_remove(struct decon_context *ctx) | |
147 | { | |
148 | /* detach this sub driver from iommu mapping if supported. */ | |
149 | if (is_drm_iommu_supported(ctx->drm_dev)) | |
150 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); | |
151 | } | |
152 | ||
153 | static u32 decon_calc_clkdiv(struct decon_context *ctx, | |
154 | const struct drm_display_mode *mode) | |
155 | { | |
156 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
157 | u32 clkdiv; | |
158 | ||
159 | /* Find the clock divider value that gets us closest to ideal_clk */ | |
160 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); | |
161 | ||
162 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
163 | } | |
164 | ||
165 | static bool decon_mode_fixup(struct exynos_drm_crtc *crtc, | |
166 | const struct drm_display_mode *mode, | |
167 | struct drm_display_mode *adjusted_mode) | |
168 | { | |
169 | if (adjusted_mode->vrefresh == 0) | |
170 | adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE; | |
171 | ||
172 | return true; | |
173 | } | |
174 | ||
175 | static void decon_commit(struct exynos_drm_crtc *crtc) | |
176 | { | |
177 | struct decon_context *ctx = crtc->ctx; | |
020e79de | 178 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
96976c3d AK |
179 | u32 val, clkdiv; |
180 | ||
181 | if (ctx->suspended) | |
182 | return; | |
183 | ||
184 | /* nothing to do if we haven't set the mode yet */ | |
185 | if (mode->htotal == 0 || mode->vtotal == 0) | |
186 | return; | |
187 | ||
188 | if (!ctx->i80_if) { | |
189 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
190 | /* setup vertical timing values. */ | |
191 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
192 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
193 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
194 | ||
195 | val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); | |
196 | writel(val, ctx->regs + VIDTCON0); | |
197 | ||
198 | val = VIDTCON1_VSPW(vsync_len - 1); | |
199 | writel(val, ctx->regs + VIDTCON1); | |
200 | ||
201 | /* setup horizontal timing values. */ | |
202 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
203 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
204 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
205 | ||
206 | /* setup horizontal timing values. */ | |
207 | val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); | |
208 | writel(val, ctx->regs + VIDTCON2); | |
209 | ||
210 | val = VIDTCON3_HSPW(hsync_len - 1); | |
211 | writel(val, ctx->regs + VIDTCON3); | |
212 | } | |
213 | ||
214 | /* setup horizontal and vertical display size. */ | |
215 | val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | | |
216 | VIDTCON4_HOZVAL(mode->hdisplay - 1); | |
217 | writel(val, ctx->regs + VIDTCON4); | |
218 | ||
219 | writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); | |
220 | ||
221 | /* | |
222 | * fields of register with prefix '_F' would be updated | |
223 | * at vsync(same as dma start) | |
224 | */ | |
225 | val = VIDCON0_ENVID | VIDCON0_ENVID_F; | |
226 | writel(val, ctx->regs + VIDCON0); | |
227 | ||
228 | clkdiv = decon_calc_clkdiv(ctx, mode); | |
229 | if (clkdiv > 1) { | |
230 | val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); | |
231 | writel(val, ctx->regs + VCLKCON1); | |
232 | writel(val, ctx->regs + VCLKCON2); | |
233 | } | |
234 | ||
235 | val = readl(ctx->regs + DECON_UPDATE); | |
236 | val |= DECON_UPDATE_STANDALONE_F; | |
237 | writel(val, ctx->regs + DECON_UPDATE); | |
238 | } | |
239 | ||
240 | static int decon_enable_vblank(struct exynos_drm_crtc *crtc) | |
241 | { | |
242 | struct decon_context *ctx = crtc->ctx; | |
243 | u32 val; | |
244 | ||
245 | if (ctx->suspended) | |
246 | return -EPERM; | |
247 | ||
248 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
249 | val = readl(ctx->regs + VIDINTCON0); | |
250 | ||
251 | val |= VIDINTCON0_INT_ENABLE; | |
252 | ||
253 | if (!ctx->i80_if) { | |
254 | val |= VIDINTCON0_INT_FRAME; | |
255 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
256 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
257 | } | |
258 | ||
259 | writel(val, ctx->regs + VIDINTCON0); | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static void decon_disable_vblank(struct exynos_drm_crtc *crtc) | |
266 | { | |
267 | struct decon_context *ctx = crtc->ctx; | |
268 | u32 val; | |
269 | ||
270 | if (ctx->suspended) | |
271 | return; | |
272 | ||
273 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
274 | val = readl(ctx->regs + VIDINTCON0); | |
275 | ||
276 | val &= ~VIDINTCON0_INT_ENABLE; | |
277 | if (!ctx->i80_if) | |
278 | val &= ~VIDINTCON0_INT_FRAME; | |
279 | ||
280 | writel(val, ctx->regs + VIDINTCON0); | |
281 | } | |
282 | } | |
283 | ||
96976c3d AK |
284 | static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win) |
285 | { | |
7ee14cdc | 286 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
96976c3d | 287 | unsigned long val; |
7ee14cdc | 288 | int padding; |
96976c3d AK |
289 | |
290 | val = readl(ctx->regs + WINCON(win)); | |
291 | val &= ~WINCONx_BPPMODE_MASK; | |
292 | ||
7ee14cdc | 293 | switch (plane->pixel_format) { |
96976c3d AK |
294 | case DRM_FORMAT_RGB565: |
295 | val |= WINCONx_BPPMODE_16BPP_565; | |
296 | val |= WINCONx_BURSTLEN_16WORD; | |
297 | break; | |
298 | case DRM_FORMAT_XRGB8888: | |
299 | val |= WINCONx_BPPMODE_24BPP_xRGB; | |
300 | val |= WINCONx_BURSTLEN_16WORD; | |
301 | break; | |
302 | case DRM_FORMAT_XBGR8888: | |
303 | val |= WINCONx_BPPMODE_24BPP_xBGR; | |
304 | val |= WINCONx_BURSTLEN_16WORD; | |
305 | break; | |
306 | case DRM_FORMAT_RGBX8888: | |
307 | val |= WINCONx_BPPMODE_24BPP_RGBx; | |
308 | val |= WINCONx_BURSTLEN_16WORD; | |
309 | break; | |
310 | case DRM_FORMAT_BGRX8888: | |
311 | val |= WINCONx_BPPMODE_24BPP_BGRx; | |
312 | val |= WINCONx_BURSTLEN_16WORD; | |
313 | break; | |
314 | case DRM_FORMAT_ARGB8888: | |
315 | val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | | |
316 | WINCONx_ALPHA_SEL; | |
317 | val |= WINCONx_BURSTLEN_16WORD; | |
318 | break; | |
319 | case DRM_FORMAT_ABGR8888: | |
320 | val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | | |
321 | WINCONx_ALPHA_SEL; | |
322 | val |= WINCONx_BURSTLEN_16WORD; | |
323 | break; | |
324 | case DRM_FORMAT_RGBA8888: | |
325 | val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | | |
326 | WINCONx_ALPHA_SEL; | |
327 | val |= WINCONx_BURSTLEN_16WORD; | |
328 | break; | |
329 | case DRM_FORMAT_BGRA8888: | |
330 | val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | | |
331 | WINCONx_ALPHA_SEL; | |
332 | val |= WINCONx_BURSTLEN_16WORD; | |
333 | break; | |
334 | default: | |
335 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
336 | ||
337 | val |= WINCONx_BPPMODE_24BPP_xRGB; | |
338 | val |= WINCONx_BURSTLEN_16WORD; | |
339 | break; | |
340 | } | |
341 | ||
7ee14cdc | 342 | DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); |
96976c3d AK |
343 | |
344 | /* | |
345 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
346 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
347 | * switching which is based on plane size is not recommended as | |
348 | * plane size varies a lot towards the end of the screen and rapid | |
349 | * movement causes unstable DMA which results into iommu crash/tear. | |
350 | */ | |
351 | ||
7ee14cdc GP |
352 | padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; |
353 | if (plane->fb_width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { | |
96976c3d AK |
354 | val &= ~WINCONx_BURSTLEN_MASK; |
355 | val |= WINCONx_BURSTLEN_8WORD; | |
356 | } | |
357 | ||
358 | writel(val, ctx->regs + WINCON(win)); | |
359 | } | |
360 | ||
361 | static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) | |
362 | { | |
363 | unsigned int keycon0 = 0, keycon1 = 0; | |
364 | ||
365 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | | |
366 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
367 | ||
368 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
369 | ||
370 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
371 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
372 | } | |
373 | ||
374 | /** | |
375 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
376 | * | |
377 | * @win: window to protect registers for | |
378 | * @protect: 1 to protect (disable updates) | |
379 | */ | |
380 | static void decon_shadow_protect_win(struct decon_context *ctx, | |
6e2a3b66 | 381 | unsigned int win, bool protect) |
96976c3d AK |
382 | { |
383 | u32 bits, val; | |
384 | ||
385 | bits = SHADOWCON_WINx_PROTECT(win); | |
386 | ||
387 | val = readl(ctx->regs + SHADOWCON); | |
388 | if (protect) | |
389 | val |= bits; | |
390 | else | |
391 | val &= ~bits; | |
392 | writel(val, ctx->regs + SHADOWCON); | |
393 | } | |
394 | ||
6e2a3b66 | 395 | static void decon_win_commit(struct exynos_drm_crtc *crtc, unsigned int win) |
96976c3d AK |
396 | { |
397 | struct decon_context *ctx = crtc->ctx; | |
020e79de | 398 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
7ee14cdc | 399 | struct exynos_drm_plane *plane; |
6e2a3b66 | 400 | int padding; |
96976c3d AK |
401 | unsigned long val, alpha; |
402 | unsigned int last_x; | |
403 | unsigned int last_y; | |
404 | ||
405 | if (ctx->suspended) | |
406 | return; | |
407 | ||
96976c3d AK |
408 | if (win < 0 || win >= WINDOWS_NR) |
409 | return; | |
410 | ||
7ee14cdc | 411 | plane = &ctx->planes[win]; |
96976c3d AK |
412 | |
413 | /* If suspended, enable this on resume */ | |
414 | if (ctx->suspended) { | |
7ee14cdc | 415 | plane->resume = true; |
96976c3d AK |
416 | return; |
417 | } | |
418 | ||
419 | /* | |
420 | * SHADOWCON/PRTCON register is used for enabling timing. | |
421 | * | |
422 | * for example, once only width value of a register is set, | |
423 | * if the dma is started then decon hardware could malfunction so | |
424 | * with protect window setting, the register fields with prefix '_F' | |
425 | * wouldn't be updated at vsync also but updated once unprotect window | |
426 | * is set. | |
427 | */ | |
428 | ||
429 | /* protect windows */ | |
430 | decon_shadow_protect_win(ctx, win, true); | |
431 | ||
432 | /* buffer start address */ | |
7ee14cdc | 433 | val = (unsigned long)plane->dma_addr[0]; |
96976c3d AK |
434 | writel(val, ctx->regs + VIDW_BUF_START(win)); |
435 | ||
7ee14cdc GP |
436 | padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; |
437 | ||
96976c3d | 438 | /* buffer size */ |
7ee14cdc GP |
439 | writel(plane->fb_width + padding, ctx->regs + VIDW_WHOLE_X(win)); |
440 | writel(plane->fb_height, ctx->regs + VIDW_WHOLE_Y(win)); | |
96976c3d AK |
441 | |
442 | /* offset from the start of the buffer to read */ | |
cb8a3db2 JS |
443 | writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win)); |
444 | writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win)); | |
96976c3d AK |
445 | |
446 | DRM_DEBUG_KMS("start addr = 0x%lx\n", | |
7ee14cdc | 447 | (unsigned long)val); |
96976c3d | 448 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
7ee14cdc | 449 | plane->crtc_width, plane->crtc_height); |
96976c3d AK |
450 | |
451 | /* | |
452 | * OSD position. | |
453 | * In case the window layout goes of LCD layout, DECON fails. | |
454 | */ | |
7ee14cdc GP |
455 | if ((plane->crtc_x + plane->crtc_width) > mode->hdisplay) |
456 | plane->crtc_x = mode->hdisplay - plane->crtc_width; | |
457 | if ((plane->crtc_y + plane->crtc_height) > mode->vdisplay) | |
458 | plane->crtc_y = mode->vdisplay - plane->crtc_height; | |
96976c3d | 459 | |
7ee14cdc GP |
460 | val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | |
461 | VIDOSDxA_TOPLEFT_Y(plane->crtc_y); | |
96976c3d AK |
462 | writel(val, ctx->regs + VIDOSD_A(win)); |
463 | ||
7ee14cdc | 464 | last_x = plane->crtc_x + plane->crtc_width; |
96976c3d AK |
465 | if (last_x) |
466 | last_x--; | |
7ee14cdc | 467 | last_y = plane->crtc_y + plane->crtc_height; |
96976c3d AK |
468 | if (last_y) |
469 | last_y--; | |
470 | ||
471 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); | |
472 | ||
473 | writel(val, ctx->regs + VIDOSD_B(win)); | |
474 | ||
475 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", | |
7ee14cdc | 476 | plane->crtc_x, plane->crtc_y, last_x, last_y); |
96976c3d AK |
477 | |
478 | /* OSD alpha */ | |
479 | alpha = VIDOSDxC_ALPHA0_R_F(0x0) | | |
480 | VIDOSDxC_ALPHA0_G_F(0x0) | | |
481 | VIDOSDxC_ALPHA0_B_F(0x0); | |
482 | ||
483 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
484 | ||
485 | alpha = VIDOSDxD_ALPHA1_R_F(0xff) | | |
486 | VIDOSDxD_ALPHA1_G_F(0xff) | | |
487 | VIDOSDxD_ALPHA1_B_F(0xff); | |
488 | ||
489 | writel(alpha, ctx->regs + VIDOSD_D(win)); | |
490 | ||
491 | decon_win_set_pixfmt(ctx, win); | |
492 | ||
493 | /* hardware window 0 doesn't support color key. */ | |
494 | if (win != 0) | |
495 | decon_win_set_colkey(ctx, win); | |
496 | ||
497 | /* wincon */ | |
498 | val = readl(ctx->regs + WINCON(win)); | |
499 | val |= WINCONx_TRIPLE_BUF_MODE; | |
500 | val |= WINCONx_ENWIN; | |
501 | writel(val, ctx->regs + WINCON(win)); | |
502 | ||
503 | /* Enable DMA channel and unprotect windows */ | |
504 | decon_shadow_protect_win(ctx, win, false); | |
505 | ||
506 | val = readl(ctx->regs + DECON_UPDATE); | |
507 | val |= DECON_UPDATE_STANDALONE_F; | |
508 | writel(val, ctx->regs + DECON_UPDATE); | |
509 | ||
7ee14cdc | 510 | plane->enabled = true; |
96976c3d AK |
511 | } |
512 | ||
6e2a3b66 | 513 | static void decon_win_disable(struct exynos_drm_crtc *crtc, unsigned int win) |
96976c3d AK |
514 | { |
515 | struct decon_context *ctx = crtc->ctx; | |
7ee14cdc | 516 | struct exynos_drm_plane *plane; |
96976c3d AK |
517 | u32 val; |
518 | ||
96976c3d AK |
519 | if (win < 0 || win >= WINDOWS_NR) |
520 | return; | |
521 | ||
7ee14cdc | 522 | plane = &ctx->planes[win]; |
96976c3d AK |
523 | |
524 | if (ctx->suspended) { | |
525 | /* do not resume this window*/ | |
7ee14cdc | 526 | plane->resume = false; |
96976c3d AK |
527 | return; |
528 | } | |
529 | ||
530 | /* protect windows */ | |
531 | decon_shadow_protect_win(ctx, win, true); | |
532 | ||
533 | /* wincon */ | |
534 | val = readl(ctx->regs + WINCON(win)); | |
535 | val &= ~WINCONx_ENWIN; | |
536 | writel(val, ctx->regs + WINCON(win)); | |
537 | ||
538 | /* unprotect windows */ | |
539 | decon_shadow_protect_win(ctx, win, false); | |
540 | ||
541 | val = readl(ctx->regs + DECON_UPDATE); | |
542 | val |= DECON_UPDATE_STANDALONE_F; | |
543 | writel(val, ctx->regs + DECON_UPDATE); | |
544 | ||
7ee14cdc | 545 | plane->enabled = false; |
96976c3d AK |
546 | } |
547 | ||
548 | static void decon_window_suspend(struct decon_context *ctx) | |
549 | { | |
7ee14cdc | 550 | struct exynos_drm_plane *plane; |
96976c3d AK |
551 | int i; |
552 | ||
553 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
554 | plane = &ctx->planes[i]; |
555 | plane->resume = plane->enabled; | |
556 | if (plane->enabled) | |
96976c3d AK |
557 | decon_win_disable(ctx->crtc, i); |
558 | } | |
559 | } | |
560 | ||
561 | static void decon_window_resume(struct decon_context *ctx) | |
562 | { | |
7ee14cdc | 563 | struct exynos_drm_plane *plane; |
96976c3d AK |
564 | int i; |
565 | ||
566 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
567 | plane = &ctx->planes[i]; |
568 | plane->enabled = plane->resume; | |
569 | plane->resume = false; | |
96976c3d AK |
570 | } |
571 | } | |
572 | ||
573 | static void decon_apply(struct decon_context *ctx) | |
574 | { | |
7ee14cdc | 575 | struct exynos_drm_plane *plane; |
96976c3d AK |
576 | int i; |
577 | ||
578 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
579 | plane = &ctx->planes[i]; |
580 | if (plane->enabled) | |
96976c3d AK |
581 | decon_win_commit(ctx->crtc, i); |
582 | else | |
583 | decon_win_disable(ctx->crtc, i); | |
584 | } | |
585 | ||
586 | decon_commit(ctx->crtc); | |
587 | } | |
588 | ||
589 | static void decon_init(struct decon_context *ctx) | |
590 | { | |
591 | u32 val; | |
592 | ||
593 | writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); | |
594 | ||
595 | val = VIDOUTCON0_DISP_IF_0_ON; | |
596 | if (!ctx->i80_if) | |
597 | val |= VIDOUTCON0_RGBIF; | |
598 | writel(val, ctx->regs + VIDOUTCON0); | |
599 | ||
600 | writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); | |
601 | ||
602 | if (!ctx->i80_if) | |
603 | writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); | |
604 | } | |
605 | ||
3cecda03 | 606 | static void decon_enable(struct exynos_drm_crtc *crtc) |
96976c3d | 607 | { |
3cecda03 | 608 | struct decon_context *ctx = crtc->ctx; |
38000dbb | 609 | int ret; |
96976c3d AK |
610 | |
611 | if (!ctx->suspended) | |
3cecda03 | 612 | return; |
96976c3d AK |
613 | |
614 | ctx->suspended = false; | |
615 | ||
616 | pm_runtime_get_sync(ctx->dev); | |
617 | ||
38000dbb GP |
618 | ret = clk_prepare_enable(ctx->pclk); |
619 | if (ret < 0) { | |
620 | DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); | |
621 | return; | |
622 | } | |
623 | ||
624 | ret = clk_prepare_enable(ctx->aclk); | |
625 | if (ret < 0) { | |
626 | DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); | |
627 | return; | |
628 | } | |
629 | ||
630 | ret = clk_prepare_enable(ctx->eclk); | |
631 | if (ret < 0) { | |
632 | DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); | |
633 | return; | |
634 | } | |
635 | ||
636 | ret = clk_prepare_enable(ctx->vclk); | |
637 | if (ret < 0) { | |
638 | DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); | |
639 | return; | |
640 | } | |
96976c3d AK |
641 | |
642 | decon_init(ctx); | |
643 | ||
644 | /* if vblank was enabled status, enable it again. */ | |
3cecda03 GP |
645 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
646 | decon_enable_vblank(ctx->crtc); | |
96976c3d AK |
647 | |
648 | decon_window_resume(ctx); | |
649 | ||
650 | decon_apply(ctx); | |
96976c3d AK |
651 | } |
652 | ||
3cecda03 | 653 | static void decon_disable(struct exynos_drm_crtc *crtc) |
96976c3d | 654 | { |
3cecda03 GP |
655 | struct decon_context *ctx = crtc->ctx; |
656 | ||
96976c3d | 657 | if (ctx->suspended) |
3cecda03 | 658 | return; |
96976c3d AK |
659 | |
660 | /* | |
661 | * We need to make sure that all windows are disabled before we | |
662 | * suspend that connector. Otherwise we might try to scan from | |
663 | * a destroyed buffer later. | |
664 | */ | |
665 | decon_window_suspend(ctx); | |
666 | ||
667 | clk_disable_unprepare(ctx->vclk); | |
668 | clk_disable_unprepare(ctx->eclk); | |
669 | clk_disable_unprepare(ctx->aclk); | |
670 | clk_disable_unprepare(ctx->pclk); | |
671 | ||
672 | pm_runtime_put_sync(ctx->dev); | |
673 | ||
674 | ctx->suspended = true; | |
96976c3d AK |
675 | } |
676 | ||
f3aaf762 | 677 | static const struct exynos_drm_crtc_ops decon_crtc_ops = { |
3cecda03 GP |
678 | .enable = decon_enable, |
679 | .disable = decon_disable, | |
96976c3d AK |
680 | .mode_fixup = decon_mode_fixup, |
681 | .commit = decon_commit, | |
682 | .enable_vblank = decon_enable_vblank, | |
683 | .disable_vblank = decon_disable_vblank, | |
684 | .wait_for_vblank = decon_wait_for_vblank, | |
96976c3d AK |
685 | .win_commit = decon_win_commit, |
686 | .win_disable = decon_win_disable, | |
687 | }; | |
688 | ||
689 | ||
690 | static irqreturn_t decon_irq_handler(int irq, void *dev_id) | |
691 | { | |
692 | struct decon_context *ctx = (struct decon_context *)dev_id; | |
693 | u32 val, clear_bit; | |
694 | ||
695 | val = readl(ctx->regs + VIDINTCON1); | |
696 | ||
697 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; | |
698 | if (val & clear_bit) | |
699 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
700 | ||
701 | /* check the crtc is detached already from encoder */ | |
702 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
703 | goto out; | |
704 | ||
705 | if (!ctx->i80_if) { | |
706 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); | |
707 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); | |
708 | ||
709 | /* set wait vsync event to zero and wake up queue. */ | |
710 | if (atomic_read(&ctx->wait_vsync_event)) { | |
711 | atomic_set(&ctx->wait_vsync_event, 0); | |
712 | wake_up(&ctx->wait_vsync_queue); | |
713 | } | |
714 | } | |
715 | out: | |
716 | return IRQ_HANDLED; | |
717 | } | |
718 | ||
719 | static int decon_bind(struct device *dev, struct device *master, void *data) | |
720 | { | |
721 | struct decon_context *ctx = dev_get_drvdata(dev); | |
722 | struct drm_device *drm_dev = data; | |
7ee14cdc GP |
723 | struct exynos_drm_plane *exynos_plane; |
724 | enum drm_plane_type type; | |
6e2a3b66 GP |
725 | unsigned int zpos; |
726 | int ret; | |
96976c3d AK |
727 | |
728 | ret = decon_ctx_initialize(ctx, drm_dev); | |
729 | if (ret) { | |
730 | DRM_ERROR("decon_ctx_initialize failed.\n"); | |
731 | return ret; | |
732 | } | |
733 | ||
7ee14cdc GP |
734 | for (zpos = 0; zpos < WINDOWS_NR; zpos++) { |
735 | type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : | |
736 | DRM_PLANE_TYPE_OVERLAY; | |
737 | ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], | |
6e2a3b66 | 738 | 1 << ctx->pipe, type, zpos); |
7ee14cdc GP |
739 | if (ret) |
740 | return ret; | |
741 | } | |
742 | ||
743 | exynos_plane = &ctx->planes[ctx->default_win]; | |
744 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, | |
745 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
96976c3d AK |
746 | &decon_crtc_ops, ctx); |
747 | if (IS_ERR(ctx->crtc)) { | |
748 | decon_ctx_remove(ctx); | |
749 | return PTR_ERR(ctx->crtc); | |
750 | } | |
751 | ||
752 | if (ctx->display) | |
753 | exynos_drm_create_enc_conn(drm_dev, ctx->display); | |
754 | ||
755 | return 0; | |
756 | ||
757 | } | |
758 | ||
759 | static void decon_unbind(struct device *dev, struct device *master, | |
760 | void *data) | |
761 | { | |
762 | struct decon_context *ctx = dev_get_drvdata(dev); | |
763 | ||
3cecda03 | 764 | decon_disable(ctx->crtc); |
96976c3d AK |
765 | |
766 | if (ctx->display) | |
767 | exynos_dpi_remove(ctx->display); | |
768 | ||
769 | decon_ctx_remove(ctx); | |
770 | } | |
771 | ||
772 | static const struct component_ops decon_component_ops = { | |
773 | .bind = decon_bind, | |
774 | .unbind = decon_unbind, | |
775 | }; | |
776 | ||
777 | static int decon_probe(struct platform_device *pdev) | |
778 | { | |
779 | struct device *dev = &pdev->dev; | |
780 | struct decon_context *ctx; | |
781 | struct device_node *i80_if_timings; | |
782 | struct resource *res; | |
783 | int ret; | |
784 | ||
785 | if (!dev->of_node) | |
786 | return -ENODEV; | |
787 | ||
788 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
789 | if (!ctx) | |
790 | return -ENOMEM; | |
791 | ||
96976c3d AK |
792 | ctx->dev = dev; |
793 | ctx->suspended = true; | |
794 | ||
795 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); | |
796 | if (i80_if_timings) | |
797 | ctx->i80_if = true; | |
798 | of_node_put(i80_if_timings); | |
799 | ||
800 | ctx->regs = of_iomap(dev->of_node, 0); | |
86650408 AH |
801 | if (!ctx->regs) |
802 | return -ENOMEM; | |
96976c3d AK |
803 | |
804 | ctx->pclk = devm_clk_get(dev, "pclk_decon0"); | |
805 | if (IS_ERR(ctx->pclk)) { | |
806 | dev_err(dev, "failed to get bus clock pclk\n"); | |
807 | ret = PTR_ERR(ctx->pclk); | |
808 | goto err_iounmap; | |
809 | } | |
810 | ||
811 | ctx->aclk = devm_clk_get(dev, "aclk_decon0"); | |
812 | if (IS_ERR(ctx->aclk)) { | |
813 | dev_err(dev, "failed to get bus clock aclk\n"); | |
814 | ret = PTR_ERR(ctx->aclk); | |
815 | goto err_iounmap; | |
816 | } | |
817 | ||
818 | ctx->eclk = devm_clk_get(dev, "decon0_eclk"); | |
819 | if (IS_ERR(ctx->eclk)) { | |
820 | dev_err(dev, "failed to get eclock\n"); | |
821 | ret = PTR_ERR(ctx->eclk); | |
822 | goto err_iounmap; | |
823 | } | |
824 | ||
825 | ctx->vclk = devm_clk_get(dev, "decon0_vclk"); | |
826 | if (IS_ERR(ctx->vclk)) { | |
827 | dev_err(dev, "failed to get vclock\n"); | |
828 | ret = PTR_ERR(ctx->vclk); | |
829 | goto err_iounmap; | |
830 | } | |
831 | ||
832 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
833 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
834 | if (!res) { | |
835 | dev_err(dev, "irq request failed.\n"); | |
836 | ret = -ENXIO; | |
837 | goto err_iounmap; | |
838 | } | |
839 | ||
840 | ret = devm_request_irq(dev, res->start, decon_irq_handler, | |
841 | 0, "drm_decon", ctx); | |
842 | if (ret) { | |
843 | dev_err(dev, "irq request failed.\n"); | |
844 | goto err_iounmap; | |
845 | } | |
846 | ||
847 | init_waitqueue_head(&ctx->wait_vsync_queue); | |
848 | atomic_set(&ctx->wait_vsync_event, 0); | |
849 | ||
850 | platform_set_drvdata(pdev, ctx); | |
851 | ||
852 | ctx->display = exynos_dpi_probe(dev); | |
853 | if (IS_ERR(ctx->display)) { | |
854 | ret = PTR_ERR(ctx->display); | |
855 | goto err_iounmap; | |
856 | } | |
857 | ||
858 | pm_runtime_enable(dev); | |
859 | ||
860 | ret = component_add(dev, &decon_component_ops); | |
861 | if (ret) | |
862 | goto err_disable_pm_runtime; | |
863 | ||
864 | return ret; | |
865 | ||
866 | err_disable_pm_runtime: | |
867 | pm_runtime_disable(dev); | |
868 | ||
869 | err_iounmap: | |
870 | iounmap(ctx->regs); | |
871 | ||
96976c3d AK |
872 | return ret; |
873 | } | |
874 | ||
875 | static int decon_remove(struct platform_device *pdev) | |
876 | { | |
877 | struct decon_context *ctx = dev_get_drvdata(&pdev->dev); | |
878 | ||
879 | pm_runtime_disable(&pdev->dev); | |
880 | ||
881 | iounmap(ctx->regs); | |
882 | ||
883 | component_del(&pdev->dev, &decon_component_ops); | |
96976c3d AK |
884 | |
885 | return 0; | |
886 | } | |
887 | ||
888 | struct platform_driver decon_driver = { | |
889 | .probe = decon_probe, | |
890 | .remove = decon_remove, | |
891 | .driver = { | |
892 | .name = "exynos-decon", | |
893 | .of_match_table = decon_driver_dt_match, | |
894 | }, | |
895 | }; |