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drm/exynos: dp: Modify driver to support drm_panel
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_dp_core.c
CommitLineData
e9474be4
JH		 1/*
2 * Samsung SoC DP (Display Port) interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
e9474be4
JH		 15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/interrupt.h>
c4e235c2 19#include <linux/of.h>
b8b52471
AB		 20#include <linux/of_gpio.h>
21#include <linux/gpio.h>
f37cd5e8 22#include <linux/component.h>
8114fabc 23#include <linux/phy/phy.h>
1417f109
SP		 24#include <video/of_display_timing.h>
25#include <video/of_videomode.h>
e9474be4 26
1417f109 27#include <drm/drmP.h>
caa5d1e5
SP		 28#include <drm/drm_crtc.h>
29#include <drm/drm_crtc_helper.h>
5f1dcd8b 30#include <drm/drm_panel.h>
1634ba25 31#include <drm/bridge/ptn3460.h>
1417f109
SP		 32
33#include "exynos_drm_drv.h"
e9474be4
JH		 34#include "exynos_dp_core.h"
35
caa5d1e5
SP		 36#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
37 connector)
38
1634ba25
SP		 39struct bridge_init {
40 struct i2c_client *client;
41 struct device_node *node;
42};
43
5f1dcd8b 44static void exynos_dp_init_dp(struct exynos_dp_device *dp)
e9474be4
JH		 45{
46 exynos_dp_reset(dp);
47
24db03a8
JH		 48 exynos_dp_swreset(dp);
49
75435c74
JH		 50 exynos_dp_init_analog_param(dp);
51 exynos_dp_init_interrupt(dp);
52
e9474be4
JH		 53 /* SW defined function Normal operation */
54 exynos_dp_enable_sw_function(dp);
55
56 exynos_dp_config_interrupt(dp);
57 exynos_dp_init_analog_func(dp);
58
59 exynos_dp_init_hpd(dp);
60 exynos_dp_init_aux(dp);
e9474be4
JH		 61}
62
63static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
64{
65 int timeout_loop = 0;
66
e9474be4
JH		 67 while (exynos_dp_get_plug_in_status(dp) != 0) {
68 timeout_loop++;
69 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
70 dev_err(dp->dev, "failed to get hpd plug status\n");
71 return -ETIMEDOUT;
72 }
a2c81bc1 73 usleep_range(10, 11);
e9474be4
JH		 74 }
75
76 return 0;
77}
78
79static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
80{
81 int i;
82 unsigned char sum = 0;
83
84 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
85 sum = sum + edid_data[i];
86
87 return sum;
88}
89
90static int exynos_dp_read_edid(struct exynos_dp_device *dp)
91{
92 unsigned char edid[EDID_BLOCK_LENGTH * 2];
93 unsigned int extend_block = 0;
94 unsigned char sum;
95 unsigned char test_vector;
96 int retval;
97
98 /*
99 * EDID device address is 0x50.
100 * However, if necessary, you must have set upper address
101 * into E-EDID in I2C device, 0x30.
102 */
103
104 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
99f54152 105 retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
e9474be4
JH		 106 EDID_EXTENSION_FLAG,
107 &extend_block);
99f54152
SP		 108 if (retval)
109 return retval;
e9474be4
JH		 110
111 if (extend_block > 0) {
112 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
113
114 /* Read EDID data */
115 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
116 EDID_HEADER_PATTERN,
117 EDID_BLOCK_LENGTH,
118 &edid[EDID_HEADER_PATTERN]);
119 if (retval != 0) {
120 dev_err(dp->dev, "EDID Read failed!\n");
121 return -EIO;
122 }
123 sum = exynos_dp_calc_edid_check_sum(edid);
124 if (sum != 0) {
125 dev_err(dp->dev, "EDID bad checksum!\n");
126 return -EIO;
127 }
128
129 /* Read additional EDID data */
130 retval = exynos_dp_read_bytes_from_i2c(dp,
131 I2C_EDID_DEVICE_ADDR,
132 EDID_BLOCK_LENGTH,
133 EDID_BLOCK_LENGTH,
134 &edid[EDID_BLOCK_LENGTH]);
135 if (retval != 0) {
136 dev_err(dp->dev, "EDID Read failed!\n");
137 return -EIO;
138 }
139 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
140 if (sum != 0) {
141 dev_err(dp->dev, "EDID bad checksum!\n");
142 return -EIO;
143 }
144
073ea2ae 145 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
e9474be4 146 &test_vector);
073ea2ae 147 if (test_vector & DP_TEST_LINK_EDID_READ) {
e9474be4 148 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae 149 DP_TEST_EDID_CHECKSUM,
e9474be4
JH		 150 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
151 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 152 DP_TEST_RESPONSE,
153 DP_TEST_EDID_CHECKSUM_WRITE);
e9474be4
JH		 154 }
155 } else {
156 dev_info(dp->dev, "EDID data does not include any extensions.\n");
157
158 /* Read EDID data */
159 retval = exynos_dp_read_bytes_from_i2c(dp,
160 I2C_EDID_DEVICE_ADDR,
161 EDID_HEADER_PATTERN,
162 EDID_BLOCK_LENGTH,
163 &edid[EDID_HEADER_PATTERN]);
164 if (retval != 0) {
165 dev_err(dp->dev, "EDID Read failed!\n");
166 return -EIO;
167 }
168 sum = exynos_dp_calc_edid_check_sum(edid);
169 if (sum != 0) {
170 dev_err(dp->dev, "EDID bad checksum!\n");
171 return -EIO;
172 }
173
174 exynos_dp_read_byte_from_dpcd(dp,
073ea2ae 175 DP_TEST_REQUEST,
e9474be4 176 &test_vector);
073ea2ae 177 if (test_vector & DP_TEST_LINK_EDID_READ) {
e9474be4 178 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae 179 DP_TEST_EDID_CHECKSUM,
e9474be4
JH		 180 edid[EDID_CHECKSUM]);
181 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 182 DP_TEST_RESPONSE,
183 DP_TEST_EDID_CHECKSUM_WRITE);
e9474be4
JH		 184 }
185 }
186
187 dev_err(dp->dev, "EDID Read success!\n");
188 return 0;
189}
190
191static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
192{
193 u8 buf[12];
194 int i;
195 int retval;
196
073ea2ae
JH		 197 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
198 retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
99f54152
SP		 199 12, buf);
200 if (retval)
201 return retval;
e9474be4
JH		 202
203 /* Read EDID */
204 for (i = 0; i < 3; i++) {
205 retval = exynos_dp_read_edid(dp);
99f54152 206 if (!retval)
e9474be4
JH		 207 break;
208 }
209
210 return retval;
211}
212
213static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
214 bool enable)
215{
216 u8 data;
217
073ea2ae 218 exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
e9474be4
JH		 219
220 if (enable)
073ea2ae
JH		 221 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
222 DP_LANE_COUNT_ENHANCED_FRAME_EN |
e9474be4
JH		 223 DPCD_LANE_COUNT_SET(data));
224 else
073ea2ae 225 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
e9474be4
JH		 226 DPCD_LANE_COUNT_SET(data));
227}
228
229static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
230{
231 u8 data;
232 int retval;
233
073ea2ae 234 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
e9474be4
JH		 235 retval = DPCD_ENHANCED_FRAME_CAP(data);
236
237 return retval;
238}
239
240static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
241{
242 u8 data;
243
244 data = exynos_dp_is_enhanced_mode_available(dp);
245 exynos_dp_enable_rx_to_enhanced_mode(dp, data);
246 exynos_dp_enable_enhanced_mode(dp, data);
247}
248
249static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
250{
251 exynos_dp_set_training_pattern(dp, DP_NONE);
252
253 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 254 DP_TRAINING_PATTERN_SET,
255 DP_TRAINING_PATTERN_DISABLE);
e9474be4
JH		 256}
257
258static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
259 int pre_emphasis, int lane)
260{
261 switch (lane) {
262 case 0:
263 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
264 break;
265 case 1:
266 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
267 break;
268
269 case 2:
270 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
271 break;
272
273 case 3:
274 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
275 break;
276 }
277}
278
ace2d7f2 279static int exynos_dp_link_start(struct exynos_dp_device *dp)
e9474be4 280{
d5c0eed0 281 u8 buf[4];
49ce41f3 282 int lane, lane_count, pll_tries, retval;
e9474be4
JH		 283
284 lane_count = dp->link_train.lane_count;
285
286 dp->link_train.lt_state = CLOCK_RECOVERY;
287 dp->link_train.eq_loop = 0;
288
289 for (lane = 0; lane < lane_count; lane++)
290 dp->link_train.cr_loop[lane] = 0;
291
e9474be4
JH		 292 /* Set link rate and count as you want to establish*/
293 exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
294 exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
295
296 /* Setup RX configuration */
297 buf[0] = dp->link_train.link_rate;
298 buf[1] = dp->link_train.lane_count;
073ea2ae 299 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
e9474be4 300 2, buf);
ace2d7f2
SP		 301 if (retval)
302 return retval;
e9474be4
JH		 303
304 /* Set TX pre-emphasis to minimum */
305 for (lane = 0; lane < lane_count; lane++)
306 exynos_dp_set_lane_lane_pre_emphasis(dp,
307 PRE_EMPHASIS_LEVEL_0, lane);
308
49ce41f3
SP		 309 /* Wait for PLL lock */
310 pll_tries = 0;
311 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
312 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
313 dev_err(dp->dev, "Wait for PLL lock timed out\n");
314 return -ETIMEDOUT;
315 }
316
317 pll_tries++;
318 usleep_range(90, 120);
319 }
320
e9474be4
JH		 321 /* Set training pattern 1 */
322 exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
323
324 /* Set RX training pattern */
fadec4b7 325 retval = exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 326 DP_TRAINING_PATTERN_SET,
327 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
fadec4b7
SP		 328 if (retval)
329 return retval;
e9474be4
JH		 330
331 for (lane = 0; lane < lane_count; lane++)
073ea2ae
JH		 332 buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
333 DP_TRAIN_VOLTAGE_SWING_400;
fadec4b7 334
073ea2ae 335 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
fadec4b7 336 lane_count, buf);
ace2d7f2
SP		 337
338 return retval;
e9474be4
JH		 339}
340
d5c0eed0 341static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
e9474be4
JH		 342{
343 int shift = (lane & 1) * 4;
344 u8 link_value = link_status[lane>>1];
345
346 return (link_value >> shift) & 0xf;
347}
348
d5c0eed0 349static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
e9474be4
JH		 350{
351 int lane;
352 u8 lane_status;
353
354 for (lane = 0; lane < lane_count; lane++) {
355 lane_status = exynos_dp_get_lane_status(link_status, lane);
073ea2ae 356 if ((lane_status & DP_LANE_CR_DONE) == 0)
e9474be4
JH		 357 return -EINVAL;
358 }
359 return 0;
360}
361
fadec4b7
SP		 362static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
363 int lane_count)
e9474be4
JH		 364{
365 int lane;
e9474be4
JH		 366 u8 lane_status;
367
073ea2ae 368 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
e9474be4
JH		 369 return -EINVAL;
370
371 for (lane = 0; lane < lane_count; lane++) {
fadec4b7 372 lane_status = exynos_dp_get_lane_status(link_status, lane);
073ea2ae
JH		 373 lane_status &= DP_CHANNEL_EQ_BITS;
374 if (lane_status != DP_CHANNEL_EQ_BITS)
e9474be4
JH		 375 return -EINVAL;
376 }
d5c0eed0 377
e9474be4
JH		 378 return 0;
379}
380
381static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
382 int lane)
383{
384 int shift = (lane & 1) * 4;
385 u8 link_value = adjust_request[lane>>1];
386
387 return (link_value >> shift) & 0x3;
388}
389
390static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
391 u8 adjust_request[2],
392 int lane)
393{
394 int shift = (lane & 1) * 4;
395 u8 link_value = adjust_request[lane>>1];
396
397 return ((link_value >> shift) & 0xc) >> 2;
398}
399
400static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
401 u8 training_lane_set, int lane)
402{
403 switch (lane) {
404 case 0:
405 exynos_dp_set_lane0_link_training(dp, training_lane_set);
406 break;
407 case 1:
408 exynos_dp_set_lane1_link_training(dp, training_lane_set);
409 break;
410
411 case 2:
412 exynos_dp_set_lane2_link_training(dp, training_lane_set);
413 break;
414
415 case 3:
416 exynos_dp_set_lane3_link_training(dp, training_lane_set);
417 break;
418 }
419}
420
421static unsigned int exynos_dp_get_lane_link_training(
422 struct exynos_dp_device *dp,
423 int lane)
424{
425 u32 reg;
426
427 switch (lane) {
428 case 0:
429 reg = exynos_dp_get_lane0_link_training(dp);
430 break;
431 case 1:
432 reg = exynos_dp_get_lane1_link_training(dp);
433 break;
434 case 2:
435 reg = exynos_dp_get_lane2_link_training(dp);
436 break;
437 case 3:
438 reg = exynos_dp_get_lane3_link_training(dp);
439 break;
64c43dfa
JH		 440 default:
441 WARN_ON(1);
442 return 0;
e9474be4
JH		 443 }
444
445 return reg;
446}
447
448static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
449{
d5c0eed0
JH		 450 exynos_dp_training_pattern_dis(dp);
451 exynos_dp_set_enhanced_mode(dp);
e9474be4 452
d5c0eed0 453 dp->link_train.lt_state = FAILED;
e9474be4
JH		 454}
455
fadec4b7
SP		 456static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
457 u8 adjust_request[2])
458{
459 int lane, lane_count;
460 u8 voltage_swing, pre_emphasis, training_lane;
461
462 lane_count = dp->link_train.lane_count;
463 for (lane = 0; lane < lane_count; lane++) {
464 voltage_swing = exynos_dp_get_adjust_request_voltage(
465 adjust_request, lane);
466 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
467 adjust_request, lane);
468 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
469 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
470
471 if (voltage_swing == VOLTAGE_LEVEL_3)
073ea2ae 472 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
fadec4b7 473 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
073ea2ae 474 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
fadec4b7
SP		 475
476 dp->link_train.training_lane[lane] = training_lane;
477 }
478}
479
e9474be4
JH		 480static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
481{
ace2d7f2 482 int lane, lane_count, retval;
fadec4b7
SP		 483 u8 voltage_swing, pre_emphasis, training_lane;
484 u8 link_status[2], adjust_request[2];
e9474be4 485
a2c81bc1 486 usleep_range(100, 101);
e9474be4 487
e9474be4
JH		 488 lane_count = dp->link_train.lane_count;
489
fadec4b7 490 retval = exynos_dp_read_bytes_from_dpcd(dp,
073ea2ae 491 DP_LANE0_1_STATUS, 2, link_status);
fadec4b7
SP		 492 if (retval)
493 return retval;
494
495 retval = exynos_dp_read_bytes_from_dpcd(dp,
073ea2ae 496 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
ace2d7f2
SP		 497 if (retval)
498 return retval;
d5c0eed0 499
e9474be4
JH		 500 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
501 /* set training pattern 2 for EQ */
502 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
503
ace2d7f2 504 retval = exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 505 DP_TRAINING_PATTERN_SET,
506 DP_LINK_SCRAMBLING_DISABLE |
507 DP_TRAINING_PATTERN_2);
ace2d7f2
SP		 508 if (retval)
509 return retval;
d5c0eed0
JH		 510
511 dev_info(dp->dev, "Link Training Clock Recovery success\n");
512 dp->link_train.lt_state = EQUALIZER_TRAINING;
513 } else {
e9474be4
JH		 514 for (lane = 0; lane < lane_count; lane++) {
515 training_lane = exynos_dp_get_lane_link_training(
516 dp, lane);
517 voltage_swing = exynos_dp_get_adjust_request_voltage(
518 adjust_request, lane);
519 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
520 adjust_request, lane);
e9474be4 521
fadec4b7
SP		 522 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
523 voltage_swing &&
524 DPCD_PRE_EMPHASIS_GET(training_lane) ==
525 pre_emphasis)
d5c0eed0 526 dp->link_train.cr_loop[lane]++;
d5c0eed0 527
fadec4b7
SP		 528 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
529 voltage_swing == VOLTAGE_LEVEL_3 ||
530 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
531 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
532 dp->link_train.cr_loop[lane],
533 voltage_swing, pre_emphasis);
534 exynos_dp_reduce_link_rate(dp);
535 return -EIO;
536 }
537 }
538 }
d5c0eed0 539
fadec4b7 540 exynos_dp_get_adjust_training_lane(dp, adjust_request);
d5c0eed0 541
fadec4b7
SP		 542 for (lane = 0; lane < lane_count; lane++)
543 exynos_dp_set_lane_link_training(dp,
544 dp->link_train.training_lane[lane], lane);
d5c0eed0 545
fadec4b7 546 retval = exynos_dp_write_bytes_to_dpcd(dp,
073ea2ae 547 DP_TRAINING_LANE0_SET, lane_count,
fadec4b7
SP		 548 dp->link_train.training_lane);
549 if (retval)
550 return retval;
e9474be4 551
ace2d7f2 552 return retval;
e9474be4
JH		 553}
554
555static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
556{
ace2d7f2 557 int lane, lane_count, retval;
e9474be4 558 u32 reg;
fadec4b7 559 u8 link_align, link_status[2], adjust_request[2];
e9474be4 560
a2c81bc1 561 usleep_range(400, 401);
e9474be4 562
e9474be4
JH		 563 lane_count = dp->link_train.lane_count;
564
fadec4b7 565 retval = exynos_dp_read_bytes_from_dpcd(dp,
073ea2ae 566 DP_LANE0_1_STATUS, 2, link_status);
ace2d7f2
SP		 567 if (retval)
568 return retval;
d5c0eed0 569
fadec4b7
SP		 570 if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
571 exynos_dp_reduce_link_rate(dp);
572 return -EIO;
573 }
d5c0eed0 574
fadec4b7 575 retval = exynos_dp_read_bytes_from_dpcd(dp,
073ea2ae 576 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
fadec4b7
SP		 577 if (retval)
578 return retval;
ace2d7f2 579
fadec4b7 580 retval = exynos_dp_read_byte_from_dpcd(dp,
073ea2ae 581 DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
fadec4b7
SP		 582 if (retval)
583 return retval;
d5c0eed0 584
fadec4b7 585 exynos_dp_get_adjust_training_lane(dp, adjust_request);
d5c0eed0 586
fadec4b7
SP		 587 if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
588 /* traing pattern Set to Normal */
589 exynos_dp_training_pattern_dis(dp);
e9474be4 590
fadec4b7 591 dev_info(dp->dev, "Link Training success!\n");
e9474be4 592
fadec4b7
SP		 593 exynos_dp_get_link_bandwidth(dp, &reg);
594 dp->link_train.link_rate = reg;
595 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
596 dp->link_train.link_rate);
e9474be4 597
fadec4b7
SP		 598 exynos_dp_get_lane_count(dp, &reg);
599 dp->link_train.lane_count = reg;
600 dev_dbg(dp->dev, "final lane count = %.2x\n",
601 dp->link_train.lane_count);
e9474be4 602
fadec4b7
SP		 603 /* set enhanced mode if available */
604 exynos_dp_set_enhanced_mode(dp);
605 dp->link_train.lt_state = FINISHED;
d5c0eed0 606
fadec4b7
SP		 607 return 0;
608 }
e9474be4 609
fadec4b7
SP		 610 /* not all locked */
611 dp->link_train.eq_loop++;
d5c0eed0 612
fadec4b7
SP		 613 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
614 dev_err(dp->dev, "EQ Max loop\n");
615 exynos_dp_reduce_link_rate(dp);
616 return -EIO;
e9474be4
JH		 617 }
618
fadec4b7
SP		 619 for (lane = 0; lane < lane_count; lane++)
620 exynos_dp_set_lane_link_training(dp,
621 dp->link_train.training_lane[lane], lane);
d5c0eed0 622
073ea2ae 623 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
fadec4b7
SP		 624 lane_count, dp->link_train.training_lane);
625
626 return retval;
e9474be4
JH		 627}
628
629static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
d5c0eed0 630 u8 *bandwidth)
e9474be4
JH		 631{
632 u8 data;
633
634 /*
635 * For DP rev.1.1, Maximum link rate of Main Link lanes
636 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
637 */
073ea2ae 638 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
e9474be4
JH		 639 *bandwidth = data;
640}
641
642static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
d5c0eed0 643 u8 *lane_count)
e9474be4
JH		 644{
645 u8 data;
646
647 /*
648 * For DP rev.1.1, Maximum number of Main Link lanes
649 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
650 */
073ea2ae 651 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
e9474be4
JH		 652 *lane_count = DPCD_MAX_LANE_COUNT(data);
653}
654
655static void exynos_dp_init_training(struct exynos_dp_device *dp,
656 enum link_lane_count_type max_lane,
657 enum link_rate_type max_rate)
658{
659 /*
660 * MACRO_RST must be applied after the PLL_LOCK to avoid
661 * the DP inter pair skew issue for at least 10 us
662 */
663 exynos_dp_reset_macro(dp);
664
665 /* Initialize by reading RX's DPCD */
666 exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
667 exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
668
669 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
670 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
671 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
672 dp->link_train.link_rate);
673 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
674 }
675
676 if (dp->link_train.lane_count == 0) {
677 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
678 dp->link_train.lane_count);
679 dp->link_train.lane_count = (u8)LANE_COUNT1;
680 }
681
682 /* Setup TX lane count & rate */
683 if (dp->link_train.lane_count > max_lane)
684 dp->link_train.lane_count = max_lane;
685 if (dp->link_train.link_rate > max_rate)
686 dp->link_train.link_rate = max_rate;
687
688 /* All DP analog module power up */
689 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
690}
691
692static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
693{
ace2d7f2 694 int retval = 0, training_finished = 0;
e9474be4
JH		 695
696 dp->link_train.lt_state = START;
697
698 /* Process here */
ace2d7f2 699 while (!retval && !training_finished) {
e9474be4
JH		 700 switch (dp->link_train.lt_state) {
701 case START:
ace2d7f2
SP		 702 retval = exynos_dp_link_start(dp);
703 if (retval)
704 dev_err(dp->dev, "LT link start failed!\n");
e9474be4
JH		 705 break;
706 case CLOCK_RECOVERY:
d5c0eed0
JH		 707 retval = exynos_dp_process_clock_recovery(dp);
708 if (retval)
709 dev_err(dp->dev, "LT CR failed!\n");
e9474be4
JH		 710 break;
711 case EQUALIZER_TRAINING:
d5c0eed0
JH		 712 retval = exynos_dp_process_equalizer_training(dp);
713 if (retval)
714 dev_err(dp->dev, "LT EQ failed!\n");
e9474be4
JH		 715 break;
716 case FINISHED:
717 training_finished = 1;
718 break;
719 case FAILED:
720 return -EREMOTEIO;
721 }
722 }
ace2d7f2
SP		 723 if (retval)
724 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
e9474be4
JH		 725
726 return retval;
727}
728
729static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
730 u32 count,
731 u32 bwtype)
732{
733 int i;
734 int retval;
735
736 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
737 exynos_dp_init_training(dp, count, bwtype);
738 retval = exynos_dp_sw_link_training(dp);
739 if (retval == 0)
740 break;
741
a2c81bc1 742 usleep_range(100, 110);
e9474be4
JH		 743 }
744
745 return retval;
746}
747
3fcb6eb4 748static int exynos_dp_config_video(struct exynos_dp_device *dp)
e9474be4
JH		 749{
750 int retval = 0;
751 int timeout_loop = 0;
752 int done_count = 0;
753
3fcb6eb4 754 exynos_dp_config_video_slave_mode(dp);
e9474be4 755
3fcb6eb4 756 exynos_dp_set_video_color_format(dp);
e9474be4
JH		 757
758 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
759 dev_err(dp->dev, "PLL is not locked yet.\n");
760 return -EINVAL;
761 }
762
763 for (;;) {
764 timeout_loop++;
765 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
766 break;
767 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
768 dev_err(dp->dev, "Timeout of video streamclk ok\n");
769 return -ETIMEDOUT;
770 }
771
a2c81bc1 772 usleep_range(1, 2);
e9474be4
JH		 773 }
774
775 /* Set to use the register calculated M/N video */
776 exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
777
778 /* For video bist, Video timing must be generated by register */
779 exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
780
781 /* Disable video mute */
782 exynos_dp_enable_video_mute(dp, 0);
783
784 /* Configure video slave mode */
785 exynos_dp_enable_video_master(dp, 0);
786
787 /* Enable video */
788 exynos_dp_start_video(dp);
789
790 timeout_loop = 0;
791
792 for (;;) {
793 timeout_loop++;
794 if (exynos_dp_is_video_stream_on(dp) == 0) {
795 done_count++;
796 if (done_count > 10)
797 break;
798 } else if (done_count) {
799 done_count = 0;
800 }
801 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
802 dev_err(dp->dev, "Timeout of video streamclk ok\n");
803 return -ETIMEDOUT;
804 }
805
a2c81bc1 806 usleep_range(1000, 1001);
e9474be4
JH		 807 }
808
809 if (retval != 0)
810 dev_err(dp->dev, "Video stream is not detected!\n");
811
812 return retval;
813}
814
815static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
816{
817 u8 data;
818
819 if (enable) {
820 exynos_dp_enable_scrambling(dp);
821
822 exynos_dp_read_byte_from_dpcd(dp,
073ea2ae 823 DP_TRAINING_PATTERN_SET,
e9474be4
JH		 824 &data);
825 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 826 DP_TRAINING_PATTERN_SET,
827 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
e9474be4
JH		 828 } else {
829 exynos_dp_disable_scrambling(dp);
830
831 exynos_dp_read_byte_from_dpcd(dp,
073ea2ae 832 DP_TRAINING_PATTERN_SET,
e9474be4
JH		 833 &data);
834 exynos_dp_write_byte_to_dpcd(dp,
073ea2ae
JH		 835 DP_TRAINING_PATTERN_SET,
836 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
e9474be4
JH		 837 }
838}
839
840static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
841{
842 struct exynos_dp_device *dp = arg;
843
c30ffb90
SP		 844 enum dp_irq_type irq_type;
845
846 irq_type = exynos_dp_get_irq_type(dp);
847 switch (irq_type) {
848 case DP_IRQ_TYPE_HP_CABLE_IN:
849 dev_dbg(dp->dev, "Received irq - cable in\n");
850 schedule_work(&dp->hotplug_work);
851 exynos_dp_clear_hotplug_interrupts(dp);
852 break;
853 case DP_IRQ_TYPE_HP_CABLE_OUT:
854 dev_dbg(dp->dev, "Received irq - cable out\n");
855 exynos_dp_clear_hotplug_interrupts(dp);
856 break;
857 case DP_IRQ_TYPE_HP_CHANGE:
858 /*
859 * We get these change notifications once in a while, but there
860 * is nothing we can do with them. Just ignore it for now and
861 * only handle cable changes.
862 */
863 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
864 exynos_dp_clear_hotplug_interrupts(dp);
865 break;
866 default:
867 dev_err(dp->dev, "Received irq - unknown type!\n");
868 break;
869 }
e9474be4
JH		 870 return IRQ_HANDLED;
871}
872
784fa9a1
SP		 873static void exynos_dp_hotplug(struct work_struct *work)
874{
875 struct exynos_dp_device *dp;
784fa9a1
SP		 876
877 dp = container_of(work, struct exynos_dp_device, hotplug_work);
878
4deabfa0
AK		 879 if (dp->drm_dev)
880 drm_helper_hpd_irq_event(dp->drm_dev);
881}
882
883static void exynos_dp_commit(struct exynos_drm_display *display)
884{
885 struct exynos_dp_device *dp = display->ctx;
886 int ret;
887
5f1dcd8b
AK		 888 /* Keep the panel disabled while we configure video */
889 if (dp->panel) {
890 if (drm_panel_disable(dp->panel))
891 DRM_ERROR("failed to disable the panel\n");
892 }
893
784fa9a1
SP		 894 ret = exynos_dp_detect_hpd(dp);
895 if (ret) {
c30ffb90 896 /* Cable has been disconnected, we're done */
784fa9a1
SP		 897 return;
898 }
899
900 ret = exynos_dp_handle_edid(dp);
901 if (ret) {
902 dev_err(dp->dev, "unable to handle edid\n");
903 return;
904 }
905
906 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
907 dp->video_info->link_rate);
908 if (ret) {
909 dev_err(dp->dev, "unable to do link train\n");
910 return;
911 }
912
913 exynos_dp_enable_scramble(dp, 1);
914 exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
915 exynos_dp_enable_enhanced_mode(dp, 1);
916
917 exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
918 exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
919
920 exynos_dp_init_video(dp);
3fcb6eb4 921 ret = exynos_dp_config_video(dp);
784fa9a1
SP		 922 if (ret)
923 dev_err(dp->dev, "unable to config video\n");
5f1dcd8b
AK		 924
925 /* Safe to enable the panel now */
926 if (dp->panel) {
927 if (drm_panel_enable(dp->panel))
928 DRM_ERROR("failed to enable the panel\n");
929 }
784fa9a1
SP		 930}
931
caa5d1e5
SP		 932static enum drm_connector_status exynos_dp_detect(
933 struct drm_connector *connector, bool force)
1417f109 934{
caa5d1e5 935 return connector_status_connected;
1417f109
SP		 936}
937
caa5d1e5 938static void exynos_dp_connector_destroy(struct drm_connector *connector)
1417f109 939{
caa5d1e5
SP		 940}
941
942static struct drm_connector_funcs exynos_dp_connector_funcs = {
943 .dpms = drm_helper_connector_dpms,
944 .fill_modes = drm_helper_probe_single_connector_modes,
945 .detect = exynos_dp_detect,
946 .destroy = exynos_dp_connector_destroy,
947};
948
949static int exynos_dp_get_modes(struct drm_connector *connector)
950{
951 struct exynos_dp_device *dp = ctx_from_connector(connector);
952 struct drm_display_mode *mode;
953
5f1dcd8b
AK		 954 if (dp->panel)
955 return drm_panel_get_modes(dp->panel);
956
caa5d1e5
SP		 957 mode = drm_mode_create(connector->dev);
958 if (!mode) {
959 DRM_ERROR("failed to create a new display mode.\n");
960 return 0;
961 }
962
5f1dcd8b
AK		 963 drm_display_mode_from_videomode(&dp->priv.vm, mode);
964 mode->width_mm = dp->priv.width_mm;
965 mode->height_mm = dp->priv.height_mm;
caa5d1e5
SP		 966 connector->display_info.width_mm = mode->width_mm;
967 connector->display_info.height_mm = mode->height_mm;
968
969 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
970 drm_mode_set_name(mode);
971 drm_mode_probed_add(connector, mode);
1417f109 972
caa5d1e5 973 return 1;
1417f109
SP		 974}
975
caa5d1e5
SP		 976static struct drm_encoder *exynos_dp_best_encoder(
977 struct drm_connector *connector)
978{
979 struct exynos_dp_device *dp = ctx_from_connector(connector);
980
981 return dp->encoder;
982}
983
984static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
985 .get_modes = exynos_dp_get_modes,
caa5d1e5
SP		 986 .best_encoder = exynos_dp_best_encoder,
987};
988
1634ba25
SP		 989static bool find_bridge(const char *compat, struct bridge_init *bridge)
990{
991 bridge->client = NULL;
992 bridge->node = of_find_compatible_node(NULL, NULL, compat);
993 if (!bridge->node)
994 return false;
995
996 bridge->client = of_find_i2c_device_by_node(bridge->node);
997 if (!bridge->client)
998 return false;
999
1000 return true;
1001}
1002
1003/* returns the number of bridges attached */
1004static int exynos_drm_attach_lcd_bridge(struct drm_device *dev,
1005 struct drm_encoder *encoder)
1006{
1007 struct bridge_init bridge;
1008 int ret;
1009
1010 if (find_bridge("nxp,ptn3460", &bridge)) {
1011 ret = ptn3460_init(dev, encoder, bridge.client, bridge.node);
1012 if (!ret)
1013 return 1;
1014 }
1015 return 0;
1016}
1017
caa5d1e5
SP		 1018static int exynos_dp_create_connector(struct exynos_drm_display *display,
1019 struct drm_encoder *encoder)
1020{
1021 struct exynos_dp_device *dp = display->ctx;
1022 struct drm_connector *connector = &dp->connector;
1023 int ret;
1024
1025 dp->encoder = encoder;
1634ba25
SP		 1026
1027 /* Pre-empt DP connector creation if there's a bridge */
1028 ret = exynos_drm_attach_lcd_bridge(dp->drm_dev, encoder);
1029 if (ret)
1030 return 0;
1031
caa5d1e5
SP		 1032 connector->polled = DRM_CONNECTOR_POLL_HPD;
1033
1034 ret = drm_connector_init(dp->drm_dev, connector,
1035 &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1036 if (ret) {
1037 DRM_ERROR("Failed to initialize connector with drm\n");
1038 return ret;
1039 }
1040
1041 drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
1042 drm_sysfs_connector_add(connector);
1043 drm_mode_connector_attach_encoder(connector, encoder);
1044
5f1dcd8b
AK		 1045 if (dp->panel)
1046 ret = drm_panel_attach(dp->panel, &dp->connector);
1047
1048 return ret;
1417f109
SP		 1049}
1050
12f5ad6c
SP		 1051static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1052{
1053 if (dp->phy) {
1054 phy_power_on(dp->phy);
1055 } else if (dp->phy_addr) {
1056 u32 reg;
1057
1058 reg = __raw_readl(dp->phy_addr);
1059 reg |= dp->enable_mask;
1060 __raw_writel(reg, dp->phy_addr);
1061 }
1062}
1063
1064static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1065{
1066 if (dp->phy) {
1067 phy_power_off(dp->phy);
1068 } else if (dp->phy_addr) {
1069 u32 reg;
1070
1071 reg = __raw_readl(dp->phy_addr);
1072 reg &= ~(dp->enable_mask);
1073 __raw_writel(reg, dp->phy_addr);
1074 }
1075}
1076
4deabfa0 1077static void exynos_dp_poweron(struct exynos_drm_display *display)
12f5ad6c 1078{
4deabfa0
AK		 1079 struct exynos_dp_device *dp = display->ctx;
1080
12f5ad6c
SP		 1081 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1082 return;
1083
5f1dcd8b
AK		 1084 if (dp->panel) {
1085 if (drm_panel_prepare(dp->panel)) {
1086 DRM_ERROR("failed to setup the panel\n");
1087 return;
1088 }
1089 }
1090
12f5ad6c
SP		 1091 clk_prepare_enable(dp->clock);
1092 exynos_dp_phy_init(dp);
1093 exynos_dp_init_dp(dp);
1094 enable_irq(dp->irq);
4deabfa0 1095 exynos_dp_commit(display);
12f5ad6c
SP		 1096}
1097
4deabfa0 1098static void exynos_dp_poweroff(struct exynos_drm_display *display)
12f5ad6c 1099{
4deabfa0
AK		 1100 struct exynos_dp_device *dp = display->ctx;
1101
12f5ad6c
SP		 1102 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1103 return;
1104
5f1dcd8b
AK		 1105 if (dp->panel) {
1106 if (drm_panel_disable(dp->panel)) {
1107 DRM_ERROR("failed to disable the panel\n");
1108 return;
1109 }
1110 }
1111
12f5ad6c
SP		 1112 disable_irq(dp->irq);
1113 flush_work(&dp->hotplug_work);
1114 exynos_dp_phy_exit(dp);
1115 clk_disable_unprepare(dp->clock);
5f1dcd8b
AK		 1116
1117 if (dp->panel) {
1118 if (drm_panel_unprepare(dp->panel))
1119 DRM_ERROR("failed to turnoff the panel\n");
1120 }
12f5ad6c
SP		 1121}
1122
1123static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
1124{
1125 struct exynos_dp_device *dp = display->ctx;
1126
1127 switch (mode) {
1128 case DRM_MODE_DPMS_ON:
4deabfa0 1129 exynos_dp_poweron(display);
12f5ad6c
SP		 1130 break;
1131 case DRM_MODE_DPMS_STANDBY:
1132 case DRM_MODE_DPMS_SUSPEND:
1133 case DRM_MODE_DPMS_OFF:
4deabfa0 1134 exynos_dp_poweroff(display);
12f5ad6c
SP		 1135 break;
1136 default:
1137 break;
10d9b4ed 1138 }
12f5ad6c
SP		 1139 dp->dpms_mode = mode;
1140}
1141
1417f109 1142static struct exynos_drm_display_ops exynos_dp_display_ops = {
caa5d1e5 1143 .create_connector = exynos_dp_create_connector,
12f5ad6c 1144 .dpms = exynos_dp_dpms,
4deabfa0 1145 .commit = exynos_dp_commit,
1417f109
SP		 1146};
1147
1148static struct exynos_drm_display exynos_dp_display = {
1149 .type = EXYNOS_DISPLAY_TYPE_LCD,
1150 .ops = &exynos_dp_display_ops,
1151};
1152
f9b1e013 1153static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
c4e235c2
AK		 1154{
1155 struct device_node *dp_node = dev->of_node;
c4e235c2
AK		 1156 struct video_info *dp_video_config;
1157
c4e235c2
AK		 1158 dp_video_config = devm_kzalloc(dev,
1159 sizeof(*dp_video_config), GFP_KERNEL);
7a5b6827 1160 if (!dp_video_config)
c4e235c2 1161 return ERR_PTR(-ENOMEM);
c4e235c2
AK		 1162
1163 dp_video_config->h_sync_polarity =
1164 of_property_read_bool(dp_node, "hsync-active-high");
1165
1166 dp_video_config->v_sync_polarity =
1167 of_property_read_bool(dp_node, "vsync-active-high");
1168
1169 dp_video_config->interlaced =
1170 of_property_read_bool(dp_node, "interlaced");
1171
1172 if (of_property_read_u32(dp_node, "samsung,color-space",
1173 &dp_video_config->color_space)) {
1174 dev_err(dev, "failed to get color-space\n");
1175 return ERR_PTR(-EINVAL);
1176 }
1177
1178 if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1179 &dp_video_config->dynamic_range)) {
1180 dev_err(dev, "failed to get dynamic-range\n");
1181 return ERR_PTR(-EINVAL);
1182 }
1183
1184 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1185 &dp_video_config->ycbcr_coeff)) {
1186 dev_err(dev, "failed to get ycbcr-coeff\n");
1187 return ERR_PTR(-EINVAL);
1188 }
1189
1190 if (of_property_read_u32(dp_node, "samsung,color-depth",
1191 &dp_video_config->color_depth)) {
1192 dev_err(dev, "failed to get color-depth\n");
1193 return ERR_PTR(-EINVAL);
1194 }
1195
1196 if (of_property_read_u32(dp_node, "samsung,link-rate",
1197 &dp_video_config->link_rate)) {
1198 dev_err(dev, "failed to get link-rate\n");
1199 return ERR_PTR(-EINVAL);
1200 }
1201
1202 if (of_property_read_u32(dp_node, "samsung,lane-count",
1203 &dp_video_config->lane_count)) {
1204 dev_err(dev, "failed to get lane-count\n");
1205 return ERR_PTR(-EINVAL);
1206 }
1207
f9b1e013 1208 return dp_video_config;
c4e235c2
AK		 1209}
1210
1211static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
1212{
d3ed9703 1213 struct device_node *dp_phy_node = of_node_get(dp->dev->of_node);
c4e235c2 1214 u32 phy_base;
d3ed9703 1215 int ret = 0;
c4e235c2 1216
d3ed9703 1217 dp_phy_node = of_find_node_by_name(dp_phy_node, "dptx-phy");
c4e235c2 1218 if (!dp_phy_node) {
8114fabc 1219 dp->phy = devm_phy_get(dp->dev, "dp");
97f98a3b 1220 return PTR_ERR_OR_ZERO(dp->phy);
c4e235c2
AK		 1221 }
1222
1223 if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) {
1051e9b3 1224 dev_err(dp->dev, "failed to get reg for dptx-phy\n");
d3ed9703
JH		 1225 ret = -EINVAL;
1226 goto err;
c4e235c2
AK		 1227 }
1228
1229 if (of_property_read_u32(dp_phy_node, "samsung,enable-mask",
1230 &dp->enable_mask)) {
1051e9b3 1231 dev_err(dp->dev, "failed to get enable-mask for dptx-phy\n");
d3ed9703
JH		 1232 ret = -EINVAL;
1233 goto err;
c4e235c2
AK		 1234 }
1235
1236 dp->phy_addr = ioremap(phy_base, SZ_4);
1237 if (!dp->phy_addr) {
1238 dev_err(dp->dev, "failed to ioremap dp-phy\n");
d3ed9703
JH		 1239 ret = -ENOMEM;
1240 goto err;
c4e235c2
AK		 1241 }
1242
d3ed9703
JH		 1243err:
1244 of_node_put(dp_phy_node);
1245
1246 return ret;
c4e235c2
AK		 1247}
1248
1417f109
SP		 1249static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
1250{
1251 int ret;
1252
5f1dcd8b 1253 ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
1417f109
SP		 1254 OF_USE_NATIVE_MODE);
1255 if (ret) {
1256 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
1257 return ret;
1258 }
1259 return 0;
1260}
1261
f37cd5e8 1262static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
e9474be4 1263{
f37cd5e8
ID		 1264 struct platform_device *pdev = to_platform_device(dev);
1265 struct drm_device *drm_dev = data;
e9474be4 1266 struct resource *res;
5f1dcd8b 1267 struct exynos_dp_device *dp = exynos_dp_display.ctx;
b8b52471 1268 unsigned int irq_flags;
e9474be4
JH		 1269 int ret = 0;
1270
e9474be4 1271 dp->dev = &pdev->dev;
12f5ad6c 1272 dp->dpms_mode = DRM_MODE_DPMS_OFF;
e9474be4 1273
f9b1e013
JH		 1274 dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1275 if (IS_ERR(dp->video_info))
1276 return PTR_ERR(dp->video_info);
c4e235c2 1277
f9b1e013
JH		 1278 ret = exynos_dp_dt_parse_phydata(dp);
1279 if (ret)
1280 return ret;
c4e235c2 1281
5f1dcd8b
AK		 1282 if (!dp->panel) {
1283 ret = exynos_dp_dt_parse_panel(dp);
1284 if (ret)
1285 return ret;
1286 }
1417f109 1287
d913f36e 1288 dp->clock = devm_clk_get(&pdev->dev, "dp");
e9474be4
JH		 1289 if (IS_ERR(dp->clock)) {
1290 dev_err(&pdev->dev, "failed to get clock\n");
4d10ecf8 1291 return PTR_ERR(dp->clock);
e9474be4
JH		 1292 }
1293
37414fbe 1294 clk_prepare_enable(dp->clock);
e9474be4
JH		 1295
1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e9474be4 1297
bc3bad16
TR		 1298 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1299 if (IS_ERR(dp->reg_base))
1300 return PTR_ERR(dp->reg_base);
e9474be4 1301
b8b52471
AB		 1302 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
1303
1304 if (gpio_is_valid(dp->hpd_gpio)) {
1305 /*
1306 * Set up the hotplug GPIO from the device tree as an interrupt.
1307 * Simply specifying a different interrupt in the device tree
1308 * doesn't work since we handle hotplug rather differently when
1309 * using a GPIO. We also need the actual GPIO specifier so
1310 * that we can get the current state of the GPIO.
1311 */
1312 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1313 "hpd_gpio");
1314 if (ret) {
1315 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1316 return ret;
1317 }
1318 dp->irq = gpio_to_irq(dp->hpd_gpio);
1319 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1320 } else {
1321 dp->hpd_gpio = -ENODEV;
1322 dp->irq = platform_get_irq(pdev, 0);
1323 irq_flags = 0;
1324 }
1325
1cefc1d6 1326 if (dp->irq == -ENXIO) {
e9474be4 1327 dev_err(&pdev->dev, "failed to get irq\n");
d913f36e 1328 return -ENODEV;
e9474be4
JH		 1329 }
1330
784fa9a1
SP		 1331 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1332
f9b1e013 1333 exynos_dp_phy_init(dp);
e9474be4
JH		 1334
1335 exynos_dp_init_dp(dp);
1336
b8b52471
AB		 1337 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
1338 irq_flags, "exynos-dp", dp);
22ce19cb
AK		 1339 if (ret) {
1340 dev_err(&pdev->dev, "failed to request irq\n");
1341 return ret;
1342 }
12f5ad6c 1343 disable_irq(dp->irq);
e9474be4 1344
f37cd5e8 1345 dp->drm_dev = drm_dev;
12f5ad6c
SP		 1346
1347 platform_set_drvdata(pdev, &exynos_dp_display);
1417f109 1348
f37cd5e8 1349 return exynos_drm_create_enc_conn(drm_dev, &exynos_dp_display);
e9474be4
JH		 1350}
1351
f37cd5e8
ID		 1352static void exynos_dp_unbind(struct device *dev, struct device *master,
1353 void *data)
e9474be4 1354{
f37cd5e8
ID		 1355 struct exynos_drm_display *display = dev_get_drvdata(dev);
1356 struct exynos_dp_device *dp = display->ctx;
1357 struct drm_encoder *encoder = dp->encoder;
e9474be4 1358
12f5ad6c 1359 exynos_dp_dpms(display, DRM_MODE_DPMS_OFF);
1417f109 1360
f37cd5e8
ID		 1361 encoder->funcs->destroy(encoder);
1362 drm_connector_cleanup(&dp->connector);
1363}
1364
1365static const struct component_ops exynos_dp_ops = {
1366 .bind = exynos_dp_bind,
1367 .unbind = exynos_dp_unbind,
1368};
1369
1370static int exynos_dp_probe(struct platform_device *pdev)
1371{
5f1dcd8b
AK		 1372 struct device *dev = &pdev->dev;
1373 struct device_node *panel_node;
1374 struct exynos_dp_device *dp;
df5225bc
ID		 1375 int ret;
1376
1377 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1378 exynos_dp_display.type);
1379 if (ret)
1380 return ret;
1381
5f1dcd8b
AK		 1382 dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1383 GFP_KERNEL);
1384 if (!dp)
1385 return -ENOMEM;
1386
1387 panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1388 if (panel_node) {
1389 dp->panel = of_drm_find_panel(panel_node);
1390 of_node_put(panel_node);
1391 if (!dp->panel)
1392 return -EPROBE_DEFER;
1393 }
1394
1395 exynos_dp_display.ctx = dp;
1396
df5225bc
ID		 1397 ret = component_add(&pdev->dev, &exynos_dp_ops);
1398 if (ret)
1399 exynos_drm_component_del(&pdev->dev,
1400 EXYNOS_DEVICE_TYPE_CONNECTOR);
1401
1402 return ret;
f37cd5e8
ID		 1403}
1404
1405static int exynos_dp_remove(struct platform_device *pdev)
1406{
df5225bc
ID		 1407 component_del(&pdev->dev, &exynos_dp_ops);
1408 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1409
e9474be4
JH		 1410 return 0;
1411}
1412
1413#ifdef CONFIG_PM_SLEEP
1414static int exynos_dp_suspend(struct device *dev)
1415{
12f5ad6c
SP		 1416 struct platform_device *pdev = to_platform_device(dev);
1417 struct exynos_drm_display *display = platform_get_drvdata(pdev);
e9474be4 1418
12f5ad6c 1419 exynos_dp_dpms(display, DRM_MODE_DPMS_OFF);
e9474be4
JH		 1420 return 0;
1421}
1422
1423static int exynos_dp_resume(struct device *dev)
1424{
12f5ad6c
SP		 1425 struct platform_device *pdev = to_platform_device(dev);
1426 struct exynos_drm_display *display = platform_get_drvdata(pdev);
e9474be4 1427
12f5ad6c 1428 exynos_dp_dpms(display, DRM_MODE_DPMS_ON);
e9474be4
JH		 1429 return 0;
1430}
1431#endif
1432
1433static const struct dev_pm_ops exynos_dp_pm_ops = {
1434 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1435};
1436
c4e235c2
AK		 1437static const struct of_device_id exynos_dp_match[] = {
1438 { .compatible = "samsung,exynos5-dp" },
1439 {},
1440};
c4e235c2 1441
1417f109 1442struct platform_driver dp_driver = {
e9474be4 1443 .probe = exynos_dp_probe,
48c68c4f 1444 .remove = exynos_dp_remove,
e9474be4
JH		 1445 .driver = {
1446 .name = "exynos-dp",
1447 .owner = THIS_MODULE,
1448 .pm = &exynos_dp_pm_ops,
f9b1e013 1449 .of_match_table = exynos_dp_match,
e9474be4
JH		 1450 },
1451};
1452
e9474be4
JH		 1453MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1454MODULE_DESCRIPTION("Samsung SoC DP Driver");
1455MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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