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e9474be4 JH |
1 | /* |
2 | * Header file for Samsung DP (Display Port) interface driver. | |
3 | * | |
4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. | |
5 | * Author: Jingoo Han <jg1.han@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #ifndef _EXYNOS_DP_CORE_H | |
14 | #define _EXYNOS_DP_CORE_H | |
15 | ||
caa5d1e5 | 16 | #include <drm/drm_crtc.h> |
073ea2ae | 17 | #include <drm/drm_dp_helper.h> |
1417f109 | 18 | #include <drm/exynos_drm.h> |
27d60e3d | 19 | #include <video/videomode.h> |
1417f109 | 20 | |
1df6e5fb AH |
21 | #include "exynos_drm_drv.h" |
22 | ||
f9b1e013 JH |
23 | #define DP_TIMEOUT_LOOP_COUNT 100 |
24 | #define MAX_CR_LOOP 5 | |
25 | #define MAX_EQ_LOOP 5 | |
26 | ||
27 | enum link_rate_type { | |
28 | LINK_RATE_1_62GBPS = 0x06, | |
29 | LINK_RATE_2_70GBPS = 0x0a | |
30 | }; | |
31 | ||
32 | enum link_lane_count_type { | |
33 | LANE_COUNT1 = 1, | |
34 | LANE_COUNT2 = 2, | |
35 | LANE_COUNT4 = 4 | |
36 | }; | |
37 | ||
38 | enum link_training_state { | |
39 | START, | |
40 | CLOCK_RECOVERY, | |
41 | EQUALIZER_TRAINING, | |
42 | FINISHED, | |
43 | FAILED | |
44 | }; | |
45 | ||
46 | enum voltage_swing_level { | |
47 | VOLTAGE_LEVEL_0, | |
48 | VOLTAGE_LEVEL_1, | |
49 | VOLTAGE_LEVEL_2, | |
50 | VOLTAGE_LEVEL_3, | |
51 | }; | |
52 | ||
53 | enum pre_emphasis_level { | |
54 | PRE_EMPHASIS_LEVEL_0, | |
55 | PRE_EMPHASIS_LEVEL_1, | |
56 | PRE_EMPHASIS_LEVEL_2, | |
57 | PRE_EMPHASIS_LEVEL_3, | |
58 | }; | |
59 | ||
60 | enum pattern_set { | |
61 | PRBS7, | |
62 | D10_2, | |
63 | TRAINING_PTN1, | |
64 | TRAINING_PTN2, | |
65 | DP_NONE | |
66 | }; | |
67 | ||
68 | enum color_space { | |
69 | COLOR_RGB, | |
70 | COLOR_YCBCR422, | |
71 | COLOR_YCBCR444 | |
72 | }; | |
73 | ||
74 | enum color_depth { | |
75 | COLOR_6, | |
76 | COLOR_8, | |
77 | COLOR_10, | |
78 | COLOR_12 | |
79 | }; | |
80 | ||
81 | enum color_coefficient { | |
82 | COLOR_YCBCR601, | |
83 | COLOR_YCBCR709 | |
84 | }; | |
85 | ||
86 | enum dynamic_range { | |
87 | VESA, | |
88 | CEA | |
89 | }; | |
90 | ||
91 | enum pll_status { | |
92 | PLL_UNLOCKED, | |
93 | PLL_LOCKED | |
94 | }; | |
95 | ||
96 | enum clock_recovery_m_value_type { | |
97 | CALCULATED_M, | |
98 | REGISTER_M | |
99 | }; | |
100 | ||
101 | enum video_timing_recognition_type { | |
102 | VIDEO_TIMING_FROM_CAPTURE, | |
103 | VIDEO_TIMING_FROM_REGISTER | |
104 | }; | |
105 | ||
106 | enum analog_power_block { | |
107 | AUX_BLOCK, | |
108 | CH0_BLOCK, | |
109 | CH1_BLOCK, | |
110 | CH2_BLOCK, | |
111 | CH3_BLOCK, | |
112 | ANALOG_TOTAL, | |
113 | POWER_ALL | |
114 | }; | |
115 | ||
c30ffb90 SP |
116 | enum dp_irq_type { |
117 | DP_IRQ_TYPE_HP_CABLE_IN, | |
118 | DP_IRQ_TYPE_HP_CABLE_OUT, | |
119 | DP_IRQ_TYPE_HP_CHANGE, | |
120 | DP_IRQ_TYPE_UNKNOWN, | |
121 | }; | |
122 | ||
f9b1e013 JH |
123 | struct video_info { |
124 | char *name; | |
125 | ||
126 | bool h_sync_polarity; | |
127 | bool v_sync_polarity; | |
128 | bool interlaced; | |
129 | ||
130 | enum color_space color_space; | |
131 | enum dynamic_range dynamic_range; | |
132 | enum color_coefficient ycbcr_coeff; | |
133 | enum color_depth color_depth; | |
134 | ||
135 | enum link_rate_type link_rate; | |
136 | enum link_lane_count_type lane_count; | |
137 | }; | |
138 | ||
e9474be4 JH |
139 | struct link_train { |
140 | int eq_loop; | |
141 | int cr_loop[4]; | |
142 | ||
143 | u8 link_rate; | |
144 | u8 lane_count; | |
145 | u8 training_lane[4]; | |
146 | ||
147 | enum link_training_state lt_state; | |
148 | }; | |
149 | ||
150 | struct exynos_dp_device { | |
2b8376c8 | 151 | struct drm_encoder encoder; |
e9474be4 | 152 | struct device *dev; |
caa5d1e5 SP |
153 | struct drm_device *drm_dev; |
154 | struct drm_connector connector; | |
5f1dcd8b | 155 | struct drm_panel *panel; |
80185567 | 156 | struct drm_bridge *bridge; |
07c42703 | 157 | struct drm_bridge *ptn_bridge; |
e9474be4 JH |
158 | struct clk *clock; |
159 | unsigned int irq; | |
160 | void __iomem *reg_base; | |
161 | ||
162 | struct video_info *video_info; | |
163 | struct link_train link_train; | |
784fa9a1 | 164 | struct work_struct hotplug_work; |
8114fabc | 165 | struct phy *phy; |
12f5ad6c | 166 | int dpms_mode; |
b8b52471 | 167 | int hpd_gpio; |
27d60e3d | 168 | struct videomode vm; |
e9474be4 JH |
169 | }; |
170 | ||
171 | /* exynos_dp_reg.c */ | |
172 | void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable); | |
173 | void exynos_dp_stop_video(struct exynos_dp_device *dp); | |
174 | void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable); | |
8affaf5c | 175 | void exynos_dp_init_analog_param(struct exynos_dp_device *dp); |
e9474be4 JH |
176 | void exynos_dp_init_interrupt(struct exynos_dp_device *dp); |
177 | void exynos_dp_reset(struct exynos_dp_device *dp); | |
24db03a8 | 178 | void exynos_dp_swreset(struct exynos_dp_device *dp); |
e9474be4 | 179 | void exynos_dp_config_interrupt(struct exynos_dp_device *dp); |
09d00d17 | 180 | enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp); |
e9474be4 JH |
181 | void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable); |
182 | void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, | |
183 | enum analog_power_block block, | |
184 | bool enable); | |
185 | void exynos_dp_init_analog_func(struct exynos_dp_device *dp); | |
186 | void exynos_dp_init_hpd(struct exynos_dp_device *dp); | |
c30ffb90 SP |
187 | enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp); |
188 | void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp); | |
e9474be4 JH |
189 | void exynos_dp_reset_aux(struct exynos_dp_device *dp); |
190 | void exynos_dp_init_aux(struct exynos_dp_device *dp); | |
191 | int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp); | |
192 | void exynos_dp_enable_sw_function(struct exynos_dp_device *dp); | |
193 | int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp); | |
194 | int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, | |
195 | unsigned int reg_addr, | |
196 | unsigned char data); | |
197 | int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, | |
198 | unsigned int reg_addr, | |
199 | unsigned char *data); | |
200 | int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, | |
201 | unsigned int reg_addr, | |
202 | unsigned int count, | |
203 | unsigned char data[]); | |
204 | int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, | |
205 | unsigned int reg_addr, | |
206 | unsigned int count, | |
207 | unsigned char data[]); | |
208 | int exynos_dp_select_i2c_device(struct exynos_dp_device *dp, | |
209 | unsigned int device_addr, | |
210 | unsigned int reg_addr); | |
211 | int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, | |
212 | unsigned int device_addr, | |
213 | unsigned int reg_addr, | |
214 | unsigned int *data); | |
215 | int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, | |
216 | unsigned int device_addr, | |
217 | unsigned int reg_addr, | |
218 | unsigned int count, | |
219 | unsigned char edid[]); | |
220 | void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype); | |
221 | void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype); | |
222 | void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count); | |
223 | void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count); | |
e9474be4 JH |
224 | void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable); |
225 | void exynos_dp_set_training_pattern(struct exynos_dp_device *dp, | |
226 | enum pattern_set pattern); | |
227 | void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level); | |
228 | void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level); | |
229 | void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level); | |
230 | void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level); | |
231 | void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp, | |
232 | u32 training_lane); | |
233 | void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp, | |
234 | u32 training_lane); | |
235 | void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp, | |
236 | u32 training_lane); | |
237 | void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp, | |
238 | u32 training_lane); | |
239 | u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp); | |
240 | u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp); | |
241 | u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp); | |
242 | u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp); | |
243 | void exynos_dp_reset_macro(struct exynos_dp_device *dp); | |
1ec7be9c | 244 | void exynos_dp_init_video(struct exynos_dp_device *dp); |
e9474be4 | 245 | |
3fcb6eb4 | 246 | void exynos_dp_set_video_color_format(struct exynos_dp_device *dp); |
e9474be4 JH |
247 | int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp); |
248 | void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp, | |
249 | enum clock_recovery_m_value_type type, | |
250 | u32 m_value, | |
251 | u32 n_value); | |
252 | void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type); | |
253 | void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable); | |
254 | void exynos_dp_start_video(struct exynos_dp_device *dp); | |
255 | int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp); | |
3fcb6eb4 | 256 | void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp); |
e9474be4 JH |
257 | void exynos_dp_enable_scrambling(struct exynos_dp_device *dp); |
258 | void exynos_dp_disable_scrambling(struct exynos_dp_device *dp); | |
259 | ||
260 | /* I2C EDID Chip ID, Slave Address */ | |
261 | #define I2C_EDID_DEVICE_ADDR 0x50 | |
262 | #define I2C_E_EDID_DEVICE_ADDR 0x30 | |
263 | ||
264 | #define EDID_BLOCK_LENGTH 0x80 | |
265 | #define EDID_HEADER_PATTERN 0x00 | |
266 | #define EDID_EXTENSION_FLAG 0x7e | |
267 | #define EDID_CHECKSUM 0x7f | |
268 | ||
073ea2ae | 269 | /* DP_MAX_LANE_COUNT */ |
e9474be4 JH |
270 | #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) |
271 | #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) | |
272 | ||
073ea2ae | 273 | /* DP_LANE_COUNT_SET */ |
e9474be4 JH |
274 | #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) |
275 | ||
073ea2ae | 276 | /* DP_TRAINING_LANE0_SET */ |
e9474be4 JH |
277 | #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) |
278 | #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) | |
e9474be4 JH |
279 | #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) |
280 | #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) | |
e9474be4 JH |
281 | |
282 | #endif /* _EXYNOS_DP_CORE_H */ |