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7eb8f069 AH |
1 | /* |
2 | * Samsung SoC MIPI DSI Master driver. | |
3 | * | |
4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd | |
5 | * | |
6 | * Contacts: Tomasz Figa <t.figa@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <drm/drmP.h> | |
14 | #include <drm/drm_crtc_helper.h> | |
15 | #include <drm/drm_mipi_dsi.h> | |
16 | #include <drm/drm_panel.h> | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/phy/phy.h> | |
21 | #include <linux/regulator/consumer.h> | |
f37cd5e8 | 22 | #include <linux/component.h> |
7eb8f069 AH |
23 | |
24 | #include <video/mipi_display.h> | |
25 | #include <video/videomode.h> | |
26 | ||
27 | #include "exynos_drm_drv.h" | |
28 | ||
29 | /* returns true iff both arguments logically differs */ | |
30 | #define NEQV(a, b) (!(a) ^ !(b)) | |
31 | ||
32 | #define DSIM_STATUS_REG 0x0 /* Status register */ | |
33 | #define DSIM_SWRST_REG 0x4 /* Software reset register */ | |
34 | #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */ | |
35 | #define DSIM_TIMEOUT_REG 0xc /* Time out register */ | |
36 | #define DSIM_CONFIG_REG 0x10 /* Configuration register */ | |
37 | #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */ | |
38 | ||
39 | /* Main display image resolution register */ | |
40 | #define DSIM_MDRESOL_REG 0x18 | |
41 | #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */ | |
42 | #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */ | |
43 | #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */ | |
44 | ||
45 | /* Sub display image resolution register */ | |
46 | #define DSIM_SDRESOL_REG 0x28 | |
47 | #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */ | |
48 | #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */ | |
49 | #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */ | |
50 | #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */ | |
51 | #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */ | |
52 | #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */ | |
53 | #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */ | |
54 | ||
55 | /* FIFO memory AC characteristic register */ | |
56 | #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */ | |
57 | #define DSIM_PLLTMR_REG 0x50 /* PLL timer register */ | |
58 | #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */ | |
59 | #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */ | |
60 | ||
61 | /* DSIM_STATUS */ | |
62 | #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) | |
63 | #define DSIM_STOP_STATE_CLK (1 << 8) | |
64 | #define DSIM_TX_READY_HS_CLK (1 << 10) | |
65 | #define DSIM_PLL_STABLE (1 << 31) | |
66 | ||
67 | /* DSIM_SWRST */ | |
68 | #define DSIM_FUNCRST (1 << 16) | |
69 | #define DSIM_SWRST (1 << 0) | |
70 | ||
71 | /* DSIM_TIMEOUT */ | |
72 | #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) | |
73 | #define DSIM_BTA_TIMEOUT(x) ((x) << 16) | |
74 | ||
75 | /* DSIM_CLKCTRL */ | |
76 | #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) | |
77 | #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) | |
78 | #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) | |
79 | #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) | |
80 | #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) | |
81 | #define DSIM_BYTE_CLKEN (1 << 24) | |
82 | #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) | |
83 | #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) | |
84 | #define DSIM_PLL_BYPASS (1 << 27) | |
85 | #define DSIM_ESC_CLKEN (1 << 28) | |
86 | #define DSIM_TX_REQUEST_HSCLK (1 << 31) | |
87 | ||
88 | /* DSIM_CONFIG */ | |
89 | #define DSIM_LANE_EN_CLK (1 << 0) | |
90 | #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) | |
91 | #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) | |
92 | #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) | |
93 | #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) | |
94 | #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) | |
95 | #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) | |
96 | #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) | |
97 | #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) | |
98 | #define DSIM_SUB_VC (((x) & 0x3) << 16) | |
99 | #define DSIM_MAIN_VC (((x) & 0x3) << 18) | |
100 | #define DSIM_HSA_MODE (1 << 20) | |
101 | #define DSIM_HBP_MODE (1 << 21) | |
102 | #define DSIM_HFP_MODE (1 << 22) | |
103 | #define DSIM_HSE_MODE (1 << 23) | |
104 | #define DSIM_AUTO_MODE (1 << 24) | |
105 | #define DSIM_VIDEO_MODE (1 << 25) | |
106 | #define DSIM_BURST_MODE (1 << 26) | |
107 | #define DSIM_SYNC_INFORM (1 << 27) | |
108 | #define DSIM_EOT_DISABLE (1 << 28) | |
109 | #define DSIM_MFLUSH_VS (1 << 29) | |
110 | ||
111 | /* DSIM_ESCMODE */ | |
112 | #define DSIM_TX_TRIGGER_RST (1 << 4) | |
113 | #define DSIM_TX_LPDT_LP (1 << 6) | |
114 | #define DSIM_CMD_LPDT_LP (1 << 7) | |
115 | #define DSIM_FORCE_BTA (1 << 16) | |
116 | #define DSIM_FORCE_STOP_STATE (1 << 20) | |
117 | #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) | |
118 | #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) | |
119 | ||
120 | /* DSIM_MDRESOL */ | |
121 | #define DSIM_MAIN_STAND_BY (1 << 31) | |
122 | #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) | |
123 | #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) | |
124 | ||
125 | /* DSIM_MVPORCH */ | |
126 | #define DSIM_CMD_ALLOW(x) ((x) << 28) | |
127 | #define DSIM_STABLE_VFP(x) ((x) << 16) | |
128 | #define DSIM_MAIN_VBP(x) ((x) << 0) | |
129 | #define DSIM_CMD_ALLOW_MASK (0xf << 28) | |
130 | #define DSIM_STABLE_VFP_MASK (0x7ff << 16) | |
131 | #define DSIM_MAIN_VBP_MASK (0x7ff << 0) | |
132 | ||
133 | /* DSIM_MHPORCH */ | |
134 | #define DSIM_MAIN_HFP(x) ((x) << 16) | |
135 | #define DSIM_MAIN_HBP(x) ((x) << 0) | |
136 | #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) | |
137 | #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) | |
138 | ||
139 | /* DSIM_MSYNC */ | |
140 | #define DSIM_MAIN_VSA(x) ((x) << 22) | |
141 | #define DSIM_MAIN_HSA(x) ((x) << 0) | |
142 | #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) | |
143 | #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) | |
144 | ||
145 | /* DSIM_SDRESOL */ | |
146 | #define DSIM_SUB_STANDY(x) ((x) << 31) | |
147 | #define DSIM_SUB_VRESOL(x) ((x) << 16) | |
148 | #define DSIM_SUB_HRESOL(x) ((x) << 0) | |
149 | #define DSIM_SUB_STANDY_MASK ((0x1) << 31) | |
150 | #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) | |
151 | #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) | |
152 | ||
153 | /* DSIM_INTSRC */ | |
154 | #define DSIM_INT_PLL_STABLE (1 << 31) | |
155 | #define DSIM_INT_SW_RST_RELEASE (1 << 30) | |
156 | #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) | |
157 | #define DSIM_INT_BTA (1 << 25) | |
158 | #define DSIM_INT_FRAME_DONE (1 << 24) | |
159 | #define DSIM_INT_RX_TIMEOUT (1 << 21) | |
160 | #define DSIM_INT_BTA_TIMEOUT (1 << 20) | |
161 | #define DSIM_INT_RX_DONE (1 << 18) | |
162 | #define DSIM_INT_RX_TE (1 << 17) | |
163 | #define DSIM_INT_RX_ACK (1 << 16) | |
164 | #define DSIM_INT_RX_ECC_ERR (1 << 15) | |
165 | #define DSIM_INT_RX_CRC_ERR (1 << 14) | |
166 | ||
167 | /* DSIM_FIFOCTRL */ | |
168 | #define DSIM_RX_DATA_FULL (1 << 25) | |
169 | #define DSIM_RX_DATA_EMPTY (1 << 24) | |
170 | #define DSIM_SFR_HEADER_FULL (1 << 23) | |
171 | #define DSIM_SFR_HEADER_EMPTY (1 << 22) | |
172 | #define DSIM_SFR_PAYLOAD_FULL (1 << 21) | |
173 | #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) | |
174 | #define DSIM_I80_HEADER_FULL (1 << 19) | |
175 | #define DSIM_I80_HEADER_EMPTY (1 << 18) | |
176 | #define DSIM_I80_PAYLOAD_FULL (1 << 17) | |
177 | #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) | |
178 | #define DSIM_SD_HEADER_FULL (1 << 15) | |
179 | #define DSIM_SD_HEADER_EMPTY (1 << 14) | |
180 | #define DSIM_SD_PAYLOAD_FULL (1 << 13) | |
181 | #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) | |
182 | #define DSIM_MD_HEADER_FULL (1 << 11) | |
183 | #define DSIM_MD_HEADER_EMPTY (1 << 10) | |
184 | #define DSIM_MD_PAYLOAD_FULL (1 << 9) | |
185 | #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) | |
186 | #define DSIM_RX_FIFO (1 << 4) | |
187 | #define DSIM_SFR_FIFO (1 << 3) | |
188 | #define DSIM_I80_FIFO (1 << 2) | |
189 | #define DSIM_SD_FIFO (1 << 1) | |
190 | #define DSIM_MD_FIFO (1 << 0) | |
191 | ||
192 | /* DSIM_PHYACCHR */ | |
193 | #define DSIM_AFC_EN (1 << 14) | |
194 | #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) | |
195 | ||
196 | /* DSIM_PLLCTRL */ | |
197 | #define DSIM_FREQ_BAND(x) ((x) << 24) | |
198 | #define DSIM_PLL_EN (1 << 23) | |
199 | #define DSIM_PLL_P(x) ((x) << 13) | |
200 | #define DSIM_PLL_M(x) ((x) << 4) | |
201 | #define DSIM_PLL_S(x) ((x) << 1) | |
202 | ||
203 | #define DSI_MAX_BUS_WIDTH 4 | |
204 | #define DSI_NUM_VIRTUAL_CHANNELS 4 | |
205 | #define DSI_TX_FIFO_SIZE 2048 | |
206 | #define DSI_RX_FIFO_SIZE 256 | |
207 | #define DSI_XFER_TIMEOUT_MS 100 | |
208 | #define DSI_RX_FIFO_EMPTY 0x30800002 | |
209 | ||
210 | enum exynos_dsi_transfer_type { | |
211 | EXYNOS_DSI_TX, | |
212 | EXYNOS_DSI_RX, | |
213 | }; | |
214 | ||
215 | struct exynos_dsi_transfer { | |
216 | struct list_head list; | |
217 | struct completion completed; | |
218 | int result; | |
219 | u8 data_id; | |
220 | u8 data[2]; | |
221 | u16 flags; | |
222 | ||
223 | const u8 *tx_payload; | |
224 | u16 tx_len; | |
225 | u16 tx_done; | |
226 | ||
227 | u8 *rx_payload; | |
228 | u16 rx_len; | |
229 | u16 rx_done; | |
230 | }; | |
231 | ||
232 | #define DSIM_STATE_ENABLED BIT(0) | |
233 | #define DSIM_STATE_INITIALIZED BIT(1) | |
234 | #define DSIM_STATE_CMD_LPM BIT(2) | |
235 | ||
236 | struct exynos_dsi { | |
237 | struct mipi_dsi_host dsi_host; | |
238 | struct drm_connector connector; | |
239 | struct drm_encoder *encoder; | |
240 | struct device_node *panel_node; | |
241 | struct drm_panel *panel; | |
242 | struct device *dev; | |
243 | ||
244 | void __iomem *reg_base; | |
245 | struct phy *phy; | |
246 | struct clk *pll_clk; | |
247 | struct clk *bus_clk; | |
248 | struct regulator_bulk_data supplies[2]; | |
249 | int irq; | |
250 | ||
251 | u32 pll_clk_rate; | |
252 | u32 burst_clk_rate; | |
253 | u32 esc_clk_rate; | |
254 | u32 lanes; | |
255 | u32 mode_flags; | |
256 | u32 format; | |
257 | struct videomode vm; | |
258 | ||
259 | int state; | |
260 | struct drm_property *brightness; | |
261 | struct completion completed; | |
262 | ||
263 | spinlock_t transfer_lock; /* protects transfer_list */ | |
264 | struct list_head transfer_list; | |
265 | }; | |
266 | ||
267 | #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) | |
268 | #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) | |
269 | ||
270 | static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) | |
271 | { | |
272 | if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) | |
273 | return; | |
274 | ||
275 | dev_err(dsi->dev, "timeout waiting for reset\n"); | |
276 | } | |
277 | ||
278 | static void exynos_dsi_reset(struct exynos_dsi *dsi) | |
279 | { | |
280 | reinit_completion(&dsi->completed); | |
281 | writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG); | |
282 | } | |
283 | ||
284 | #ifndef MHZ | |
285 | #define MHZ (1000*1000) | |
286 | #endif | |
287 | ||
288 | static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, | |
289 | unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) | |
290 | { | |
291 | unsigned long best_freq = 0; | |
292 | u32 min_delta = 0xffffffff; | |
293 | u8 p_min, p_max; | |
294 | u8 _p, uninitialized_var(best_p); | |
295 | u16 _m, uninitialized_var(best_m); | |
296 | u8 _s, uninitialized_var(best_s); | |
297 | ||
298 | p_min = DIV_ROUND_UP(fin, (12 * MHZ)); | |
299 | p_max = fin / (6 * MHZ); | |
300 | ||
301 | for (_p = p_min; _p <= p_max; ++_p) { | |
302 | for (_s = 0; _s <= 5; ++_s) { | |
303 | u64 tmp; | |
304 | u32 delta; | |
305 | ||
306 | tmp = (u64)fout * (_p << _s); | |
307 | do_div(tmp, fin); | |
308 | _m = tmp; | |
309 | if (_m < 41 || _m > 125) | |
310 | continue; | |
311 | ||
312 | tmp = (u64)_m * fin; | |
313 | do_div(tmp, _p); | |
314 | if (tmp < 500 * MHZ || tmp > 1000 * MHZ) | |
315 | continue; | |
316 | ||
317 | tmp = (u64)_m * fin; | |
318 | do_div(tmp, _p << _s); | |
319 | ||
320 | delta = abs(fout - tmp); | |
321 | if (delta < min_delta) { | |
322 | best_p = _p; | |
323 | best_m = _m; | |
324 | best_s = _s; | |
325 | min_delta = delta; | |
326 | best_freq = tmp; | |
327 | } | |
328 | } | |
329 | } | |
330 | ||
331 | if (best_freq) { | |
332 | *p = best_p; | |
333 | *m = best_m; | |
334 | *s = best_s; | |
335 | } | |
336 | ||
337 | return best_freq; | |
338 | } | |
339 | ||
340 | static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, | |
341 | unsigned long freq) | |
342 | { | |
343 | static const unsigned long freq_bands[] = { | |
344 | 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, | |
345 | 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, | |
346 | 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, | |
347 | 770 * MHZ, 870 * MHZ, 950 * MHZ, | |
348 | }; | |
349 | unsigned long fin, fout; | |
350 | int timeout, band; | |
351 | u8 p, s; | |
352 | u16 m; | |
353 | u32 reg; | |
354 | ||
355 | clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); | |
356 | ||
357 | fin = clk_get_rate(dsi->pll_clk); | |
358 | if (!fin) { | |
359 | dev_err(dsi->dev, "failed to get PLL clock frequency\n"); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin); | |
364 | ||
365 | fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); | |
366 | if (!fout) { | |
367 | dev_err(dsi->dev, | |
368 | "failed to find PLL PMS for requested frequency\n"); | |
369 | return -EFAULT; | |
370 | } | |
371 | ||
372 | for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) | |
373 | if (fout < freq_bands[band]) | |
374 | break; | |
375 | ||
376 | dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d), band %d\n", fout, | |
377 | p, m, s, band); | |
378 | ||
379 | writel(500, dsi->reg_base + DSIM_PLLTMR_REG); | |
380 | ||
381 | reg = DSIM_FREQ_BAND(band) | DSIM_PLL_EN | |
382 | | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); | |
383 | writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); | |
384 | ||
385 | timeout = 1000; | |
386 | do { | |
387 | if (timeout-- == 0) { | |
388 | dev_err(dsi->dev, "PLL failed to stabilize\n"); | |
389 | return -EFAULT; | |
390 | } | |
391 | reg = readl(dsi->reg_base + DSIM_STATUS_REG); | |
392 | } while ((reg & DSIM_PLL_STABLE) == 0); | |
393 | ||
394 | return fout; | |
395 | } | |
396 | ||
397 | static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | |
398 | { | |
399 | unsigned long hs_clk, byte_clk, esc_clk; | |
400 | unsigned long esc_div; | |
401 | u32 reg; | |
402 | ||
403 | hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); | |
404 | if (!hs_clk) { | |
405 | dev_err(dsi->dev, "failed to configure DSI PLL\n"); | |
406 | return -EFAULT; | |
407 | } | |
408 | ||
409 | byte_clk = hs_clk / 8; | |
410 | esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); | |
411 | esc_clk = byte_clk / esc_div; | |
412 | ||
413 | if (esc_clk > 20 * MHZ) { | |
414 | ++esc_div; | |
415 | esc_clk = byte_clk / esc_div; | |
416 | } | |
417 | ||
418 | dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", | |
419 | hs_clk, byte_clk, esc_clk); | |
420 | ||
421 | reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); | |
422 | reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK | |
423 | | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS | |
424 | | DSIM_BYTE_CLK_SRC_MASK); | |
425 | reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN | |
426 | | DSIM_ESC_PRESCALER(esc_div) | |
427 | | DSIM_LANE_ESC_CLK_EN_CLK | |
428 | | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) | |
429 | | DSIM_BYTE_CLK_SRC(0) | |
430 | | DSIM_TX_REQUEST_HSCLK; | |
431 | writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) | |
437 | { | |
438 | u32 reg; | |
439 | ||
440 | reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); | |
441 | reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK | |
442 | | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); | |
443 | writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); | |
444 | ||
445 | reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG); | |
446 | reg &= ~DSIM_PLL_EN; | |
447 | writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); | |
448 | } | |
449 | ||
450 | static int exynos_dsi_init_link(struct exynos_dsi *dsi) | |
451 | { | |
452 | int timeout; | |
453 | u32 reg; | |
454 | u32 lanes_mask; | |
455 | ||
456 | /* Initialize FIFO pointers */ | |
457 | reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG); | |
458 | reg &= ~0x1f; | |
459 | writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG); | |
460 | ||
461 | usleep_range(9000, 11000); | |
462 | ||
463 | reg |= 0x1f; | |
464 | writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG); | |
465 | ||
466 | usleep_range(9000, 11000); | |
467 | ||
468 | /* DSI configuration */ | |
469 | reg = 0; | |
470 | ||
2f36e33a YC |
471 | /* |
472 | * The first bit of mode_flags specifies display configuration. | |
473 | * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video | |
474 | * mode, otherwise it will support command mode. | |
475 | */ | |
7eb8f069 AH |
476 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
477 | reg |= DSIM_VIDEO_MODE; | |
478 | ||
2f36e33a YC |
479 | /* |
480 | * The user manual describes that following bits are ignored in | |
481 | * command mode. | |
482 | */ | |
7eb8f069 AH |
483 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) |
484 | reg |= DSIM_MFLUSH_VS; | |
7eb8f069 AH |
485 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
486 | reg |= DSIM_SYNC_INFORM; | |
487 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
488 | reg |= DSIM_BURST_MODE; | |
489 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) | |
490 | reg |= DSIM_AUTO_MODE; | |
491 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) | |
492 | reg |= DSIM_HSE_MODE; | |
493 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) | |
494 | reg |= DSIM_HFP_MODE; | |
495 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) | |
496 | reg |= DSIM_HBP_MODE; | |
497 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) | |
498 | reg |= DSIM_HSA_MODE; | |
499 | } | |
500 | ||
2f36e33a YC |
501 | if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) |
502 | reg |= DSIM_EOT_DISABLE; | |
503 | ||
7eb8f069 AH |
504 | switch (dsi->format) { |
505 | case MIPI_DSI_FMT_RGB888: | |
506 | reg |= DSIM_MAIN_PIX_FORMAT_RGB888; | |
507 | break; | |
508 | case MIPI_DSI_FMT_RGB666: | |
509 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666; | |
510 | break; | |
511 | case MIPI_DSI_FMT_RGB666_PACKED: | |
512 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; | |
513 | break; | |
514 | case MIPI_DSI_FMT_RGB565: | |
515 | reg |= DSIM_MAIN_PIX_FORMAT_RGB565; | |
516 | break; | |
517 | default: | |
518 | dev_err(dsi->dev, "invalid pixel format\n"); | |
519 | return -EINVAL; | |
520 | } | |
521 | ||
522 | reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1); | |
523 | ||
524 | writel(reg, dsi->reg_base + DSIM_CONFIG_REG); | |
525 | ||
526 | reg |= DSIM_LANE_EN_CLK; | |
527 | writel(reg, dsi->reg_base + DSIM_CONFIG_REG); | |
528 | ||
529 | lanes_mask = BIT(dsi->lanes) - 1; | |
530 | reg |= DSIM_LANE_EN(lanes_mask); | |
531 | writel(reg, dsi->reg_base + DSIM_CONFIG_REG); | |
532 | ||
533 | /* Check clock and data lane state are stop state */ | |
534 | timeout = 100; | |
535 | do { | |
536 | if (timeout-- == 0) { | |
537 | dev_err(dsi->dev, "waiting for bus lanes timed out\n"); | |
538 | return -EFAULT; | |
539 | } | |
540 | ||
541 | reg = readl(dsi->reg_base + DSIM_STATUS_REG); | |
542 | if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) | |
543 | != DSIM_STOP_STATE_DAT(lanes_mask)) | |
544 | continue; | |
545 | } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); | |
546 | ||
547 | reg = readl(dsi->reg_base + DSIM_ESCMODE_REG); | |
548 | reg &= ~DSIM_STOP_STATE_CNT_MASK; | |
549 | reg |= DSIM_STOP_STATE_CNT(0xf); | |
550 | writel(reg, dsi->reg_base + DSIM_ESCMODE_REG); | |
551 | ||
552 | reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); | |
553 | writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG); | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) | |
559 | { | |
560 | struct videomode *vm = &dsi->vm; | |
561 | u32 reg; | |
562 | ||
563 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
564 | reg = DSIM_CMD_ALLOW(0xf) | |
565 | | DSIM_STABLE_VFP(vm->vfront_porch) | |
566 | | DSIM_MAIN_VBP(vm->vback_porch); | |
567 | writel(reg, dsi->reg_base + DSIM_MVPORCH_REG); | |
568 | ||
569 | reg = DSIM_MAIN_HFP(vm->hfront_porch) | |
570 | | DSIM_MAIN_HBP(vm->hback_porch); | |
571 | writel(reg, dsi->reg_base + DSIM_MHPORCH_REG); | |
572 | ||
573 | reg = DSIM_MAIN_VSA(vm->vsync_len) | |
574 | | DSIM_MAIN_HSA(vm->hsync_len); | |
575 | writel(reg, dsi->reg_base + DSIM_MSYNC_REG); | |
576 | } | |
577 | ||
578 | reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive); | |
579 | writel(reg, dsi->reg_base + DSIM_MDRESOL_REG); | |
580 | ||
581 | dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); | |
582 | } | |
583 | ||
584 | static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) | |
585 | { | |
586 | u32 reg; | |
587 | ||
588 | reg = readl(dsi->reg_base + DSIM_MDRESOL_REG); | |
589 | if (enable) | |
590 | reg |= DSIM_MAIN_STAND_BY; | |
591 | else | |
592 | reg &= ~DSIM_MAIN_STAND_BY; | |
593 | writel(reg, dsi->reg_base + DSIM_MDRESOL_REG); | |
594 | } | |
595 | ||
596 | static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) | |
597 | { | |
598 | int timeout = 2000; | |
599 | ||
600 | do { | |
601 | u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG); | |
602 | ||
603 | if (!(reg & DSIM_SFR_HEADER_FULL)) | |
604 | return 0; | |
605 | ||
606 | if (!cond_resched()) | |
607 | usleep_range(950, 1050); | |
608 | } while (--timeout); | |
609 | ||
610 | return -ETIMEDOUT; | |
611 | } | |
612 | ||
613 | static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) | |
614 | { | |
615 | u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG); | |
616 | ||
617 | if (lpm) | |
618 | v |= DSIM_CMD_LPDT_LP; | |
619 | else | |
620 | v &= ~DSIM_CMD_LPDT_LP; | |
621 | ||
622 | writel(v, dsi->reg_base + DSIM_ESCMODE_REG); | |
623 | } | |
624 | ||
625 | static void exynos_dsi_force_bta(struct exynos_dsi *dsi) | |
626 | { | |
627 | u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG); | |
628 | ||
629 | v |= DSIM_FORCE_BTA; | |
630 | writel(v, dsi->reg_base + DSIM_ESCMODE_REG); | |
631 | } | |
632 | ||
633 | static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, | |
634 | struct exynos_dsi_transfer *xfer) | |
635 | { | |
636 | struct device *dev = dsi->dev; | |
637 | const u8 *payload = xfer->tx_payload + xfer->tx_done; | |
638 | u16 length = xfer->tx_len - xfer->tx_done; | |
639 | bool first = !xfer->tx_done; | |
640 | u32 reg; | |
641 | ||
642 | dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", | |
643 | xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); | |
644 | ||
645 | if (length > DSI_TX_FIFO_SIZE) | |
646 | length = DSI_TX_FIFO_SIZE; | |
647 | ||
648 | xfer->tx_done += length; | |
649 | ||
650 | /* Send payload */ | |
651 | while (length >= 4) { | |
652 | reg = (payload[3] << 24) | (payload[2] << 16) | |
653 | | (payload[1] << 8) | payload[0]; | |
654 | writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG); | |
655 | payload += 4; | |
656 | length -= 4; | |
657 | } | |
658 | ||
659 | reg = 0; | |
660 | switch (length) { | |
661 | case 3: | |
662 | reg |= payload[2] << 16; | |
663 | /* Fall through */ | |
664 | case 2: | |
665 | reg |= payload[1] << 8; | |
666 | /* Fall through */ | |
667 | case 1: | |
668 | reg |= payload[0]; | |
669 | writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG); | |
670 | break; | |
671 | case 0: | |
672 | /* Do nothing */ | |
673 | break; | |
674 | } | |
675 | ||
676 | /* Send packet header */ | |
677 | if (!first) | |
678 | return; | |
679 | ||
680 | reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; | |
681 | if (exynos_dsi_wait_for_hdr_fifo(dsi)) { | |
682 | dev_err(dev, "waiting for header FIFO timed out\n"); | |
683 | return; | |
684 | } | |
685 | ||
686 | if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, | |
687 | dsi->state & DSIM_STATE_CMD_LPM)) { | |
688 | exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); | |
689 | dsi->state ^= DSIM_STATE_CMD_LPM; | |
690 | } | |
691 | ||
692 | writel(reg, dsi->reg_base + DSIM_PKTHDR_REG); | |
693 | ||
694 | if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) | |
695 | exynos_dsi_force_bta(dsi); | |
696 | } | |
697 | ||
698 | static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, | |
699 | struct exynos_dsi_transfer *xfer) | |
700 | { | |
701 | u8 *payload = xfer->rx_payload + xfer->rx_done; | |
702 | bool first = !xfer->rx_done; | |
703 | struct device *dev = dsi->dev; | |
704 | u16 length; | |
705 | u32 reg; | |
706 | ||
707 | if (first) { | |
708 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
709 | ||
710 | switch (reg & 0x3f) { | |
711 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
712 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
713 | if (xfer->rx_len >= 2) { | |
714 | payload[1] = reg >> 16; | |
715 | ++xfer->rx_done; | |
716 | } | |
717 | /* Fall through */ | |
718 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: | |
719 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
720 | payload[0] = reg >> 8; | |
721 | ++xfer->rx_done; | |
722 | xfer->rx_len = xfer->rx_done; | |
723 | xfer->result = 0; | |
724 | goto clear_fifo; | |
725 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
726 | dev_err(dev, "DSI Error Report: 0x%04x\n", | |
727 | (reg >> 8) & 0xffff); | |
728 | xfer->result = 0; | |
729 | goto clear_fifo; | |
730 | } | |
731 | ||
732 | length = (reg >> 8) & 0xffff; | |
733 | if (length > xfer->rx_len) { | |
734 | dev_err(dev, | |
735 | "response too long (%u > %u bytes), stripping\n", | |
736 | xfer->rx_len, length); | |
737 | length = xfer->rx_len; | |
738 | } else if (length < xfer->rx_len) | |
739 | xfer->rx_len = length; | |
740 | } | |
741 | ||
742 | length = xfer->rx_len - xfer->rx_done; | |
743 | xfer->rx_done += length; | |
744 | ||
745 | /* Receive payload */ | |
746 | while (length >= 4) { | |
747 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
748 | payload[0] = (reg >> 0) & 0xff; | |
749 | payload[1] = (reg >> 8) & 0xff; | |
750 | payload[2] = (reg >> 16) & 0xff; | |
751 | payload[3] = (reg >> 24) & 0xff; | |
752 | payload += 4; | |
753 | length -= 4; | |
754 | } | |
755 | ||
756 | if (length) { | |
757 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
758 | switch (length) { | |
759 | case 3: | |
760 | payload[2] = (reg >> 16) & 0xff; | |
761 | /* Fall through */ | |
762 | case 2: | |
763 | payload[1] = (reg >> 8) & 0xff; | |
764 | /* Fall through */ | |
765 | case 1: | |
766 | payload[0] = reg & 0xff; | |
767 | } | |
768 | } | |
769 | ||
770 | if (xfer->rx_done == xfer->rx_len) | |
771 | xfer->result = 0; | |
772 | ||
773 | clear_fifo: | |
774 | length = DSI_RX_FIFO_SIZE / 4; | |
775 | do { | |
776 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
777 | if (reg == DSI_RX_FIFO_EMPTY) | |
778 | break; | |
779 | } while (--length); | |
780 | } | |
781 | ||
782 | static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) | |
783 | { | |
784 | unsigned long flags; | |
785 | struct exynos_dsi_transfer *xfer; | |
786 | bool start = false; | |
787 | ||
788 | again: | |
789 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
790 | ||
791 | if (list_empty(&dsi->transfer_list)) { | |
792 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
793 | return; | |
794 | } | |
795 | ||
796 | xfer = list_first_entry(&dsi->transfer_list, | |
797 | struct exynos_dsi_transfer, list); | |
798 | ||
799 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
800 | ||
801 | if (xfer->tx_len && xfer->tx_done == xfer->tx_len) | |
802 | /* waiting for RX */ | |
803 | return; | |
804 | ||
805 | exynos_dsi_send_to_fifo(dsi, xfer); | |
806 | ||
807 | if (xfer->tx_len || xfer->rx_len) | |
808 | return; | |
809 | ||
810 | xfer->result = 0; | |
811 | complete(&xfer->completed); | |
812 | ||
813 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
814 | ||
815 | list_del_init(&xfer->list); | |
816 | start = !list_empty(&dsi->transfer_list); | |
817 | ||
818 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
819 | ||
820 | if (start) | |
821 | goto again; | |
822 | } | |
823 | ||
824 | static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) | |
825 | { | |
826 | struct exynos_dsi_transfer *xfer; | |
827 | unsigned long flags; | |
828 | bool start = true; | |
829 | ||
830 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
831 | ||
832 | if (list_empty(&dsi->transfer_list)) { | |
833 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
834 | return false; | |
835 | } | |
836 | ||
837 | xfer = list_first_entry(&dsi->transfer_list, | |
838 | struct exynos_dsi_transfer, list); | |
839 | ||
840 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
841 | ||
842 | dev_dbg(dsi->dev, | |
843 | "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", | |
844 | xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); | |
845 | ||
846 | if (xfer->tx_done != xfer->tx_len) | |
847 | return true; | |
848 | ||
849 | if (xfer->rx_done != xfer->rx_len) | |
850 | exynos_dsi_read_from_fifo(dsi, xfer); | |
851 | ||
852 | if (xfer->rx_done != xfer->rx_len) | |
853 | return true; | |
854 | ||
855 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
856 | ||
857 | list_del_init(&xfer->list); | |
858 | start = !list_empty(&dsi->transfer_list); | |
859 | ||
860 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
861 | ||
862 | if (!xfer->rx_len) | |
863 | xfer->result = 0; | |
864 | complete(&xfer->completed); | |
865 | ||
866 | return start; | |
867 | } | |
868 | ||
869 | static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, | |
870 | struct exynos_dsi_transfer *xfer) | |
871 | { | |
872 | unsigned long flags; | |
873 | bool start; | |
874 | ||
875 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
876 | ||
877 | if (!list_empty(&dsi->transfer_list) && | |
878 | xfer == list_first_entry(&dsi->transfer_list, | |
879 | struct exynos_dsi_transfer, list)) { | |
880 | list_del_init(&xfer->list); | |
881 | start = !list_empty(&dsi->transfer_list); | |
882 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
883 | if (start) | |
884 | exynos_dsi_transfer_start(dsi); | |
885 | return; | |
886 | } | |
887 | ||
888 | list_del_init(&xfer->list); | |
889 | ||
890 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
891 | } | |
892 | ||
893 | static int exynos_dsi_transfer(struct exynos_dsi *dsi, | |
894 | struct exynos_dsi_transfer *xfer) | |
895 | { | |
896 | unsigned long flags; | |
897 | bool stopped; | |
898 | ||
899 | xfer->tx_done = 0; | |
900 | xfer->rx_done = 0; | |
901 | xfer->result = -ETIMEDOUT; | |
902 | init_completion(&xfer->completed); | |
903 | ||
904 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
905 | ||
906 | stopped = list_empty(&dsi->transfer_list); | |
907 | list_add_tail(&xfer->list, &dsi->transfer_list); | |
908 | ||
909 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
910 | ||
911 | if (stopped) | |
912 | exynos_dsi_transfer_start(dsi); | |
913 | ||
914 | wait_for_completion_timeout(&xfer->completed, | |
915 | msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); | |
916 | if (xfer->result == -ETIMEDOUT) { | |
917 | exynos_dsi_remove_transfer(dsi, xfer); | |
918 | dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, | |
919 | xfer->tx_len, xfer->tx_payload); | |
920 | return -ETIMEDOUT; | |
921 | } | |
922 | ||
923 | /* Also covers hardware timeout condition */ | |
924 | return xfer->result; | |
925 | } | |
926 | ||
927 | static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) | |
928 | { | |
929 | struct exynos_dsi *dsi = dev_id; | |
930 | u32 status; | |
931 | ||
932 | status = readl(dsi->reg_base + DSIM_INTSRC_REG); | |
933 | if (!status) { | |
934 | static unsigned long int j; | |
935 | if (printk_timed_ratelimit(&j, 500)) | |
936 | dev_warn(dsi->dev, "spurious interrupt\n"); | |
937 | return IRQ_HANDLED; | |
938 | } | |
939 | writel(status, dsi->reg_base + DSIM_INTSRC_REG); | |
940 | ||
941 | if (status & DSIM_INT_SW_RST_RELEASE) { | |
942 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY); | |
943 | writel(mask, dsi->reg_base + DSIM_INTMSK_REG); | |
944 | complete(&dsi->completed); | |
945 | return IRQ_HANDLED; | |
946 | } | |
947 | ||
948 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY))) | |
949 | return IRQ_HANDLED; | |
950 | ||
951 | if (exynos_dsi_transfer_finish(dsi)) | |
952 | exynos_dsi_transfer_start(dsi); | |
953 | ||
954 | return IRQ_HANDLED; | |
955 | } | |
956 | ||
957 | static int exynos_dsi_init(struct exynos_dsi *dsi) | |
958 | { | |
959 | exynos_dsi_enable_clock(dsi); | |
960 | exynos_dsi_reset(dsi); | |
961 | enable_irq(dsi->irq); | |
962 | exynos_dsi_wait_for_reset(dsi); | |
963 | exynos_dsi_init_link(dsi); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | static int exynos_dsi_host_attach(struct mipi_dsi_host *host, | |
969 | struct mipi_dsi_device *device) | |
970 | { | |
971 | struct exynos_dsi *dsi = host_to_dsi(host); | |
972 | ||
973 | dsi->lanes = device->lanes; | |
974 | dsi->format = device->format; | |
975 | dsi->mode_flags = device->mode_flags; | |
976 | dsi->panel_node = device->dev.of_node; | |
977 | ||
978 | if (dsi->connector.dev) | |
979 | drm_helper_hpd_irq_event(dsi->connector.dev); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
984 | static int exynos_dsi_host_detach(struct mipi_dsi_host *host, | |
985 | struct mipi_dsi_device *device) | |
986 | { | |
987 | struct exynos_dsi *dsi = host_to_dsi(host); | |
988 | ||
989 | dsi->panel_node = NULL; | |
990 | ||
991 | if (dsi->connector.dev) | |
992 | drm_helper_hpd_irq_event(dsi->connector.dev); | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
997 | /* distinguish between short and long DSI packet types */ | |
998 | static bool exynos_dsi_is_short_dsi_type(u8 type) | |
999 | { | |
1000 | return (type & 0x0f) <= 8; | |
1001 | } | |
1002 | ||
1003 | static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, | |
1004 | struct mipi_dsi_msg *msg) | |
1005 | { | |
1006 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1007 | struct exynos_dsi_transfer xfer; | |
1008 | int ret; | |
1009 | ||
1010 | if (!(dsi->state & DSIM_STATE_INITIALIZED)) { | |
1011 | ret = exynos_dsi_init(dsi); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | dsi->state |= DSIM_STATE_INITIALIZED; | |
1015 | } | |
1016 | ||
1017 | if (msg->tx_len == 0) | |
1018 | return -EINVAL; | |
1019 | ||
1020 | xfer.data_id = msg->type | (msg->channel << 6); | |
1021 | ||
1022 | if (exynos_dsi_is_short_dsi_type(msg->type)) { | |
1023 | const char *tx_buf = msg->tx_buf; | |
1024 | ||
1025 | if (msg->tx_len > 2) | |
1026 | return -EINVAL; | |
1027 | xfer.tx_len = 0; | |
1028 | xfer.data[0] = tx_buf[0]; | |
1029 | xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; | |
1030 | } else { | |
1031 | xfer.tx_len = msg->tx_len; | |
1032 | xfer.data[0] = msg->tx_len & 0xff; | |
1033 | xfer.data[1] = msg->tx_len >> 8; | |
1034 | xfer.tx_payload = msg->tx_buf; | |
1035 | } | |
1036 | ||
1037 | xfer.rx_len = msg->rx_len; | |
1038 | xfer.rx_payload = msg->rx_buf; | |
1039 | xfer.flags = msg->flags; | |
1040 | ||
1041 | ret = exynos_dsi_transfer(dsi, &xfer); | |
1042 | return (ret < 0) ? ret : xfer.rx_done; | |
1043 | } | |
1044 | ||
1045 | static const struct mipi_dsi_host_ops exynos_dsi_ops = { | |
1046 | .attach = exynos_dsi_host_attach, | |
1047 | .detach = exynos_dsi_host_detach, | |
1048 | .transfer = exynos_dsi_host_transfer, | |
1049 | }; | |
1050 | ||
1051 | static int exynos_dsi_poweron(struct exynos_dsi *dsi) | |
1052 | { | |
1053 | int ret; | |
1054 | ||
1055 | ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1056 | if (ret < 0) { | |
1057 | dev_err(dsi->dev, "cannot enable regulators %d\n", ret); | |
1058 | return ret; | |
1059 | } | |
1060 | ||
1061 | ret = clk_prepare_enable(dsi->bus_clk); | |
1062 | if (ret < 0) { | |
1063 | dev_err(dsi->dev, "cannot enable bus clock %d\n", ret); | |
1064 | goto err_bus_clk; | |
1065 | } | |
1066 | ||
1067 | ret = clk_prepare_enable(dsi->pll_clk); | |
1068 | if (ret < 0) { | |
1069 | dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); | |
1070 | goto err_pll_clk; | |
1071 | } | |
1072 | ||
1073 | ret = phy_power_on(dsi->phy); | |
1074 | if (ret < 0) { | |
1075 | dev_err(dsi->dev, "cannot enable phy %d\n", ret); | |
1076 | goto err_phy; | |
1077 | } | |
1078 | ||
1079 | return 0; | |
1080 | ||
1081 | err_phy: | |
1082 | clk_disable_unprepare(dsi->pll_clk); | |
1083 | err_pll_clk: | |
1084 | clk_disable_unprepare(dsi->bus_clk); | |
1085 | err_bus_clk: | |
1086 | regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1087 | ||
1088 | return ret; | |
1089 | } | |
1090 | ||
1091 | static void exynos_dsi_poweroff(struct exynos_dsi *dsi) | |
1092 | { | |
1093 | int ret; | |
1094 | ||
1095 | usleep_range(10000, 20000); | |
1096 | ||
1097 | if (dsi->state & DSIM_STATE_INITIALIZED) { | |
1098 | dsi->state &= ~DSIM_STATE_INITIALIZED; | |
1099 | ||
1100 | exynos_dsi_disable_clock(dsi); | |
1101 | ||
1102 | disable_irq(dsi->irq); | |
1103 | } | |
1104 | ||
1105 | dsi->state &= ~DSIM_STATE_CMD_LPM; | |
1106 | ||
1107 | phy_power_off(dsi->phy); | |
1108 | ||
1109 | clk_disable_unprepare(dsi->pll_clk); | |
1110 | clk_disable_unprepare(dsi->bus_clk); | |
1111 | ||
1112 | ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1113 | if (ret < 0) | |
1114 | dev_err(dsi->dev, "cannot disable regulators %d\n", ret); | |
1115 | } | |
1116 | ||
1117 | static int exynos_dsi_enable(struct exynos_dsi *dsi) | |
1118 | { | |
1119 | int ret; | |
1120 | ||
1121 | if (dsi->state & DSIM_STATE_ENABLED) | |
1122 | return 0; | |
1123 | ||
1124 | ret = exynos_dsi_poweron(dsi); | |
1125 | if (ret < 0) | |
1126 | return ret; | |
1127 | ||
1128 | ret = drm_panel_enable(dsi->panel); | |
1129 | if (ret < 0) { | |
1130 | exynos_dsi_poweroff(dsi); | |
1131 | return ret; | |
1132 | } | |
1133 | ||
1134 | exynos_dsi_set_display_mode(dsi); | |
1135 | exynos_dsi_set_display_enable(dsi, true); | |
1136 | ||
1137 | dsi->state |= DSIM_STATE_ENABLED; | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static void exynos_dsi_disable(struct exynos_dsi *dsi) | |
1143 | { | |
1144 | if (!(dsi->state & DSIM_STATE_ENABLED)) | |
1145 | return; | |
1146 | ||
1147 | exynos_dsi_set_display_enable(dsi, false); | |
1148 | drm_panel_disable(dsi->panel); | |
1149 | exynos_dsi_poweroff(dsi); | |
1150 | ||
1151 | dsi->state &= ~DSIM_STATE_ENABLED; | |
1152 | } | |
1153 | ||
1154 | static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode) | |
1155 | { | |
1156 | struct exynos_dsi *dsi = display->ctx; | |
1157 | ||
1158 | if (dsi->panel) { | |
1159 | switch (mode) { | |
1160 | case DRM_MODE_DPMS_ON: | |
1161 | exynos_dsi_enable(dsi); | |
1162 | break; | |
1163 | case DRM_MODE_DPMS_STANDBY: | |
1164 | case DRM_MODE_DPMS_SUSPEND: | |
1165 | case DRM_MODE_DPMS_OFF: | |
1166 | exynos_dsi_disable(dsi); | |
1167 | break; | |
1168 | default: | |
1169 | break; | |
1170 | } | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | static enum drm_connector_status | |
1175 | exynos_dsi_detect(struct drm_connector *connector, bool force) | |
1176 | { | |
1177 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1178 | ||
1179 | if (!dsi->panel) { | |
1180 | dsi->panel = of_drm_find_panel(dsi->panel_node); | |
1181 | if (dsi->panel) | |
1182 | drm_panel_attach(dsi->panel, &dsi->connector); | |
1183 | } else if (!dsi->panel_node) { | |
1184 | struct exynos_drm_display *display; | |
1185 | ||
1186 | display = platform_get_drvdata(to_platform_device(dsi->dev)); | |
1187 | exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); | |
1188 | drm_panel_detach(dsi->panel); | |
1189 | dsi->panel = NULL; | |
1190 | } | |
1191 | ||
1192 | if (dsi->panel) | |
1193 | return connector_status_connected; | |
1194 | ||
1195 | return connector_status_disconnected; | |
1196 | } | |
1197 | ||
1198 | static void exynos_dsi_connector_destroy(struct drm_connector *connector) | |
1199 | { | |
1200 | } | |
1201 | ||
1202 | static struct drm_connector_funcs exynos_dsi_connector_funcs = { | |
1203 | .dpms = drm_helper_connector_dpms, | |
1204 | .detect = exynos_dsi_detect, | |
1205 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1206 | .destroy = exynos_dsi_connector_destroy, | |
1207 | }; | |
1208 | ||
1209 | static int exynos_dsi_get_modes(struct drm_connector *connector) | |
1210 | { | |
1211 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1212 | ||
1213 | if (dsi->panel) | |
1214 | return dsi->panel->funcs->get_modes(dsi->panel); | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int exynos_dsi_mode_valid(struct drm_connector *connector, | |
1220 | struct drm_display_mode *mode) | |
1221 | { | |
1222 | return MODE_OK; | |
1223 | } | |
1224 | ||
1225 | static struct drm_encoder * | |
1226 | exynos_dsi_best_encoder(struct drm_connector *connector) | |
1227 | { | |
1228 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1229 | ||
1230 | return dsi->encoder; | |
1231 | } | |
1232 | ||
1233 | static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { | |
1234 | .get_modes = exynos_dsi_get_modes, | |
1235 | .mode_valid = exynos_dsi_mode_valid, | |
1236 | .best_encoder = exynos_dsi_best_encoder, | |
1237 | }; | |
1238 | ||
1239 | static int exynos_dsi_create_connector(struct exynos_drm_display *display, | |
1240 | struct drm_encoder *encoder) | |
1241 | { | |
1242 | struct exynos_dsi *dsi = display->ctx; | |
1243 | struct drm_connector *connector = &dsi->connector; | |
1244 | int ret; | |
1245 | ||
1246 | dsi->encoder = encoder; | |
1247 | ||
1248 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1249 | ||
1250 | ret = drm_connector_init(encoder->dev, connector, | |
1251 | &exynos_dsi_connector_funcs, | |
1252 | DRM_MODE_CONNECTOR_DSI); | |
1253 | if (ret) { | |
1254 | DRM_ERROR("Failed to initialize connector with drm\n"); | |
1255 | return ret; | |
1256 | } | |
1257 | ||
1258 | drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); | |
34ea3d38 | 1259 | drm_connector_register(connector); |
7eb8f069 AH |
1260 | drm_mode_connector_attach_encoder(connector, encoder); |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static void exynos_dsi_mode_set(struct exynos_drm_display *display, | |
1266 | struct drm_display_mode *mode) | |
1267 | { | |
1268 | struct exynos_dsi *dsi = display->ctx; | |
1269 | struct videomode *vm = &dsi->vm; | |
1270 | ||
1271 | vm->hactive = mode->hdisplay; | |
1272 | vm->vactive = mode->vdisplay; | |
1273 | vm->vfront_porch = mode->vsync_start - mode->vdisplay; | |
1274 | vm->vback_porch = mode->vtotal - mode->vsync_end; | |
1275 | vm->vsync_len = mode->vsync_end - mode->vsync_start; | |
1276 | vm->hfront_porch = mode->hsync_start - mode->hdisplay; | |
1277 | vm->hback_porch = mode->htotal - mode->hsync_end; | |
1278 | vm->hsync_len = mode->hsync_end - mode->hsync_start; | |
1279 | } | |
1280 | ||
1281 | static struct exynos_drm_display_ops exynos_dsi_display_ops = { | |
1282 | .create_connector = exynos_dsi_create_connector, | |
1283 | .mode_set = exynos_dsi_mode_set, | |
1284 | .dpms = exynos_dsi_dpms | |
1285 | }; | |
1286 | ||
1287 | static struct exynos_drm_display exynos_dsi_display = { | |
1288 | .type = EXYNOS_DISPLAY_TYPE_LCD, | |
1289 | .ops = &exynos_dsi_display_ops, | |
1290 | }; | |
1291 | ||
1292 | /* of_* functions will be removed after merge of of_graph patches */ | |
1293 | static struct device_node * | |
1294 | of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) | |
1295 | { | |
1296 | struct device_node *np; | |
1297 | ||
1298 | for_each_child_of_node(parent, np) { | |
1299 | u32 r; | |
1300 | ||
1301 | if (!np->name || of_node_cmp(np->name, name)) | |
1302 | continue; | |
1303 | ||
1304 | if (of_property_read_u32(np, "reg", &r) < 0) | |
1305 | r = 0; | |
1306 | ||
1307 | if (reg == r) | |
1308 | break; | |
1309 | } | |
1310 | ||
1311 | return np; | |
1312 | } | |
1313 | ||
1314 | static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, | |
1315 | u32 reg) | |
1316 | { | |
1317 | struct device_node *ports, *port; | |
1318 | ||
1319 | ports = of_get_child_by_name(parent, "ports"); | |
1320 | if (ports) | |
1321 | parent = ports; | |
1322 | ||
1323 | port = of_get_child_by_name_reg(parent, "port", reg); | |
1324 | ||
1325 | of_node_put(ports); | |
1326 | ||
1327 | return port; | |
1328 | } | |
1329 | ||
1330 | static struct device_node * | |
1331 | of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) | |
1332 | { | |
1333 | return of_get_child_by_name_reg(port, "endpoint", reg); | |
1334 | } | |
1335 | ||
1336 | static int exynos_dsi_of_read_u32(const struct device_node *np, | |
1337 | const char *propname, u32 *out_value) | |
1338 | { | |
1339 | int ret = of_property_read_u32(np, propname, out_value); | |
1340 | ||
1341 | if (ret < 0) | |
1342 | pr_err("%s: failed to get '%s' property\n", np->full_name, | |
1343 | propname); | |
1344 | ||
1345 | return ret; | |
1346 | } | |
1347 | ||
1348 | enum { | |
1349 | DSI_PORT_IN, | |
1350 | DSI_PORT_OUT | |
1351 | }; | |
1352 | ||
1353 | static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) | |
1354 | { | |
1355 | struct device *dev = dsi->dev; | |
1356 | struct device_node *node = dev->of_node; | |
1357 | struct device_node *port, *ep; | |
1358 | int ret; | |
1359 | ||
1360 | ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", | |
1361 | &dsi->pll_clk_rate); | |
1362 | if (ret < 0) | |
1363 | return ret; | |
1364 | ||
1365 | port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); | |
1366 | if (!port) { | |
1367 | dev_err(dev, "no output port specified\n"); | |
1368 | return -EINVAL; | |
1369 | } | |
1370 | ||
1371 | ep = of_graph_get_endpoint_by_reg(port, 0); | |
1372 | of_node_put(port); | |
1373 | if (!ep) { | |
1374 | dev_err(dev, "no endpoint specified in output port\n"); | |
1375 | return -EINVAL; | |
1376 | } | |
1377 | ||
1378 | ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", | |
1379 | &dsi->burst_clk_rate); | |
1380 | if (ret < 0) | |
1381 | goto end; | |
1382 | ||
1383 | ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", | |
1384 | &dsi->esc_clk_rate); | |
1385 | ||
1386 | end: | |
1387 | of_node_put(ep); | |
1388 | ||
1389 | return ret; | |
1390 | } | |
1391 | ||
f37cd5e8 ID |
1392 | static int exynos_dsi_bind(struct device *dev, struct device *master, |
1393 | void *data) | |
1394 | { | |
1395 | struct drm_device *drm_dev = data; | |
1396 | struct exynos_dsi *dsi; | |
1397 | int ret; | |
1398 | ||
1399 | ret = exynos_drm_create_enc_conn(drm_dev, &exynos_dsi_display); | |
1400 | if (ret) { | |
1401 | DRM_ERROR("Encoder create [%d] failed with %d\n", | |
1402 | exynos_dsi_display.type, ret); | |
1403 | return ret; | |
1404 | } | |
1405 | ||
1406 | dsi = exynos_dsi_display.ctx; | |
1407 | ||
1408 | return mipi_dsi_host_register(&dsi->dsi_host); | |
1409 | } | |
1410 | ||
1411 | static void exynos_dsi_unbind(struct device *dev, struct device *master, | |
1412 | void *data) | |
1413 | { | |
1414 | struct exynos_dsi *dsi = exynos_dsi_display.ctx; | |
1415 | struct drm_encoder *encoder = dsi->encoder; | |
1416 | ||
1417 | exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF); | |
1418 | ||
1419 | mipi_dsi_host_unregister(&dsi->dsi_host); | |
1420 | ||
1421 | encoder->funcs->destroy(encoder); | |
1422 | drm_connector_cleanup(&dsi->connector); | |
1423 | } | |
1424 | ||
f37cd5e8 ID |
1425 | static const struct component_ops exynos_dsi_component_ops = { |
1426 | .bind = exynos_dsi_bind, | |
1427 | .unbind = exynos_dsi_unbind, | |
1428 | }; | |
1429 | ||
7eb8f069 AH |
1430 | static int exynos_dsi_probe(struct platform_device *pdev) |
1431 | { | |
1432 | struct resource *res; | |
1433 | struct exynos_dsi *dsi; | |
1434 | int ret; | |
1435 | ||
df5225bc ID |
1436 | ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR, |
1437 | exynos_dsi_display.type); | |
1438 | if (ret) | |
1439 | return ret; | |
1440 | ||
7eb8f069 AH |
1441 | dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); |
1442 | if (!dsi) { | |
1443 | dev_err(&pdev->dev, "failed to allocate dsi object.\n"); | |
df5225bc ID |
1444 | ret = -ENOMEM; |
1445 | goto err_del_component; | |
7eb8f069 AH |
1446 | } |
1447 | ||
1448 | init_completion(&dsi->completed); | |
1449 | spin_lock_init(&dsi->transfer_lock); | |
1450 | INIT_LIST_HEAD(&dsi->transfer_list); | |
1451 | ||
1452 | dsi->dsi_host.ops = &exynos_dsi_ops; | |
1453 | dsi->dsi_host.dev = &pdev->dev; | |
1454 | ||
1455 | dsi->dev = &pdev->dev; | |
1456 | ||
1457 | ret = exynos_dsi_parse_dt(dsi); | |
1458 | if (ret) | |
df5225bc | 1459 | goto err_del_component; |
7eb8f069 AH |
1460 | |
1461 | dsi->supplies[0].supply = "vddcore"; | |
1462 | dsi->supplies[1].supply = "vddio"; | |
1463 | ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies), | |
1464 | dsi->supplies); | |
1465 | if (ret) { | |
1466 | dev_info(&pdev->dev, "failed to get regulators: %d\n", ret); | |
1467 | return -EPROBE_DEFER; | |
1468 | } | |
1469 | ||
1470 | dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk"); | |
1471 | if (IS_ERR(dsi->pll_clk)) { | |
1472 | dev_info(&pdev->dev, "failed to get dsi pll input clock\n"); | |
df5225bc ID |
1473 | ret = PTR_ERR(dsi->pll_clk); |
1474 | goto err_del_component; | |
7eb8f069 AH |
1475 | } |
1476 | ||
1477 | dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); | |
1478 | if (IS_ERR(dsi->bus_clk)) { | |
1479 | dev_info(&pdev->dev, "failed to get dsi bus clock\n"); | |
df5225bc ID |
1480 | ret = PTR_ERR(dsi->bus_clk); |
1481 | goto err_del_component; | |
7eb8f069 AH |
1482 | } |
1483 | ||
1484 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1485 | dsi->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
293d3f6a | 1486 | if (IS_ERR(dsi->reg_base)) { |
7eb8f069 | 1487 | dev_err(&pdev->dev, "failed to remap io region\n"); |
df5225bc ID |
1488 | ret = PTR_ERR(dsi->reg_base); |
1489 | goto err_del_component; | |
7eb8f069 AH |
1490 | } |
1491 | ||
1492 | dsi->phy = devm_phy_get(&pdev->dev, "dsim"); | |
1493 | if (IS_ERR(dsi->phy)) { | |
1494 | dev_info(&pdev->dev, "failed to get dsim phy\n"); | |
df5225bc ID |
1495 | ret = PTR_ERR(dsi->phy); |
1496 | goto err_del_component; | |
7eb8f069 AH |
1497 | } |
1498 | ||
1499 | dsi->irq = platform_get_irq(pdev, 0); | |
1500 | if (dsi->irq < 0) { | |
1501 | dev_err(&pdev->dev, "failed to request dsi irq resource\n"); | |
df5225bc ID |
1502 | ret = dsi->irq; |
1503 | goto err_del_component; | |
7eb8f069 AH |
1504 | } |
1505 | ||
1506 | irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); | |
1507 | ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL, | |
1508 | exynos_dsi_irq, IRQF_ONESHOT, | |
1509 | dev_name(&pdev->dev), dsi); | |
1510 | if (ret) { | |
1511 | dev_err(&pdev->dev, "failed to request dsi irq\n"); | |
df5225bc | 1512 | goto err_del_component; |
7eb8f069 AH |
1513 | } |
1514 | ||
1515 | exynos_dsi_display.ctx = dsi; | |
1516 | ||
1517 | platform_set_drvdata(pdev, &exynos_dsi_display); | |
7eb8f069 | 1518 | |
df5225bc ID |
1519 | ret = component_add(&pdev->dev, &exynos_dsi_component_ops); |
1520 | if (ret) | |
1521 | goto err_del_component; | |
1522 | ||
1523 | return ret; | |
1524 | ||
1525 | err_del_component: | |
1526 | exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); | |
1527 | return ret; | |
7eb8f069 AH |
1528 | } |
1529 | ||
1530 | static int exynos_dsi_remove(struct platform_device *pdev) | |
1531 | { | |
df5225bc ID |
1532 | component_del(&pdev->dev, &exynos_dsi_component_ops); |
1533 | exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); | |
1534 | ||
7eb8f069 AH |
1535 | return 0; |
1536 | } | |
1537 | ||
7eb8f069 AH |
1538 | static struct of_device_id exynos_dsi_of_match[] = { |
1539 | { .compatible = "samsung,exynos4210-mipi-dsi" }, | |
1540 | { } | |
1541 | }; | |
1542 | ||
7eb8f069 AH |
1543 | struct platform_driver dsi_driver = { |
1544 | .probe = exynos_dsi_probe, | |
1545 | .remove = exynos_dsi_remove, | |
1546 | .driver = { | |
1547 | .name = "exynos-dsi", | |
1548 | .owner = THIS_MODULE, | |
7eb8f069 AH |
1549 | .of_match_table = exynos_dsi_of_match, |
1550 | }, | |
1551 | }; | |
1552 | ||
1553 | MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); | |
1554 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); | |
1555 | MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); | |
1556 | MODULE_LICENSE("GPL v2"); |