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Merge branch 'for-linus' of git://git.samba.org/sfrench/cifs-2.6
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
CommitLineData
1c248b7d
ID		 1/* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
760285e7 14#include <drm/drmP.h>
1c248b7d
ID		 15
16#include <linux/kernel.h>
1c248b7d
ID		 17#include <linux/platform_device.h>
18#include <linux/clk.h>
3f1c781d 19#include <linux/of.h>
d636ead8 20#include <linux/of_device.h>
cb91f6a0 21#include <linux/pm_runtime.h>
f37cd5e8 22#include <linux/component.h>
3854fab2
YC		 23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
1c248b7d 25
7f4596f4 26#include <video/of_display_timing.h>
111e6055 27#include <video/of_videomode.h>
5a213a55 28#include <video/samsung_fimd.h>
1c248b7d 29#include <drm/exynos_drm.h>
1c248b7d
ID		 30
31#include "exynos_drm_drv.h"
32#include "exynos_drm_fbdev.h"
33#include "exynos_drm_crtc.h"
bcc5cd1c 34#include "exynos_drm_iommu.h"
1c248b7d
ID		 35
36/*
b8654b37 37 * FIMD stands for Fully Interactive Mobile Display and
1c248b7d
ID		 38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
40 * CPU Interface.
41 */
42
111e6055 43#define FIMD_DEFAULT_FRAMERATE 60
66367461 44#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
111e6055 45
1c248b7d
ID		 46/* position control register for hardware window 0, 2 ~ 4.*/
47#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
0f10cf14
LKA		 49/*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54/* size control register for hardware windows 1 ~ 2. */
1c248b7d
ID		 55#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
60
61/* color key control register for hardware window 1 ~ 4. */
0f10cf14 62#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
1c248b7d 63/* color key value register for hardware window 1 ~ 4. */
0f10cf14 64#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
1c248b7d 65
3854fab2
YC		 66/* I80 / RGB trigger control register */
67#define TRIGCON 0x1A4
68#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69#define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
70
71/* display mode change control register except exynos4 */
72#define VIDOUT_CON 0x000
73#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
74
75/* I80 interface control for main LDI register */
76#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78#define LCD_CS_SETUP(x) ((x) << 16)
79#define LCD_WR_SETUP(x) ((x) << 12)
80#define LCD_WR_ACTIVE(x) ((x) << 8)
81#define LCD_WR_HOLD(x) ((x) << 4)
82#define I80IFEN_ENABLE (1 << 0)
83
1c248b7d
ID		 84/* FIMD has totally five hardware windows. */
85#define WINDOWS_NR 5
86
e2e13389
LKA		 87struct fimd_driver_data {
88 unsigned int timing_base;
3854fab2
YC		 89 unsigned int lcdblk_offset;
90 unsigned int lcdblk_vt_shift;
91 unsigned int lcdblk_bypass_shift;
de7af100
TF		 92
93 unsigned int has_shadowcon:1;
411d9ed4 94 unsigned int has_clksel:1;
5cc4621a 95 unsigned int has_limited_fmt:1;
3854fab2 96 unsigned int has_vidoutcon:1;
3c3c9c1d 97 unsigned int has_vtsel:1;
e2e13389
LKA		 98};
99
725ddead
TF		 100static struct fimd_driver_data s3c64xx_fimd_driver_data = {
101 .timing_base = 0x0,
102 .has_clksel = 1,
5cc4621a 103 .has_limited_fmt = 1,
725ddead
TF		 104};
105
d6ce7b58
ID		 106static struct fimd_driver_data exynos3_fimd_driver_data = {
107 .timing_base = 0x20000,
108 .lcdblk_offset = 0x210,
109 .lcdblk_bypass_shift = 1,
110 .has_shadowcon = 1,
111 .has_vidoutcon = 1,
112};
113
6ecf18f9 114static struct fimd_driver_data exynos4_fimd_driver_data = {
e2e13389 115 .timing_base = 0x0,
3854fab2
YC		 116 .lcdblk_offset = 0x210,
117 .lcdblk_vt_shift = 10,
118 .lcdblk_bypass_shift = 1,
de7af100 119 .has_shadowcon = 1,
3c3c9c1d 120 .has_vtsel = 1,
e2e13389
LKA		 121};
122
dcb622aa
YC		 123static struct fimd_driver_data exynos4415_fimd_driver_data = {
124 .timing_base = 0x20000,
125 .lcdblk_offset = 0x210,
126 .lcdblk_vt_shift = 10,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
3c3c9c1d 130 .has_vtsel = 1,
dcb622aa
YC		 131};
132
6ecf18f9 133static struct fimd_driver_data exynos5_fimd_driver_data = {
e2e13389 134 .timing_base = 0x20000,
3854fab2
YC		 135 .lcdblk_offset = 0x214,
136 .lcdblk_vt_shift = 24,
137 .lcdblk_bypass_shift = 15,
de7af100 138 .has_shadowcon = 1,
3854fab2 139 .has_vidoutcon = 1,
3c3c9c1d 140 .has_vtsel = 1,
e2e13389
LKA		 141};
142
1c248b7d
ID		 143struct fimd_win_data {
144 unsigned int offset_x;
145 unsigned int offset_y;
19c8b834
ID		 146 unsigned int ovl_width;
147 unsigned int ovl_height;
148 unsigned int fb_width;
149 unsigned int fb_height;
1c248b7d 150 unsigned int bpp;
a4f38a80 151 unsigned int pixel_format;
2c871127 152 dma_addr_t dma_addr;
1c248b7d
ID		 153 unsigned int buf_offsize;
154 unsigned int line_size; /* bytes */
ec05da95 155 bool enabled;
db7e55ae 156 bool resume;
1c248b7d
ID		 157};
158
159struct fimd_context {
e152dbd7 160 struct exynos_drm_manager manager;
bb7704d6 161 struct device *dev;
40c8ab4b 162 struct drm_device *drm_dev;
1c248b7d
ID		 163 struct clk *bus_clk;
164 struct clk *lcd_clk;
1c248b7d 165 void __iomem *regs;
3854fab2 166 struct regmap *sysreg;
a968e727 167 struct drm_display_mode mode;
1c248b7d 168 struct fimd_win_data win_data[WINDOWS_NR];
1c248b7d
ID		 169 unsigned int default_win;
170 unsigned long irq_flags;
3854fab2 171 u32 vidcon0;
1c248b7d 172 u32 vidcon1;
3854fab2
YC		 173 u32 vidout_con;
174 u32 i80ifcon;
175 bool i80_if;
cb91f6a0 176 bool suspended;
080be03d 177 int pipe;
01ce113c
P		 178 wait_queue_head_t wait_vsync_queue;
179 atomic_t wait_vsync_event;
3854fab2
YC		 180 atomic_t win_updated;
181 atomic_t triggering;
1c248b7d 182
562ad9f4 183 struct exynos_drm_panel_info panel;
18873465 184 struct fimd_driver_data *driver_data;
000cc920 185 struct exynos_drm_display *display;
1c248b7d
ID		 186};
187
400c8ac8
AH		 188static inline struct fimd_context *mgr_to_fimd(struct exynos_drm_manager *mgr)
189{
190 return container_of(mgr, struct fimd_context, manager);
191}
192
d636ead8 193static const struct of_device_id fimd_driver_dt_match[] = {
725ddead
TF		 194 { .compatible = "samsung,s3c6400-fimd",
195 .data = &s3c64xx_fimd_driver_data },
d6ce7b58
ID		 196 { .compatible = "samsung,exynos3250-fimd",
197 .data = &exynos3_fimd_driver_data },
5830daf8 198 { .compatible = "samsung,exynos4210-fimd",
d636ead8 199 .data = &exynos4_fimd_driver_data },
dcb622aa
YC		 200 { .compatible = "samsung,exynos4415-fimd",
201 .data = &exynos4415_fimd_driver_data },
5830daf8 202 { .compatible = "samsung,exynos5250-fimd",
d636ead8
JS		 203 .data = &exynos5_fimd_driver_data },
204 {},
205};
0262ceeb 206MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
d636ead8 207
e2e13389
LKA		 208static inline struct fimd_driver_data *drm_fimd_get_driver_data(
209 struct platform_device *pdev)
210{
d636ead8
JS		 211 const struct of_device_id *of_id =
212 of_match_device(fimd_driver_dt_match, &pdev->dev);
213
2d3f173c 214 return (struct fimd_driver_data *)of_id->data;
e2e13389
LKA		 215}
216
f13bdbd1
AA		 217static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
218{
400c8ac8 219 struct fimd_context *ctx = mgr_to_fimd(mgr);
f13bdbd1
AA		 220
221 if (ctx->suspended)
222 return;
223
224 atomic_set(&ctx->wait_vsync_event, 1);
225
226 /*
227 * wait for FIMD to signal VSYNC interrupt or return after
228 * timeout which is set to 50ms (refresh rate of 20).
229 */
230 if (!wait_event_timeout(ctx->wait_vsync_queue,
231 !atomic_read(&ctx->wait_vsync_event),
232 HZ/20))
233 DRM_DEBUG_KMS("vblank wait timed out.\n");
234}
235
f181a543
YC		 236static void fimd_enable_video_output(struct fimd_context *ctx, int win,
237 bool enable)
238{
239 u32 val = readl(ctx->regs + WINCON(win));
240
241 if (enable)
242 val |= WINCONx_ENWIN;
243 else
244 val &= ~WINCONx_ENWIN;
245
246 writel(val, ctx->regs + WINCON(win));
247}
248
999d8b31
YC		 249static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
250 bool enable)
251{
252 u32 val = readl(ctx->regs + SHADOWCON);
253
254 if (enable)
255 val |= SHADOWCON_CHx_ENABLE(win);
256 else
257 val &= ~SHADOWCON_CHx_ENABLE(win);
258
259 writel(val, ctx->regs + SHADOWCON);
260}
261
f13bdbd1
AA		 262static void fimd_clear_channel(struct exynos_drm_manager *mgr)
263{
400c8ac8 264 struct fimd_context *ctx = mgr_to_fimd(mgr);
f13bdbd1
AA		 265 int win, ch_enabled = 0;
266
267 DRM_DEBUG_KMS("%s\n", __FILE__);
268
269 /* Check if any channel is enabled. */
270 for (win = 0; win < WINDOWS_NR; win++) {
eb8a3bf7
MS		 271 u32 val = readl(ctx->regs + WINCON(win));
272
273 if (val & WINCONx_ENWIN) {
f181a543 274 fimd_enable_video_output(ctx, win, false);
eb8a3bf7 275
999d8b31
YC		 276 if (ctx->driver_data->has_shadowcon)
277 fimd_enable_shadow_channel_path(ctx, win,
278 false);
279
f13bdbd1
AA		 280 ch_enabled = 1;
281 }
282 }
283
284 /* Wait for vsync, as disable channel takes effect at next vsync */
eb8a3bf7
MS		 285 if (ch_enabled) {
286 unsigned int state = ctx->suspended;
287
288 ctx->suspended = 0;
f13bdbd1 289 fimd_wait_for_vblank(mgr);
eb8a3bf7
MS		 290 ctx->suspended = state;
291 }
f13bdbd1
AA		 292}
293
bb7704d6 294static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
f37cd5e8 295 struct drm_device *drm_dev)
40c8ab4b 296{
400c8ac8 297 struct fimd_context *ctx = mgr_to_fimd(mgr);
f37cd5e8
ID		 298 struct exynos_drm_private *priv;
299 priv = drm_dev->dev_private;
40c8ab4b 300
f37cd5e8
ID		 301 mgr->drm_dev = ctx->drm_dev = drm_dev;
302 mgr->pipe = ctx->pipe = priv->pipe++;
40c8ab4b 303
080be03d 304 /* attach this sub driver to iommu mapping if supported. */
f13bdbd1
AA		 305 if (is_drm_iommu_supported(ctx->drm_dev)) {
306 /*
307 * If any channel is already active, iommu will throw
308 * a PAGE FAULT when enabled. So clear any channel if enabled.
309 */
310 fimd_clear_channel(mgr);
080be03d 311 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
f13bdbd1 312 }
c32b06ef 313
080be03d 314 return 0;
ec05da95
ID		 315}
316
080be03d 317static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
ec05da95 318{
400c8ac8 319 struct fimd_context *ctx = mgr_to_fimd(mgr);
ec05da95 320
080be03d
SP		 321 /* detach this sub driver from iommu mapping if supported. */
322 if (is_drm_iommu_supported(ctx->drm_dev))
323 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
ec05da95
ID		 324}
325
a968e727
SP		 326static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
327 const struct drm_display_mode *mode)
328{
329 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
330 u32 clkdiv;
331
3854fab2
YC		 332 if (ctx->i80_if) {
333 /*
334 * The frame done interrupt should be occurred prior to the
335 * next TE signal.
336 */
337 ideal_clk *= 2;
338 }
339
a968e727
SP		 340 /* Find the clock divider value that gets us closest to ideal_clk */
341 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
342
343 return (clkdiv < 0x100) ? clkdiv : 0xff;
344}
345
346static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
347 const struct drm_display_mode *mode,
348 struct drm_display_mode *adjusted_mode)
349{
350 if (adjusted_mode->vrefresh == 0)
351 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
352
353 return true;
354}
355
356static void fimd_mode_set(struct exynos_drm_manager *mgr,
357 const struct drm_display_mode *in_mode)
358{
400c8ac8 359 struct fimd_context *ctx = mgr_to_fimd(mgr);
a968e727
SP		 360
361 drm_mode_copy(&ctx->mode, in_mode);
362}
363
bb7704d6 364static void fimd_commit(struct exynos_drm_manager *mgr)
1c248b7d 365{
400c8ac8 366 struct fimd_context *ctx = mgr_to_fimd(mgr);
a968e727 367 struct drm_display_mode *mode = &ctx->mode;
3854fab2
YC		 368 struct fimd_driver_data *driver_data = ctx->driver_data;
369 void *timing_base = ctx->regs + driver_data->timing_base;
370 u32 val, clkdiv;
1c248b7d 371
e30d4bcf
ID		 372 if (ctx->suspended)
373 return;
374
a968e727
SP		 375 /* nothing to do if we haven't set the mode yet */
376 if (mode->htotal == 0 || mode->vtotal == 0)
377 return;
378
3854fab2
YC		 379 if (ctx->i80_if) {
380 val = ctx->i80ifcon | I80IFEN_ENABLE;
381 writel(val, timing_base + I80IFCONFAx(0));
382
383 /* disable auto frame rate */
384 writel(0, timing_base + I80IFCONFBx(0));
385
386 /* set video type selection to I80 interface */
3c3c9c1d
JS		 387 if (driver_data->has_vtsel && ctx->sysreg &&
388 regmap_update_bits(ctx->sysreg,
3854fab2
YC		 389 driver_data->lcdblk_offset,
390 0x3 << driver_data->lcdblk_vt_shift,
391 0x1 << driver_data->lcdblk_vt_shift)) {
392 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
393 return;
394 }
395 } else {
396 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
397 u32 vidcon1;
398
399 /* setup polarity values */
400 vidcon1 = ctx->vidcon1;
401 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
402 vidcon1 |= VIDCON1_INV_VSYNC;
403 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
404 vidcon1 |= VIDCON1_INV_HSYNC;
405 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
406
407 /* setup vertical timing values. */
408 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
409 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
410 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
411
412 val = VIDTCON0_VBPD(vbpd - 1) |
413 VIDTCON0_VFPD(vfpd - 1) |
414 VIDTCON0_VSPW(vsync_len - 1);
415 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
416
417 /* setup horizontal timing values. */
418 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
419 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
420 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
421
422 val = VIDTCON1_HBPD(hbpd - 1) |
423 VIDTCON1_HFPD(hfpd - 1) |
424 VIDTCON1_HSPW(hsync_len - 1);
425 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
426 }
427
428 if (driver_data->has_vidoutcon)
429 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
430
431 /* set bypass selection */
432 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
433 driver_data->lcdblk_offset,
434 0x1 << driver_data->lcdblk_bypass_shift,
435 0x1 << driver_data->lcdblk_bypass_shift)) {
436 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
437 return;
438 }
1c248b7d
ID		 439
440 /* setup horizontal and vertical display size. */
a968e727
SP		 441 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
442 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
443 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
444 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
e2e13389 445 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
1c248b7d 446
1d531062
AH		 447 /*
448 * fields of register with prefix '_F' would be updated
449 * at vsync(same as dma start)
450 */
3854fab2
YC		 451 val = ctx->vidcon0;
452 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
1c248b7d 453
1d531062 454 if (ctx->driver_data->has_clksel)
411d9ed4 455 val |= VIDCON0_CLKSEL_LCD;
411d9ed4 456
a968e727
SP		 457 clkdiv = fimd_calc_clkdiv(ctx, mode);
458 if (clkdiv > 1)
459 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
1c248b7d 460
1c248b7d
ID		 461 writel(val, ctx->regs + VIDCON0);
462}
463
bb7704d6 464static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
1c248b7d 465{
400c8ac8 466 struct fimd_context *ctx = mgr_to_fimd(mgr);
1c248b7d
ID		 467 u32 val;
468
cb91f6a0
JS		 469 if (ctx->suspended)
470 return -EPERM;
471
1c248b7d
ID		 472 if (!test_and_set_bit(0, &ctx->irq_flags)) {
473 val = readl(ctx->regs + VIDINTCON0);
474
475 val |= VIDINTCON0_INT_ENABLE;
1c248b7d 476
1c905d95
YC		 477 if (ctx->i80_if) {
478 val |= VIDINTCON0_INT_I80IFDONE;
479 val |= VIDINTCON0_INT_SYSMAINCON;
480 val &= ~VIDINTCON0_INT_SYSSUBCON;
481 } else {
482 val |= VIDINTCON0_INT_FRAME;
483
484 val &= ~VIDINTCON0_FRAMESEL0_MASK;
485 val |= VIDINTCON0_FRAMESEL0_VSYNC;
486 val &= ~VIDINTCON0_FRAMESEL1_MASK;
487 val |= VIDINTCON0_FRAMESEL1_NONE;
488 }
1c248b7d
ID		 489
490 writel(val, ctx->regs + VIDINTCON0);
491 }
492
493 return 0;
494}
495
bb7704d6 496static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
1c248b7d 497{
400c8ac8 498 struct fimd_context *ctx = mgr_to_fimd(mgr);
1c248b7d
ID		 499 u32 val;
500
cb91f6a0
JS		 501 if (ctx->suspended)
502 return;
503
1c248b7d
ID		 504 if (test_and_clear_bit(0, &ctx->irq_flags)) {
505 val = readl(ctx->regs + VIDINTCON0);
506
1c248b7d
ID		 507 val &= ~VIDINTCON0_INT_ENABLE;
508
1c905d95
YC		 509 if (ctx->i80_if) {
510 val &= ~VIDINTCON0_INT_I80IFDONE;
511 val &= ~VIDINTCON0_INT_SYSMAINCON;
512 val &= ~VIDINTCON0_INT_SYSSUBCON;
513 } else
514 val &= ~VIDINTCON0_INT_FRAME;
515
1c248b7d
ID		 516 writel(val, ctx->regs + VIDINTCON0);
517 }
518}
519
bb7704d6
SP		 520static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
521 struct exynos_drm_overlay *overlay)
1c248b7d 522{
400c8ac8 523 struct fimd_context *ctx = mgr_to_fimd(mgr);
1c248b7d 524 struct fimd_win_data *win_data;
864ee9e6 525 int win;
19c8b834 526 unsigned long offset;
1c248b7d 527
1c248b7d 528 if (!overlay) {
bb7704d6 529 DRM_ERROR("overlay is NULL\n");
1c248b7d
ID		 530 return;
531 }
532
864ee9e6
JS		 533 win = overlay->zpos;
534 if (win == DEFAULT_ZPOS)
535 win = ctx->default_win;
536
37b006e8 537 if (win < 0 || win >= WINDOWS_NR)
864ee9e6
JS		 538 return;
539
19c8b834
ID		 540 offset = overlay->fb_x * (overlay->bpp >> 3);
541 offset += overlay->fb_y * overlay->pitch;
542
543 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
544
864ee9e6 545 win_data = &ctx->win_data[win];
1c248b7d 546
19c8b834
ID		 547 win_data->offset_x = overlay->crtc_x;
548 win_data->offset_y = overlay->crtc_y;
549 win_data->ovl_width = overlay->crtc_width;
550 win_data->ovl_height = overlay->crtc_height;
551 win_data->fb_width = overlay->fb_width;
552 win_data->fb_height = overlay->fb_height;
229d3534 553 win_data->dma_addr = overlay->dma_addr[0] + offset;
1c248b7d 554 win_data->bpp = overlay->bpp;
a4f38a80 555 win_data->pixel_format = overlay->pixel_format;
19c8b834
ID		 556 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
557 (overlay->bpp >> 3);
558 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
559
560 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
561 win_data->offset_x, win_data->offset_y);
562 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
563 win_data->ovl_width, win_data->ovl_height);
ddd8e959 564 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
19c8b834
ID		 565 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
566 overlay->fb_width, overlay->crtc_width);
1c248b7d
ID		 567}
568
bb7704d6 569static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
1c248b7d 570{
1c248b7d
ID		 571 struct fimd_win_data *win_data = &ctx->win_data[win];
572 unsigned long val;
573
1c248b7d
ID		 574 val = WINCONx_ENWIN;
575
5cc4621a
ID		 576 /*
577 * In case of s3c64xx, window 0 doesn't support alpha channel.
578 * So the request format is ARGB8888 then change it to XRGB8888.
579 */
580 if (ctx->driver_data->has_limited_fmt && !win) {
581 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
582 win_data->pixel_format = DRM_FORMAT_XRGB8888;
583 }
584
a4f38a80
ID		 585 switch (win_data->pixel_format) {
586 case DRM_FORMAT_C8:
1c248b7d
ID		 587 val |= WINCON0_BPPMODE_8BPP_PALETTE;
588 val |= WINCONx_BURSTLEN_8WORD;
589 val |= WINCONx_BYTSWP;
590 break;
a4f38a80
ID		 591 case DRM_FORMAT_XRGB1555:
592 val |= WINCON0_BPPMODE_16BPP_1555;
593 val |= WINCONx_HAWSWP;
594 val |= WINCONx_BURSTLEN_16WORD;
595 break;
596 case DRM_FORMAT_RGB565:
1c248b7d
ID		 597 val |= WINCON0_BPPMODE_16BPP_565;
598 val |= WINCONx_HAWSWP;
599 val |= WINCONx_BURSTLEN_16WORD;
600 break;
a4f38a80 601 case DRM_FORMAT_XRGB8888:
1c248b7d
ID		 602 val |= WINCON0_BPPMODE_24BPP_888;
603 val |= WINCONx_WSWP;
604 val |= WINCONx_BURSTLEN_16WORD;
605 break;
a4f38a80
ID		 606 case DRM_FORMAT_ARGB8888:
607 val |= WINCON1_BPPMODE_25BPP_A1888
1c248b7d
ID		 608 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
609 val |= WINCONx_WSWP;
610 val |= WINCONx_BURSTLEN_16WORD;
611 break;
612 default:
613 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
614
615 val |= WINCON0_BPPMODE_24BPP_888;
616 val |= WINCONx_WSWP;
617 val |= WINCONx_BURSTLEN_16WORD;
618 break;
619 }
620
621 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
622
66367461
RS		 623 /*
624 * In case of exynos, setting dma-burst to 16Word causes permanent
625 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
626 * switching which is based on overlay size is not recommended as
627 * overlay size varies alot towards the end of the screen and rapid
628 * movement causes unstable DMA which results into iommu crash/tear.
629 */
630
631 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
632 val &= ~WINCONx_BURSTLEN_MASK;
633 val |= WINCONx_BURSTLEN_4WORD;
634 }
635
1c248b7d
ID		 636 writel(val, ctx->regs + WINCON(win));
637}
638
bb7704d6 639static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
1c248b7d 640{
1c248b7d
ID		 641 unsigned int keycon0 = 0, keycon1 = 0;
642
1c248b7d
ID		 643 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
644 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
645
646 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
647
648 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
649 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
650}
651
de7af100
TF		 652/**
653 * shadow_protect_win() - disable updating values from shadow registers at vsync
654 *
655 * @win: window to protect registers for
656 * @protect: 1 to protect (disable updates)
657 */
658static void fimd_shadow_protect_win(struct fimd_context *ctx,
659 int win, bool protect)
660{
661 u32 reg, bits, val;
662
663 if (ctx->driver_data->has_shadowcon) {
664 reg = SHADOWCON;
665 bits = SHADOWCON_WINx_PROTECT(win);
666 } else {
667 reg = PRTCON;
668 bits = PRTCON_PROTECT;
669 }
670
671 val = readl(ctx->regs + reg);
672 if (protect)
673 val |= bits;
674 else
675 val &= ~bits;
676 writel(val, ctx->regs + reg);
677}
678
bb7704d6 679static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
1c248b7d 680{
400c8ac8 681 struct fimd_context *ctx = mgr_to_fimd(mgr);
1c248b7d 682 struct fimd_win_data *win_data;
864ee9e6 683 int win = zpos;
1c248b7d 684 unsigned long val, alpha, size;
f56aad3a
JS		 685 unsigned int last_x;
686 unsigned int last_y;
1c248b7d 687
e30d4bcf
ID		 688 if (ctx->suspended)
689 return;
690
864ee9e6
JS		 691 if (win == DEFAULT_ZPOS)
692 win = ctx->default_win;
693
37b006e8 694 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 695 return;
696
697 win_data = &ctx->win_data[win];
698
a43b933b
SP		 699 /* If suspended, enable this on resume */
700 if (ctx->suspended) {
701 win_data->resume = true;
702 return;
703 }
704
1c248b7d 705 /*
de7af100 706 * SHADOWCON/PRTCON register is used for enabling timing.
1c248b7d
ID		 707 *
708 * for example, once only width value of a register is set,
709 * if the dma is started then fimd hardware could malfunction so
710 * with protect window setting, the register fields with prefix '_F'
711 * wouldn't be updated at vsync also but updated once unprotect window
712 * is set.
713 */
714
715 /* protect windows */
de7af100 716 fimd_shadow_protect_win(ctx, win, true);
1c248b7d
ID		 717
718 /* buffer start address */
2c871127 719 val = (unsigned long)win_data->dma_addr;
1c248b7d
ID		 720 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
721
722 /* buffer end address */
19c8b834 723 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
2c871127 724 val = (unsigned long)(win_data->dma_addr + size);
1c248b7d
ID		 725 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
726
727 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
2c871127 728 (unsigned long)win_data->dma_addr, val, size);
19c8b834
ID		 729 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
730 win_data->ovl_width, win_data->ovl_height);
1c248b7d
ID		 731
732 /* buffer size */
733 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
ca555e5a
JS		 734 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
735 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
736 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
1c248b7d
ID		 737 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
738
739 /* OSD position */
740 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
ca555e5a
JS		 741 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
742 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
743 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
1c248b7d
ID		 744 writel(val, ctx->regs + VIDOSD_A(win));
745
f56aad3a
JS		 746 last_x = win_data->offset_x + win_data->ovl_width;
747 if (last_x)
748 last_x--;
749 last_y = win_data->offset_y + win_data->ovl_height;
750 if (last_y)
751 last_y--;
752
ca555e5a
JS		 753 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
754 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
755
1c248b7d
ID		 756 writel(val, ctx->regs + VIDOSD_B(win));
757
19c8b834 758 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
f56aad3a 759 win_data->offset_x, win_data->offset_y, last_x, last_y);
1c248b7d
ID		 760
761 /* hardware window 0 doesn't support alpha channel. */
762 if (win != 0) {
763 /* OSD alpha */
764 alpha = VIDISD14C_ALPHA1_R(0xf) |
765 VIDISD14C_ALPHA1_G(0xf) |
766 VIDISD14C_ALPHA1_B(0xf);
767
768 writel(alpha, ctx->regs + VIDOSD_C(win));
769 }
770
771 /* OSD size */
772 if (win != 3 && win != 4) {
773 u32 offset = VIDOSD_D(win);
774 if (win == 0)
0f10cf14 775 offset = VIDOSD_C(win);
19c8b834 776 val = win_data->ovl_width * win_data->ovl_height;
1c248b7d
ID		 777 writel(val, ctx->regs + offset);
778
779 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
780 }
781
bb7704d6 782 fimd_win_set_pixfmt(ctx, win);
1c248b7d
ID		 783
784 /* hardware window 0 doesn't support color key. */
785 if (win != 0)
bb7704d6 786 fimd_win_set_colkey(ctx, win);
1c248b7d 787
f181a543 788 fimd_enable_video_output(ctx, win, true);
ec05da95 789
999d8b31
YC		 790 if (ctx->driver_data->has_shadowcon)
791 fimd_enable_shadow_channel_path(ctx, win, true);
ec05da95 792
74944a58
YC		 793 /* Enable DMA channel and unprotect windows */
794 fimd_shadow_protect_win(ctx, win, false);
795
ec05da95 796 win_data->enabled = true;
3854fab2
YC		 797
798 if (ctx->i80_if)
799 atomic_set(&ctx->win_updated, 1);
1c248b7d
ID		 800}
801
bb7704d6 802static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
1c248b7d 803{
400c8ac8 804 struct fimd_context *ctx = mgr_to_fimd(mgr);
ec05da95 805 struct fimd_win_data *win_data;
864ee9e6 806 int win = zpos;
1c248b7d 807
864ee9e6
JS		 808 if (win == DEFAULT_ZPOS)
809 win = ctx->default_win;
810
37b006e8 811 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 812 return;
813
ec05da95
ID		 814 win_data = &ctx->win_data[win];
815
db7e55ae
P		 816 if (ctx->suspended) {
817 /* do not resume this window*/
818 win_data->resume = false;
819 return;
820 }
821
1c248b7d 822 /* protect windows */
de7af100 823 fimd_shadow_protect_win(ctx, win, true);
1c248b7d 824
f181a543 825 fimd_enable_video_output(ctx, win, false);
1c248b7d 826
999d8b31
YC		 827 if (ctx->driver_data->has_shadowcon)
828 fimd_enable_shadow_channel_path(ctx, win, false);
de7af100 829
999d8b31 830 /* unprotect windows */
de7af100 831 fimd_shadow_protect_win(ctx, win, false);
ec05da95
ID		 832
833 win_data->enabled = false;
1c248b7d
ID		 834}
835
a43b933b
SP		 836static void fimd_window_suspend(struct exynos_drm_manager *mgr)
837{
400c8ac8 838 struct fimd_context *ctx = mgr_to_fimd(mgr);
a43b933b
SP		 839 struct fimd_win_data *win_data;
840 int i;
841
842 for (i = 0; i < WINDOWS_NR; i++) {
843 win_data = &ctx->win_data[i];
844 win_data->resume = win_data->enabled;
845 if (win_data->enabled)
846 fimd_win_disable(mgr, i);
847 }
a43b933b
SP		 848}
849
850static void fimd_window_resume(struct exynos_drm_manager *mgr)
851{
400c8ac8 852 struct fimd_context *ctx = mgr_to_fimd(mgr);
a43b933b
SP		 853 struct fimd_win_data *win_data;
854 int i;
855
856 for (i = 0; i < WINDOWS_NR; i++) {
857 win_data = &ctx->win_data[i];
858 win_data->enabled = win_data->resume;
859 win_data->resume = false;
860 }
861}
862
863static void fimd_apply(struct exynos_drm_manager *mgr)
864{
400c8ac8 865 struct fimd_context *ctx = mgr_to_fimd(mgr);
a43b933b
SP		 866 struct fimd_win_data *win_data;
867 int i;
868
869 for (i = 0; i < WINDOWS_NR; i++) {
870 win_data = &ctx->win_data[i];
871 if (win_data->enabled)
872 fimd_win_commit(mgr, i);
d9b68d89
AH		 873 else
874 fimd_win_disable(mgr, i);
a43b933b
SP		 875 }
876
877 fimd_commit(mgr);
878}
879
880static int fimd_poweron(struct exynos_drm_manager *mgr)
881{
400c8ac8 882 struct fimd_context *ctx = mgr_to_fimd(mgr);
a43b933b
SP		 883 int ret;
884
885 if (!ctx->suspended)
886 return 0;
887
888 ctx->suspended = false;
889
af65c804
SP		 890 pm_runtime_get_sync(ctx->dev);
891
a43b933b
SP		 892 ret = clk_prepare_enable(ctx->bus_clk);
893 if (ret < 0) {
894 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
895 goto bus_clk_err;
896 }
897
898 ret = clk_prepare_enable(ctx->lcd_clk);
899 if (ret < 0) {
900 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
901 goto lcd_clk_err;
902 }
903
904 /* if vblank was enabled status, enable it again. */
905 if (test_and_clear_bit(0, &ctx->irq_flags)) {
906 ret = fimd_enable_vblank(mgr);
907 if (ret) {
908 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
909 goto enable_vblank_err;
910 }
911 }
912
913 fimd_window_resume(mgr);
914
915 fimd_apply(mgr);
916
917 return 0;
918
919enable_vblank_err:
920 clk_disable_unprepare(ctx->lcd_clk);
921lcd_clk_err:
922 clk_disable_unprepare(ctx->bus_clk);
923bus_clk_err:
924 ctx->suspended = true;
925 return ret;
926}
927
928static int fimd_poweroff(struct exynos_drm_manager *mgr)
929{
400c8ac8 930 struct fimd_context *ctx = mgr_to_fimd(mgr);
a43b933b
SP		 931
932 if (ctx->suspended)
933 return 0;
934
935 /*
936 * We need to make sure that all windows are disabled before we
937 * suspend that connector. Otherwise we might try to scan from
938 * a destroyed buffer later.
939 */
940 fimd_window_suspend(mgr);
941
942 clk_disable_unprepare(ctx->lcd_clk);
943 clk_disable_unprepare(ctx->bus_clk);
944
af65c804
SP		 945 pm_runtime_put_sync(ctx->dev);
946
a43b933b
SP		 947 ctx->suspended = true;
948 return 0;
949}
950
080be03d
SP		 951static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
952{
af65c804 953 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
080be03d 954
080be03d
SP		 955 switch (mode) {
956 case DRM_MODE_DPMS_ON:
af65c804 957 fimd_poweron(mgr);
080be03d
SP		 958 break;
959 case DRM_MODE_DPMS_STANDBY:
960 case DRM_MODE_DPMS_SUSPEND:
961 case DRM_MODE_DPMS_OFF:
af65c804 962 fimd_poweroff(mgr);
080be03d
SP		 963 break;
964 default:
965 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
966 break;
967 }
080be03d
SP		 968}
969
3854fab2
YC		 970static void fimd_trigger(struct device *dev)
971{
e152dbd7 972 struct fimd_context *ctx = dev_get_drvdata(dev);
3854fab2
YC		 973 struct fimd_driver_data *driver_data = ctx->driver_data;
974 void *timing_base = ctx->regs + driver_data->timing_base;
975 u32 reg;
976
9b67eb73 977 /*
1c905d95
YC		 978 * Skips triggering if in triggering state, because multiple triggering
979 * requests can cause panel reset.
980 */
9b67eb73
JS		 981 if (atomic_read(&ctx->triggering))
982 return;
983
1c905d95 984 /* Enters triggering mode */
3854fab2
YC		 985 atomic_set(&ctx->triggering, 1);
986
3854fab2
YC		 987 reg = readl(timing_base + TRIGCON);
988 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
989 writel(reg, timing_base + TRIGCON);
87ab85b3
YC		 990
991 /*
992 * Exits triggering mode if vblank is not enabled yet, because when the
993 * VIDINTCON0 register is not set, it can not exit from triggering mode.
994 */
995 if (!test_bit(0, &ctx->irq_flags))
996 atomic_set(&ctx->triggering, 0);
3854fab2
YC		 997}
998
999static void fimd_te_handler(struct exynos_drm_manager *mgr)
1000{
400c8ac8 1001 struct fimd_context *ctx = mgr_to_fimd(mgr);
3854fab2
YC		 1002
1003 /* Checks the crtc is detached already from encoder */
1004 if (ctx->pipe < 0 || !ctx->drm_dev)
1005 return;
1006
3854fab2
YC		 1007 /*
1008 * If there is a page flip request, triggers and handles the page flip
1009 * event so that current fb can be updated into panel GRAM.
1010 */
1011 if (atomic_add_unless(&ctx->win_updated, -1, 0))
1012 fimd_trigger(ctx->dev);
1013
1014 /* Wakes up vsync event queue */
1015 if (atomic_read(&ctx->wait_vsync_event)) {
1016 atomic_set(&ctx->wait_vsync_event, 0);
1017 wake_up(&ctx->wait_vsync_queue);
3854fab2 1018 }
b301ae24 1019
adf67abf 1020 if (test_bit(0, &ctx->irq_flags))
b301ae24 1021 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
3854fab2
YC		 1022}
1023
1c6244c3
SP		 1024static struct exynos_drm_manager_ops fimd_manager_ops = {
1025 .dpms = fimd_dpms,
a968e727
SP		 1026 .mode_fixup = fimd_mode_fixup,
1027 .mode_set = fimd_mode_set,
1c6244c3
SP		 1028 .commit = fimd_commit,
1029 .enable_vblank = fimd_enable_vblank,
1030 .disable_vblank = fimd_disable_vblank,
1031 .wait_for_vblank = fimd_wait_for_vblank,
1032 .win_mode_set = fimd_win_mode_set,
1033 .win_commit = fimd_win_commit,
1034 .win_disable = fimd_win_disable,
3854fab2 1035 .te_handler = fimd_te_handler,
1c248b7d
ID		 1036};
1037
1c248b7d
ID		 1038static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1039{
1040 struct fimd_context *ctx = (struct fimd_context *)dev_id;
3854fab2 1041 u32 val, clear_bit;
1c248b7d
ID		 1042
1043 val = readl(ctx->regs + VIDINTCON1);
1044
3854fab2
YC		 1045 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1046 if (val & clear_bit)
1047 writel(clear_bit, ctx->regs + VIDINTCON1);
1c248b7d 1048
ec05da95 1049 /* check the crtc is detached already from encoder */
080be03d 1050 if (ctx->pipe < 0 || !ctx->drm_dev)
ec05da95 1051 goto out;
483b88f8 1052
1c905d95 1053 if (ctx->i80_if) {
adf67abf
JS		 1054 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1055
1c905d95 1056 /* Exits triggering mode */
3854fab2 1057 atomic_set(&ctx->triggering, 0);
3854fab2 1058 } else {
adf67abf
JS		 1059 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1060 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1061
3854fab2
YC		 1062 /* set wait vsync event to zero and wake up queue. */
1063 if (atomic_read(&ctx->wait_vsync_event)) {
1064 atomic_set(&ctx->wait_vsync_event, 0);
1065 wake_up(&ctx->wait_vsync_queue);
1066 }
01ce113c 1067 }
3854fab2 1068
ec05da95 1069out:
1c248b7d
ID		 1070 return IRQ_HANDLED;
1071}
1072
f37cd5e8 1073static int fimd_bind(struct device *dev, struct device *master, void *data)
562ad9f4 1074{
e152dbd7 1075 struct fimd_context *ctx = dev_get_drvdata(dev);
f37cd5e8 1076 struct drm_device *drm_dev = data;
000cc920 1077
e152dbd7
AH		 1078 fimd_mgr_initialize(&ctx->manager, drm_dev);
1079 exynos_drm_crtc_create(&ctx->manager);
000cc920
AH		 1080 if (ctx->display)
1081 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1082
000cc920
AH		 1083 return 0;
1084
1085}
1086
1087static void fimd_unbind(struct device *dev, struct device *master,
1088 void *data)
1089{
e152dbd7 1090 struct fimd_context *ctx = dev_get_drvdata(dev);
000cc920 1091
e152dbd7 1092 fimd_dpms(&ctx->manager, DRM_MODE_DPMS_OFF);
000cc920
AH		 1093
1094 if (ctx->display)
4cfde1f2 1095 exynos_dpi_remove(ctx->display);
000cc920 1096
e152dbd7 1097 fimd_mgr_remove(&ctx->manager);
000cc920
AH		 1098}
1099
1100static const struct component_ops fimd_component_ops = {
1101 .bind = fimd_bind,
1102 .unbind = fimd_unbind,
1103};
1104
1105static int fimd_probe(struct platform_device *pdev)
1106{
1107 struct device *dev = &pdev->dev;
562ad9f4 1108 struct fimd_context *ctx;
3854fab2 1109 struct device_node *i80_if_timings;
562ad9f4 1110 struct resource *res;
562ad9f4 1111 int ret = -EINVAL;
1c248b7d 1112
e152dbd7
AH		 1113 if (!dev->of_node)
1114 return -ENODEV;
2d3f173c 1115
d873ab99 1116 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
e152dbd7
AH		 1117 if (!ctx)
1118 return -ENOMEM;
1119
1120 ctx->manager.type = EXYNOS_DISPLAY_TYPE_LCD;
1121 ctx->manager.ops = &fimd_manager_ops;
1122
1123 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1124 ctx->manager.type);
1125 if (ret)
1126 return ret;
1c248b7d 1127
bb7704d6 1128 ctx->dev = dev;
a43b933b 1129 ctx->suspended = true;
3854fab2 1130 ctx->driver_data = drm_fimd_get_driver_data(pdev);
bb7704d6 1131
1417f109
SP		 1132 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1133 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1134 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1135 ctx->vidcon1 |= VIDCON1_INV_VCLK;
562ad9f4 1136
3854fab2
YC		 1137 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1138 if (i80_if_timings) {
1139 u32 val;
1140
1141 ctx->i80_if = true;
1142
1143 if (ctx->driver_data->has_vidoutcon)
1144 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1145 else
1146 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1147 /*
1148 * The user manual describes that this "DSI_EN" bit is required
1149 * to enable I80 24-bit data interface.
1150 */
1151 ctx->vidcon0 |= VIDCON0_DSI_EN;
1152
1153 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1154 val = 0;
1155 ctx->i80ifcon = LCD_CS_SETUP(val);
1156 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1157 val = 0;
1158 ctx->i80ifcon |= LCD_WR_SETUP(val);
1159 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1160 val = 1;
1161 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1162 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1163 val = 0;
1164 ctx->i80ifcon |= LCD_WR_HOLD(val);
1165 }
1166 of_node_put(i80_if_timings);
1167
1168 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1169 "samsung,sysreg");
1170 if (IS_ERR(ctx->sysreg)) {
1171 dev_warn(dev, "failed to get system register.\n");
1172 ctx->sysreg = NULL;
1173 }
1174
a968e727
SP		 1175 ctx->bus_clk = devm_clk_get(dev, "fimd");
1176 if (IS_ERR(ctx->bus_clk)) {
1177 dev_err(dev, "failed to get bus clock\n");
df5225bc
ID		 1178 ret = PTR_ERR(ctx->bus_clk);
1179 goto err_del_component;
a968e727
SP		 1180 }
1181
1182 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1183 if (IS_ERR(ctx->lcd_clk)) {
1184 dev_err(dev, "failed to get lcd clock\n");
df5225bc
ID		 1185 ret = PTR_ERR(ctx->lcd_clk);
1186 goto err_del_component;
a968e727 1187 }
1c248b7d 1188
1c248b7d 1189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1c248b7d 1190
d873ab99 1191 ctx->regs = devm_ioremap_resource(dev, res);
df5225bc
ID		 1192 if (IS_ERR(ctx->regs)) {
1193 ret = PTR_ERR(ctx->regs);
1194 goto err_del_component;
1195 }
1c248b7d 1196
3854fab2
YC		 1197 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1198 ctx->i80_if ? "lcd_sys" : "vsync");
1c248b7d
ID		 1199 if (!res) {
1200 dev_err(dev, "irq request failed.\n");
df5225bc
ID		 1201 ret = -ENXIO;
1202 goto err_del_component;
1c248b7d
ID		 1203 }
1204
055e0c06 1205 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
edc57266
SK		 1206 0, "drm_fimd", ctx);
1207 if (ret) {
1c248b7d 1208 dev_err(dev, "irq request failed.\n");
df5225bc 1209 goto err_del_component;
1c248b7d
ID		 1210 }
1211
57ed0f7b 1212 init_waitqueue_head(&ctx->wait_vsync_queue);
01ce113c 1213 atomic_set(&ctx->wait_vsync_event, 0);
1c248b7d 1214
e152dbd7 1215 platform_set_drvdata(pdev, ctx);
14b6873a 1216
000cc920 1217 ctx->display = exynos_dpi_probe(dev);
5baf5d44
GP		 1218 if (IS_ERR(ctx->display)) {
1219 ret = PTR_ERR(ctx->display);
1220 goto err_del_component;
1221 }
f37cd5e8 1222
e152dbd7 1223 pm_runtime_enable(dev);
f37cd5e8 1224
e152dbd7 1225 ret = component_add(dev, &fimd_component_ops);
df5225bc
ID		 1226 if (ret)
1227 goto err_disable_pm_runtime;
1228
1229 return ret;
1230
1231err_disable_pm_runtime:
e152dbd7 1232 pm_runtime_disable(dev);
df5225bc
ID		 1233
1234err_del_component:
e152dbd7 1235 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
df5225bc 1236 return ret;
f37cd5e8 1237}
cb91f6a0 1238
f37cd5e8
ID		 1239static int fimd_remove(struct platform_device *pdev)
1240{
af65c804 1241 pm_runtime_disable(&pdev->dev);
5d55393a 1242
df5225bc
ID		 1243 component_del(&pdev->dev, &fimd_component_ops);
1244 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1245
5d55393a 1246 return 0;
e30d4bcf
ID		 1247}
1248
132a5b91 1249struct platform_driver fimd_driver = {
1c248b7d 1250 .probe = fimd_probe,
56550d94 1251 .remove = fimd_remove,
1c248b7d
ID		 1252 .driver = {
1253 .name = "exynos4-fb",
1254 .owner = THIS_MODULE,
2d3f173c 1255 .of_match_table = fimd_driver_dt_match,
1c248b7d
ID		 1256 },
1257};
Linux kernel - Deliverables
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