Commit | Line | Data |
---|---|---|
1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
f37cd5e8 | 22 | #include <linux/component.h> |
1c248b7d | 23 | |
7f4596f4 | 24 | #include <video/of_display_timing.h> |
111e6055 | 25 | #include <video/of_videomode.h> |
5a213a55 | 26 | #include <video/samsung_fimd.h> |
1c248b7d | 27 | #include <drm/exynos_drm.h> |
1c248b7d ID |
28 | |
29 | #include "exynos_drm_drv.h" | |
30 | #include "exynos_drm_fbdev.h" | |
31 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 32 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
33 | |
34 | /* | |
b8654b37 | 35 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
36 | * as a display controller, it transfers contents drawn on memory |
37 | * to a LCD Panel through Display Interfaces such as RGB or | |
38 | * CPU Interface. | |
39 | */ | |
40 | ||
111e6055 AH |
41 | #define FIMD_DEFAULT_FRAMERATE 60 |
42 | ||
1c248b7d ID |
43 | /* position control register for hardware window 0, 2 ~ 4.*/ |
44 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
45 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
46 | /* |
47 | * size control register for hardware windows 0 and alpha control register | |
48 | * for hardware windows 1 ~ 4 | |
49 | */ | |
50 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
51 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
52 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
53 | ||
54 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
55 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
56 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
57 | ||
58 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 59 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 60 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 61 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d ID |
62 | |
63 | /* FIMD has totally five hardware windows. */ | |
64 | #define WINDOWS_NR 5 | |
65 | ||
bb7704d6 | 66 | #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev)) |
1c248b7d | 67 | |
e2e13389 LKA |
68 | struct fimd_driver_data { |
69 | unsigned int timing_base; | |
de7af100 TF |
70 | |
71 | unsigned int has_shadowcon:1; | |
411d9ed4 | 72 | unsigned int has_clksel:1; |
5cc4621a | 73 | unsigned int has_limited_fmt:1; |
e2e13389 LKA |
74 | }; |
75 | ||
725ddead TF |
76 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
77 | .timing_base = 0x0, | |
78 | .has_clksel = 1, | |
5cc4621a | 79 | .has_limited_fmt = 1, |
725ddead TF |
80 | }; |
81 | ||
6ecf18f9 | 82 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 83 | .timing_base = 0x0, |
de7af100 | 84 | .has_shadowcon = 1, |
e2e13389 LKA |
85 | }; |
86 | ||
6ecf18f9 | 87 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 88 | .timing_base = 0x20000, |
de7af100 | 89 | .has_shadowcon = 1, |
e2e13389 LKA |
90 | }; |
91 | ||
1c248b7d ID |
92 | struct fimd_win_data { |
93 | unsigned int offset_x; | |
94 | unsigned int offset_y; | |
19c8b834 ID |
95 | unsigned int ovl_width; |
96 | unsigned int ovl_height; | |
97 | unsigned int fb_width; | |
98 | unsigned int fb_height; | |
1c248b7d | 99 | unsigned int bpp; |
a4f38a80 | 100 | unsigned int pixel_format; |
2c871127 | 101 | dma_addr_t dma_addr; |
1c248b7d ID |
102 | unsigned int buf_offsize; |
103 | unsigned int line_size; /* bytes */ | |
ec05da95 | 104 | bool enabled; |
db7e55ae | 105 | bool resume; |
1c248b7d ID |
106 | }; |
107 | ||
108 | struct fimd_context { | |
bb7704d6 | 109 | struct device *dev; |
40c8ab4b | 110 | struct drm_device *drm_dev; |
1c248b7d ID |
111 | struct clk *bus_clk; |
112 | struct clk *lcd_clk; | |
1c248b7d | 113 | void __iomem *regs; |
a968e727 | 114 | struct drm_display_mode mode; |
1c248b7d | 115 | struct fimd_win_data win_data[WINDOWS_NR]; |
1c248b7d ID |
116 | unsigned int default_win; |
117 | unsigned long irq_flags; | |
1c248b7d | 118 | u32 vidcon1; |
cb91f6a0 | 119 | bool suspended; |
080be03d | 120 | int pipe; |
01ce113c P |
121 | wait_queue_head_t wait_vsync_queue; |
122 | atomic_t wait_vsync_event; | |
1c248b7d | 123 | |
562ad9f4 | 124 | struct exynos_drm_panel_info panel; |
18873465 | 125 | struct fimd_driver_data *driver_data; |
000cc920 | 126 | struct exynos_drm_display *display; |
1c248b7d ID |
127 | }; |
128 | ||
d636ead8 | 129 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
130 | { .compatible = "samsung,s3c6400-fimd", |
131 | .data = &s3c64xx_fimd_driver_data }, | |
5830daf8 | 132 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 133 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 134 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
135 | .data = &exynos5_fimd_driver_data }, |
136 | {}, | |
137 | }; | |
d636ead8 | 138 | |
e2e13389 LKA |
139 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
140 | struct platform_device *pdev) | |
141 | { | |
d636ead8 JS |
142 | const struct of_device_id *of_id = |
143 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
144 | ||
2d3f173c | 145 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
146 | } |
147 | ||
f13bdbd1 AA |
148 | static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr) |
149 | { | |
150 | struct fimd_context *ctx = mgr->ctx; | |
151 | ||
152 | if (ctx->suspended) | |
153 | return; | |
154 | ||
155 | atomic_set(&ctx->wait_vsync_event, 1); | |
156 | ||
157 | /* | |
158 | * wait for FIMD to signal VSYNC interrupt or return after | |
159 | * timeout which is set to 50ms (refresh rate of 20). | |
160 | */ | |
161 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
162 | !atomic_read(&ctx->wait_vsync_event), | |
163 | HZ/20)) | |
164 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
165 | } | |
166 | ||
167 | ||
168 | static void fimd_clear_channel(struct exynos_drm_manager *mgr) | |
169 | { | |
170 | struct fimd_context *ctx = mgr->ctx; | |
171 | int win, ch_enabled = 0; | |
172 | ||
173 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
174 | ||
175 | /* Check if any channel is enabled. */ | |
176 | for (win = 0; win < WINDOWS_NR; win++) { | |
177 | u32 val = readl(ctx->regs + SHADOWCON); | |
178 | if (val & SHADOWCON_CHx_ENABLE(win)) { | |
179 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
180 | writel(val, ctx->regs + SHADOWCON); | |
181 | ch_enabled = 1; | |
182 | } | |
183 | } | |
184 | ||
185 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
186 | if (ch_enabled) | |
187 | fimd_wait_for_vblank(mgr); | |
188 | } | |
189 | ||
bb7704d6 | 190 | static int fimd_mgr_initialize(struct exynos_drm_manager *mgr, |
f37cd5e8 | 191 | struct drm_device *drm_dev) |
40c8ab4b | 192 | { |
bb7704d6 | 193 | struct fimd_context *ctx = mgr->ctx; |
f37cd5e8 ID |
194 | struct exynos_drm_private *priv; |
195 | priv = drm_dev->dev_private; | |
40c8ab4b | 196 | |
f37cd5e8 ID |
197 | mgr->drm_dev = ctx->drm_dev = drm_dev; |
198 | mgr->pipe = ctx->pipe = priv->pipe++; | |
40c8ab4b | 199 | |
080be03d SP |
200 | /* |
201 | * enable drm irq mode. | |
202 | * - with irq_enabled = true, we can use the vblank feature. | |
203 | * | |
204 | * P.S. note that we wouldn't use drm irq handler but | |
205 | * just specific driver own one instead because | |
206 | * drm framework supports only one irq handler. | |
207 | */ | |
208 | drm_dev->irq_enabled = true; | |
ec05da95 | 209 | |
080be03d SP |
210 | /* |
211 | * with vblank_disable_allowed = true, vblank interrupt will be disabled | |
212 | * by drm timer once a current process gives up ownership of | |
213 | * vblank event.(after drm_vblank_put function is called) | |
214 | */ | |
215 | drm_dev->vblank_disable_allowed = true; | |
c32b06ef | 216 | |
080be03d | 217 | /* attach this sub driver to iommu mapping if supported. */ |
f13bdbd1 AA |
218 | if (is_drm_iommu_supported(ctx->drm_dev)) { |
219 | /* | |
220 | * If any channel is already active, iommu will throw | |
221 | * a PAGE FAULT when enabled. So clear any channel if enabled. | |
222 | */ | |
223 | fimd_clear_channel(mgr); | |
080be03d | 224 | drm_iommu_attach_device(ctx->drm_dev, ctx->dev); |
f13bdbd1 | 225 | } |
c32b06ef | 226 | |
080be03d | 227 | return 0; |
ec05da95 ID |
228 | } |
229 | ||
080be03d | 230 | static void fimd_mgr_remove(struct exynos_drm_manager *mgr) |
ec05da95 | 231 | { |
bb7704d6 | 232 | struct fimd_context *ctx = mgr->ctx; |
ec05da95 | 233 | |
080be03d SP |
234 | /* detach this sub driver from iommu mapping if supported. */ |
235 | if (is_drm_iommu_supported(ctx->drm_dev)) | |
236 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); | |
ec05da95 ID |
237 | } |
238 | ||
a968e727 SP |
239 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
240 | const struct drm_display_mode *mode) | |
241 | { | |
242 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
243 | u32 clkdiv; | |
244 | ||
245 | /* Find the clock divider value that gets us closest to ideal_clk */ | |
246 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); | |
247 | ||
248 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
249 | } | |
250 | ||
251 | static bool fimd_mode_fixup(struct exynos_drm_manager *mgr, | |
252 | const struct drm_display_mode *mode, | |
253 | struct drm_display_mode *adjusted_mode) | |
254 | { | |
255 | if (adjusted_mode->vrefresh == 0) | |
256 | adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; | |
257 | ||
258 | return true; | |
259 | } | |
260 | ||
261 | static void fimd_mode_set(struct exynos_drm_manager *mgr, | |
262 | const struct drm_display_mode *in_mode) | |
263 | { | |
264 | struct fimd_context *ctx = mgr->ctx; | |
265 | ||
266 | drm_mode_copy(&ctx->mode, in_mode); | |
267 | } | |
268 | ||
bb7704d6 | 269 | static void fimd_commit(struct exynos_drm_manager *mgr) |
1c248b7d | 270 | { |
bb7704d6 | 271 | struct fimd_context *ctx = mgr->ctx; |
a968e727 | 272 | struct drm_display_mode *mode = &ctx->mode; |
e2e13389 | 273 | struct fimd_driver_data *driver_data; |
1417f109 | 274 | u32 val, clkdiv, vidcon1; |
8b4cad23 | 275 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; |
1c248b7d | 276 | |
18873465 | 277 | driver_data = ctx->driver_data; |
e30d4bcf ID |
278 | if (ctx->suspended) |
279 | return; | |
280 | ||
a968e727 SP |
281 | /* nothing to do if we haven't set the mode yet */ |
282 | if (mode->htotal == 0 || mode->vtotal == 0) | |
283 | return; | |
284 | ||
1417f109 SP |
285 | /* setup polarity values */ |
286 | vidcon1 = ctx->vidcon1; | |
287 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
288 | vidcon1 |= VIDCON1_INV_VSYNC; | |
289 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
290 | vidcon1 |= VIDCON1_INV_HSYNC; | |
291 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
1c248b7d ID |
292 | |
293 | /* setup vertical timing values. */ | |
a968e727 | 294 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
8b4cad23 AH |
295 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; |
296 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
a968e727 SP |
297 | |
298 | val = VIDTCON0_VBPD(vbpd - 1) | | |
299 | VIDTCON0_VFPD(vfpd - 1) | | |
300 | VIDTCON0_VSPW(vsync_len - 1); | |
e2e13389 | 301 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
302 | |
303 | /* setup horizontal timing values. */ | |
a968e727 | 304 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
8b4cad23 AH |
305 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; |
306 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
a968e727 SP |
307 | |
308 | val = VIDTCON1_HBPD(hbpd - 1) | | |
309 | VIDTCON1_HFPD(hfpd - 1) | | |
310 | VIDTCON1_HSPW(hsync_len - 1); | |
e2e13389 | 311 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
312 | |
313 | /* setup horizontal and vertical display size. */ | |
a968e727 SP |
314 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
315 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
316 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
317 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 318 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 319 | |
1d531062 AH |
320 | /* |
321 | * fields of register with prefix '_F' would be updated | |
322 | * at vsync(same as dma start) | |
323 | */ | |
324 | val = VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 325 | |
1d531062 | 326 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 327 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 328 | |
a968e727 SP |
329 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
330 | if (clkdiv > 1) | |
331 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 332 | |
1c248b7d ID |
333 | writel(val, ctx->regs + VIDCON0); |
334 | } | |
335 | ||
bb7704d6 | 336 | static int fimd_enable_vblank(struct exynos_drm_manager *mgr) |
1c248b7d | 337 | { |
bb7704d6 | 338 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d ID |
339 | u32 val; |
340 | ||
cb91f6a0 JS |
341 | if (ctx->suspended) |
342 | return -EPERM; | |
343 | ||
1c248b7d ID |
344 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
345 | val = readl(ctx->regs + VIDINTCON0); | |
346 | ||
347 | val |= VIDINTCON0_INT_ENABLE; | |
348 | val |= VIDINTCON0_INT_FRAME; | |
349 | ||
350 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
351 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
352 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
353 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
354 | ||
355 | writel(val, ctx->regs + VIDINTCON0); | |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
bb7704d6 | 361 | static void fimd_disable_vblank(struct exynos_drm_manager *mgr) |
1c248b7d | 362 | { |
bb7704d6 | 363 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d ID |
364 | u32 val; |
365 | ||
cb91f6a0 JS |
366 | if (ctx->suspended) |
367 | return; | |
368 | ||
1c248b7d ID |
369 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
370 | val = readl(ctx->regs + VIDINTCON0); | |
371 | ||
372 | val &= ~VIDINTCON0_INT_FRAME; | |
373 | val &= ~VIDINTCON0_INT_ENABLE; | |
374 | ||
375 | writel(val, ctx->regs + VIDINTCON0); | |
376 | } | |
377 | } | |
378 | ||
bb7704d6 SP |
379 | static void fimd_win_mode_set(struct exynos_drm_manager *mgr, |
380 | struct exynos_drm_overlay *overlay) | |
1c248b7d | 381 | { |
bb7704d6 | 382 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d | 383 | struct fimd_win_data *win_data; |
864ee9e6 | 384 | int win; |
19c8b834 | 385 | unsigned long offset; |
1c248b7d | 386 | |
1c248b7d | 387 | if (!overlay) { |
bb7704d6 | 388 | DRM_ERROR("overlay is NULL\n"); |
1c248b7d ID |
389 | return; |
390 | } | |
391 | ||
864ee9e6 JS |
392 | win = overlay->zpos; |
393 | if (win == DEFAULT_ZPOS) | |
394 | win = ctx->default_win; | |
395 | ||
37b006e8 | 396 | if (win < 0 || win >= WINDOWS_NR) |
864ee9e6 JS |
397 | return; |
398 | ||
19c8b834 ID |
399 | offset = overlay->fb_x * (overlay->bpp >> 3); |
400 | offset += overlay->fb_y * overlay->pitch; | |
401 | ||
402 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
403 | ||
864ee9e6 | 404 | win_data = &ctx->win_data[win]; |
1c248b7d | 405 | |
19c8b834 ID |
406 | win_data->offset_x = overlay->crtc_x; |
407 | win_data->offset_y = overlay->crtc_y; | |
408 | win_data->ovl_width = overlay->crtc_width; | |
409 | win_data->ovl_height = overlay->crtc_height; | |
410 | win_data->fb_width = overlay->fb_width; | |
411 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 412 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 413 | win_data->bpp = overlay->bpp; |
a4f38a80 | 414 | win_data->pixel_format = overlay->pixel_format; |
19c8b834 ID |
415 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
416 | (overlay->bpp >> 3); | |
417 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
418 | ||
419 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
420 | win_data->offset_x, win_data->offset_y); | |
421 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
422 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 423 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
424 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
425 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
426 | } |
427 | ||
bb7704d6 | 428 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 429 | { |
1c248b7d ID |
430 | struct fimd_win_data *win_data = &ctx->win_data[win]; |
431 | unsigned long val; | |
432 | ||
1c248b7d ID |
433 | val = WINCONx_ENWIN; |
434 | ||
5cc4621a ID |
435 | /* |
436 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
437 | * So the request format is ARGB8888 then change it to XRGB8888. | |
438 | */ | |
439 | if (ctx->driver_data->has_limited_fmt && !win) { | |
440 | if (win_data->pixel_format == DRM_FORMAT_ARGB8888) | |
441 | win_data->pixel_format = DRM_FORMAT_XRGB8888; | |
442 | } | |
443 | ||
a4f38a80 ID |
444 | switch (win_data->pixel_format) { |
445 | case DRM_FORMAT_C8: | |
1c248b7d ID |
446 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
447 | val |= WINCONx_BURSTLEN_8WORD; | |
448 | val |= WINCONx_BYTSWP; | |
449 | break; | |
a4f38a80 ID |
450 | case DRM_FORMAT_XRGB1555: |
451 | val |= WINCON0_BPPMODE_16BPP_1555; | |
452 | val |= WINCONx_HAWSWP; | |
453 | val |= WINCONx_BURSTLEN_16WORD; | |
454 | break; | |
455 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
456 | val |= WINCON0_BPPMODE_16BPP_565; |
457 | val |= WINCONx_HAWSWP; | |
458 | val |= WINCONx_BURSTLEN_16WORD; | |
459 | break; | |
a4f38a80 | 460 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
461 | val |= WINCON0_BPPMODE_24BPP_888; |
462 | val |= WINCONx_WSWP; | |
463 | val |= WINCONx_BURSTLEN_16WORD; | |
464 | break; | |
a4f38a80 ID |
465 | case DRM_FORMAT_ARGB8888: |
466 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
467 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
468 | val |= WINCONx_WSWP; | |
469 | val |= WINCONx_BURSTLEN_16WORD; | |
470 | break; | |
471 | default: | |
472 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
473 | ||
474 | val |= WINCON0_BPPMODE_24BPP_888; | |
475 | val |= WINCONx_WSWP; | |
476 | val |= WINCONx_BURSTLEN_16WORD; | |
477 | break; | |
478 | } | |
479 | ||
480 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
481 | ||
482 | writel(val, ctx->regs + WINCON(win)); | |
483 | } | |
484 | ||
bb7704d6 | 485 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 486 | { |
1c248b7d ID |
487 | unsigned int keycon0 = 0, keycon1 = 0; |
488 | ||
1c248b7d ID |
489 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
490 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
491 | ||
492 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
493 | ||
494 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
495 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
496 | } | |
497 | ||
de7af100 TF |
498 | /** |
499 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
500 | * | |
501 | * @win: window to protect registers for | |
502 | * @protect: 1 to protect (disable updates) | |
503 | */ | |
504 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
505 | int win, bool protect) | |
506 | { | |
507 | u32 reg, bits, val; | |
508 | ||
509 | if (ctx->driver_data->has_shadowcon) { | |
510 | reg = SHADOWCON; | |
511 | bits = SHADOWCON_WINx_PROTECT(win); | |
512 | } else { | |
513 | reg = PRTCON; | |
514 | bits = PRTCON_PROTECT; | |
515 | } | |
516 | ||
517 | val = readl(ctx->regs + reg); | |
518 | if (protect) | |
519 | val |= bits; | |
520 | else | |
521 | val &= ~bits; | |
522 | writel(val, ctx->regs + reg); | |
523 | } | |
524 | ||
bb7704d6 | 525 | static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos) |
1c248b7d | 526 | { |
bb7704d6 | 527 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d | 528 | struct fimd_win_data *win_data; |
864ee9e6 | 529 | int win = zpos; |
1c248b7d | 530 | unsigned long val, alpha, size; |
f56aad3a JS |
531 | unsigned int last_x; |
532 | unsigned int last_y; | |
1c248b7d | 533 | |
e30d4bcf ID |
534 | if (ctx->suspended) |
535 | return; | |
536 | ||
864ee9e6 JS |
537 | if (win == DEFAULT_ZPOS) |
538 | win = ctx->default_win; | |
539 | ||
37b006e8 | 540 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
541 | return; |
542 | ||
543 | win_data = &ctx->win_data[win]; | |
544 | ||
a43b933b SP |
545 | /* If suspended, enable this on resume */ |
546 | if (ctx->suspended) { | |
547 | win_data->resume = true; | |
548 | return; | |
549 | } | |
550 | ||
1c248b7d | 551 | /* |
de7af100 | 552 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
553 | * |
554 | * for example, once only width value of a register is set, | |
555 | * if the dma is started then fimd hardware could malfunction so | |
556 | * with protect window setting, the register fields with prefix '_F' | |
557 | * wouldn't be updated at vsync also but updated once unprotect window | |
558 | * is set. | |
559 | */ | |
560 | ||
561 | /* protect windows */ | |
de7af100 | 562 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
563 | |
564 | /* buffer start address */ | |
2c871127 | 565 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
566 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
567 | ||
568 | /* buffer end address */ | |
19c8b834 | 569 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 570 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
571 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
572 | ||
573 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 574 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
575 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
576 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
577 | |
578 | /* buffer size */ | |
579 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
580 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
581 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
582 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
583 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
584 | ||
585 | /* OSD position */ | |
586 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
587 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
588 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
589 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
590 | writel(val, ctx->regs + VIDOSD_A(win)); |
591 | ||
f56aad3a JS |
592 | last_x = win_data->offset_x + win_data->ovl_width; |
593 | if (last_x) | |
594 | last_x--; | |
595 | last_y = win_data->offset_y + win_data->ovl_height; | |
596 | if (last_y) | |
597 | last_y--; | |
598 | ||
ca555e5a JS |
599 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
600 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
601 | ||
1c248b7d ID |
602 | writel(val, ctx->regs + VIDOSD_B(win)); |
603 | ||
19c8b834 | 604 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 605 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
606 | |
607 | /* hardware window 0 doesn't support alpha channel. */ | |
608 | if (win != 0) { | |
609 | /* OSD alpha */ | |
610 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
611 | VIDISD14C_ALPHA1_G(0xf) | | |
612 | VIDISD14C_ALPHA1_B(0xf); | |
613 | ||
614 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
615 | } | |
616 | ||
617 | /* OSD size */ | |
618 | if (win != 3 && win != 4) { | |
619 | u32 offset = VIDOSD_D(win); | |
620 | if (win == 0) | |
0f10cf14 | 621 | offset = VIDOSD_C(win); |
19c8b834 | 622 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
623 | writel(val, ctx->regs + offset); |
624 | ||
625 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
626 | } | |
627 | ||
bb7704d6 | 628 | fimd_win_set_pixfmt(ctx, win); |
1c248b7d ID |
629 | |
630 | /* hardware window 0 doesn't support color key. */ | |
631 | if (win != 0) | |
bb7704d6 | 632 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 633 | |
ec05da95 ID |
634 | /* wincon */ |
635 | val = readl(ctx->regs + WINCON(win)); | |
636 | val |= WINCONx_ENWIN; | |
637 | writel(val, ctx->regs + WINCON(win)); | |
638 | ||
1c248b7d | 639 | /* Enable DMA channel and unprotect windows */ |
de7af100 TF |
640 | fimd_shadow_protect_win(ctx, win, false); |
641 | ||
642 | if (ctx->driver_data->has_shadowcon) { | |
643 | val = readl(ctx->regs + SHADOWCON); | |
644 | val |= SHADOWCON_CHx_ENABLE(win); | |
645 | writel(val, ctx->regs + SHADOWCON); | |
646 | } | |
ec05da95 ID |
647 | |
648 | win_data->enabled = true; | |
1c248b7d ID |
649 | } |
650 | ||
bb7704d6 | 651 | static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos) |
1c248b7d | 652 | { |
bb7704d6 | 653 | struct fimd_context *ctx = mgr->ctx; |
ec05da95 | 654 | struct fimd_win_data *win_data; |
864ee9e6 | 655 | int win = zpos; |
1c248b7d ID |
656 | u32 val; |
657 | ||
864ee9e6 JS |
658 | if (win == DEFAULT_ZPOS) |
659 | win = ctx->default_win; | |
660 | ||
37b006e8 | 661 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
662 | return; |
663 | ||
ec05da95 ID |
664 | win_data = &ctx->win_data[win]; |
665 | ||
db7e55ae P |
666 | if (ctx->suspended) { |
667 | /* do not resume this window*/ | |
668 | win_data->resume = false; | |
669 | return; | |
670 | } | |
671 | ||
1c248b7d | 672 | /* protect windows */ |
de7af100 | 673 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
674 | |
675 | /* wincon */ | |
676 | val = readl(ctx->regs + WINCON(win)); | |
677 | val &= ~WINCONx_ENWIN; | |
678 | writel(val, ctx->regs + WINCON(win)); | |
679 | ||
680 | /* unprotect windows */ | |
de7af100 TF |
681 | if (ctx->driver_data->has_shadowcon) { |
682 | val = readl(ctx->regs + SHADOWCON); | |
683 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
684 | writel(val, ctx->regs + SHADOWCON); | |
685 | } | |
686 | ||
687 | fimd_shadow_protect_win(ctx, win, false); | |
ec05da95 ID |
688 | |
689 | win_data->enabled = false; | |
1c248b7d ID |
690 | } |
691 | ||
a43b933b SP |
692 | static void fimd_clear_win(struct fimd_context *ctx, int win) |
693 | { | |
694 | writel(0, ctx->regs + WINCON(win)); | |
695 | writel(0, ctx->regs + VIDOSD_A(win)); | |
696 | writel(0, ctx->regs + VIDOSD_B(win)); | |
697 | writel(0, ctx->regs + VIDOSD_C(win)); | |
698 | ||
699 | if (win == 1 || win == 2) | |
700 | writel(0, ctx->regs + VIDOSD_D(win)); | |
701 | ||
702 | fimd_shadow_protect_win(ctx, win, false); | |
703 | } | |
704 | ||
705 | static void fimd_window_suspend(struct exynos_drm_manager *mgr) | |
706 | { | |
707 | struct fimd_context *ctx = mgr->ctx; | |
708 | struct fimd_win_data *win_data; | |
709 | int i; | |
710 | ||
711 | for (i = 0; i < WINDOWS_NR; i++) { | |
712 | win_data = &ctx->win_data[i]; | |
713 | win_data->resume = win_data->enabled; | |
714 | if (win_data->enabled) | |
715 | fimd_win_disable(mgr, i); | |
716 | } | |
717 | fimd_wait_for_vblank(mgr); | |
718 | } | |
719 | ||
720 | static void fimd_window_resume(struct exynos_drm_manager *mgr) | |
721 | { | |
722 | struct fimd_context *ctx = mgr->ctx; | |
723 | struct fimd_win_data *win_data; | |
724 | int i; | |
725 | ||
726 | for (i = 0; i < WINDOWS_NR; i++) { | |
727 | win_data = &ctx->win_data[i]; | |
728 | win_data->enabled = win_data->resume; | |
729 | win_data->resume = false; | |
730 | } | |
731 | } | |
732 | ||
733 | static void fimd_apply(struct exynos_drm_manager *mgr) | |
734 | { | |
735 | struct fimd_context *ctx = mgr->ctx; | |
736 | struct fimd_win_data *win_data; | |
737 | int i; | |
738 | ||
739 | for (i = 0; i < WINDOWS_NR; i++) { | |
740 | win_data = &ctx->win_data[i]; | |
741 | if (win_data->enabled) | |
742 | fimd_win_commit(mgr, i); | |
743 | } | |
744 | ||
745 | fimd_commit(mgr); | |
746 | } | |
747 | ||
748 | static int fimd_poweron(struct exynos_drm_manager *mgr) | |
749 | { | |
750 | struct fimd_context *ctx = mgr->ctx; | |
751 | int ret; | |
752 | ||
753 | if (!ctx->suspended) | |
754 | return 0; | |
755 | ||
756 | ctx->suspended = false; | |
757 | ||
af65c804 SP |
758 | pm_runtime_get_sync(ctx->dev); |
759 | ||
a43b933b SP |
760 | ret = clk_prepare_enable(ctx->bus_clk); |
761 | if (ret < 0) { | |
762 | DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); | |
763 | goto bus_clk_err; | |
764 | } | |
765 | ||
766 | ret = clk_prepare_enable(ctx->lcd_clk); | |
767 | if (ret < 0) { | |
768 | DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); | |
769 | goto lcd_clk_err; | |
770 | } | |
771 | ||
772 | /* if vblank was enabled status, enable it again. */ | |
773 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
774 | ret = fimd_enable_vblank(mgr); | |
775 | if (ret) { | |
776 | DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); | |
777 | goto enable_vblank_err; | |
778 | } | |
779 | } | |
780 | ||
781 | fimd_window_resume(mgr); | |
782 | ||
783 | fimd_apply(mgr); | |
784 | ||
785 | return 0; | |
786 | ||
787 | enable_vblank_err: | |
788 | clk_disable_unprepare(ctx->lcd_clk); | |
789 | lcd_clk_err: | |
790 | clk_disable_unprepare(ctx->bus_clk); | |
791 | bus_clk_err: | |
792 | ctx->suspended = true; | |
793 | return ret; | |
794 | } | |
795 | ||
796 | static int fimd_poweroff(struct exynos_drm_manager *mgr) | |
797 | { | |
798 | struct fimd_context *ctx = mgr->ctx; | |
799 | ||
800 | if (ctx->suspended) | |
801 | return 0; | |
802 | ||
803 | /* | |
804 | * We need to make sure that all windows are disabled before we | |
805 | * suspend that connector. Otherwise we might try to scan from | |
806 | * a destroyed buffer later. | |
807 | */ | |
808 | fimd_window_suspend(mgr); | |
809 | ||
810 | clk_disable_unprepare(ctx->lcd_clk); | |
811 | clk_disable_unprepare(ctx->bus_clk); | |
812 | ||
af65c804 SP |
813 | pm_runtime_put_sync(ctx->dev); |
814 | ||
a43b933b SP |
815 | ctx->suspended = true; |
816 | return 0; | |
817 | } | |
818 | ||
080be03d SP |
819 | static void fimd_dpms(struct exynos_drm_manager *mgr, int mode) |
820 | { | |
af65c804 | 821 | DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); |
080be03d | 822 | |
080be03d SP |
823 | switch (mode) { |
824 | case DRM_MODE_DPMS_ON: | |
af65c804 | 825 | fimd_poweron(mgr); |
080be03d SP |
826 | break; |
827 | case DRM_MODE_DPMS_STANDBY: | |
828 | case DRM_MODE_DPMS_SUSPEND: | |
829 | case DRM_MODE_DPMS_OFF: | |
af65c804 | 830 | fimd_poweroff(mgr); |
080be03d SP |
831 | break; |
832 | default: | |
833 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
834 | break; | |
835 | } | |
080be03d SP |
836 | } |
837 | ||
1c6244c3 SP |
838 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
839 | .dpms = fimd_dpms, | |
a968e727 SP |
840 | .mode_fixup = fimd_mode_fixup, |
841 | .mode_set = fimd_mode_set, | |
1c6244c3 SP |
842 | .commit = fimd_commit, |
843 | .enable_vblank = fimd_enable_vblank, | |
844 | .disable_vblank = fimd_disable_vblank, | |
845 | .wait_for_vblank = fimd_wait_for_vblank, | |
846 | .win_mode_set = fimd_win_mode_set, | |
847 | .win_commit = fimd_win_commit, | |
848 | .win_disable = fimd_win_disable, | |
1c248b7d ID |
849 | }; |
850 | ||
677e84c1 | 851 | static struct exynos_drm_manager fimd_manager = { |
080be03d SP |
852 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
853 | .ops = &fimd_manager_ops, | |
677e84c1 JS |
854 | }; |
855 | ||
1c248b7d ID |
856 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
857 | { | |
858 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
1c248b7d ID |
859 | u32 val; |
860 | ||
861 | val = readl(ctx->regs + VIDINTCON1); | |
862 | ||
863 | if (val & VIDINTCON1_INT_FRAME) | |
864 | /* VSYNC interrupt */ | |
865 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
866 | ||
ec05da95 | 867 | /* check the crtc is detached already from encoder */ |
080be03d | 868 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 869 | goto out; |
483b88f8 | 870 | |
080be03d SP |
871 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); |
872 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); | |
1c248b7d | 873 | |
01ce113c P |
874 | /* set wait vsync event to zero and wake up queue. */ |
875 | if (atomic_read(&ctx->wait_vsync_event)) { | |
876 | atomic_set(&ctx->wait_vsync_event, 0); | |
8dd9ad5d | 877 | wake_up(&ctx->wait_vsync_queue); |
01ce113c | 878 | } |
ec05da95 | 879 | out: |
1c248b7d ID |
880 | return IRQ_HANDLED; |
881 | } | |
882 | ||
f37cd5e8 | 883 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 884 | { |
000cc920 | 885 | struct fimd_context *ctx = fimd_manager.ctx; |
f37cd5e8 | 886 | struct drm_device *drm_dev = data; |
000cc920 AH |
887 | int win; |
888 | ||
889 | fimd_mgr_initialize(&fimd_manager, drm_dev); | |
890 | exynos_drm_crtc_create(&fimd_manager); | |
891 | if (ctx->display) | |
892 | exynos_drm_create_enc_conn(drm_dev, ctx->display); | |
893 | ||
894 | for (win = 0; win < WINDOWS_NR; win++) | |
895 | fimd_clear_win(ctx, win); | |
896 | ||
897 | return 0; | |
898 | ||
899 | } | |
900 | ||
901 | static void fimd_unbind(struct device *dev, struct device *master, | |
902 | void *data) | |
903 | { | |
904 | struct exynos_drm_manager *mgr = dev_get_drvdata(dev); | |
905 | struct fimd_context *ctx = fimd_manager.ctx; | |
906 | struct drm_crtc *crtc = mgr->crtc; | |
907 | ||
908 | fimd_dpms(mgr, DRM_MODE_DPMS_OFF); | |
909 | ||
910 | if (ctx->display) | |
911 | exynos_dpi_remove(dev); | |
912 | ||
913 | fimd_mgr_remove(mgr); | |
914 | ||
915 | crtc->funcs->destroy(crtc); | |
916 | } | |
917 | ||
918 | static const struct component_ops fimd_component_ops = { | |
919 | .bind = fimd_bind, | |
920 | .unbind = fimd_unbind, | |
921 | }; | |
922 | ||
923 | static int fimd_probe(struct platform_device *pdev) | |
924 | { | |
925 | struct device *dev = &pdev->dev; | |
562ad9f4 | 926 | struct fimd_context *ctx; |
562ad9f4 | 927 | struct resource *res; |
562ad9f4 | 928 | int ret = -EINVAL; |
1c248b7d | 929 | |
2d3f173c SK |
930 | if (!dev->of_node) |
931 | return -ENODEV; | |
932 | ||
d873ab99 | 933 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
934 | if (!ctx) |
935 | return -ENOMEM; | |
936 | ||
bb7704d6 | 937 | ctx->dev = dev; |
a43b933b | 938 | ctx->suspended = true; |
bb7704d6 | 939 | |
1417f109 SP |
940 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
941 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
942 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
943 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 944 | |
a968e727 SP |
945 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
946 | if (IS_ERR(ctx->bus_clk)) { | |
947 | dev_err(dev, "failed to get bus clock\n"); | |
948 | return PTR_ERR(ctx->bus_clk); | |
949 | } | |
950 | ||
951 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
952 | if (IS_ERR(ctx->lcd_clk)) { | |
953 | dev_err(dev, "failed to get lcd clock\n"); | |
954 | return PTR_ERR(ctx->lcd_clk); | |
955 | } | |
1c248b7d | 956 | |
1c248b7d | 957 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 958 | |
d873ab99 | 959 | ctx->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
960 | if (IS_ERR(ctx->regs)) |
961 | return PTR_ERR(ctx->regs); | |
1c248b7d | 962 | |
1977e6d8 | 963 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync"); |
1c248b7d ID |
964 | if (!res) { |
965 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 966 | return -ENXIO; |
1c248b7d ID |
967 | } |
968 | ||
055e0c06 | 969 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
970 | 0, "drm_fimd", ctx); |
971 | if (ret) { | |
1c248b7d | 972 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 973 | return ret; |
1c248b7d ID |
974 | } |
975 | ||
18873465 | 976 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
57ed0f7b | 977 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 978 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 979 | |
bb7704d6 | 980 | platform_set_drvdata(pdev, &fimd_manager); |
c32b06ef | 981 | |
080be03d | 982 | fimd_manager.ctx = ctx; |
14b6873a | 983 | |
000cc920 AH |
984 | ctx->display = exynos_dpi_probe(dev); |
985 | if (IS_ERR(ctx->display)) | |
986 | return PTR_ERR(ctx->display); | |
f37cd5e8 ID |
987 | |
988 | pm_runtime_enable(&pdev->dev); | |
989 | ||
990 | return exynos_drm_component_add(&pdev->dev, &fimd_component_ops); | |
991 | } | |
cb91f6a0 | 992 | |
f37cd5e8 ID |
993 | static int fimd_remove(struct platform_device *pdev) |
994 | { | |
af65c804 | 995 | pm_runtime_disable(&pdev->dev); |
5d55393a | 996 | |
f37cd5e8 | 997 | exynos_drm_component_del(&pdev->dev, &fimd_component_ops); |
5d55393a | 998 | return 0; |
e30d4bcf ID |
999 | } |
1000 | ||
132a5b91 | 1001 | struct platform_driver fimd_driver = { |
1c248b7d | 1002 | .probe = fimd_probe, |
56550d94 | 1003 | .remove = fimd_remove, |
1c248b7d ID |
1004 | .driver = { |
1005 | .name = "exynos4-fb", | |
1006 | .owner = THIS_MODULE, | |
2d3f173c | 1007 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1008 | }, |
1009 | }; |