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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
CommitLineData
1c248b7d
ID		 1/* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
760285e7 14#include <drm/drmP.h>
1c248b7d
ID		 15
16#include <linux/kernel.h>
1c248b7d
ID		 17#include <linux/platform_device.h>
18#include <linux/clk.h>
3f1c781d 19#include <linux/of.h>
d636ead8 20#include <linux/of_device.h>
cb91f6a0 21#include <linux/pm_runtime.h>
f37cd5e8 22#include <linux/component.h>
3854fab2
YC		 23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
1c248b7d 25
7f4596f4 26#include <video/of_display_timing.h>
111e6055 27#include <video/of_videomode.h>
5a213a55 28#include <video/samsung_fimd.h>
1c248b7d 29#include <drm/exynos_drm.h>
1c248b7d
ID		 30
31#include "exynos_drm_drv.h"
32#include "exynos_drm_fbdev.h"
33#include "exynos_drm_crtc.h"
bcc5cd1c 34#include "exynos_drm_iommu.h"
1c248b7d
ID		 35
36/*
b8654b37 37 * FIMD stands for Fully Interactive Mobile Display and
1c248b7d
ID		 38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
40 * CPU Interface.
41 */
42
111e6055 43#define FIMD_DEFAULT_FRAMERATE 60
66367461 44#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
111e6055 45
1c248b7d
ID		 46/* position control register for hardware window 0, 2 ~ 4.*/
47#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
0f10cf14
LKA		 49/*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54/* size control register for hardware windows 1 ~ 2. */
1c248b7d
ID		 55#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
60
61/* color key control register for hardware window 1 ~ 4. */
0f10cf14 62#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
1c248b7d 63/* color key value register for hardware window 1 ~ 4. */
0f10cf14 64#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
1c248b7d 65
3854fab2
YC		 66/* I80 / RGB trigger control register */
67#define TRIGCON 0x1A4
68#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69#define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
70
71/* display mode change control register except exynos4 */
72#define VIDOUT_CON 0x000
73#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
74
75/* I80 interface control for main LDI register */
76#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78#define LCD_CS_SETUP(x) ((x) << 16)
79#define LCD_WR_SETUP(x) ((x) << 12)
80#define LCD_WR_ACTIVE(x) ((x) << 8)
81#define LCD_WR_HOLD(x) ((x) << 4)
82#define I80IFEN_ENABLE (1 << 0)
83
1c248b7d
ID		 84/* FIMD has totally five hardware windows. */
85#define WINDOWS_NR 5
86
e2e13389
LKA		 87struct fimd_driver_data {
88 unsigned int timing_base;
3854fab2
YC		 89 unsigned int lcdblk_offset;
90 unsigned int lcdblk_vt_shift;
91 unsigned int lcdblk_bypass_shift;
de7af100
TF		 92
93 unsigned int has_shadowcon:1;
411d9ed4 94 unsigned int has_clksel:1;
5cc4621a 95 unsigned int has_limited_fmt:1;
3854fab2 96 unsigned int has_vidoutcon:1;
3c3c9c1d 97 unsigned int has_vtsel:1;
e2e13389
LKA		 98};
99
725ddead
TF		 100static struct fimd_driver_data s3c64xx_fimd_driver_data = {
101 .timing_base = 0x0,
102 .has_clksel = 1,
5cc4621a 103 .has_limited_fmt = 1,
725ddead
TF		 104};
105
d6ce7b58
ID		 106static struct fimd_driver_data exynos3_fimd_driver_data = {
107 .timing_base = 0x20000,
108 .lcdblk_offset = 0x210,
109 .lcdblk_bypass_shift = 1,
110 .has_shadowcon = 1,
111 .has_vidoutcon = 1,
112};
113
6ecf18f9 114static struct fimd_driver_data exynos4_fimd_driver_data = {
e2e13389 115 .timing_base = 0x0,
3854fab2
YC		 116 .lcdblk_offset = 0x210,
117 .lcdblk_vt_shift = 10,
118 .lcdblk_bypass_shift = 1,
de7af100 119 .has_shadowcon = 1,
3c3c9c1d 120 .has_vtsel = 1,
e2e13389
LKA		 121};
122
dcb622aa
YC		 123static struct fimd_driver_data exynos4415_fimd_driver_data = {
124 .timing_base = 0x20000,
125 .lcdblk_offset = 0x210,
126 .lcdblk_vt_shift = 10,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
3c3c9c1d 130 .has_vtsel = 1,
dcb622aa
YC		 131};
132
6ecf18f9 133static struct fimd_driver_data exynos5_fimd_driver_data = {
e2e13389 134 .timing_base = 0x20000,
3854fab2
YC		 135 .lcdblk_offset = 0x214,
136 .lcdblk_vt_shift = 24,
137 .lcdblk_bypass_shift = 15,
de7af100 138 .has_shadowcon = 1,
3854fab2 139 .has_vidoutcon = 1,
3c3c9c1d 140 .has_vtsel = 1,
e2e13389
LKA		 141};
142
1c248b7d
ID		 143struct fimd_win_data {
144 unsigned int offset_x;
145 unsigned int offset_y;
19c8b834
ID		 146 unsigned int ovl_width;
147 unsigned int ovl_height;
148 unsigned int fb_width;
149 unsigned int fb_height;
adacb228 150 unsigned int fb_pitch;
1c248b7d 151 unsigned int bpp;
a4f38a80 152 unsigned int pixel_format;
2c871127 153 dma_addr_t dma_addr;
1c248b7d
ID		 154 unsigned int buf_offsize;
155 unsigned int line_size; /* bytes */
ec05da95 156 bool enabled;
db7e55ae 157 bool resume;
1c248b7d
ID		 158};
159
160struct fimd_context {
bb7704d6 161 struct device *dev;
40c8ab4b 162 struct drm_device *drm_dev;
93bca243 163 struct exynos_drm_crtc *crtc;
1c248b7d
ID		 164 struct clk *bus_clk;
165 struct clk *lcd_clk;
1c248b7d 166 void __iomem *regs;
3854fab2 167 struct regmap *sysreg;
1c248b7d 168 struct fimd_win_data win_data[WINDOWS_NR];
1c248b7d
ID		 169 unsigned int default_win;
170 unsigned long irq_flags;
3854fab2 171 u32 vidcon0;
1c248b7d 172 u32 vidcon1;
3854fab2
YC		 173 u32 vidout_con;
174 u32 i80ifcon;
175 bool i80_if;
cb91f6a0 176 bool suspended;
080be03d 177 int pipe;
01ce113c
P		 178 wait_queue_head_t wait_vsync_queue;
179 atomic_t wait_vsync_event;
3854fab2
YC		 180 atomic_t win_updated;
181 atomic_t triggering;
1c248b7d 182
562ad9f4 183 struct exynos_drm_panel_info panel;
18873465 184 struct fimd_driver_data *driver_data;
000cc920 185 struct exynos_drm_display *display;
1c248b7d
ID		 186};
187
d636ead8 188static const struct of_device_id fimd_driver_dt_match[] = {
725ddead
TF		 189 { .compatible = "samsung,s3c6400-fimd",
190 .data = &s3c64xx_fimd_driver_data },
d6ce7b58
ID		 191 { .compatible = "samsung,exynos3250-fimd",
192 .data = &exynos3_fimd_driver_data },
5830daf8 193 { .compatible = "samsung,exynos4210-fimd",
d636ead8 194 .data = &exynos4_fimd_driver_data },
dcb622aa
YC		 195 { .compatible = "samsung,exynos4415-fimd",
196 .data = &exynos4415_fimd_driver_data },
5830daf8 197 { .compatible = "samsung,exynos5250-fimd",
d636ead8
JS		 198 .data = &exynos5_fimd_driver_data },
199 {},
200};
0262ceeb 201MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
d636ead8 202
e2e13389
LKA		 203static inline struct fimd_driver_data *drm_fimd_get_driver_data(
204 struct platform_device *pdev)
205{
d636ead8
JS		 206 const struct of_device_id *of_id =
207 of_match_device(fimd_driver_dt_match, &pdev->dev);
208
2d3f173c 209 return (struct fimd_driver_data *)of_id->data;
e2e13389
LKA		 210}
211
93bca243 212static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
f13bdbd1 213{
93bca243 214 struct fimd_context *ctx = crtc->ctx;
f13bdbd1
AA		 215
216 if (ctx->suspended)
217 return;
218
219 atomic_set(&ctx->wait_vsync_event, 1);
220
221 /*
222 * wait for FIMD to signal VSYNC interrupt or return after
223 * timeout which is set to 50ms (refresh rate of 20).
224 */
225 if (!wait_event_timeout(ctx->wait_vsync_queue,
226 !atomic_read(&ctx->wait_vsync_event),
227 HZ/20))
228 DRM_DEBUG_KMS("vblank wait timed out.\n");
229}
230
f181a543
YC		 231static void fimd_enable_video_output(struct fimd_context *ctx, int win,
232 bool enable)
233{
234 u32 val = readl(ctx->regs + WINCON(win));
235
236 if (enable)
237 val |= WINCONx_ENWIN;
238 else
239 val &= ~WINCONx_ENWIN;
240
241 writel(val, ctx->regs + WINCON(win));
242}
243
999d8b31
YC		 244static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
245 bool enable)
246{
247 u32 val = readl(ctx->regs + SHADOWCON);
248
249 if (enable)
250 val |= SHADOWCON_CHx_ENABLE(win);
251 else
252 val &= ~SHADOWCON_CHx_ENABLE(win);
253
254 writel(val, ctx->regs + SHADOWCON);
255}
256
92dc7a04 257static void fimd_clear_channel(struct fimd_context *ctx)
f13bdbd1 258{
f13bdbd1
AA		 259 int win, ch_enabled = 0;
260
261 DRM_DEBUG_KMS("%s\n", __FILE__);
262
263 /* Check if any channel is enabled. */
264 for (win = 0; win < WINDOWS_NR; win++) {
eb8a3bf7
MS		 265 u32 val = readl(ctx->regs + WINCON(win));
266
267 if (val & WINCONx_ENWIN) {
f181a543 268 fimd_enable_video_output(ctx, win, false);
eb8a3bf7 269
999d8b31
YC		 270 if (ctx->driver_data->has_shadowcon)
271 fimd_enable_shadow_channel_path(ctx, win,
272 false);
273
f13bdbd1
AA		 274 ch_enabled = 1;
275 }
276 }
277
278 /* Wait for vsync, as disable channel takes effect at next vsync */
eb8a3bf7
MS		 279 if (ch_enabled) {
280 unsigned int state = ctx->suspended;
281
282 ctx->suspended = 0;
92dc7a04 283 fimd_wait_for_vblank(ctx->crtc);
eb8a3bf7
MS		 284 ctx->suspended = state;
285 }
f13bdbd1
AA		 286}
287
cdbfca89 288static int fimd_iommu_attach_devices(struct fimd_context *ctx,
f37cd5e8 289 struct drm_device *drm_dev)
40c8ab4b 290{
40c8ab4b 291
080be03d 292 /* attach this sub driver to iommu mapping if supported. */
f13bdbd1 293 if (is_drm_iommu_supported(ctx->drm_dev)) {
efa75bcd
AK		 294 int ret;
295
f13bdbd1
AA		 296 /*
297 * If any channel is already active, iommu will throw
298 * a PAGE FAULT when enabled. So clear any channel if enabled.
299 */
92dc7a04 300 fimd_clear_channel(ctx);
efa75bcd
AK		 301 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
302 if (ret) {
303 DRM_ERROR("drm_iommu_attach failed.\n");
304 return ret;
305 }
306
f13bdbd1 307 }
c32b06ef 308
080be03d 309 return 0;
ec05da95
ID		 310}
311
cdbfca89 312static void fimd_iommu_detach_devices(struct fimd_context *ctx)
ec05da95 313{
080be03d
SP		 314 /* detach this sub driver from iommu mapping if supported. */
315 if (is_drm_iommu_supported(ctx->drm_dev))
316 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
ec05da95
ID		 317}
318
a968e727
SP		 319static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
320 const struct drm_display_mode *mode)
321{
322 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
323 u32 clkdiv;
324
3854fab2
YC		 325 if (ctx->i80_if) {
326 /*
327 * The frame done interrupt should be occurred prior to the
328 * next TE signal.
329 */
330 ideal_clk *= 2;
331 }
332
a968e727
SP		 333 /* Find the clock divider value that gets us closest to ideal_clk */
334 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
335
336 return (clkdiv < 0x100) ? clkdiv : 0xff;
337}
338
93bca243 339static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
a968e727
SP		 340 const struct drm_display_mode *mode,
341 struct drm_display_mode *adjusted_mode)
342{
343 if (adjusted_mode->vrefresh == 0)
344 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
345
346 return true;
347}
348
93bca243 349static void fimd_commit(struct exynos_drm_crtc *crtc)
1c248b7d 350{
93bca243 351 struct fimd_context *ctx = crtc->ctx;
a8dc5ed6 352 struct drm_display_mode *mode = &crtc->base.mode;
3854fab2
YC		 353 struct fimd_driver_data *driver_data = ctx->driver_data;
354 void *timing_base = ctx->regs + driver_data->timing_base;
355 u32 val, clkdiv;
1c248b7d 356
e30d4bcf
ID		 357 if (ctx->suspended)
358 return;
359
a968e727
SP		 360 /* nothing to do if we haven't set the mode yet */
361 if (mode->htotal == 0 || mode->vtotal == 0)
362 return;
363
3854fab2
YC		 364 if (ctx->i80_if) {
365 val = ctx->i80ifcon | I80IFEN_ENABLE;
366 writel(val, timing_base + I80IFCONFAx(0));
367
368 /* disable auto frame rate */
369 writel(0, timing_base + I80IFCONFBx(0));
370
371 /* set video type selection to I80 interface */
3c3c9c1d
JS		 372 if (driver_data->has_vtsel && ctx->sysreg &&
373 regmap_update_bits(ctx->sysreg,
3854fab2
YC		 374 driver_data->lcdblk_offset,
375 0x3 << driver_data->lcdblk_vt_shift,
376 0x1 << driver_data->lcdblk_vt_shift)) {
377 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
378 return;
379 }
380 } else {
381 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
382 u32 vidcon1;
383
384 /* setup polarity values */
385 vidcon1 = ctx->vidcon1;
386 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
387 vidcon1 |= VIDCON1_INV_VSYNC;
388 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
389 vidcon1 |= VIDCON1_INV_HSYNC;
390 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
391
392 /* setup vertical timing values. */
393 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
394 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
395 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
396
397 val = VIDTCON0_VBPD(vbpd - 1) |
398 VIDTCON0_VFPD(vfpd - 1) |
399 VIDTCON0_VSPW(vsync_len - 1);
400 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
401
402 /* setup horizontal timing values. */
403 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
404 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
405 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
406
407 val = VIDTCON1_HBPD(hbpd - 1) |
408 VIDTCON1_HFPD(hfpd - 1) |
409 VIDTCON1_HSPW(hsync_len - 1);
410 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
411 }
412
413 if (driver_data->has_vidoutcon)
414 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
415
416 /* set bypass selection */
417 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
418 driver_data->lcdblk_offset,
419 0x1 << driver_data->lcdblk_bypass_shift,
420 0x1 << driver_data->lcdblk_bypass_shift)) {
421 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
422 return;
423 }
1c248b7d
ID		 424
425 /* setup horizontal and vertical display size. */
a968e727
SP		 426 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
427 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
428 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
429 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
e2e13389 430 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
1c248b7d 431
1d531062
AH		 432 /*
433 * fields of register with prefix '_F' would be updated
434 * at vsync(same as dma start)
435 */
3854fab2
YC		 436 val = ctx->vidcon0;
437 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
1c248b7d 438
1d531062 439 if (ctx->driver_data->has_clksel)
411d9ed4 440 val |= VIDCON0_CLKSEL_LCD;
411d9ed4 441
a968e727
SP		 442 clkdiv = fimd_calc_clkdiv(ctx, mode);
443 if (clkdiv > 1)
444 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
1c248b7d 445
1c248b7d
ID		 446 writel(val, ctx->regs + VIDCON0);
447}
448
93bca243 449static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
1c248b7d 450{
93bca243 451 struct fimd_context *ctx = crtc->ctx;
1c248b7d
ID		 452 u32 val;
453
cb91f6a0
JS		 454 if (ctx->suspended)
455 return -EPERM;
456
1c248b7d
ID		 457 if (!test_and_set_bit(0, &ctx->irq_flags)) {
458 val = readl(ctx->regs + VIDINTCON0);
459
460 val |= VIDINTCON0_INT_ENABLE;
1c248b7d 461
1c905d95
YC		 462 if (ctx->i80_if) {
463 val |= VIDINTCON0_INT_I80IFDONE;
464 val |= VIDINTCON0_INT_SYSMAINCON;
465 val &= ~VIDINTCON0_INT_SYSSUBCON;
466 } else {
467 val |= VIDINTCON0_INT_FRAME;
468
469 val &= ~VIDINTCON0_FRAMESEL0_MASK;
470 val |= VIDINTCON0_FRAMESEL0_VSYNC;
471 val &= ~VIDINTCON0_FRAMESEL1_MASK;
472 val |= VIDINTCON0_FRAMESEL1_NONE;
473 }
1c248b7d
ID		 474
475 writel(val, ctx->regs + VIDINTCON0);
476 }
477
478 return 0;
479}
480
93bca243 481static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
1c248b7d 482{
93bca243 483 struct fimd_context *ctx = crtc->ctx;
1c248b7d
ID		 484 u32 val;
485
cb91f6a0
JS		 486 if (ctx->suspended)
487 return;
488
1c248b7d
ID		 489 if (test_and_clear_bit(0, &ctx->irq_flags)) {
490 val = readl(ctx->regs + VIDINTCON0);
491
1c248b7d
ID		 492 val &= ~VIDINTCON0_INT_ENABLE;
493
1c905d95
YC		 494 if (ctx->i80_if) {
495 val &= ~VIDINTCON0_INT_I80IFDONE;
496 val &= ~VIDINTCON0_INT_SYSMAINCON;
497 val &= ~VIDINTCON0_INT_SYSSUBCON;
498 } else
499 val &= ~VIDINTCON0_INT_FRAME;
500
1c248b7d
ID		 501 writel(val, ctx->regs + VIDINTCON0);
502 }
503}
504
93bca243 505static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
8837deea 506 struct exynos_drm_plane *plane)
1c248b7d 507{
93bca243 508 struct fimd_context *ctx = crtc->ctx;
1c248b7d 509 struct fimd_win_data *win_data;
864ee9e6 510 int win;
19c8b834 511 unsigned long offset;
1c248b7d 512
8837deea
GP		 513 if (!plane) {
514 DRM_ERROR("plane is NULL\n");
1c248b7d
ID		 515 return;
516 }
517
8837deea 518 win = plane->zpos;
864ee9e6
JS		 519 if (win == DEFAULT_ZPOS)
520 win = ctx->default_win;
521
37b006e8 522 if (win < 0 || win >= WINDOWS_NR)
864ee9e6
JS		 523 return;
524
8837deea
GP		 525 offset = plane->fb_x * (plane->bpp >> 3);
526 offset += plane->fb_y * plane->pitch;
19c8b834 527
8837deea 528 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, plane->pitch);
19c8b834 529
864ee9e6 530 win_data = &ctx->win_data[win];
1c248b7d 531
8837deea
GP		 532 win_data->offset_x = plane->crtc_x;
533 win_data->offset_y = plane->crtc_y;
534 win_data->ovl_width = plane->crtc_width;
535 win_data->ovl_height = plane->crtc_height;
adacb228 536 win_data->fb_pitch = plane->pitch;
8837deea
GP		 537 win_data->fb_width = plane->fb_width;
538 win_data->fb_height = plane->fb_height;
539 win_data->dma_addr = plane->dma_addr[0] + offset;
540 win_data->bpp = plane->bpp;
541 win_data->pixel_format = plane->pixel_format;
adacb228
DS		 542 win_data->buf_offsize =
543 plane->pitch - (plane->crtc_width * (plane->bpp >> 3));
8837deea 544 win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
19c8b834
ID		 545
546 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
547 win_data->offset_x, win_data->offset_y);
548 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
549 win_data->ovl_width, win_data->ovl_height);
ddd8e959 550 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
19c8b834 551 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
8837deea 552 plane->fb_width, plane->crtc_width);
1c248b7d
ID		 553}
554
bb7704d6 555static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
1c248b7d 556{
1c248b7d
ID		 557 struct fimd_win_data *win_data = &ctx->win_data[win];
558 unsigned long val;
559
1c248b7d
ID		 560 val = WINCONx_ENWIN;
561
5cc4621a
ID		 562 /*
563 * In case of s3c64xx, window 0 doesn't support alpha channel.
564 * So the request format is ARGB8888 then change it to XRGB8888.
565 */
566 if (ctx->driver_data->has_limited_fmt && !win) {
567 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
568 win_data->pixel_format = DRM_FORMAT_XRGB8888;
569 }
570
a4f38a80
ID		 571 switch (win_data->pixel_format) {
572 case DRM_FORMAT_C8:
1c248b7d
ID		 573 val |= WINCON0_BPPMODE_8BPP_PALETTE;
574 val |= WINCONx_BURSTLEN_8WORD;
575 val |= WINCONx_BYTSWP;
576 break;
a4f38a80
ID		 577 case DRM_FORMAT_XRGB1555:
578 val |= WINCON0_BPPMODE_16BPP_1555;
579 val |= WINCONx_HAWSWP;
580 val |= WINCONx_BURSTLEN_16WORD;
581 break;
582 case DRM_FORMAT_RGB565:
1c248b7d
ID		 583 val |= WINCON0_BPPMODE_16BPP_565;
584 val |= WINCONx_HAWSWP;
585 val |= WINCONx_BURSTLEN_16WORD;
586 break;
a4f38a80 587 case DRM_FORMAT_XRGB8888:
1c248b7d
ID		 588 val |= WINCON0_BPPMODE_24BPP_888;
589 val |= WINCONx_WSWP;
590 val |= WINCONx_BURSTLEN_16WORD;
591 break;
a4f38a80
ID		 592 case DRM_FORMAT_ARGB8888:
593 val |= WINCON1_BPPMODE_25BPP_A1888
1c248b7d
ID		 594 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
595 val |= WINCONx_WSWP;
596 val |= WINCONx_BURSTLEN_16WORD;
597 break;
598 default:
599 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
600
601 val |= WINCON0_BPPMODE_24BPP_888;
602 val |= WINCONx_WSWP;
603 val |= WINCONx_BURSTLEN_16WORD;
604 break;
605 }
606
607 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
608
66367461
RS		 609 /*
610 * In case of exynos, setting dma-burst to 16Word causes permanent
611 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
8837deea
GP		 612 * switching which is based on plane size is not recommended as
613 * plane size varies alot towards the end of the screen and rapid
66367461
RS		 614 * movement causes unstable DMA which results into iommu crash/tear.
615 */
616
617 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
618 val &= ~WINCONx_BURSTLEN_MASK;
619 val |= WINCONx_BURSTLEN_4WORD;
620 }
621
1c248b7d
ID		 622 writel(val, ctx->regs + WINCON(win));
623}
624
bb7704d6 625static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
1c248b7d 626{
1c248b7d
ID		 627 unsigned int keycon0 = 0, keycon1 = 0;
628
1c248b7d
ID		 629 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
630 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
631
632 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
633
634 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
635 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
636}
637
de7af100
TF		 638/**
639 * shadow_protect_win() - disable updating values from shadow registers at vsync
640 *
641 * @win: window to protect registers for
642 * @protect: 1 to protect (disable updates)
643 */
644static void fimd_shadow_protect_win(struct fimd_context *ctx,
645 int win, bool protect)
646{
647 u32 reg, bits, val;
648
649 if (ctx->driver_data->has_shadowcon) {
650 reg = SHADOWCON;
651 bits = SHADOWCON_WINx_PROTECT(win);
652 } else {
653 reg = PRTCON;
654 bits = PRTCON_PROTECT;
655 }
656
657 val = readl(ctx->regs + reg);
658 if (protect)
659 val |= bits;
660 else
661 val &= ~bits;
662 writel(val, ctx->regs + reg);
663}
664
93bca243 665static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
1c248b7d 666{
93bca243 667 struct fimd_context *ctx = crtc->ctx;
1c248b7d 668 struct fimd_win_data *win_data;
864ee9e6 669 int win = zpos;
1c248b7d 670 unsigned long val, alpha, size;
f56aad3a
JS		 671 unsigned int last_x;
672 unsigned int last_y;
1c248b7d 673
e30d4bcf
ID		 674 if (ctx->suspended)
675 return;
676
864ee9e6
JS		 677 if (win == DEFAULT_ZPOS)
678 win = ctx->default_win;
679
37b006e8 680 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 681 return;
682
683 win_data = &ctx->win_data[win];
684
a43b933b
SP		 685 /* If suspended, enable this on resume */
686 if (ctx->suspended) {
687 win_data->resume = true;
688 return;
689 }
690
1c248b7d 691 /*
de7af100 692 * SHADOWCON/PRTCON register is used for enabling timing.
1c248b7d
ID		 693 *
694 * for example, once only width value of a register is set,
695 * if the dma is started then fimd hardware could malfunction so
696 * with protect window setting, the register fields with prefix '_F'
697 * wouldn't be updated at vsync also but updated once unprotect window
698 * is set.
699 */
700
701 /* protect windows */
de7af100 702 fimd_shadow_protect_win(ctx, win, true);
1c248b7d
ID		 703
704 /* buffer start address */
2c871127 705 val = (unsigned long)win_data->dma_addr;
1c248b7d
ID		 706 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
707
708 /* buffer end address */
adacb228 709 size = win_data->fb_pitch * win_data->ovl_height * (win_data->bpp >> 3);
2c871127 710 val = (unsigned long)(win_data->dma_addr + size);
1c248b7d
ID		 711 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
712
713 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
2c871127 714 (unsigned long)win_data->dma_addr, val, size);
19c8b834
ID		 715 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
716 win_data->ovl_width, win_data->ovl_height);
1c248b7d
ID		 717
718 /* buffer size */
719 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
ca555e5a
JS		 720 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
721 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
722 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
1c248b7d
ID		 723 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
724
725 /* OSD position */
726 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
ca555e5a
JS		 727 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
728 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
729 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
1c248b7d
ID		 730 writel(val, ctx->regs + VIDOSD_A(win));
731
f56aad3a
JS		 732 last_x = win_data->offset_x + win_data->ovl_width;
733 if (last_x)
734 last_x--;
735 last_y = win_data->offset_y + win_data->ovl_height;
736 if (last_y)
737 last_y--;
738
ca555e5a
JS		 739 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
740 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
741
1c248b7d
ID		 742 writel(val, ctx->regs + VIDOSD_B(win));
743
19c8b834 744 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
f56aad3a 745 win_data->offset_x, win_data->offset_y, last_x, last_y);
1c248b7d
ID		 746
747 /* hardware window 0 doesn't support alpha channel. */
748 if (win != 0) {
749 /* OSD alpha */
750 alpha = VIDISD14C_ALPHA1_R(0xf) |
751 VIDISD14C_ALPHA1_G(0xf) |
752 VIDISD14C_ALPHA1_B(0xf);
753
754 writel(alpha, ctx->regs + VIDOSD_C(win));
755 }
756
757 /* OSD size */
758 if (win != 3 && win != 4) {
759 u32 offset = VIDOSD_D(win);
760 if (win == 0)
0f10cf14 761 offset = VIDOSD_C(win);
19c8b834 762 val = win_data->ovl_width * win_data->ovl_height;
1c248b7d
ID		 763 writel(val, ctx->regs + offset);
764
765 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
766 }
767
bb7704d6 768 fimd_win_set_pixfmt(ctx, win);
1c248b7d
ID		 769
770 /* hardware window 0 doesn't support color key. */
771 if (win != 0)
bb7704d6 772 fimd_win_set_colkey(ctx, win);
1c248b7d 773
f181a543 774 fimd_enable_video_output(ctx, win, true);
ec05da95 775
999d8b31
YC		 776 if (ctx->driver_data->has_shadowcon)
777 fimd_enable_shadow_channel_path(ctx, win, true);
ec05da95 778
74944a58
YC		 779 /* Enable DMA channel and unprotect windows */
780 fimd_shadow_protect_win(ctx, win, false);
781
ec05da95 782 win_data->enabled = true;
3854fab2
YC		 783
784 if (ctx->i80_if)
785 atomic_set(&ctx->win_updated, 1);
1c248b7d
ID		 786}
787
93bca243 788static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos)
1c248b7d 789{
93bca243 790 struct fimd_context *ctx = crtc->ctx;
ec05da95 791 struct fimd_win_data *win_data;
864ee9e6 792 int win = zpos;
1c248b7d 793
864ee9e6
JS		 794 if (win == DEFAULT_ZPOS)
795 win = ctx->default_win;
796
37b006e8 797 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 798 return;
799
ec05da95
ID		 800 win_data = &ctx->win_data[win];
801
db7e55ae
P		 802 if (ctx->suspended) {
803 /* do not resume this window*/
804 win_data->resume = false;
805 return;
806 }
807
1c248b7d 808 /* protect windows */
de7af100 809 fimd_shadow_protect_win(ctx, win, true);
1c248b7d 810
f181a543 811 fimd_enable_video_output(ctx, win, false);
1c248b7d 812
999d8b31
YC		 813 if (ctx->driver_data->has_shadowcon)
814 fimd_enable_shadow_channel_path(ctx, win, false);
de7af100 815
999d8b31 816 /* unprotect windows */
de7af100 817 fimd_shadow_protect_win(ctx, win, false);
ec05da95
ID		 818
819 win_data->enabled = false;
1c248b7d
ID		 820}
821
92dc7a04 822static void fimd_window_suspend(struct fimd_context *ctx)
a43b933b 823{
a43b933b
SP		 824 struct fimd_win_data *win_data;
825 int i;
826
827 for (i = 0; i < WINDOWS_NR; i++) {
828 win_data = &ctx->win_data[i];
829 win_data->resume = win_data->enabled;
830 if (win_data->enabled)
92dc7a04 831 fimd_win_disable(ctx->crtc, i);
a43b933b 832 }
a43b933b
SP		 833}
834
92dc7a04 835static void fimd_window_resume(struct fimd_context *ctx)
a43b933b 836{
a43b933b
SP		 837 struct fimd_win_data *win_data;
838 int i;
839
840 for (i = 0; i < WINDOWS_NR; i++) {
841 win_data = &ctx->win_data[i];
842 win_data->enabled = win_data->resume;
843 win_data->resume = false;
844 }
845}
846
92dc7a04 847static void fimd_apply(struct fimd_context *ctx)
a43b933b 848{
a43b933b
SP		 849 struct fimd_win_data *win_data;
850 int i;
851
852 for (i = 0; i < WINDOWS_NR; i++) {
853 win_data = &ctx->win_data[i];
854 if (win_data->enabled)
92dc7a04 855 fimd_win_commit(ctx->crtc, i);
d9b68d89 856 else
92dc7a04 857 fimd_win_disable(ctx->crtc, i);
a43b933b
SP		 858 }
859
92dc7a04 860 fimd_commit(ctx->crtc);
a43b933b
SP		 861}
862
92dc7a04 863static int fimd_poweron(struct fimd_context *ctx)
a43b933b 864{
a43b933b
SP		 865 int ret;
866
867 if (!ctx->suspended)
868 return 0;
869
870 ctx->suspended = false;
871
af65c804
SP		 872 pm_runtime_get_sync(ctx->dev);
873
a43b933b
SP		 874 ret = clk_prepare_enable(ctx->bus_clk);
875 if (ret < 0) {
876 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
877 goto bus_clk_err;
878 }
879
880 ret = clk_prepare_enable(ctx->lcd_clk);
881 if (ret < 0) {
882 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
883 goto lcd_clk_err;
884 }
885
886 /* if vblank was enabled status, enable it again. */
887 if (test_and_clear_bit(0, &ctx->irq_flags)) {
92dc7a04 888 ret = fimd_enable_vblank(ctx->crtc);
a43b933b
SP		 889 if (ret) {
890 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
891 goto enable_vblank_err;
892 }
893 }
894
92dc7a04 895 fimd_window_resume(ctx);
a43b933b 896
92dc7a04 897 fimd_apply(ctx);
a43b933b
SP		 898
899 return 0;
900
901enable_vblank_err:
902 clk_disable_unprepare(ctx->lcd_clk);
903lcd_clk_err:
904 clk_disable_unprepare(ctx->bus_clk);
905bus_clk_err:
906 ctx->suspended = true;
907 return ret;
908}
909
92dc7a04 910static int fimd_poweroff(struct fimd_context *ctx)
a43b933b 911{
a43b933b
SP		 912 if (ctx->suspended)
913 return 0;
914
915 /*
916 * We need to make sure that all windows are disabled before we
917 * suspend that connector. Otherwise we might try to scan from
918 * a destroyed buffer later.
919 */
92dc7a04 920 fimd_window_suspend(ctx);
a43b933b
SP		 921
922 clk_disable_unprepare(ctx->lcd_clk);
923 clk_disable_unprepare(ctx->bus_clk);
924
af65c804
SP		 925 pm_runtime_put_sync(ctx->dev);
926
a43b933b
SP		 927 ctx->suspended = true;
928 return 0;
929}
930
93bca243 931static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
080be03d 932{
af65c804 933 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
080be03d 934
080be03d
SP		 935 switch (mode) {
936 case DRM_MODE_DPMS_ON:
92dc7a04 937 fimd_poweron(crtc->ctx);
080be03d
SP		 938 break;
939 case DRM_MODE_DPMS_STANDBY:
940 case DRM_MODE_DPMS_SUSPEND:
941 case DRM_MODE_DPMS_OFF:
92dc7a04 942 fimd_poweroff(crtc->ctx);
080be03d
SP		 943 break;
944 default:
945 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
946 break;
947 }
080be03d
SP		 948}
949
3854fab2
YC		 950static void fimd_trigger(struct device *dev)
951{
e152dbd7 952 struct fimd_context *ctx = dev_get_drvdata(dev);
3854fab2
YC		 953 struct fimd_driver_data *driver_data = ctx->driver_data;
954 void *timing_base = ctx->regs + driver_data->timing_base;
955 u32 reg;
956
9b67eb73 957 /*
1c905d95
YC		 958 * Skips triggering if in triggering state, because multiple triggering
959 * requests can cause panel reset.
960 */
9b67eb73
JS		 961 if (atomic_read(&ctx->triggering))
962 return;
963
1c905d95 964 /* Enters triggering mode */
3854fab2
YC		 965 atomic_set(&ctx->triggering, 1);
966
3854fab2
YC		 967 reg = readl(timing_base + TRIGCON);
968 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
969 writel(reg, timing_base + TRIGCON);
87ab85b3
YC		 970
971 /*
972 * Exits triggering mode if vblank is not enabled yet, because when the
973 * VIDINTCON0 register is not set, it can not exit from triggering mode.
974 */
975 if (!test_bit(0, &ctx->irq_flags))
976 atomic_set(&ctx->triggering, 0);
3854fab2
YC		 977}
978
93bca243 979static void fimd_te_handler(struct exynos_drm_crtc *crtc)
3854fab2 980{
93bca243 981 struct fimd_context *ctx = crtc->ctx;
3854fab2
YC		 982
983 /* Checks the crtc is detached already from encoder */
984 if (ctx->pipe < 0 || !ctx->drm_dev)
985 return;
986
3854fab2
YC		 987 /*
988 * If there is a page flip request, triggers and handles the page flip
989 * event so that current fb can be updated into panel GRAM.
990 */
991 if (atomic_add_unless(&ctx->win_updated, -1, 0))
992 fimd_trigger(ctx->dev);
993
994 /* Wakes up vsync event queue */
995 if (atomic_read(&ctx->wait_vsync_event)) {
996 atomic_set(&ctx->wait_vsync_event, 0);
997 wake_up(&ctx->wait_vsync_queue);
3854fab2 998 }
b301ae24 999
adf67abf 1000 if (test_bit(0, &ctx->irq_flags))
b301ae24 1001 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
3854fab2
YC		 1002}
1003
93bca243 1004static struct exynos_drm_crtc_ops fimd_crtc_ops = {
1c6244c3 1005 .dpms = fimd_dpms,
a968e727 1006 .mode_fixup = fimd_mode_fixup,
1c6244c3
SP		 1007 .commit = fimd_commit,
1008 .enable_vblank = fimd_enable_vblank,
1009 .disable_vblank = fimd_disable_vblank,
1010 .wait_for_vblank = fimd_wait_for_vblank,
1011 .win_mode_set = fimd_win_mode_set,
1012 .win_commit = fimd_win_commit,
1013 .win_disable = fimd_win_disable,
3854fab2 1014 .te_handler = fimd_te_handler,
1c248b7d
ID		 1015};
1016
1c248b7d
ID		 1017static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1018{
1019 struct fimd_context *ctx = (struct fimd_context *)dev_id;
3854fab2 1020 u32 val, clear_bit;
1c248b7d
ID		 1021
1022 val = readl(ctx->regs + VIDINTCON1);
1023
3854fab2
YC		 1024 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1025 if (val & clear_bit)
1026 writel(clear_bit, ctx->regs + VIDINTCON1);
1c248b7d 1027
ec05da95 1028 /* check the crtc is detached already from encoder */
080be03d 1029 if (ctx->pipe < 0 || !ctx->drm_dev)
ec05da95 1030 goto out;
483b88f8 1031
1c905d95 1032 if (ctx->i80_if) {
adf67abf
JS		 1033 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1034
1c905d95 1035 /* Exits triggering mode */
3854fab2 1036 atomic_set(&ctx->triggering, 0);
3854fab2 1037 } else {
adf67abf
JS		 1038 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1039 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1040
3854fab2
YC		 1041 /* set wait vsync event to zero and wake up queue. */
1042 if (atomic_read(&ctx->wait_vsync_event)) {
1043 atomic_set(&ctx->wait_vsync_event, 0);
1044 wake_up(&ctx->wait_vsync_queue);
1045 }
01ce113c 1046 }
3854fab2 1047
ec05da95 1048out:
1c248b7d
ID		 1049 return IRQ_HANDLED;
1050}
1051
f37cd5e8 1052static int fimd_bind(struct device *dev, struct device *master, void *data)
562ad9f4 1053{
e152dbd7 1054 struct fimd_context *ctx = dev_get_drvdata(dev);
f37cd5e8 1055 struct drm_device *drm_dev = data;
cdbfca89 1056 struct exynos_drm_private *priv = drm_dev->dev_private;
efa75bcd 1057 int ret;
000cc920 1058
cdbfca89
HH		 1059 ctx->drm_dev = drm_dev;
1060 ctx->pipe = priv->pipe++;
efa75bcd 1061
0f04cf8d
JS		 1062 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1063 EXYNOS_DISPLAY_TYPE_LCD,
1064 &fimd_crtc_ops, ctx);
93bca243 1065
000cc920
AH		 1066 if (ctx->display)
1067 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1068
cdbfca89
HH		 1069 ret = fimd_iommu_attach_devices(ctx, drm_dev);
1070 if (ret)
1071 return ret;
1072
000cc920
AH		 1073 return 0;
1074
1075}
1076
1077static void fimd_unbind(struct device *dev, struct device *master,
1078 void *data)
1079{
e152dbd7 1080 struct fimd_context *ctx = dev_get_drvdata(dev);
000cc920 1081
93bca243 1082 fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
000cc920 1083
cdbfca89
HH		 1084 fimd_iommu_detach_devices(ctx);
1085
000cc920 1086 if (ctx->display)
4cfde1f2 1087 exynos_dpi_remove(ctx->display);
000cc920
AH		 1088}
1089
1090static const struct component_ops fimd_component_ops = {
1091 .bind = fimd_bind,
1092 .unbind = fimd_unbind,
1093};
1094
1095static int fimd_probe(struct platform_device *pdev)
1096{
1097 struct device *dev = &pdev->dev;
562ad9f4 1098 struct fimd_context *ctx;
3854fab2 1099 struct device_node *i80_if_timings;
562ad9f4 1100 struct resource *res;
fe42cfb4 1101 int ret;
1c248b7d 1102
e152dbd7
AH		 1103 if (!dev->of_node)
1104 return -ENODEV;
2d3f173c 1105
d873ab99 1106 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
e152dbd7
AH		 1107 if (!ctx)
1108 return -ENOMEM;
1109
e152dbd7 1110 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
5d1741ad 1111 EXYNOS_DISPLAY_TYPE_LCD);
e152dbd7
AH		 1112 if (ret)
1113 return ret;
1c248b7d 1114
bb7704d6 1115 ctx->dev = dev;
a43b933b 1116 ctx->suspended = true;
3854fab2 1117 ctx->driver_data = drm_fimd_get_driver_data(pdev);
bb7704d6 1118
1417f109
SP		 1119 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1120 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1121 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1122 ctx->vidcon1 |= VIDCON1_INV_VCLK;
562ad9f4 1123
3854fab2
YC		 1124 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1125 if (i80_if_timings) {
1126 u32 val;
1127
1128 ctx->i80_if = true;
1129
1130 if (ctx->driver_data->has_vidoutcon)
1131 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1132 else
1133 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1134 /*
1135 * The user manual describes that this "DSI_EN" bit is required
1136 * to enable I80 24-bit data interface.
1137 */
1138 ctx->vidcon0 |= VIDCON0_DSI_EN;
1139
1140 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1141 val = 0;
1142 ctx->i80ifcon = LCD_CS_SETUP(val);
1143 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1144 val = 0;
1145 ctx->i80ifcon |= LCD_WR_SETUP(val);
1146 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1147 val = 1;
1148 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1149 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1150 val = 0;
1151 ctx->i80ifcon |= LCD_WR_HOLD(val);
1152 }
1153 of_node_put(i80_if_timings);
1154
1155 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1156 "samsung,sysreg");
1157 if (IS_ERR(ctx->sysreg)) {
1158 dev_warn(dev, "failed to get system register.\n");
1159 ctx->sysreg = NULL;
1160 }
1161
a968e727
SP		 1162 ctx->bus_clk = devm_clk_get(dev, "fimd");
1163 if (IS_ERR(ctx->bus_clk)) {
1164 dev_err(dev, "failed to get bus clock\n");
df5225bc
ID		 1165 ret = PTR_ERR(ctx->bus_clk);
1166 goto err_del_component;
a968e727
SP		 1167 }
1168
1169 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1170 if (IS_ERR(ctx->lcd_clk)) {
1171 dev_err(dev, "failed to get lcd clock\n");
df5225bc
ID		 1172 ret = PTR_ERR(ctx->lcd_clk);
1173 goto err_del_component;
a968e727 1174 }
1c248b7d 1175
1c248b7d 1176 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1c248b7d 1177
d873ab99 1178 ctx->regs = devm_ioremap_resource(dev, res);
df5225bc
ID		 1179 if (IS_ERR(ctx->regs)) {
1180 ret = PTR_ERR(ctx->regs);
1181 goto err_del_component;
1182 }
1c248b7d 1183
3854fab2
YC		 1184 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1185 ctx->i80_if ? "lcd_sys" : "vsync");
1c248b7d
ID		 1186 if (!res) {
1187 dev_err(dev, "irq request failed.\n");
df5225bc
ID		 1188 ret = -ENXIO;
1189 goto err_del_component;
1c248b7d
ID		 1190 }
1191
055e0c06 1192 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
edc57266
SK		 1193 0, "drm_fimd", ctx);
1194 if (ret) {
1c248b7d 1195 dev_err(dev, "irq request failed.\n");
df5225bc 1196 goto err_del_component;
1c248b7d
ID		 1197 }
1198
57ed0f7b 1199 init_waitqueue_head(&ctx->wait_vsync_queue);
01ce113c 1200 atomic_set(&ctx->wait_vsync_event, 0);
1c248b7d 1201
e152dbd7 1202 platform_set_drvdata(pdev, ctx);
14b6873a 1203
000cc920 1204 ctx->display = exynos_dpi_probe(dev);
5baf5d44
GP		 1205 if (IS_ERR(ctx->display)) {
1206 ret = PTR_ERR(ctx->display);
1207 goto err_del_component;
1208 }
f37cd5e8 1209
e152dbd7 1210 pm_runtime_enable(dev);
f37cd5e8 1211
e152dbd7 1212 ret = component_add(dev, &fimd_component_ops);
df5225bc
ID		 1213 if (ret)
1214 goto err_disable_pm_runtime;
1215
1216 return ret;
1217
1218err_disable_pm_runtime:
e152dbd7 1219 pm_runtime_disable(dev);
df5225bc
ID		 1220
1221err_del_component:
e152dbd7 1222 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
df5225bc 1223 return ret;
f37cd5e8 1224}
cb91f6a0 1225
f37cd5e8
ID		 1226static int fimd_remove(struct platform_device *pdev)
1227{
af65c804 1228 pm_runtime_disable(&pdev->dev);
5d55393a 1229
df5225bc
ID		 1230 component_del(&pdev->dev, &fimd_component_ops);
1231 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1232
5d55393a 1233 return 0;
e30d4bcf
ID		 1234}
1235
132a5b91 1236struct platform_driver fimd_driver = {
1c248b7d 1237 .probe = fimd_probe,
56550d94 1238 .remove = fimd_remove,
1c248b7d
ID		 1239 .driver = {
1240 .name = "exynos4-fb",
1241 .owner = THIS_MODULE,
2d3f173c 1242 .of_match_table = fimd_driver_dt_match,
1c248b7d
ID		 1243 },
1244};
Linux kernel - Deliverables
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