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drm/exynos: fimd: support LCD I80 interface
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
CommitLineData
1c248b7d
ID		 1/* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
760285e7 14#include <drm/drmP.h>
1c248b7d
ID		 15
16#include <linux/kernel.h>
1c248b7d
ID		 17#include <linux/platform_device.h>
18#include <linux/clk.h>
3f1c781d 19#include <linux/of.h>
d636ead8 20#include <linux/of_device.h>
cb91f6a0 21#include <linux/pm_runtime.h>
f37cd5e8 22#include <linux/component.h>
3854fab2
YC		 23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
1c248b7d 25
7f4596f4 26#include <video/of_display_timing.h>
111e6055 27#include <video/of_videomode.h>
5a213a55 28#include <video/samsung_fimd.h>
1c248b7d 29#include <drm/exynos_drm.h>
1c248b7d
ID		 30
31#include "exynos_drm_drv.h"
32#include "exynos_drm_fbdev.h"
33#include "exynos_drm_crtc.h"
bcc5cd1c 34#include "exynos_drm_iommu.h"
1c248b7d
ID		 35
36/*
b8654b37 37 * FIMD stands for Fully Interactive Mobile Display and
1c248b7d
ID		 38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
40 * CPU Interface.
41 */
42
111e6055 43#define FIMD_DEFAULT_FRAMERATE 60
66367461 44#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
111e6055 45
1c248b7d
ID		 46/* position control register for hardware window 0, 2 ~ 4.*/
47#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
0f10cf14
LKA		 49/*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54/* size control register for hardware windows 1 ~ 2. */
1c248b7d
ID		 55#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
60
61/* color key control register for hardware window 1 ~ 4. */
0f10cf14 62#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
1c248b7d 63/* color key value register for hardware window 1 ~ 4. */
0f10cf14 64#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
1c248b7d 65
3854fab2
YC		 66/* I80 / RGB trigger control register */
67#define TRIGCON 0x1A4
68#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69#define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
70
71/* display mode change control register except exynos4 */
72#define VIDOUT_CON 0x000
73#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
74
75/* I80 interface control for main LDI register */
76#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78#define LCD_CS_SETUP(x) ((x) << 16)
79#define LCD_WR_SETUP(x) ((x) << 12)
80#define LCD_WR_ACTIVE(x) ((x) << 8)
81#define LCD_WR_HOLD(x) ((x) << 4)
82#define I80IFEN_ENABLE (1 << 0)
83
1c248b7d
ID		 84/* FIMD has totally five hardware windows. */
85#define WINDOWS_NR 5
86
bb7704d6 87#define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
1c248b7d 88
e2e13389
LKA		 89struct fimd_driver_data {
90 unsigned int timing_base;
3854fab2
YC		 91 unsigned int lcdblk_offset;
92 unsigned int lcdblk_vt_shift;
93 unsigned int lcdblk_bypass_shift;
de7af100
TF		 94
95 unsigned int has_shadowcon:1;
411d9ed4 96 unsigned int has_clksel:1;
5cc4621a 97 unsigned int has_limited_fmt:1;
3854fab2 98 unsigned int has_vidoutcon:1;
e2e13389
LKA		 99};
100
725ddead
TF		 101static struct fimd_driver_data s3c64xx_fimd_driver_data = {
102 .timing_base = 0x0,
103 .has_clksel = 1,
5cc4621a 104 .has_limited_fmt = 1,
725ddead
TF		 105};
106
6ecf18f9 107static struct fimd_driver_data exynos4_fimd_driver_data = {
e2e13389 108 .timing_base = 0x0,
3854fab2
YC		 109 .lcdblk_offset = 0x210,
110 .lcdblk_vt_shift = 10,
111 .lcdblk_bypass_shift = 1,
de7af100 112 .has_shadowcon = 1,
e2e13389
LKA		 113};
114
6ecf18f9 115static struct fimd_driver_data exynos5_fimd_driver_data = {
e2e13389 116 .timing_base = 0x20000,
3854fab2
YC		 117 .lcdblk_offset = 0x214,
118 .lcdblk_vt_shift = 24,
119 .lcdblk_bypass_shift = 15,
de7af100 120 .has_shadowcon = 1,
3854fab2 121 .has_vidoutcon = 1,
e2e13389
LKA		 122};
123
1c248b7d
ID		 124struct fimd_win_data {
125 unsigned int offset_x;
126 unsigned int offset_y;
19c8b834
ID		 127 unsigned int ovl_width;
128 unsigned int ovl_height;
129 unsigned int fb_width;
130 unsigned int fb_height;
1c248b7d 131 unsigned int bpp;
a4f38a80 132 unsigned int pixel_format;
2c871127 133 dma_addr_t dma_addr;
1c248b7d
ID		 134 unsigned int buf_offsize;
135 unsigned int line_size; /* bytes */
ec05da95 136 bool enabled;
db7e55ae 137 bool resume;
1c248b7d
ID		 138};
139
140struct fimd_context {
bb7704d6 141 struct device *dev;
40c8ab4b 142 struct drm_device *drm_dev;
1c248b7d
ID		 143 struct clk *bus_clk;
144 struct clk *lcd_clk;
1c248b7d 145 void __iomem *regs;
3854fab2 146 struct regmap *sysreg;
a968e727 147 struct drm_display_mode mode;
1c248b7d 148 struct fimd_win_data win_data[WINDOWS_NR];
1c248b7d
ID		 149 unsigned int default_win;
150 unsigned long irq_flags;
3854fab2 151 u32 vidcon0;
1c248b7d 152 u32 vidcon1;
3854fab2
YC		 153 u32 vidout_con;
154 u32 i80ifcon;
155 bool i80_if;
cb91f6a0 156 bool suspended;
080be03d 157 int pipe;
01ce113c
P		 158 wait_queue_head_t wait_vsync_queue;
159 atomic_t wait_vsync_event;
3854fab2
YC		 160 atomic_t win_updated;
161 atomic_t triggering;
1c248b7d 162
562ad9f4 163 struct exynos_drm_panel_info panel;
18873465 164 struct fimd_driver_data *driver_data;
000cc920 165 struct exynos_drm_display *display;
1c248b7d
ID		 166};
167
d636ead8 168static const struct of_device_id fimd_driver_dt_match[] = {
725ddead
TF		 169 { .compatible = "samsung,s3c6400-fimd",
170 .data = &s3c64xx_fimd_driver_data },
5830daf8 171 { .compatible = "samsung,exynos4210-fimd",
d636ead8 172 .data = &exynos4_fimd_driver_data },
5830daf8 173 { .compatible = "samsung,exynos5250-fimd",
d636ead8
JS		 174 .data = &exynos5_fimd_driver_data },
175 {},
176};
d636ead8 177
e2e13389
LKA		 178static inline struct fimd_driver_data *drm_fimd_get_driver_data(
179 struct platform_device *pdev)
180{
d636ead8
JS		 181 const struct of_device_id *of_id =
182 of_match_device(fimd_driver_dt_match, &pdev->dev);
183
2d3f173c 184 return (struct fimd_driver_data *)of_id->data;
e2e13389
LKA		 185}
186
f13bdbd1
AA		 187static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
188{
189 struct fimd_context *ctx = mgr->ctx;
190
191 if (ctx->suspended)
192 return;
193
194 atomic_set(&ctx->wait_vsync_event, 1);
195
196 /*
197 * wait for FIMD to signal VSYNC interrupt or return after
198 * timeout which is set to 50ms (refresh rate of 20).
199 */
200 if (!wait_event_timeout(ctx->wait_vsync_queue,
201 !atomic_read(&ctx->wait_vsync_event),
202 HZ/20))
203 DRM_DEBUG_KMS("vblank wait timed out.\n");
204}
205
206
207static void fimd_clear_channel(struct exynos_drm_manager *mgr)
208{
209 struct fimd_context *ctx = mgr->ctx;
210 int win, ch_enabled = 0;
211
212 DRM_DEBUG_KMS("%s\n", __FILE__);
213
214 /* Check if any channel is enabled. */
215 for (win = 0; win < WINDOWS_NR; win++) {
216 u32 val = readl(ctx->regs + SHADOWCON);
217 if (val & SHADOWCON_CHx_ENABLE(win)) {
218 val &= ~SHADOWCON_CHx_ENABLE(win);
219 writel(val, ctx->regs + SHADOWCON);
220 ch_enabled = 1;
221 }
222 }
223
224 /* Wait for vsync, as disable channel takes effect at next vsync */
225 if (ch_enabled)
226 fimd_wait_for_vblank(mgr);
227}
228
bb7704d6 229static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
f37cd5e8 230 struct drm_device *drm_dev)
40c8ab4b 231{
bb7704d6 232 struct fimd_context *ctx = mgr->ctx;
f37cd5e8
ID		 233 struct exynos_drm_private *priv;
234 priv = drm_dev->dev_private;
40c8ab4b 235
f37cd5e8
ID		 236 mgr->drm_dev = ctx->drm_dev = drm_dev;
237 mgr->pipe = ctx->pipe = priv->pipe++;
40c8ab4b 238
080be03d
SP		 239 /*
240 * enable drm irq mode.
241 * - with irq_enabled = true, we can use the vblank feature.
242 *
243 * P.S. note that we wouldn't use drm irq handler but
244 * just specific driver own one instead because
245 * drm framework supports only one irq handler.
246 */
247 drm_dev->irq_enabled = true;
ec05da95 248
080be03d
SP		 249 /*
250 * with vblank_disable_allowed = true, vblank interrupt will be disabled
251 * by drm timer once a current process gives up ownership of
252 * vblank event.(after drm_vblank_put function is called)
253 */
254 drm_dev->vblank_disable_allowed = true;
c32b06ef 255
080be03d 256 /* attach this sub driver to iommu mapping if supported. */
f13bdbd1
AA		 257 if (is_drm_iommu_supported(ctx->drm_dev)) {
258 /*
259 * If any channel is already active, iommu will throw
260 * a PAGE FAULT when enabled. So clear any channel if enabled.
261 */
262 fimd_clear_channel(mgr);
080be03d 263 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
f13bdbd1 264 }
c32b06ef 265
080be03d 266 return 0;
ec05da95
ID		 267}
268
080be03d 269static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
ec05da95 270{
bb7704d6 271 struct fimd_context *ctx = mgr->ctx;
ec05da95 272
080be03d
SP		 273 /* detach this sub driver from iommu mapping if supported. */
274 if (is_drm_iommu_supported(ctx->drm_dev))
275 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
ec05da95
ID		 276}
277
a968e727
SP		 278static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
279 const struct drm_display_mode *mode)
280{
281 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
282 u32 clkdiv;
283
3854fab2
YC		 284 if (ctx->i80_if) {
285 /*
286 * The frame done interrupt should be occurred prior to the
287 * next TE signal.
288 */
289 ideal_clk *= 2;
290 }
291
a968e727
SP		 292 /* Find the clock divider value that gets us closest to ideal_clk */
293 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
294
295 return (clkdiv < 0x100) ? clkdiv : 0xff;
296}
297
298static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
299 const struct drm_display_mode *mode,
300 struct drm_display_mode *adjusted_mode)
301{
302 if (adjusted_mode->vrefresh == 0)
303 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
304
305 return true;
306}
307
308static void fimd_mode_set(struct exynos_drm_manager *mgr,
309 const struct drm_display_mode *in_mode)
310{
311 struct fimd_context *ctx = mgr->ctx;
312
313 drm_mode_copy(&ctx->mode, in_mode);
314}
315
bb7704d6 316static void fimd_commit(struct exynos_drm_manager *mgr)
1c248b7d 317{
bb7704d6 318 struct fimd_context *ctx = mgr->ctx;
a968e727 319 struct drm_display_mode *mode = &ctx->mode;
3854fab2
YC		 320 struct fimd_driver_data *driver_data = ctx->driver_data;
321 void *timing_base = ctx->regs + driver_data->timing_base;
322 u32 val, clkdiv;
1c248b7d 323
e30d4bcf
ID		 324 if (ctx->suspended)
325 return;
326
a968e727
SP		 327 /* nothing to do if we haven't set the mode yet */
328 if (mode->htotal == 0 || mode->vtotal == 0)
329 return;
330
3854fab2
YC		 331 if (ctx->i80_if) {
332 val = ctx->i80ifcon | I80IFEN_ENABLE;
333 writel(val, timing_base + I80IFCONFAx(0));
334
335 /* disable auto frame rate */
336 writel(0, timing_base + I80IFCONFBx(0));
337
338 /* set video type selection to I80 interface */
339 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
340 driver_data->lcdblk_offset,
341 0x3 << driver_data->lcdblk_vt_shift,
342 0x1 << driver_data->lcdblk_vt_shift)) {
343 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
344 return;
345 }
346 } else {
347 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
348 u32 vidcon1;
349
350 /* setup polarity values */
351 vidcon1 = ctx->vidcon1;
352 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
353 vidcon1 |= VIDCON1_INV_VSYNC;
354 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
355 vidcon1 |= VIDCON1_INV_HSYNC;
356 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
357
358 /* setup vertical timing values. */
359 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
360 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
361 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
362
363 val = VIDTCON0_VBPD(vbpd - 1) |
364 VIDTCON0_VFPD(vfpd - 1) |
365 VIDTCON0_VSPW(vsync_len - 1);
366 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
367
368 /* setup horizontal timing values. */
369 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
370 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
371 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
372
373 val = VIDTCON1_HBPD(hbpd - 1) |
374 VIDTCON1_HFPD(hfpd - 1) |
375 VIDTCON1_HSPW(hsync_len - 1);
376 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
377 }
378
379 if (driver_data->has_vidoutcon)
380 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
381
382 /* set bypass selection */
383 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
384 driver_data->lcdblk_offset,
385 0x1 << driver_data->lcdblk_bypass_shift,
386 0x1 << driver_data->lcdblk_bypass_shift)) {
387 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
388 return;
389 }
1c248b7d
ID		 390
391 /* setup horizontal and vertical display size. */
a968e727
SP		 392 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
393 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
394 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
395 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
e2e13389 396 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
1c248b7d 397
1d531062
AH		 398 /*
399 * fields of register with prefix '_F' would be updated
400 * at vsync(same as dma start)
401 */
3854fab2
YC		 402 val = ctx->vidcon0;
403 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
1c248b7d 404
1d531062 405 if (ctx->driver_data->has_clksel)
411d9ed4 406 val |= VIDCON0_CLKSEL_LCD;
411d9ed4 407
a968e727
SP		 408 clkdiv = fimd_calc_clkdiv(ctx, mode);
409 if (clkdiv > 1)
410 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
1c248b7d 411
1c248b7d
ID		 412 writel(val, ctx->regs + VIDCON0);
413}
414
bb7704d6 415static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
1c248b7d 416{
bb7704d6 417 struct fimd_context *ctx = mgr->ctx;
1c248b7d
ID		 418 u32 val;
419
cb91f6a0
JS		 420 if (ctx->suspended)
421 return -EPERM;
422
1c248b7d
ID		 423 if (!test_and_set_bit(0, &ctx->irq_flags)) {
424 val = readl(ctx->regs + VIDINTCON0);
425
426 val |= VIDINTCON0_INT_ENABLE;
427 val |= VIDINTCON0_INT_FRAME;
428
429 val &= ~VIDINTCON0_FRAMESEL0_MASK;
430 val |= VIDINTCON0_FRAMESEL0_VSYNC;
431 val &= ~VIDINTCON0_FRAMESEL1_MASK;
432 val |= VIDINTCON0_FRAMESEL1_NONE;
433
434 writel(val, ctx->regs + VIDINTCON0);
435 }
436
437 return 0;
438}
439
bb7704d6 440static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
1c248b7d 441{
bb7704d6 442 struct fimd_context *ctx = mgr->ctx;
1c248b7d
ID		 443 u32 val;
444
cb91f6a0
JS		 445 if (ctx->suspended)
446 return;
447
1c248b7d
ID		 448 if (test_and_clear_bit(0, &ctx->irq_flags)) {
449 val = readl(ctx->regs + VIDINTCON0);
450
451 val &= ~VIDINTCON0_INT_FRAME;
452 val &= ~VIDINTCON0_INT_ENABLE;
453
454 writel(val, ctx->regs + VIDINTCON0);
455 }
456}
457
bb7704d6
SP		 458static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
459 struct exynos_drm_overlay *overlay)
1c248b7d 460{
bb7704d6 461 struct fimd_context *ctx = mgr->ctx;
1c248b7d 462 struct fimd_win_data *win_data;
864ee9e6 463 int win;
19c8b834 464 unsigned long offset;
1c248b7d 465
1c248b7d 466 if (!overlay) {
bb7704d6 467 DRM_ERROR("overlay is NULL\n");
1c248b7d
ID		 468 return;
469 }
470
864ee9e6
JS		 471 win = overlay->zpos;
472 if (win == DEFAULT_ZPOS)
473 win = ctx->default_win;
474
37b006e8 475 if (win < 0 || win >= WINDOWS_NR)
864ee9e6
JS		 476 return;
477
19c8b834
ID		 478 offset = overlay->fb_x * (overlay->bpp >> 3);
479 offset += overlay->fb_y * overlay->pitch;
480
481 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
482
864ee9e6 483 win_data = &ctx->win_data[win];
1c248b7d 484
19c8b834
ID		 485 win_data->offset_x = overlay->crtc_x;
486 win_data->offset_y = overlay->crtc_y;
487 win_data->ovl_width = overlay->crtc_width;
488 win_data->ovl_height = overlay->crtc_height;
489 win_data->fb_width = overlay->fb_width;
490 win_data->fb_height = overlay->fb_height;
229d3534 491 win_data->dma_addr = overlay->dma_addr[0] + offset;
1c248b7d 492 win_data->bpp = overlay->bpp;
a4f38a80 493 win_data->pixel_format = overlay->pixel_format;
19c8b834
ID		 494 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
495 (overlay->bpp >> 3);
496 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
497
498 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
499 win_data->offset_x, win_data->offset_y);
500 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
501 win_data->ovl_width, win_data->ovl_height);
ddd8e959 502 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
19c8b834
ID		 503 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
504 overlay->fb_width, overlay->crtc_width);
1c248b7d
ID		 505}
506
bb7704d6 507static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
1c248b7d 508{
1c248b7d
ID		 509 struct fimd_win_data *win_data = &ctx->win_data[win];
510 unsigned long val;
511
1c248b7d
ID		 512 val = WINCONx_ENWIN;
513
5cc4621a
ID		 514 /*
515 * In case of s3c64xx, window 0 doesn't support alpha channel.
516 * So the request format is ARGB8888 then change it to XRGB8888.
517 */
518 if (ctx->driver_data->has_limited_fmt && !win) {
519 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
520 win_data->pixel_format = DRM_FORMAT_XRGB8888;
521 }
522
a4f38a80
ID		 523 switch (win_data->pixel_format) {
524 case DRM_FORMAT_C8:
1c248b7d
ID		 525 val |= WINCON0_BPPMODE_8BPP_PALETTE;
526 val |= WINCONx_BURSTLEN_8WORD;
527 val |= WINCONx_BYTSWP;
528 break;
a4f38a80
ID		 529 case DRM_FORMAT_XRGB1555:
530 val |= WINCON0_BPPMODE_16BPP_1555;
531 val |= WINCONx_HAWSWP;
532 val |= WINCONx_BURSTLEN_16WORD;
533 break;
534 case DRM_FORMAT_RGB565:
1c248b7d
ID		 535 val |= WINCON0_BPPMODE_16BPP_565;
536 val |= WINCONx_HAWSWP;
537 val |= WINCONx_BURSTLEN_16WORD;
538 break;
a4f38a80 539 case DRM_FORMAT_XRGB8888:
1c248b7d
ID		 540 val |= WINCON0_BPPMODE_24BPP_888;
541 val |= WINCONx_WSWP;
542 val |= WINCONx_BURSTLEN_16WORD;
543 break;
a4f38a80
ID		 544 case DRM_FORMAT_ARGB8888:
545 val |= WINCON1_BPPMODE_25BPP_A1888
1c248b7d
ID		 546 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
547 val |= WINCONx_WSWP;
548 val |= WINCONx_BURSTLEN_16WORD;
549 break;
550 default:
551 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
552
553 val |= WINCON0_BPPMODE_24BPP_888;
554 val |= WINCONx_WSWP;
555 val |= WINCONx_BURSTLEN_16WORD;
556 break;
557 }
558
559 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
560
66367461
RS		 561 /*
562 * In case of exynos, setting dma-burst to 16Word causes permanent
563 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
564 * switching which is based on overlay size is not recommended as
565 * overlay size varies alot towards the end of the screen and rapid
566 * movement causes unstable DMA which results into iommu crash/tear.
567 */
568
569 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
570 val &= ~WINCONx_BURSTLEN_MASK;
571 val |= WINCONx_BURSTLEN_4WORD;
572 }
573
1c248b7d
ID		 574 writel(val, ctx->regs + WINCON(win));
575}
576
bb7704d6 577static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
1c248b7d 578{
1c248b7d
ID		 579 unsigned int keycon0 = 0, keycon1 = 0;
580
1c248b7d
ID		 581 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
582 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
583
584 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
585
586 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
587 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
588}
589
de7af100
TF		 590/**
591 * shadow_protect_win() - disable updating values from shadow registers at vsync
592 *
593 * @win: window to protect registers for
594 * @protect: 1 to protect (disable updates)
595 */
596static void fimd_shadow_protect_win(struct fimd_context *ctx,
597 int win, bool protect)
598{
599 u32 reg, bits, val;
600
601 if (ctx->driver_data->has_shadowcon) {
602 reg = SHADOWCON;
603 bits = SHADOWCON_WINx_PROTECT(win);
604 } else {
605 reg = PRTCON;
606 bits = PRTCON_PROTECT;
607 }
608
609 val = readl(ctx->regs + reg);
610 if (protect)
611 val |= bits;
612 else
613 val &= ~bits;
614 writel(val, ctx->regs + reg);
615}
616
bb7704d6 617static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
1c248b7d 618{
bb7704d6 619 struct fimd_context *ctx = mgr->ctx;
1c248b7d 620 struct fimd_win_data *win_data;
864ee9e6 621 int win = zpos;
1c248b7d 622 unsigned long val, alpha, size;
f56aad3a
JS		 623 unsigned int last_x;
624 unsigned int last_y;
1c248b7d 625
e30d4bcf
ID		 626 if (ctx->suspended)
627 return;
628
864ee9e6
JS		 629 if (win == DEFAULT_ZPOS)
630 win = ctx->default_win;
631
37b006e8 632 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 633 return;
634
635 win_data = &ctx->win_data[win];
636
a43b933b
SP		 637 /* If suspended, enable this on resume */
638 if (ctx->suspended) {
639 win_data->resume = true;
640 return;
641 }
642
1c248b7d 643 /*
de7af100 644 * SHADOWCON/PRTCON register is used for enabling timing.
1c248b7d
ID		 645 *
646 * for example, once only width value of a register is set,
647 * if the dma is started then fimd hardware could malfunction so
648 * with protect window setting, the register fields with prefix '_F'
649 * wouldn't be updated at vsync also but updated once unprotect window
650 * is set.
651 */
652
653 /* protect windows */
de7af100 654 fimd_shadow_protect_win(ctx, win, true);
1c248b7d
ID		 655
656 /* buffer start address */
2c871127 657 val = (unsigned long)win_data->dma_addr;
1c248b7d
ID		 658 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
659
660 /* buffer end address */
19c8b834 661 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
2c871127 662 val = (unsigned long)(win_data->dma_addr + size);
1c248b7d
ID		 663 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
664
665 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
2c871127 666 (unsigned long)win_data->dma_addr, val, size);
19c8b834
ID		 667 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
668 win_data->ovl_width, win_data->ovl_height);
1c248b7d
ID		 669
670 /* buffer size */
671 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
ca555e5a
JS		 672 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
673 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
674 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
1c248b7d
ID		 675 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
676
677 /* OSD position */
678 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
ca555e5a
JS		 679 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
680 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
681 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
1c248b7d
ID		 682 writel(val, ctx->regs + VIDOSD_A(win));
683
f56aad3a
JS		 684 last_x = win_data->offset_x + win_data->ovl_width;
685 if (last_x)
686 last_x--;
687 last_y = win_data->offset_y + win_data->ovl_height;
688 if (last_y)
689 last_y--;
690
ca555e5a
JS		 691 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
692 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
693
1c248b7d
ID		 694 writel(val, ctx->regs + VIDOSD_B(win));
695
19c8b834 696 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
f56aad3a 697 win_data->offset_x, win_data->offset_y, last_x, last_y);
1c248b7d
ID		 698
699 /* hardware window 0 doesn't support alpha channel. */
700 if (win != 0) {
701 /* OSD alpha */
702 alpha = VIDISD14C_ALPHA1_R(0xf) |
703 VIDISD14C_ALPHA1_G(0xf) |
704 VIDISD14C_ALPHA1_B(0xf);
705
706 writel(alpha, ctx->regs + VIDOSD_C(win));
707 }
708
709 /* OSD size */
710 if (win != 3 && win != 4) {
711 u32 offset = VIDOSD_D(win);
712 if (win == 0)
0f10cf14 713 offset = VIDOSD_C(win);
19c8b834 714 val = win_data->ovl_width * win_data->ovl_height;
1c248b7d
ID		 715 writel(val, ctx->regs + offset);
716
717 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
718 }
719
bb7704d6 720 fimd_win_set_pixfmt(ctx, win);
1c248b7d
ID		 721
722 /* hardware window 0 doesn't support color key. */
723 if (win != 0)
bb7704d6 724 fimd_win_set_colkey(ctx, win);
1c248b7d 725
ec05da95
ID		 726 /* wincon */
727 val = readl(ctx->regs + WINCON(win));
728 val |= WINCONx_ENWIN;
729 writel(val, ctx->regs + WINCON(win));
730
1c248b7d 731 /* Enable DMA channel and unprotect windows */
de7af100
TF		 732 fimd_shadow_protect_win(ctx, win, false);
733
734 if (ctx->driver_data->has_shadowcon) {
735 val = readl(ctx->regs + SHADOWCON);
736 val |= SHADOWCON_CHx_ENABLE(win);
737 writel(val, ctx->regs + SHADOWCON);
738 }
ec05da95
ID		 739
740 win_data->enabled = true;
3854fab2
YC		 741
742 if (ctx->i80_if)
743 atomic_set(&ctx->win_updated, 1);
1c248b7d
ID		 744}
745
bb7704d6 746static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
1c248b7d 747{
bb7704d6 748 struct fimd_context *ctx = mgr->ctx;
ec05da95 749 struct fimd_win_data *win_data;
864ee9e6 750 int win = zpos;
1c248b7d
ID		 751 u32 val;
752
864ee9e6
JS		 753 if (win == DEFAULT_ZPOS)
754 win = ctx->default_win;
755
37b006e8 756 if (win < 0 || win >= WINDOWS_NR)
1c248b7d
ID		 757 return;
758
ec05da95
ID		 759 win_data = &ctx->win_data[win];
760
db7e55ae
P		 761 if (ctx->suspended) {
762 /* do not resume this window*/
763 win_data->resume = false;
764 return;
765 }
766
1c248b7d 767 /* protect windows */
de7af100 768 fimd_shadow_protect_win(ctx, win, true);
1c248b7d
ID		 769
770 /* wincon */
771 val = readl(ctx->regs + WINCON(win));
772 val &= ~WINCONx_ENWIN;
773 writel(val, ctx->regs + WINCON(win));
774
775 /* unprotect windows */
de7af100
TF		 776 if (ctx->driver_data->has_shadowcon) {
777 val = readl(ctx->regs + SHADOWCON);
778 val &= ~SHADOWCON_CHx_ENABLE(win);
779 writel(val, ctx->regs + SHADOWCON);
780 }
781
782 fimd_shadow_protect_win(ctx, win, false);
ec05da95
ID		 783
784 win_data->enabled = false;
1c248b7d
ID		 785}
786
a43b933b
SP		 787static void fimd_window_suspend(struct exynos_drm_manager *mgr)
788{
789 struct fimd_context *ctx = mgr->ctx;
790 struct fimd_win_data *win_data;
791 int i;
792
793 for (i = 0; i < WINDOWS_NR; i++) {
794 win_data = &ctx->win_data[i];
795 win_data->resume = win_data->enabled;
796 if (win_data->enabled)
797 fimd_win_disable(mgr, i);
798 }
799 fimd_wait_for_vblank(mgr);
800}
801
802static void fimd_window_resume(struct exynos_drm_manager *mgr)
803{
804 struct fimd_context *ctx = mgr->ctx;
805 struct fimd_win_data *win_data;
806 int i;
807
808 for (i = 0; i < WINDOWS_NR; i++) {
809 win_data = &ctx->win_data[i];
810 win_data->enabled = win_data->resume;
811 win_data->resume = false;
812 }
813}
814
815static void fimd_apply(struct exynos_drm_manager *mgr)
816{
817 struct fimd_context *ctx = mgr->ctx;
818 struct fimd_win_data *win_data;
819 int i;
820
821 for (i = 0; i < WINDOWS_NR; i++) {
822 win_data = &ctx->win_data[i];
823 if (win_data->enabled)
824 fimd_win_commit(mgr, i);
d9b68d89
AH		 825 else
826 fimd_win_disable(mgr, i);
a43b933b
SP		 827 }
828
829 fimd_commit(mgr);
830}
831
832static int fimd_poweron(struct exynos_drm_manager *mgr)
833{
834 struct fimd_context *ctx = mgr->ctx;
835 int ret;
836
837 if (!ctx->suspended)
838 return 0;
839
840 ctx->suspended = false;
841
af65c804
SP		 842 pm_runtime_get_sync(ctx->dev);
843
a43b933b
SP		 844 ret = clk_prepare_enable(ctx->bus_clk);
845 if (ret < 0) {
846 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
847 goto bus_clk_err;
848 }
849
850 ret = clk_prepare_enable(ctx->lcd_clk);
851 if (ret < 0) {
852 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
853 goto lcd_clk_err;
854 }
855
856 /* if vblank was enabled status, enable it again. */
857 if (test_and_clear_bit(0, &ctx->irq_flags)) {
858 ret = fimd_enable_vblank(mgr);
859 if (ret) {
860 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
861 goto enable_vblank_err;
862 }
863 }
864
865 fimd_window_resume(mgr);
866
867 fimd_apply(mgr);
868
869 return 0;
870
871enable_vblank_err:
872 clk_disable_unprepare(ctx->lcd_clk);
873lcd_clk_err:
874 clk_disable_unprepare(ctx->bus_clk);
875bus_clk_err:
876 ctx->suspended = true;
877 return ret;
878}
879
880static int fimd_poweroff(struct exynos_drm_manager *mgr)
881{
882 struct fimd_context *ctx = mgr->ctx;
883
884 if (ctx->suspended)
885 return 0;
886
887 /*
888 * We need to make sure that all windows are disabled before we
889 * suspend that connector. Otherwise we might try to scan from
890 * a destroyed buffer later.
891 */
892 fimd_window_suspend(mgr);
893
894 clk_disable_unprepare(ctx->lcd_clk);
895 clk_disable_unprepare(ctx->bus_clk);
896
af65c804
SP		 897 pm_runtime_put_sync(ctx->dev);
898
a43b933b
SP		 899 ctx->suspended = true;
900 return 0;
901}
902
080be03d
SP		 903static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
904{
af65c804 905 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
080be03d 906
080be03d
SP		 907 switch (mode) {
908 case DRM_MODE_DPMS_ON:
af65c804 909 fimd_poweron(mgr);
080be03d
SP		 910 break;
911 case DRM_MODE_DPMS_STANDBY:
912 case DRM_MODE_DPMS_SUSPEND:
913 case DRM_MODE_DPMS_OFF:
af65c804 914 fimd_poweroff(mgr);
080be03d
SP		 915 break;
916 default:
917 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
918 break;
919 }
080be03d
SP		 920}
921
3854fab2
YC		 922static void fimd_trigger(struct device *dev)
923{
924 struct exynos_drm_manager *mgr = get_fimd_manager(dev);
925 struct fimd_context *ctx = mgr->ctx;
926 struct fimd_driver_data *driver_data = ctx->driver_data;
927 void *timing_base = ctx->regs + driver_data->timing_base;
928 u32 reg;
929
930 atomic_set(&ctx->triggering, 1);
931
932 reg = readl(ctx->regs + VIDINTCON0);
933 reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
934 VIDINTCON0_INT_SYSMAINCON);
935 writel(reg, ctx->regs + VIDINTCON0);
936
937 reg = readl(timing_base + TRIGCON);
938 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
939 writel(reg, timing_base + TRIGCON);
940}
941
942static void fimd_te_handler(struct exynos_drm_manager *mgr)
943{
944 struct fimd_context *ctx = mgr->ctx;
945
946 /* Checks the crtc is detached already from encoder */
947 if (ctx->pipe < 0 || !ctx->drm_dev)
948 return;
949
950 /*
951 * Skips to trigger if in triggering state, because multiple triggering
952 * requests can cause panel reset.
953 */
954 if (atomic_read(&ctx->triggering))
955 return;
956
957 /*
958 * If there is a page flip request, triggers and handles the page flip
959 * event so that current fb can be updated into panel GRAM.
960 */
961 if (atomic_add_unless(&ctx->win_updated, -1, 0))
962 fimd_trigger(ctx->dev);
963
964 /* Wakes up vsync event queue */
965 if (atomic_read(&ctx->wait_vsync_event)) {
966 atomic_set(&ctx->wait_vsync_event, 0);
967 wake_up(&ctx->wait_vsync_queue);
968
969 if (!atomic_read(&ctx->triggering))
970 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
971 }
972}
973
1c6244c3
SP		 974static struct exynos_drm_manager_ops fimd_manager_ops = {
975 .dpms = fimd_dpms,
a968e727
SP		 976 .mode_fixup = fimd_mode_fixup,
977 .mode_set = fimd_mode_set,
1c6244c3
SP		 978 .commit = fimd_commit,
979 .enable_vblank = fimd_enable_vblank,
980 .disable_vblank = fimd_disable_vblank,
981 .wait_for_vblank = fimd_wait_for_vblank,
982 .win_mode_set = fimd_win_mode_set,
983 .win_commit = fimd_win_commit,
984 .win_disable = fimd_win_disable,
3854fab2 985 .te_handler = fimd_te_handler,
1c248b7d
ID		 986};
987
677e84c1 988static struct exynos_drm_manager fimd_manager = {
080be03d
SP		 989 .type = EXYNOS_DISPLAY_TYPE_LCD,
990 .ops = &fimd_manager_ops,
677e84c1
JS		 991};
992
1c248b7d
ID		 993static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
994{
995 struct fimd_context *ctx = (struct fimd_context *)dev_id;
3854fab2 996 u32 val, clear_bit;
1c248b7d
ID		 997
998 val = readl(ctx->regs + VIDINTCON1);
999
3854fab2
YC		 1000 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1001 if (val & clear_bit)
1002 writel(clear_bit, ctx->regs + VIDINTCON1);
1c248b7d 1003
ec05da95 1004 /* check the crtc is detached already from encoder */
080be03d 1005 if (ctx->pipe < 0 || !ctx->drm_dev)
ec05da95 1006 goto out;
483b88f8 1007
3854fab2
YC		 1008 if (ctx->i80_if) {
1009 /* unset I80 frame done interrupt */
1010 val = readl(ctx->regs + VIDINTCON0);
1011 val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
1012 writel(val, ctx->regs + VIDINTCON0);
1c248b7d 1013
3854fab2
YC		 1014 /* exit triggering mode */
1015 atomic_set(&ctx->triggering, 0);
1016
1017 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1018 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1019 } else {
1020 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1021 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1022
1023 /* set wait vsync event to zero and wake up queue. */
1024 if (atomic_read(&ctx->wait_vsync_event)) {
1025 atomic_set(&ctx->wait_vsync_event, 0);
1026 wake_up(&ctx->wait_vsync_queue);
1027 }
01ce113c 1028 }
3854fab2 1029
ec05da95 1030out:
1c248b7d
ID		 1031 return IRQ_HANDLED;
1032}
1033
f37cd5e8 1034static int fimd_bind(struct device *dev, struct device *master, void *data)
562ad9f4 1035{
000cc920 1036 struct fimd_context *ctx = fimd_manager.ctx;
f37cd5e8 1037 struct drm_device *drm_dev = data;
000cc920
AH		 1038
1039 fimd_mgr_initialize(&fimd_manager, drm_dev);
1040 exynos_drm_crtc_create(&fimd_manager);
1041 if (ctx->display)
1042 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1043
000cc920
AH		 1044 return 0;
1045
1046}
1047
1048static void fimd_unbind(struct device *dev, struct device *master,
1049 void *data)
1050{
1051 struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
1052 struct fimd_context *ctx = fimd_manager.ctx;
1053 struct drm_crtc *crtc = mgr->crtc;
1054
1055 fimd_dpms(mgr, DRM_MODE_DPMS_OFF);
1056
1057 if (ctx->display)
1058 exynos_dpi_remove(dev);
1059
1060 fimd_mgr_remove(mgr);
1061
1062 crtc->funcs->destroy(crtc);
1063}
1064
1065static const struct component_ops fimd_component_ops = {
1066 .bind = fimd_bind,
1067 .unbind = fimd_unbind,
1068};
1069
1070static int fimd_probe(struct platform_device *pdev)
1071{
1072 struct device *dev = &pdev->dev;
562ad9f4 1073 struct fimd_context *ctx;
3854fab2 1074 struct device_node *i80_if_timings;
562ad9f4 1075 struct resource *res;
562ad9f4 1076 int ret = -EINVAL;
1c248b7d 1077
df5225bc
ID		 1078 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1079 fimd_manager.type);
1080 if (ret)
1081 return ret;
1082
1083 if (!dev->of_node) {
1084 ret = -ENODEV;
1085 goto err_del_component;
1086 }
2d3f173c 1087
d873ab99 1088 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
df5225bc
ID		 1089 if (!ctx) {
1090 ret = -ENOMEM;
1091 goto err_del_component;
1092 }
1c248b7d 1093
bb7704d6 1094 ctx->dev = dev;
a43b933b 1095 ctx->suspended = true;
3854fab2 1096 ctx->driver_data = drm_fimd_get_driver_data(pdev);
bb7704d6 1097
1417f109
SP		 1098 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1099 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1100 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1101 ctx->vidcon1 |= VIDCON1_INV_VCLK;
562ad9f4 1102
3854fab2
YC		 1103 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1104 if (i80_if_timings) {
1105 u32 val;
1106
1107 ctx->i80_if = true;
1108
1109 if (ctx->driver_data->has_vidoutcon)
1110 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1111 else
1112 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1113 /*
1114 * The user manual describes that this "DSI_EN" bit is required
1115 * to enable I80 24-bit data interface.
1116 */
1117 ctx->vidcon0 |= VIDCON0_DSI_EN;
1118
1119 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1120 val = 0;
1121 ctx->i80ifcon = LCD_CS_SETUP(val);
1122 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1123 val = 0;
1124 ctx->i80ifcon |= LCD_WR_SETUP(val);
1125 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1126 val = 1;
1127 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1128 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1129 val = 0;
1130 ctx->i80ifcon |= LCD_WR_HOLD(val);
1131 }
1132 of_node_put(i80_if_timings);
1133
1134 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1135 "samsung,sysreg");
1136 if (IS_ERR(ctx->sysreg)) {
1137 dev_warn(dev, "failed to get system register.\n");
1138 ctx->sysreg = NULL;
1139 }
1140
a968e727
SP		 1141 ctx->bus_clk = devm_clk_get(dev, "fimd");
1142 if (IS_ERR(ctx->bus_clk)) {
1143 dev_err(dev, "failed to get bus clock\n");
df5225bc
ID		 1144 ret = PTR_ERR(ctx->bus_clk);
1145 goto err_del_component;
a968e727
SP		 1146 }
1147
1148 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1149 if (IS_ERR(ctx->lcd_clk)) {
1150 dev_err(dev, "failed to get lcd clock\n");
df5225bc
ID		 1151 ret = PTR_ERR(ctx->lcd_clk);
1152 goto err_del_component;
a968e727 1153 }
1c248b7d 1154
1c248b7d 1155 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1c248b7d 1156
d873ab99 1157 ctx->regs = devm_ioremap_resource(dev, res);
df5225bc
ID		 1158 if (IS_ERR(ctx->regs)) {
1159 ret = PTR_ERR(ctx->regs);
1160 goto err_del_component;
1161 }
1c248b7d 1162
3854fab2
YC		 1163 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1164 ctx->i80_if ? "lcd_sys" : "vsync");
1c248b7d
ID		 1165 if (!res) {
1166 dev_err(dev, "irq request failed.\n");
df5225bc
ID		 1167 ret = -ENXIO;
1168 goto err_del_component;
1c248b7d
ID		 1169 }
1170
055e0c06 1171 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
edc57266
SK		 1172 0, "drm_fimd", ctx);
1173 if (ret) {
1c248b7d 1174 dev_err(dev, "irq request failed.\n");
df5225bc 1175 goto err_del_component;
1c248b7d
ID		 1176 }
1177
57ed0f7b 1178 init_waitqueue_head(&ctx->wait_vsync_queue);
01ce113c 1179 atomic_set(&ctx->wait_vsync_event, 0);
1c248b7d 1180
bb7704d6 1181 platform_set_drvdata(pdev, &fimd_manager);
c32b06ef 1182
080be03d 1183 fimd_manager.ctx = ctx;
14b6873a 1184
000cc920
AH		 1185 ctx->display = exynos_dpi_probe(dev);
1186 if (IS_ERR(ctx->display))
1187 return PTR_ERR(ctx->display);
f37cd5e8
ID		 1188
1189 pm_runtime_enable(&pdev->dev);
1190
df5225bc
ID		 1191 ret = component_add(&pdev->dev, &fimd_component_ops);
1192 if (ret)
1193 goto err_disable_pm_runtime;
1194
1195 return ret;
1196
1197err_disable_pm_runtime:
1198 pm_runtime_disable(&pdev->dev);
1199
1200err_del_component:
1201 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1202 return ret;
f37cd5e8 1203}
cb91f6a0 1204
f37cd5e8
ID		 1205static int fimd_remove(struct platform_device *pdev)
1206{
af65c804 1207 pm_runtime_disable(&pdev->dev);
5d55393a 1208
df5225bc
ID		 1209 component_del(&pdev->dev, &fimd_component_ops);
1210 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1211
5d55393a 1212 return 0;
e30d4bcf
ID		 1213}
1214
132a5b91 1215struct platform_driver fimd_driver = {
1c248b7d 1216 .probe = fimd_probe,
56550d94 1217 .remove = fimd_remove,
1c248b7d
ID		 1218 .driver = {
1219 .name = "exynos4-fb",
1220 .owner = THIS_MODULE,
2d3f173c 1221 .of_match_table = fimd_driver_dt_match,
1c248b7d
ID		 1222 },
1223};
Linux kernel - Deliverables
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