projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/exynos: fix fb offset calculation for plane
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
CommitLineData
1c248b7d
ID		 1/* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
760285e7 14#include <drm/drmP.h>
1c248b7d
ID		 15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
cb91f6a0 20#include <linux/pm_runtime.h>
1c248b7d 21
5a213a55 22#include <video/samsung_fimd.h>
1c248b7d 23#include <drm/exynos_drm.h>
1c248b7d
ID		 24
25#include "exynos_drm_drv.h"
26#include "exynos_drm_fbdev.h"
27#include "exynos_drm_crtc.h"
bcc5cd1c 28#include "exynos_drm_iommu.h"
1c248b7d
ID		 29
30/*
31 * FIMD is stand for Fully Interactive Mobile Display and
32 * as a display controller, it transfers contents drawn on memory
33 * to a LCD Panel through Display Interfaces such as RGB or
34 * CPU Interface.
35 */
36
37/* position control register for hardware window 0, 2 ~ 4.*/
38#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
39#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
40/* size control register for hardware window 0. */
41#define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
42/* alpha control register for hardware window 1 ~ 4. */
43#define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
44/* size control register for hardware window 1 ~ 4. */
45#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
46
47#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
48#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
49#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
50
51/* color key control register for hardware window 1 ~ 4. */
52#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
53/* color key value register for hardware window 1 ~ 4. */
54#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
55
56/* FIMD has totally five hardware windows. */
57#define WINDOWS_NR 5
58
59#define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
60
e2e13389
LKA		 61struct fimd_driver_data {
62 unsigned int timing_base;
63};
64
6ecf18f9 65static struct fimd_driver_data exynos4_fimd_driver_data = {
e2e13389
LKA		 66 .timing_base = 0x0,
67};
68
6ecf18f9 69static struct fimd_driver_data exynos5_fimd_driver_data = {
e2e13389
LKA		 70 .timing_base = 0x20000,
71};
72
1c248b7d
ID		 73struct fimd_win_data {
74 unsigned int offset_x;
75 unsigned int offset_y;
19c8b834
ID		 76 unsigned int ovl_width;
77 unsigned int ovl_height;
78 unsigned int fb_width;
79 unsigned int fb_height;
1c248b7d 80 unsigned int bpp;
2c871127 81 dma_addr_t dma_addr;
1c248b7d
ID		 82 unsigned int buf_offsize;
83 unsigned int line_size; /* bytes */
ec05da95 84 bool enabled;
db7e55ae 85 bool resume;
1c248b7d
ID		 86};
87
88struct fimd_context {
89 struct exynos_drm_subdrv subdrv;
90 int irq;
91 struct drm_crtc *crtc;
92 struct clk *bus_clk;
93 struct clk *lcd_clk;
1c248b7d
ID		 94 void __iomem *regs;
95 struct fimd_win_data win_data[WINDOWS_NR];
96 unsigned int clkdiv;
97 unsigned int default_win;
98 unsigned long irq_flags;
99 u32 vidcon0;
100 u32 vidcon1;
cb91f6a0 101 bool suspended;
c32b06ef 102 struct mutex lock;
01ce113c
P		 103 wait_queue_head_t wait_vsync_queue;
104 atomic_t wait_vsync_event;
1c248b7d 105
607c50d4 106 struct exynos_drm_panel_info *panel;
1c248b7d
ID		 107};
108
e2e13389
LKA		 109static inline struct fimd_driver_data *drm_fimd_get_driver_data(
110 struct platform_device *pdev)
111{
112 return (struct fimd_driver_data *)
113 platform_get_device_id(pdev)->driver_data;
114}
115
1c248b7d
ID		 116static bool fimd_display_is_connected(struct device *dev)
117{
1c248b7d
ID		 118 DRM_DEBUG_KMS("%s\n", __FILE__);
119
120 /* TODO. */
121
122 return true;
123}
124
607c50d4 125static void *fimd_get_panel(struct device *dev)
1c248b7d
ID		 126{
127 struct fimd_context *ctx = get_fimd_context(dev);
128
129 DRM_DEBUG_KMS("%s\n", __FILE__);
130
607c50d4 131 return ctx->panel;
1c248b7d
ID		 132}
133
134static int fimd_check_timing(struct device *dev, void *timing)
135{
1c248b7d
ID		 136 DRM_DEBUG_KMS("%s\n", __FILE__);
137
138 /* TODO. */
139
140 return 0;
141}
142
143static int fimd_display_power_on(struct device *dev, int mode)
144{
1c248b7d
ID		 145 DRM_DEBUG_KMS("%s\n", __FILE__);
146
ec05da95 147 /* TODO */
1c248b7d
ID		 148
149 return 0;
150}
151
74ccc539 152static struct exynos_drm_display_ops fimd_display_ops = {
1c248b7d
ID		 153 .type = EXYNOS_DISPLAY_TYPE_LCD,
154 .is_connected = fimd_display_is_connected,
607c50d4 155 .get_panel = fimd_get_panel,
1c248b7d
ID		 156 .check_timing = fimd_check_timing,
157 .power_on = fimd_display_power_on,
158};
159
ec05da95
ID		 160static void fimd_dpms(struct device *subdrv_dev, int mode)
161{
c32b06ef
ID		 162 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
163
ec05da95
ID		 164 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
165
c32b06ef
ID		 166 mutex_lock(&ctx->lock);
167
cb91f6a0
JS		 168 switch (mode) {
169 case DRM_MODE_DPMS_ON:
c32b06ef
ID		 170 /*
171 * enable fimd hardware only if suspended status.
172 *
173 * P.S. fimd_dpms function would be called at booting time so
174 * clk_enable could be called double time.
175 */
176 if (ctx->suspended)
177 pm_runtime_get_sync(subdrv_dev);
cb91f6a0
JS		 178 break;
179 case DRM_MODE_DPMS_STANDBY:
180 case DRM_MODE_DPMS_SUSPEND:
181 case DRM_MODE_DPMS_OFF:
373af0c0
ID		 182 if (!ctx->suspended)
183 pm_runtime_put_sync(subdrv_dev);
cb91f6a0
JS		 184 break;
185 default:
186 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
187 break;
188 }
c32b06ef
ID		 189
190 mutex_unlock(&ctx->lock);
ec05da95
ID		 191}
192
193static void fimd_apply(struct device *subdrv_dev)
194{
195 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
677e84c1 196 struct exynos_drm_manager *mgr = ctx->subdrv.manager;
ec05da95
ID		 197 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
198 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
199 struct fimd_win_data *win_data;
864ee9e6 200 int i;
ec05da95
ID		 201
202 DRM_DEBUG_KMS("%s\n", __FILE__);
203
864ee9e6
JS		 204 for (i = 0; i < WINDOWS_NR; i++) {
205 win_data = &ctx->win_data[i];
206 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
207 ovl_ops->commit(subdrv_dev, i);
208 }
ec05da95
ID		 209
210 if (mgr_ops && mgr_ops->commit)
211 mgr_ops->commit(subdrv_dev);
212}
213
1c248b7d
ID		 214static void fimd_commit(struct device *dev)
215{
216 struct fimd_context *ctx = get_fimd_context(dev);
607c50d4
ECK		 217 struct exynos_drm_panel_info *panel = ctx->panel;
218 struct fb_videomode *timing = &panel->timing;
e2e13389
LKA		 219 struct fimd_driver_data *driver_data;
220 struct platform_device *pdev = to_platform_device(dev);
1c248b7d
ID		 221 u32 val;
222
e2e13389 223 driver_data = drm_fimd_get_driver_data(pdev);
e30d4bcf
ID		 224 if (ctx->suspended)
225 return;
226
1c248b7d
ID		 227 DRM_DEBUG_KMS("%s\n", __FILE__);
228
229 /* setup polarity values from machine code. */
e2e13389 230 writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
1c248b7d
ID		 231
232 /* setup vertical timing values. */
233 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
234 VIDTCON0_VFPD(timing->lower_margin - 1) |
235 VIDTCON0_VSPW(timing->vsync_len - 1);
e2e13389 236 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
1c248b7d
ID		 237
238 /* setup horizontal timing values. */
239 val = VIDTCON1_HBPD(timing->left_margin - 1) |
240 VIDTCON1_HFPD(timing->right_margin - 1) |
241 VIDTCON1_HSPW(timing->hsync_len - 1);
e2e13389 242 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
1c248b7d
ID		 243
244 /* setup horizontal and vertical display size. */
245 val = VIDTCON2_LINEVAL(timing->yres - 1) |
246 VIDTCON2_HOZVAL(timing->xres - 1);
e2e13389 247 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
1c248b7d
ID		 248
249 /* setup clock source, clock divider, enable dma. */
250 val = ctx->vidcon0;
251 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
252
253 if (ctx->clkdiv > 1)
254 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
255 else
256 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
257
258 /*
259 * fields of register with prefix '_F' would be updated
260 * at vsync(same as dma start)
261 */
262 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
263 writel(val, ctx->regs + VIDCON0);
264}
265
266static int fimd_enable_vblank(struct device *dev)
267{
268 struct fimd_context *ctx = get_fimd_context(dev);
269 u32 val;
270
271 DRM_DEBUG_KMS("%s\n", __FILE__);
272
cb91f6a0
JS		 273 if (ctx->suspended)
274 return -EPERM;
275
1c248b7d
ID		 276 if (!test_and_set_bit(0, &ctx->irq_flags)) {
277 val = readl(ctx->regs + VIDINTCON0);
278
279 val |= VIDINTCON0_INT_ENABLE;
280 val |= VIDINTCON0_INT_FRAME;
281
282 val &= ~VIDINTCON0_FRAMESEL0_MASK;
283 val |= VIDINTCON0_FRAMESEL0_VSYNC;
284 val &= ~VIDINTCON0_FRAMESEL1_MASK;
285 val |= VIDINTCON0_FRAMESEL1_NONE;
286
287 writel(val, ctx->regs + VIDINTCON0);
288 }
289
290 return 0;
291}
292
293static void fimd_disable_vblank(struct device *dev)
294{
295 struct fimd_context *ctx = get_fimd_context(dev);
296 u32 val;
297
298 DRM_DEBUG_KMS("%s\n", __FILE__);
299
cb91f6a0
JS		 300 if (ctx->suspended)
301 return;
302
1c248b7d
ID		 303 if (test_and_clear_bit(0, &ctx->irq_flags)) {
304 val = readl(ctx->regs + VIDINTCON0);
305
306 val &= ~VIDINTCON0_INT_FRAME;
307 val &= ~VIDINTCON0_INT_ENABLE;
308
309 writel(val, ctx->regs + VIDINTCON0);
310 }
311}
312
07033970
P		 313static void fimd_wait_for_vblank(struct device *dev)
314{
315 struct fimd_context *ctx = get_fimd_context(dev);
07033970 316
01ce113c
P		 317 if (ctx->suspended)
318 return;
319
320 atomic_set(&ctx->wait_vsync_event, 1);
321
322 /*
323 * wait for FIMD to signal VSYNC interrupt or return after
324 * timeout which is set to 50ms (refresh rate of 20).
325 */
326 if (!wait_event_timeout(ctx->wait_vsync_queue,
327 !atomic_read(&ctx->wait_vsync_event),
328 DRM_HZ/20))
07033970
P		 329 DRM_DEBUG_KMS("vblank wait timed out.\n");
330}
331
1c248b7d 332static struct exynos_drm_manager_ops fimd_manager_ops = {
ec05da95
ID		 333 .dpms = fimd_dpms,
334 .apply = fimd_apply,
1c248b7d
ID		 335 .commit = fimd_commit,
336 .enable_vblank = fimd_enable_vblank,
337 .disable_vblank = fimd_disable_vblank,
07033970 338 .wait_for_vblank = fimd_wait_for_vblank,
1c248b7d
ID		 339};
340
341static void fimd_win_mode_set(struct device *dev,
342 struct exynos_drm_overlay *overlay)
343{
344 struct fimd_context *ctx = get_fimd_context(dev);
345 struct fimd_win_data *win_data;
864ee9e6 346 int win;
19c8b834 347 unsigned long offset;
1c248b7d
ID		 348
349 DRM_DEBUG_KMS("%s\n", __FILE__);
350
351 if (!overlay) {
352 dev_err(dev, "overlay is NULL\n");
353 return;
354 }
355
864ee9e6
JS		 356 win = overlay->zpos;
357 if (win == DEFAULT_ZPOS)
358 win = ctx->default_win;
359
360 if (win < 0 || win > WINDOWS_NR)
361 return;
362
19c8b834
ID		 363 offset = overlay->fb_x * (overlay->bpp >> 3);
364 offset += overlay->fb_y * overlay->pitch;
365
366 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
367
864ee9e6 368 win_data = &ctx->win_data[win];
1c248b7d 369
19c8b834
ID		 370 win_data->offset_x = overlay->crtc_x;
371 win_data->offset_y = overlay->crtc_y;
372 win_data->ovl_width = overlay->crtc_width;
373 win_data->ovl_height = overlay->crtc_height;
374 win_data->fb_width = overlay->fb_width;
375 win_data->fb_height = overlay->fb_height;
229d3534 376 win_data->dma_addr = overlay->dma_addr[0] + offset;
1c248b7d 377 win_data->bpp = overlay->bpp;
19c8b834
ID		 378 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
379 (overlay->bpp >> 3);
380 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
381
382 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
383 win_data->offset_x, win_data->offset_y);
384 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
385 win_data->ovl_width, win_data->ovl_height);
ddd8e959 386 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
19c8b834
ID		 387 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
388 overlay->fb_width, overlay->crtc_width);
1c248b7d
ID		 389}
390
391static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
392{
393 struct fimd_context *ctx = get_fimd_context(dev);
394 struct fimd_win_data *win_data = &ctx->win_data[win];
395 unsigned long val;
396
397 DRM_DEBUG_KMS("%s\n", __FILE__);
398
399 val = WINCONx_ENWIN;
400
401 switch (win_data->bpp) {
402 case 1:
403 val |= WINCON0_BPPMODE_1BPP;
404 val |= WINCONx_BITSWP;
405 val |= WINCONx_BURSTLEN_4WORD;
406 break;
407 case 2:
408 val |= WINCON0_BPPMODE_2BPP;
409 val |= WINCONx_BITSWP;
410 val |= WINCONx_BURSTLEN_8WORD;
411 break;
412 case 4:
413 val |= WINCON0_BPPMODE_4BPP;
414 val |= WINCONx_BITSWP;
415 val |= WINCONx_BURSTLEN_8WORD;
416 break;
417 case 8:
418 val |= WINCON0_BPPMODE_8BPP_PALETTE;
419 val |= WINCONx_BURSTLEN_8WORD;
420 val |= WINCONx_BYTSWP;
421 break;
422 case 16:
423 val |= WINCON0_BPPMODE_16BPP_565;
424 val |= WINCONx_HAWSWP;
425 val |= WINCONx_BURSTLEN_16WORD;
426 break;
427 case 24:
428 val |= WINCON0_BPPMODE_24BPP_888;
429 val |= WINCONx_WSWP;
430 val |= WINCONx_BURSTLEN_16WORD;
431 break;
432 case 32:
433 val |= WINCON1_BPPMODE_28BPP_A4888
434 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
435 val |= WINCONx_WSWP;
436 val |= WINCONx_BURSTLEN_16WORD;
437 break;
438 default:
439 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
440
441 val |= WINCON0_BPPMODE_24BPP_888;
442 val |= WINCONx_WSWP;
443 val |= WINCONx_BURSTLEN_16WORD;
444 break;
445 }
446
447 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
448
449 writel(val, ctx->regs + WINCON(win));
450}
451
452static void fimd_win_set_colkey(struct device *dev, unsigned int win)
453{
454 struct fimd_context *ctx = get_fimd_context(dev);
455 unsigned int keycon0 = 0, keycon1 = 0;
456
457 DRM_DEBUG_KMS("%s\n", __FILE__);
458
459 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
460 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
461
462 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
463
464 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
465 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
466}
467
864ee9e6 468static void fimd_win_commit(struct device *dev, int zpos)
1c248b7d
ID		 469{
470 struct fimd_context *ctx = get_fimd_context(dev);
471 struct fimd_win_data *win_data;
864ee9e6 472 int win = zpos;
1c248b7d
ID		 473 unsigned long val, alpha, size;
474
475 DRM_DEBUG_KMS("%s\n", __FILE__);
476
e30d4bcf
ID		 477 if (ctx->suspended)
478 return;
479
864ee9e6
JS		 480 if (win == DEFAULT_ZPOS)
481 win = ctx->default_win;
482
1c248b7d
ID		 483 if (win < 0 || win > WINDOWS_NR)
484 return;
485
486 win_data = &ctx->win_data[win];
487
488 /*
489 * SHADOWCON register is used for enabling timing.
490 *
491 * for example, once only width value of a register is set,
492 * if the dma is started then fimd hardware could malfunction so
493 * with protect window setting, the register fields with prefix '_F'
494 * wouldn't be updated at vsync also but updated once unprotect window
495 * is set.
496 */
497
498 /* protect windows */
499 val = readl(ctx->regs + SHADOWCON);
500 val |= SHADOWCON_WINx_PROTECT(win);
501 writel(val, ctx->regs + SHADOWCON);
502
503 /* buffer start address */
2c871127 504 val = (unsigned long)win_data->dma_addr;
1c248b7d
ID		 505 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
506
507 /* buffer end address */
19c8b834 508 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
2c871127 509 val = (unsigned long)(win_data->dma_addr + size);
1c248b7d
ID		 510 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
511
512 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
2c871127 513 (unsigned long)win_data->dma_addr, val, size);
19c8b834
ID		 514 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
515 win_data->ovl_width, win_data->ovl_height);
1c248b7d
ID		 516
517 /* buffer size */
518 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
519 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
520 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
521
522 /* OSD position */
523 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
524 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
525 writel(val, ctx->regs + VIDOSD_A(win));
526
19c8b834
ID		 527 val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
528 win_data->ovl_width - 1) |
529 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
530 win_data->ovl_height - 1);
1c248b7d
ID		 531 writel(val, ctx->regs + VIDOSD_B(win));
532
19c8b834 533 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
1c248b7d 534 win_data->offset_x, win_data->offset_y,
19c8b834
ID		 535 win_data->offset_x + win_data->ovl_width - 1,
536 win_data->offset_y + win_data->ovl_height - 1);
1c248b7d
ID		 537
538 /* hardware window 0 doesn't support alpha channel. */
539 if (win != 0) {
540 /* OSD alpha */
541 alpha = VIDISD14C_ALPHA1_R(0xf) |
542 VIDISD14C_ALPHA1_G(0xf) |
543 VIDISD14C_ALPHA1_B(0xf);
544
545 writel(alpha, ctx->regs + VIDOSD_C(win));
546 }
547
548 /* OSD size */
549 if (win != 3 && win != 4) {
550 u32 offset = VIDOSD_D(win);
551 if (win == 0)
552 offset = VIDOSD_C_SIZE_W0;
19c8b834 553 val = win_data->ovl_width * win_data->ovl_height;
1c248b7d
ID		 554 writel(val, ctx->regs + offset);
555
556 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
557 }
558
559 fimd_win_set_pixfmt(dev, win);
560
561 /* hardware window 0 doesn't support color key. */
562 if (win != 0)
563 fimd_win_set_colkey(dev, win);
564
ec05da95
ID		 565 /* wincon */
566 val = readl(ctx->regs + WINCON(win));
567 val |= WINCONx_ENWIN;
568 writel(val, ctx->regs + WINCON(win));
569
1c248b7d
ID		 570 /* Enable DMA channel and unprotect windows */
571 val = readl(ctx->regs + SHADOWCON);
572 val |= SHADOWCON_CHx_ENABLE(win);
573 val &= ~SHADOWCON_WINx_PROTECT(win);
574 writel(val, ctx->regs + SHADOWCON);
ec05da95
ID		 575
576 win_data->enabled = true;
1c248b7d
ID		 577}
578
864ee9e6 579static void fimd_win_disable(struct device *dev, int zpos)
1c248b7d
ID		 580{
581 struct fimd_context *ctx = get_fimd_context(dev);
ec05da95 582 struct fimd_win_data *win_data;
864ee9e6 583 int win = zpos;
1c248b7d
ID		 584 u32 val;
585
586 DRM_DEBUG_KMS("%s\n", __FILE__);
587
864ee9e6
JS		 588 if (win == DEFAULT_ZPOS)
589 win = ctx->default_win;
590
1c248b7d
ID		 591 if (win < 0 || win > WINDOWS_NR)
592 return;
593
ec05da95
ID		 594 win_data = &ctx->win_data[win];
595
db7e55ae
P		 596 if (ctx->suspended) {
597 /* do not resume this window*/
598 win_data->resume = false;
599 return;
600 }
601
1c248b7d
ID		 602 /* protect windows */
603 val = readl(ctx->regs + SHADOWCON);
604 val |= SHADOWCON_WINx_PROTECT(win);
605 writel(val, ctx->regs + SHADOWCON);
606
607 /* wincon */
608 val = readl(ctx->regs + WINCON(win));
609 val &= ~WINCONx_ENWIN;
610 writel(val, ctx->regs + WINCON(win));
611
612 /* unprotect windows */
613 val = readl(ctx->regs + SHADOWCON);
614 val &= ~SHADOWCON_CHx_ENABLE(win);
615 val &= ~SHADOWCON_WINx_PROTECT(win);
616 writel(val, ctx->regs + SHADOWCON);
ec05da95
ID		 617
618 win_data->enabled = false;
1c248b7d
ID		 619}
620
621static struct exynos_drm_overlay_ops fimd_overlay_ops = {
622 .mode_set = fimd_win_mode_set,
623 .commit = fimd_win_commit,
624 .disable = fimd_win_disable,
625};
626
677e84c1
JS		 627static struct exynos_drm_manager fimd_manager = {
628 .pipe = -1,
629 .ops = &fimd_manager_ops,
630 .overlay_ops = &fimd_overlay_ops,
631 .display_ops = &fimd_display_ops,
632};
633
1c248b7d
ID		 634static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
635{
636 struct exynos_drm_private *dev_priv = drm_dev->dev_private;
637 struct drm_pending_vblank_event *e, *t;
638 struct timeval now;
639 unsigned long flags;
1c248b7d
ID		 640
641 spin_lock_irqsave(&drm_dev->event_lock, flags);
642
1c248b7d
ID		 643 list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
644 base.link) {
a88cab2b 645 /* if event's pipe isn't same as crtc then ignore it. */
ccf4d883
ID		 646 if (crtc != e->pipe)
647 continue;
648
1c248b7d
ID		 649 do_gettimeofday(&now);
650 e->event.sequence = 0;
651 e->event.tv_sec = now.tv_sec;
652 e->event.tv_usec = now.tv_usec;
653
654 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
655 wake_up_interruptible(&e->base.file_priv->event_wait);
e1f48ee5 656 drm_vblank_put(drm_dev, crtc);
1c248b7d
ID		 657 }
658
1c248b7d
ID		 659 spin_unlock_irqrestore(&drm_dev->event_lock, flags);
660}
661
662static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
663{
664 struct fimd_context *ctx = (struct fimd_context *)dev_id;
665 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
666 struct drm_device *drm_dev = subdrv->drm_dev;
677e84c1 667 struct exynos_drm_manager *manager = subdrv->manager;
1c248b7d
ID		 668 u32 val;
669
670 val = readl(ctx->regs + VIDINTCON1);
671
672 if (val & VIDINTCON1_INT_FRAME)
673 /* VSYNC interrupt */
674 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
675
ec05da95
ID		 676 /* check the crtc is detached already from encoder */
677 if (manager->pipe < 0)
678 goto out;
483b88f8 679
1c248b7d
ID		 680 drm_handle_vblank(drm_dev, manager->pipe);
681 fimd_finish_pageflip(drm_dev, manager->pipe);
682
01ce113c
P		 683 /* set wait vsync event to zero and wake up queue. */
684 if (atomic_read(&ctx->wait_vsync_event)) {
685 atomic_set(&ctx->wait_vsync_event, 0);
686 DRM_WAKEUP(&ctx->wait_vsync_queue);
687 }
ec05da95 688out:
1c248b7d
ID		 689 return IRQ_HANDLED;
690}
691
41c24346 692static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
1c248b7d 693{
1c248b7d
ID		 694 DRM_DEBUG_KMS("%s\n", __FILE__);
695
696 /*
697 * enable drm irq mode.
698 * - with irq_enabled = 1, we can use the vblank feature.
699 *
700 * P.S. note that we wouldn't use drm irq handler but
701 * just specific driver own one instead because
702 * drm framework supports only one irq handler.
703 */
704 drm_dev->irq_enabled = 1;
705
ec05da95
ID		 706 /*
707 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
708 * by drm timer once a current process gives up ownership of
709 * vblank event.(after drm_vblank_put function is called)
710 */
711 drm_dev->vblank_disable_allowed = 1;
712
bcc5cd1c
ID		 713 /* attach this sub driver to iommu mapping if supported. */
714 if (is_drm_iommu_supported(drm_dev))
715 drm_iommu_attach_device(drm_dev, dev);
716
1c248b7d
ID		 717 return 0;
718}
719
29cb6025 720static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
1c248b7d 721{
1c248b7d
ID		 722 DRM_DEBUG_KMS("%s\n", __FILE__);
723
bcc5cd1c
ID		 724 /* detach this sub driver from iommu mapping if supported. */
725 if (is_drm_iommu_supported(drm_dev))
726 drm_iommu_detach_device(drm_dev, dev);
1c248b7d
ID		 727}
728
729static int fimd_calc_clkdiv(struct fimd_context *ctx,
730 struct fb_videomode *timing)
731{
732 unsigned long clk = clk_get_rate(ctx->lcd_clk);
733 u32 retrace;
734 u32 clkdiv;
735 u32 best_framerate = 0;
736 u32 framerate;
737
738 DRM_DEBUG_KMS("%s\n", __FILE__);
739
740 retrace = timing->left_margin + timing->hsync_len +
741 timing->right_margin + timing->xres;
742 retrace *= timing->upper_margin + timing->vsync_len +
743 timing->lower_margin + timing->yres;
744
745 /* default framerate is 60Hz */
746 if (!timing->refresh)
747 timing->refresh = 60;
748
749 clk /= retrace;
750
751 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
752 int tmp;
753
754 /* get best framerate */
755 framerate = clk / clkdiv;
756 tmp = timing->refresh - framerate;
757 if (tmp < 0) {
758 best_framerate = framerate;
759 continue;
760 } else {
761 if (!best_framerate)
762 best_framerate = framerate;
763 else if (tmp < (best_framerate - framerate))
764 best_framerate = framerate;
765 break;
766 }
767 }
768
769 return clkdiv;
770}
771
772static void fimd_clear_win(struct fimd_context *ctx, int win)
773{
774 u32 val;
775
776 DRM_DEBUG_KMS("%s\n", __FILE__);
777
778 writel(0, ctx->regs + WINCON(win));
779 writel(0, ctx->regs + VIDOSD_A(win));
780 writel(0, ctx->regs + VIDOSD_B(win));
781 writel(0, ctx->regs + VIDOSD_C(win));
782
783 if (win == 1 || win == 2)
784 writel(0, ctx->regs + VIDOSD_D(win));
785
786 val = readl(ctx->regs + SHADOWCON);
787 val &= ~SHADOWCON_WINx_PROTECT(win);
788 writel(val, ctx->regs + SHADOWCON);
789}
790
5d55393a 791static int fimd_clock(struct fimd_context *ctx, bool enable)
373af0c0 792{
373af0c0
ID		 793 DRM_DEBUG_KMS("%s\n", __FILE__);
794
373af0c0
ID		 795 if (enable) {
796 int ret;
797
798 ret = clk_enable(ctx->bus_clk);
799 if (ret < 0)
800 return ret;
801
802 ret = clk_enable(ctx->lcd_clk);
803 if (ret < 0) {
804 clk_disable(ctx->bus_clk);
805 return ret;
806 }
5d55393a
ID		 807 } else {
808 clk_disable(ctx->lcd_clk);
809 clk_disable(ctx->bus_clk);
810 }
811
812 return 0;
813}
814
db7e55ae
P		 815static void fimd_window_suspend(struct device *dev)
816{
817 struct fimd_context *ctx = get_fimd_context(dev);
818 struct fimd_win_data *win_data;
819 int i;
820
821 for (i = 0; i < WINDOWS_NR; i++) {
822 win_data = &ctx->win_data[i];
823 win_data->resume = win_data->enabled;
824 fimd_win_disable(dev, i);
825 }
826 fimd_wait_for_vblank(dev);
827}
828
829static void fimd_window_resume(struct device *dev)
830{
831 struct fimd_context *ctx = get_fimd_context(dev);
832 struct fimd_win_data *win_data;
833 int i;
834
835 for (i = 0; i < WINDOWS_NR; i++) {
836 win_data = &ctx->win_data[i];
837 win_data->enabled = win_data->resume;
838 win_data->resume = false;
839 }
840}
841
5d55393a
ID		 842static int fimd_activate(struct fimd_context *ctx, bool enable)
843{
db7e55ae 844 struct device *dev = ctx->subdrv.dev;
5d55393a
ID		 845 if (enable) {
846 int ret;
5d55393a
ID		 847
848 ret = fimd_clock(ctx, true);
849 if (ret < 0)
850 return ret;
373af0c0
ID		 851
852 ctx->suspended = false;
853
854 /* if vblank was enabled status, enable it again. */
855 if (test_and_clear_bit(0, &ctx->irq_flags))
856 fimd_enable_vblank(dev);
db7e55ae
P		 857
858 fimd_window_resume(dev);
373af0c0 859 } else {
db7e55ae
P		 860 fimd_window_suspend(dev);
861
5d55393a 862 fimd_clock(ctx, false);
373af0c0
ID		 863 ctx->suspended = true;
864 }
865
866 return 0;
867}
868
1c248b7d
ID		 869static int __devinit fimd_probe(struct platform_device *pdev)
870{
871 struct device *dev = &pdev->dev;
872 struct fimd_context *ctx;
873 struct exynos_drm_subdrv *subdrv;
874 struct exynos_drm_fimd_pdata *pdata;
607c50d4 875 struct exynos_drm_panel_info *panel;
1c248b7d
ID		 876 struct resource *res;
877 int win;
878 int ret = -EINVAL;
879
880 DRM_DEBUG_KMS("%s\n", __FILE__);
881
882 pdata = pdev->dev.platform_data;
883 if (!pdata) {
884 dev_err(dev, "no platform data specified\n");
885 return -EINVAL;
886 }
887
607c50d4
ECK		 888 panel = &pdata->panel;
889 if (!panel) {
890 dev_err(dev, "panel is null.\n");
1c248b7d
ID		 891 return -EINVAL;
892 }
893
edc57266 894 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
1c248b7d
ID		 895 if (!ctx)
896 return -ENOMEM;
897
a4d8de5f 898 ctx->bus_clk = devm_clk_get(dev, "fimd");
1c248b7d
ID		 899 if (IS_ERR(ctx->bus_clk)) {
900 dev_err(dev, "failed to get bus clock\n");
a4d8de5f 901 return PTR_ERR(ctx->bus_clk);
1c248b7d
ID		 902 }
903
a4d8de5f 904 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1c248b7d
ID		 905 if (IS_ERR(ctx->lcd_clk)) {
906 dev_err(dev, "failed to get lcd clock\n");
a4d8de5f 907 return PTR_ERR(ctx->lcd_clk);
1c248b7d
ID		 908 }
909
1c248b7d 910 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1c248b7d 911
edc57266 912 ctx->regs = devm_request_and_ioremap(&pdev->dev, res);
1c248b7d
ID		 913 if (!ctx->regs) {
914 dev_err(dev, "failed to map registers\n");
a4d8de5f 915 return -ENXIO;
1c248b7d
ID		 916 }
917
918 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
919 if (!res) {
920 dev_err(dev, "irq request failed.\n");
a4d8de5f 921 return -ENXIO;
1c248b7d
ID		 922 }
923
924 ctx->irq = res->start;
925
edc57266
SK		 926 ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler,
927 0, "drm_fimd", ctx);
928 if (ret) {
1c248b7d 929 dev_err(dev, "irq request failed.\n");
a4d8de5f 930 return ret;
1c248b7d
ID		 931 }
932
1c248b7d
ID		 933 ctx->vidcon0 = pdata->vidcon0;
934 ctx->vidcon1 = pdata->vidcon1;
935 ctx->default_win = pdata->default_win;
607c50d4 936 ctx->panel = panel;
01ce113c
P		 937 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
938 atomic_set(&ctx->wait_vsync_event, 0);
1c248b7d 939
1c248b7d
ID		 940 subdrv = &ctx->subdrv;
941
677e84c1
JS		 942 subdrv->dev = dev;
943 subdrv->manager = &fimd_manager;
1c248b7d
ID		 944 subdrv->probe = fimd_subdrv_probe;
945 subdrv->remove = fimd_subdrv_remove;
1c248b7d 946
c32b06ef
ID		 947 mutex_init(&ctx->lock);
948
1c248b7d 949 platform_set_drvdata(pdev, ctx);
c32b06ef 950
c32b06ef
ID		 951 pm_runtime_enable(dev);
952 pm_runtime_get_sync(dev);
953
0d8ce3ae
MS		 954 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
955 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
956
957 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
958 panel->timing.pixclock, ctx->clkdiv);
959
c32b06ef
ID		 960 for (win = 0; win < WINDOWS_NR; win++)
961 fimd_clear_win(ctx, win);
962
1c248b7d
ID		 963 exynos_drm_subdrv_register(subdrv);
964
965 return 0;
1c248b7d
ID		 966}
967
968static int __devexit fimd_remove(struct platform_device *pdev)
969{
cb91f6a0 970 struct device *dev = &pdev->dev;
1c248b7d
ID		 971 struct fimd_context *ctx = platform_get_drvdata(pdev);
972
973 DRM_DEBUG_KMS("%s\n", __FILE__);
974
975 exynos_drm_subdrv_unregister(&ctx->subdrv);
976
cb91f6a0
JS		 977 if (ctx->suspended)
978 goto out;
979
1c248b7d
ID		 980 clk_disable(ctx->lcd_clk);
981 clk_disable(ctx->bus_clk);
cb91f6a0
JS		 982
983 pm_runtime_set_suspended(dev);
984 pm_runtime_put_sync(dev);
985
986out:
987 pm_runtime_disable(dev);
988
1c248b7d
ID		 989 return 0;
990}
991
e30d4bcf
ID		 992#ifdef CONFIG_PM_SLEEP
993static int fimd_suspend(struct device *dev)
994{
373af0c0 995 struct fimd_context *ctx = get_fimd_context(dev);
e30d4bcf 996
373af0c0
ID		 997 /*
998 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
999 * called here, an error would be returned by that interface
1000 * because the usage_count of pm runtime is more than 1.
1001 */
5d55393a
ID		 1002 if (!pm_runtime_suspended(dev))
1003 return fimd_activate(ctx, false);
1004
1005 return 0;
e30d4bcf
ID		 1006}
1007
1008static int fimd_resume(struct device *dev)
1009{
373af0c0 1010 struct fimd_context *ctx = get_fimd_context(dev);
e30d4bcf 1011
373af0c0
ID		 1012 /*
1013 * if entered to sleep when lcd panel was on, the usage_count
1014 * of pm runtime would still be 1 so in this case, fimd driver
1015 * should be on directly not drawing on pm runtime interface.
1016 */
5d55393a
ID		 1017 if (pm_runtime_suspended(dev)) {
1018 int ret;
1019
1020 ret = fimd_activate(ctx, true);
1021 if (ret < 0)
1022 return ret;
1023
1024 /*
1025 * in case of dpms on(standby), fimd_apply function will
1026 * be called by encoder's dpms callback to update fimd's
1027 * registers but in case of sleep wakeup, it's not.
1028 * so fimd_apply function should be called at here.
1029 */
1030 fimd_apply(dev);
1031 }
e30d4bcf 1032
e30d4bcf
ID		 1033 return 0;
1034}
1035#endif
1036
cb91f6a0
JS		 1037#ifdef CONFIG_PM_RUNTIME
1038static int fimd_runtime_suspend(struct device *dev)
1039{
1040 struct fimd_context *ctx = get_fimd_context(dev);
1041
1042 DRM_DEBUG_KMS("%s\n", __FILE__);
1043
5d55393a 1044 return fimd_activate(ctx, false);
cb91f6a0
JS		 1045}
1046
1047static int fimd_runtime_resume(struct device *dev)
1048{
1049 struct fimd_context *ctx = get_fimd_context(dev);
cb91f6a0
JS		 1050
1051 DRM_DEBUG_KMS("%s\n", __FILE__);
1052
5d55393a 1053 return fimd_activate(ctx, true);
cb91f6a0
JS		 1054}
1055#endif
1056
e2e13389
LKA		 1057static struct platform_device_id fimd_driver_ids[] = {
1058 {
1059 .name = "exynos4-fb",
1060 .driver_data = (unsigned long)&exynos4_fimd_driver_data,
1061 }, {
1062 .name = "exynos5-fb",
1063 .driver_data = (unsigned long)&exynos5_fimd_driver_data,
1064 },
1065 {},
1066};
1067MODULE_DEVICE_TABLE(platform, fimd_driver_ids);
1068
cb91f6a0 1069static const struct dev_pm_ops fimd_pm_ops = {
e30d4bcf 1070 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
cb91f6a0
JS		 1071 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1072};
1073
132a5b91 1074struct platform_driver fimd_driver = {
1c248b7d
ID		 1075 .probe = fimd_probe,
1076 .remove = __devexit_p(fimd_remove),
e2e13389 1077 .id_table = fimd_driver_ids,
1c248b7d
ID		 1078 .driver = {
1079 .name = "exynos4-fb",
1080 .owner = THIS_MODULE,
cb91f6a0 1081 .pm = &fimd_pm_ops,
1c248b7d
ID		 1082 },
1083};
Linux kernel - Deliverables
This page took 0.173305 seconds and 5 git commands to generate.