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Merge remote-tracking branch 'asoc/topic/ac97' into asoc-fsl
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_gsc.c
CommitLineData
f2646380
EK		 1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Authors:
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <linux/kernel.h>
f2646380
EK		 15#include <linux/platform_device.h>
16#include <linux/clk.h>
17#include <linux/pm_runtime.h>
18#include <plat/map-base.h>
19
20#include <drm/drmP.h>
21#include <drm/exynos_drm.h>
22#include "regs-gsc.h"
23#include "exynos_drm_ipp.h"
24#include "exynos_drm_gsc.h"
25
26/*
6fe891f6 27 * GSC stands for General SCaler and
f2646380
EK		 28 * supports image scaler/rotator and input/output DMA operations.
29 * input DMA reads image data from the memory.
30 * output DMA writes image data to memory.
31 * GSC supports image rotation and image effect functions.
32 *
33 * M2M operation : supports crop/scale/rotation/csc so on.
34 * Memory ----> GSC H/W ----> Memory.
35 * Writeback operation : supports cloned screen with FIMD.
36 * FIMD ----> GSC H/W ----> Memory.
37 * Output operation : supports direct display using local path.
38 * Memory ----> GSC H/W ----> FIMD, Mixer.
39 */
40
41/*
42 * TODO
43 * 1. check suspend/resume api if needed.
44 * 2. need to check use case platform_device_id.
45 * 3. check src/dst size with, height.
46 * 4. added check_prepare api for right register.
47 * 5. need to add supported list in prop_list.
48 * 6. check prescaler/scaler optimization.
49 */
50
51#define GSC_MAX_DEVS 4
52#define GSC_MAX_SRC 4
53#define GSC_MAX_DST 16
54#define GSC_RESET_TIMEOUT 50
55#define GSC_BUF_STOP 1
56#define GSC_BUF_START 2
57#define GSC_REG_SZ 16
58#define GSC_WIDTH_ITU_709 1280
59#define GSC_SC_UP_MAX_RATIO 65536
60#define GSC_SC_DOWN_RATIO_7_8 74898
61#define GSC_SC_DOWN_RATIO_6_8 87381
62#define GSC_SC_DOWN_RATIO_5_8 104857
63#define GSC_SC_DOWN_RATIO_4_8 131072
64#define GSC_SC_DOWN_RATIO_3_8 174762
65#define GSC_SC_DOWN_RATIO_2_8 262144
66#define GSC_REFRESH_MIN 12
67#define GSC_REFRESH_MAX 60
68#define GSC_CROP_MAX 8192
69#define GSC_CROP_MIN 32
70#define GSC_SCALE_MAX 4224
71#define GSC_SCALE_MIN 32
72#define GSC_COEF_RATIO 7
73#define GSC_COEF_PHASE 9
74#define GSC_COEF_ATTR 16
75#define GSC_COEF_H_8T 8
76#define GSC_COEF_V_4T 4
77#define GSC_COEF_DEPTH 3
78
79#define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
80#define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
81 struct gsc_context, ippdrv);
82#define gsc_read(offset) readl(ctx->regs + (offset))
83#define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
84
85/*
86 * A structure of scaler.
87 *
88 * @range: narrow, wide.
89 * @pre_shfactor: pre sclaer shift factor.
90 * @pre_hratio: horizontal ratio of the prescaler.
91 * @pre_vratio: vertical ratio of the prescaler.
92 * @main_hratio: the main scaler's horizontal ratio.
93 * @main_vratio: the main scaler's vertical ratio.
94 */
95struct gsc_scaler {
96 bool range;
97 u32 pre_shfactor;
98 u32 pre_hratio;
99 u32 pre_vratio;
100 unsigned long main_hratio;
101 unsigned long main_vratio;
102};
103
104/*
105 * A structure of scaler capability.
106 *
107 * find user manual 49.2 features.
108 * @tile_w: tile mode or rotation width.
109 * @tile_h: tile mode or rotation height.
110 * @w: other cases width.
111 * @h: other cases height.
112 */
113struct gsc_capability {
114 /* tile or rotation */
115 u32 tile_w;
116 u32 tile_h;
117 /* other cases */
118 u32 w;
119 u32 h;
120};
121
122/*
123 * A structure of gsc context.
124 *
125 * @ippdrv: prepare initialization using ippdrv.
126 * @regs_res: register resources.
127 * @regs: memory mapped io registers.
128 * @lock: locking of operations.
129 * @gsc_clk: gsc gate clock.
130 * @sc: scaler infomations.
131 * @id: gsc id.
132 * @irq: irq number.
133 * @rotation: supports rotation of src.
134 * @suspended: qos operations.
135 */
136struct gsc_context {
137 struct exynos_drm_ippdrv ippdrv;
138 struct resource *regs_res;
139 void __iomem *regs;
140 struct mutex lock;
141 struct clk *gsc_clk;
142 struct gsc_scaler sc;
143 int id;
144 int irq;
145 bool rotation;
146 bool suspended;
147};
148
149/* 8-tap Filter Coefficient */
150static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
151 { /* Ratio <= 65536 (~8:8) */
152 { 0, 0, 0, 128, 0, 0, 0, 0 },
153 { -1, 2, -6, 127, 7, -2, 1, 0 },
154 { -1, 4, -12, 125, 16, -5, 1, 0 },
155 { -1, 5, -15, 120, 25, -8, 2, 0 },
156 { -1, 6, -18, 114, 35, -10, 3, -1 },
157 { -1, 6, -20, 107, 46, -13, 4, -1 },
158 { -2, 7, -21, 99, 57, -16, 5, -1 },
159 { -1, 6, -20, 89, 68, -18, 5, -1 },
160 { -1, 6, -20, 79, 79, -20, 6, -1 },
161 { -1, 5, -18, 68, 89, -20, 6, -1 },
162 { -1, 5, -16, 57, 99, -21, 7, -2 },
163 { -1, 4, -13, 46, 107, -20, 6, -1 },
164 { -1, 3, -10, 35, 114, -18, 6, -1 },
165 { 0, 2, -8, 25, 120, -15, 5, -1 },
166 { 0, 1, -5, 16, 125, -12, 4, -1 },
167 { 0, 1, -2, 7, 127, -6, 2, -1 }
168 }, { /* 65536 < Ratio <= 74898 (~8:7) */
169 { 3, -8, 14, 111, 13, -8, 3, 0 },
170 { 2, -6, 7, 112, 21, -10, 3, -1 },
171 { 2, -4, 1, 110, 28, -12, 4, -1 },
172 { 1, -2, -3, 106, 36, -13, 4, -1 },
173 { 1, -1, -7, 103, 44, -15, 4, -1 },
174 { 1, 1, -11, 97, 53, -16, 4, -1 },
175 { 0, 2, -13, 91, 61, -16, 4, -1 },
176 { 0, 3, -15, 85, 69, -17, 4, -1 },
177 { 0, 3, -16, 77, 77, -16, 3, 0 },
178 { -1, 4, -17, 69, 85, -15, 3, 0 },
179 { -1, 4, -16, 61, 91, -13, 2, 0 },
180 { -1, 4, -16, 53, 97, -11, 1, 1 },
181 { -1, 4, -15, 44, 103, -7, -1, 1 },
182 { -1, 4, -13, 36, 106, -3, -2, 1 },
183 { -1, 4, -12, 28, 110, 1, -4, 2 },
184 { -1, 3, -10, 21, 112, 7, -6, 2 }
185 }, { /* 74898 < Ratio <= 87381 (~8:6) */
186 { 2, -11, 25, 96, 25, -11, 2, 0 },
187 { 2, -10, 19, 96, 31, -12, 2, 0 },
188 { 2, -9, 14, 94, 37, -12, 2, 0 },
189 { 2, -8, 10, 92, 43, -12, 1, 0 },
190 { 2, -7, 5, 90, 49, -12, 1, 0 },
191 { 2, -5, 1, 86, 55, -12, 0, 1 },
192 { 2, -4, -2, 82, 61, -11, -1, 1 },
193 { 1, -3, -5, 77, 67, -9, -1, 1 },
194 { 1, -2, -7, 72, 72, -7, -2, 1 },
195 { 1, -1, -9, 67, 77, -5, -3, 1 },
196 { 1, -1, -11, 61, 82, -2, -4, 2 },
197 { 1, 0, -12, 55, 86, 1, -5, 2 },
198 { 0, 1, -12, 49, 90, 5, -7, 2 },
199 { 0, 1, -12, 43, 92, 10, -8, 2 },
200 { 0, 2, -12, 37, 94, 14, -9, 2 },
201 { 0, 2, -12, 31, 96, 19, -10, 2 }
202 }, { /* 87381 < Ratio <= 104857 (~8:5) */
203 { -1, -8, 33, 80, 33, -8, -1, 0 },
204 { -1, -8, 28, 80, 37, -7, -2, 1 },
205 { 0, -8, 24, 79, 41, -7, -2, 1 },
206 { 0, -8, 20, 78, 46, -6, -3, 1 },
207 { 0, -8, 16, 76, 50, -4, -3, 1 },
208 { 0, -7, 13, 74, 54, -3, -4, 1 },
209 { 1, -7, 10, 71, 58, -1, -5, 1 },
210 { 1, -6, 6, 68, 62, 1, -5, 1 },
211 { 1, -6, 4, 65, 65, 4, -6, 1 },
212 { 1, -5, 1, 62, 68, 6, -6, 1 },
213 { 1, -5, -1, 58, 71, 10, -7, 1 },
214 { 1, -4, -3, 54, 74, 13, -7, 0 },
215 { 1, -3, -4, 50, 76, 16, -8, 0 },
216 { 1, -3, -6, 46, 78, 20, -8, 0 },
217 { 1, -2, -7, 41, 79, 24, -8, 0 },
218 { 1, -2, -7, 37, 80, 28, -8, -1 }
219 }, { /* 104857 < Ratio <= 131072 (~8:4) */
220 { -3, 0, 35, 64, 35, 0, -3, 0 },
221 { -3, -1, 32, 64, 38, 1, -3, 0 },
222 { -2, -2, 29, 63, 41, 2, -3, 0 },
223 { -2, -3, 27, 63, 43, 4, -4, 0 },
224 { -2, -3, 24, 61, 46, 6, -4, 0 },
225 { -2, -3, 21, 60, 49, 7, -4, 0 },
226 { -1, -4, 19, 59, 51, 9, -4, -1 },
227 { -1, -4, 16, 57, 53, 12, -4, -1 },
228 { -1, -4, 14, 55, 55, 14, -4, -1 },
229 { -1, -4, 12, 53, 57, 16, -4, -1 },
230 { -1, -4, 9, 51, 59, 19, -4, -1 },
231 { 0, -4, 7, 49, 60, 21, -3, -2 },
232 { 0, -4, 6, 46, 61, 24, -3, -2 },
233 { 0, -4, 4, 43, 63, 27, -3, -2 },
234 { 0, -3, 2, 41, 63, 29, -2, -2 },
235 { 0, -3, 1, 38, 64, 32, -1, -3 }
236 }, { /* 131072 < Ratio <= 174762 (~8:3) */
237 { -1, 8, 33, 48, 33, 8, -1, 0 },
238 { -1, 7, 31, 49, 35, 9, -1, -1 },
239 { -1, 6, 30, 49, 36, 10, -1, -1 },
240 { -1, 5, 28, 48, 38, 12, -1, -1 },
241 { -1, 4, 26, 48, 39, 13, 0, -1 },
242 { -1, 3, 24, 47, 41, 15, 0, -1 },
243 { -1, 2, 23, 47, 42, 16, 0, -1 },
244 { -1, 2, 21, 45, 43, 18, 1, -1 },
245 { -1, 1, 19, 45, 45, 19, 1, -1 },
246 { -1, 1, 18, 43, 45, 21, 2, -1 },
247 { -1, 0, 16, 42, 47, 23, 2, -1 },
248 { -1, 0, 15, 41, 47, 24, 3, -1 },
249 { -1, 0, 13, 39, 48, 26, 4, -1 },
250 { -1, -1, 12, 38, 48, 28, 5, -1 },
251 { -1, -1, 10, 36, 49, 30, 6, -1 },
252 { -1, -1, 9, 35, 49, 31, 7, -1 }
253 }, { /* 174762 < Ratio <= 262144 (~8:2) */
254 { 2, 13, 30, 38, 30, 13, 2, 0 },
255 { 2, 12, 29, 38, 30, 14, 3, 0 },
256 { 2, 11, 28, 38, 31, 15, 3, 0 },
257 { 2, 10, 26, 38, 32, 16, 4, 0 },
258 { 1, 10, 26, 37, 33, 17, 4, 0 },
259 { 1, 9, 24, 37, 34, 18, 5, 0 },
260 { 1, 8, 24, 37, 34, 19, 5, 0 },
261 { 1, 7, 22, 36, 35, 20, 6, 1 },
262 { 1, 6, 21, 36, 36, 21, 6, 1 },
263 { 1, 6, 20, 35, 36, 22, 7, 1 },
264 { 0, 5, 19, 34, 37, 24, 8, 1 },
265 { 0, 5, 18, 34, 37, 24, 9, 1 },
266 { 0, 4, 17, 33, 37, 26, 10, 1 },
267 { 0, 4, 16, 32, 38, 26, 10, 2 },
268 { 0, 3, 15, 31, 38, 28, 11, 2 },
269 { 0, 3, 14, 30, 38, 29, 12, 2 }
270 }
271};
272
273/* 4-tap Filter Coefficient */
274static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
275 { /* Ratio <= 65536 (~8:8) */
276 { 0, 128, 0, 0 },
277 { -4, 127, 5, 0 },
278 { -6, 124, 11, -1 },
279 { -8, 118, 19, -1 },
280 { -8, 111, 27, -2 },
281 { -8, 102, 37, -3 },
282 { -8, 92, 48, -4 },
283 { -7, 81, 59, -5 },
284 { -6, 70, 70, -6 },
285 { -5, 59, 81, -7 },
286 { -4, 48, 92, -8 },
287 { -3, 37, 102, -8 },
288 { -2, 27, 111, -8 },
289 { -1, 19, 118, -8 },
290 { -1, 11, 124, -6 },
291 { 0, 5, 127, -4 }
292 }, { /* 65536 < Ratio <= 74898 (~8:7) */
293 { 8, 112, 8, 0 },
294 { 4, 111, 14, -1 },
295 { 1, 109, 20, -2 },
296 { -2, 105, 27, -2 },
297 { -3, 100, 34, -3 },
298 { -5, 93, 43, -3 },
299 { -5, 86, 51, -4 },
300 { -5, 77, 60, -4 },
301 { -5, 69, 69, -5 },
302 { -4, 60, 77, -5 },
303 { -4, 51, 86, -5 },
304 { -3, 43, 93, -5 },
305 { -3, 34, 100, -3 },
306 { -2, 27, 105, -2 },
307 { -2, 20, 109, 1 },
308 { -1, 14, 111, 4 }
309 }, { /* 74898 < Ratio <= 87381 (~8:6) */
310 { 16, 96, 16, 0 },
311 { 12, 97, 21, -2 },
312 { 8, 96, 26, -2 },
313 { 5, 93, 32, -2 },
314 { 2, 89, 39, -2 },
315 { 0, 84, 46, -2 },
316 { -1, 79, 53, -3 },
317 { -2, 73, 59, -2 },
318 { -2, 66, 66, -2 },
319 { -2, 59, 73, -2 },
320 { -3, 53, 79, -1 },
321 { -2, 46, 84, 0 },
322 { -2, 39, 89, 2 },
323 { -2, 32, 93, 5 },
324 { -2, 26, 96, 8 },
325 { -2, 21, 97, 12 }
326 }, { /* 87381 < Ratio <= 104857 (~8:5) */
327 { 22, 84, 22, 0 },
328 { 18, 85, 26, -1 },
329 { 14, 84, 31, -1 },
330 { 11, 82, 36, -1 },
331 { 8, 79, 42, -1 },
332 { 6, 76, 47, -1 },
333 { 4, 72, 52, 0 },
334 { 2, 68, 58, 0 },
335 { 1, 63, 63, 1 },
336 { 0, 58, 68, 2 },
337 { 0, 52, 72, 4 },
338 { -1, 47, 76, 6 },
339 { -1, 42, 79, 8 },
340 { -1, 36, 82, 11 },
341 { -1, 31, 84, 14 },
342 { -1, 26, 85, 18 }
343 }, { /* 104857 < Ratio <= 131072 (~8:4) */
344 { 26, 76, 26, 0 },
345 { 22, 76, 30, 0 },
346 { 19, 75, 34, 0 },
347 { 16, 73, 38, 1 },
348 { 13, 71, 43, 1 },
349 { 10, 69, 47, 2 },
350 { 8, 66, 51, 3 },
351 { 6, 63, 55, 4 },
352 { 5, 59, 59, 5 },
353 { 4, 55, 63, 6 },
354 { 3, 51, 66, 8 },
355 { 2, 47, 69, 10 },
356 { 1, 43, 71, 13 },
357 { 1, 38, 73, 16 },
358 { 0, 34, 75, 19 },
359 { 0, 30, 76, 22 }
360 }, { /* 131072 < Ratio <= 174762 (~8:3) */
361 { 29, 70, 29, 0 },
362 { 26, 68, 32, 2 },
363 { 23, 67, 36, 2 },
364 { 20, 66, 39, 3 },
365 { 17, 65, 43, 3 },
366 { 15, 63, 46, 4 },
367 { 12, 61, 50, 5 },
368 { 10, 58, 53, 7 },
369 { 8, 56, 56, 8 },
370 { 7, 53, 58, 10 },
371 { 5, 50, 61, 12 },
372 { 4, 46, 63, 15 },
373 { 3, 43, 65, 17 },
374 { 3, 39, 66, 20 },
375 { 2, 36, 67, 23 },
376 { 2, 32, 68, 26 }
377 }, { /* 174762 < Ratio <= 262144 (~8:2) */
378 { 32, 64, 32, 0 },
379 { 28, 63, 34, 3 },
380 { 25, 62, 37, 4 },
381 { 22, 62, 40, 4 },
382 { 19, 61, 43, 5 },
383 { 17, 59, 46, 6 },
384 { 15, 58, 48, 7 },
385 { 13, 55, 51, 9 },
386 { 11, 53, 53, 11 },
387 { 9, 51, 55, 13 },
388 { 7, 48, 58, 15 },
389 { 6, 46, 59, 17 },
390 { 5, 43, 61, 19 },
391 { 4, 40, 62, 22 },
392 { 4, 37, 62, 25 },
393 { 3, 34, 63, 28 }
394 }
395};
396
397static int gsc_sw_reset(struct gsc_context *ctx)
398{
399 u32 cfg;
400 int count = GSC_RESET_TIMEOUT;
401
f2646380
EK		 402 /* s/w reset */
403 cfg = (GSC_SW_RESET_SRESET);
404 gsc_write(cfg, GSC_SW_RESET);
405
406 /* wait s/w reset complete */
407 while (count--) {
408 cfg = gsc_read(GSC_SW_RESET);
409 if (!cfg)
410 break;
411 usleep_range(1000, 2000);
412 }
413
414 if (cfg) {
415 DRM_ERROR("failed to reset gsc h/w.\n");
416 return -EBUSY;
417 }
418
419 /* reset sequence */
420 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
421 cfg |= (GSC_IN_BASE_ADDR_MASK |
422 GSC_IN_BASE_ADDR_PINGPONG(0));
423 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
424 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
425 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
426
427 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
428 cfg |= (GSC_OUT_BASE_ADDR_MASK |
429 GSC_OUT_BASE_ADDR_PINGPONG(0));
430 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
431 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
432 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
433
434 return 0;
435}
436
437static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable)
438{
439 u32 gscblk_cfg;
440
f2646380
EK		 441 gscblk_cfg = readl(SYSREG_GSCBLK_CFG1);
442
443 if (enable)
444 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |
445 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |
446 GSC_BLK_SW_RESET_WB_DEST(ctx->id);
447 else
448 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);
449
450 writel(gscblk_cfg, SYSREG_GSCBLK_CFG1);
451}
452
453static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
454 bool overflow, bool done)
455{
456 u32 cfg;
457
cbc4c33d 458 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
f2646380
EK		 459 enable, overflow, done);
460
461 cfg = gsc_read(GSC_IRQ);
462 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
463
464 if (enable)
465 cfg |= GSC_IRQ_ENABLE;
466 else
467 cfg &= ~GSC_IRQ_ENABLE;
468
469 if (overflow)
470 cfg &= ~GSC_IRQ_OR_MASK;
471 else
472 cfg |= GSC_IRQ_OR_MASK;
473
474 if (done)
475 cfg &= ~GSC_IRQ_FRMDONE_MASK;
476 else
477 cfg |= GSC_IRQ_FRMDONE_MASK;
478
479 gsc_write(cfg, GSC_IRQ);
480}
481
482
483static int gsc_src_set_fmt(struct device *dev, u32 fmt)
484{
485 struct gsc_context *ctx = get_gsc_context(dev);
486 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
487 u32 cfg;
488
cbc4c33d 489 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
f2646380
EK		 490
491 cfg = gsc_read(GSC_IN_CON);
492 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
493 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
494 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
495 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
496
497 switch (fmt) {
498 case DRM_FORMAT_RGB565:
499 cfg |= GSC_IN_RGB565;
500 break;
501 case DRM_FORMAT_XRGB8888:
502 cfg |= GSC_IN_XRGB8888;
503 break;
504 case DRM_FORMAT_BGRX8888:
505 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
506 break;
507 case DRM_FORMAT_YUYV:
508 cfg |= (GSC_IN_YUV422_1P |
509 GSC_IN_YUV422_1P_ORDER_LSB_Y |
510 GSC_IN_CHROMA_ORDER_CBCR);
511 break;
512 case DRM_FORMAT_YVYU:
513 cfg |= (GSC_IN_YUV422_1P |
514 GSC_IN_YUV422_1P_ORDER_LSB_Y |
515 GSC_IN_CHROMA_ORDER_CRCB);
516 break;
517 case DRM_FORMAT_UYVY:
518 cfg |= (GSC_IN_YUV422_1P |
519 GSC_IN_YUV422_1P_OEDER_LSB_C |
520 GSC_IN_CHROMA_ORDER_CBCR);
521 break;
522 case DRM_FORMAT_VYUY:
523 cfg |= (GSC_IN_YUV422_1P |
524 GSC_IN_YUV422_1P_OEDER_LSB_C |
525 GSC_IN_CHROMA_ORDER_CRCB);
526 break;
527 case DRM_FORMAT_NV21:
528 case DRM_FORMAT_NV61:
529 cfg |= (GSC_IN_CHROMA_ORDER_CRCB |
530 GSC_IN_YUV420_2P);
531 break;
532 case DRM_FORMAT_YUV422:
533 cfg |= GSC_IN_YUV422_3P;
534 break;
535 case DRM_FORMAT_YUV420:
536 case DRM_FORMAT_YVU420:
537 cfg |= GSC_IN_YUV420_3P;
538 break;
539 case DRM_FORMAT_NV12:
540 case DRM_FORMAT_NV16:
541 cfg |= (GSC_IN_CHROMA_ORDER_CBCR |
542 GSC_IN_YUV420_2P);
543 break;
544 case DRM_FORMAT_NV12MT:
545 cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
546 break;
547 default:
548 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
549 return -EINVAL;
550 }
551
552 gsc_write(cfg, GSC_IN_CON);
553
554 return 0;
555}
556
557static int gsc_src_set_transf(struct device *dev,
558 enum drm_exynos_degree degree,
559 enum drm_exynos_flip flip, bool *swap)
560{
561 struct gsc_context *ctx = get_gsc_context(dev);
562 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
563 u32 cfg;
564
cbc4c33d 565 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
f2646380
EK		 566
567 cfg = gsc_read(GSC_IN_CON);
568 cfg &= ~GSC_IN_ROT_MASK;
569
570 switch (degree) {
571 case EXYNOS_DRM_DEGREE_0:
572 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
573 cfg |= GSC_IN_ROT_XFLIP;
574 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
575 cfg |= GSC_IN_ROT_YFLIP;
576 break;
577 case EXYNOS_DRM_DEGREE_90:
578 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
579 cfg |= GSC_IN_ROT_90_XFLIP;
580 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
581 cfg |= GSC_IN_ROT_90_YFLIP;
582 else
583 cfg |= GSC_IN_ROT_90;
584 break;
585 case EXYNOS_DRM_DEGREE_180:
586 cfg |= GSC_IN_ROT_180;
587 break;
588 case EXYNOS_DRM_DEGREE_270:
589 cfg |= GSC_IN_ROT_270;
590 break;
591 default:
592 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
593 return -EINVAL;
594 }
595
596 gsc_write(cfg, GSC_IN_CON);
597
598 ctx->rotation = cfg &
599 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
600 *swap = ctx->rotation;
601
602 return 0;
603}
604
605static int gsc_src_set_size(struct device *dev, int swap,
606 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
607{
608 struct gsc_context *ctx = get_gsc_context(dev);
609 struct drm_exynos_pos img_pos = *pos;
610 struct gsc_scaler *sc = &ctx->sc;
611 u32 cfg;
612
cbc4c33d
YC		 613 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
614 swap, pos->x, pos->y, pos->w, pos->h);
f2646380
EK		 615
616 if (swap) {
617 img_pos.w = pos->h;
618 img_pos.h = pos->w;
619 }
620
621 /* pixel offset */
622 cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
623 GSC_SRCIMG_OFFSET_Y(img_pos.y));
624 gsc_write(cfg, GSC_SRCIMG_OFFSET);
625
626 /* cropped size */
627 cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
628 GSC_CROPPED_HEIGHT(img_pos.h));
629 gsc_write(cfg, GSC_CROPPED_SIZE);
630
cbc4c33d 631 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
f2646380
EK		 632
633 /* original size */
634 cfg = gsc_read(GSC_SRCIMG_SIZE);
635 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
636 GSC_SRCIMG_WIDTH_MASK);
637
638 cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
639 GSC_SRCIMG_HEIGHT(sz->vsize));
640
641 gsc_write(cfg, GSC_SRCIMG_SIZE);
642
643 cfg = gsc_read(GSC_IN_CON);
644 cfg &= ~GSC_IN_RGB_TYPE_MASK;
645
cbc4c33d 646 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
f2646380
EK		 647
648 if (pos->w >= GSC_WIDTH_ITU_709)
649 if (sc->range)
650 cfg |= GSC_IN_RGB_HD_WIDE;
651 else
652 cfg |= GSC_IN_RGB_HD_NARROW;
653 else
654 if (sc->range)
655 cfg |= GSC_IN_RGB_SD_WIDE;
656 else
657 cfg |= GSC_IN_RGB_SD_NARROW;
658
659 gsc_write(cfg, GSC_IN_CON);
660
661 return 0;
662}
663
664static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
665 enum drm_exynos_ipp_buf_type buf_type)
666{
667 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
668 bool masked;
669 u32 cfg;
670 u32 mask = 0x00000001 << buf_id;
671
cbc4c33d 672 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
f2646380
EK		 673
674 /* mask register set */
675 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
676
677 switch (buf_type) {
678 case IPP_BUF_ENQUEUE:
679 masked = false;
680 break;
681 case IPP_BUF_DEQUEUE:
682 masked = true;
683 break;
684 default:
685 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
686 return -EINVAL;
687 }
688
689 /* sequence id */
690 cfg &= ~mask;
691 cfg |= masked << buf_id;
692 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
693 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
694 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
695
696 return 0;
697}
698
699static int gsc_src_set_addr(struct device *dev,
700 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
701 enum drm_exynos_ipp_buf_type buf_type)
702{
703 struct gsc_context *ctx = get_gsc_context(dev);
704 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
7259c3d6 705 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
f2646380
EK		 706 struct drm_exynos_ipp_property *property;
707
708 if (!c_node) {
709 DRM_ERROR("failed to get c_node.\n");
710 return -EFAULT;
711 }
712
713 property = &c_node->property;
f2646380 714
cbc4c33d 715 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
f2646380
EK		 716 property->prop_id, buf_id, buf_type);
717
718 if (buf_id > GSC_MAX_SRC) {
719 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
720 return -EINVAL;
721 }
722
723 /* address register set */
724 switch (buf_type) {
725 case IPP_BUF_ENQUEUE:
726 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
727 GSC_IN_BASE_ADDR_Y(buf_id));
728 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
729 GSC_IN_BASE_ADDR_CB(buf_id));
730 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
731 GSC_IN_BASE_ADDR_CR(buf_id));
732 break;
733 case IPP_BUF_DEQUEUE:
734 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
735 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
736 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
737 break;
738 default:
739 /* bypass */
740 break;
741 }
742
743 return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
744}
745
746static struct exynos_drm_ipp_ops gsc_src_ops = {
747 .set_fmt = gsc_src_set_fmt,
748 .set_transf = gsc_src_set_transf,
749 .set_size = gsc_src_set_size,
750 .set_addr = gsc_src_set_addr,
751};
752
753static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
754{
755 struct gsc_context *ctx = get_gsc_context(dev);
756 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
757 u32 cfg;
758
cbc4c33d 759 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
f2646380
EK		 760
761 cfg = gsc_read(GSC_OUT_CON);
762 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
763 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
764 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
765 GSC_OUT_GLOBAL_ALPHA_MASK);
766
767 switch (fmt) {
768 case DRM_FORMAT_RGB565:
769 cfg |= GSC_OUT_RGB565;
770 break;
771 case DRM_FORMAT_XRGB8888:
772 cfg |= GSC_OUT_XRGB8888;
773 break;
774 case DRM_FORMAT_BGRX8888:
775 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
776 break;
777 case DRM_FORMAT_YUYV:
778 cfg |= (GSC_OUT_YUV422_1P |
779 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
780 GSC_OUT_CHROMA_ORDER_CBCR);
781 break;
782 case DRM_FORMAT_YVYU:
783 cfg |= (GSC_OUT_YUV422_1P |
784 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
785 GSC_OUT_CHROMA_ORDER_CRCB);
786 break;
787 case DRM_FORMAT_UYVY:
788 cfg |= (GSC_OUT_YUV422_1P |
789 GSC_OUT_YUV422_1P_OEDER_LSB_C |
790 GSC_OUT_CHROMA_ORDER_CBCR);
791 break;
792 case DRM_FORMAT_VYUY:
793 cfg |= (GSC_OUT_YUV422_1P |
794 GSC_OUT_YUV422_1P_OEDER_LSB_C |
795 GSC_OUT_CHROMA_ORDER_CRCB);
796 break;
797 case DRM_FORMAT_NV21:
798 case DRM_FORMAT_NV61:
799 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
800 break;
801 case DRM_FORMAT_YUV422:
802 case DRM_FORMAT_YUV420:
803 case DRM_FORMAT_YVU420:
804 cfg |= GSC_OUT_YUV420_3P;
805 break;
806 case DRM_FORMAT_NV12:
807 case DRM_FORMAT_NV16:
808 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |
809 GSC_OUT_YUV420_2P);
810 break;
811 case DRM_FORMAT_NV12MT:
812 cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE);
813 break;
814 default:
815 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
816 return -EINVAL;
817 }
818
819 gsc_write(cfg, GSC_OUT_CON);
820
821 return 0;
822}
823
824static int gsc_dst_set_transf(struct device *dev,
825 enum drm_exynos_degree degree,
826 enum drm_exynos_flip flip, bool *swap)
827{
828 struct gsc_context *ctx = get_gsc_context(dev);
829 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
830 u32 cfg;
831
cbc4c33d 832 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
f2646380
EK		 833
834 cfg = gsc_read(GSC_IN_CON);
835 cfg &= ~GSC_IN_ROT_MASK;
836
837 switch (degree) {
838 case EXYNOS_DRM_DEGREE_0:
839 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
840 cfg |= GSC_IN_ROT_XFLIP;
841 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
842 cfg |= GSC_IN_ROT_YFLIP;
843 break;
844 case EXYNOS_DRM_DEGREE_90:
845 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
846 cfg |= GSC_IN_ROT_90_XFLIP;
847 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
848 cfg |= GSC_IN_ROT_90_YFLIP;
849 else
850 cfg |= GSC_IN_ROT_90;
851 break;
852 case EXYNOS_DRM_DEGREE_180:
853 cfg |= GSC_IN_ROT_180;
854 break;
855 case EXYNOS_DRM_DEGREE_270:
856 cfg |= GSC_IN_ROT_270;
857 break;
858 default:
859 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
860 return -EINVAL;
861 }
862
863 gsc_write(cfg, GSC_IN_CON);
864
865 ctx->rotation = cfg &
866 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
867 *swap = ctx->rotation;
868
869 return 0;
870}
871
872static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
873{
cbc4c33d 874 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
f2646380
EK		 875
876 if (src >= dst * 8) {
877 DRM_ERROR("failed to make ratio and shift.\n");
878 return -EINVAL;
879 } else if (src >= dst * 4)
880 *ratio = 4;
881 else if (src >= dst * 2)
882 *ratio = 2;
883 else
884 *ratio = 1;
885
886 return 0;
887}
888
889static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
890{
891 if (hratio == 4 && vratio == 4)
892 *shfactor = 4;
893 else if ((hratio == 4 && vratio == 2) ||
894 (hratio == 2 && vratio == 4))
895 *shfactor = 3;
896 else if ((hratio == 4 && vratio == 1) ||
897 (hratio == 1 && vratio == 4) ||
898 (hratio == 2 && vratio == 2))
899 *shfactor = 2;
900 else if (hratio == 1 && vratio == 1)
901 *shfactor = 0;
902 else
903 *shfactor = 1;
904}
905
906static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
907 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
908{
909 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
910 u32 cfg;
911 u32 src_w, src_h, dst_w, dst_h;
912 int ret = 0;
913
914 src_w = src->w;
915 src_h = src->h;
916
917 if (ctx->rotation) {
918 dst_w = dst->h;
919 dst_h = dst->w;
920 } else {
921 dst_w = dst->w;
922 dst_h = dst->h;
923 }
924
925 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
926 if (ret) {
927 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
928 return ret;
929 }
930
931 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
932 if (ret) {
933 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
934 return ret;
935 }
936
cbc4c33d
YC		 937 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n",
938 sc->pre_hratio, sc->pre_vratio);
f2646380
EK		 939
940 sc->main_hratio = (src_w << 16) / dst_w;
941 sc->main_vratio = (src_h << 16) / dst_h;
942
cbc4c33d
YC		 943 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
944 sc->main_hratio, sc->main_vratio);
f2646380
EK		 945
946 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
947 &sc->pre_shfactor);
948
cbc4c33d 949 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor);
f2646380
EK		 950
951 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
952 GSC_PRESC_H_RATIO(sc->pre_hratio) |
953 GSC_PRESC_V_RATIO(sc->pre_vratio));
954 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
955
956 return ret;
957}
958
959static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
960{
961 int i, j, k, sc_ratio;
962
963 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
964 sc_ratio = 0;
965 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
966 sc_ratio = 1;
967 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
968 sc_ratio = 2;
969 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
970 sc_ratio = 3;
971 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
972 sc_ratio = 4;
973 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
974 sc_ratio = 5;
975 else
976 sc_ratio = 6;
977
978 for (i = 0; i < GSC_COEF_PHASE; i++)
979 for (j = 0; j < GSC_COEF_H_8T; j++)
980 for (k = 0; k < GSC_COEF_DEPTH; k++)
981 gsc_write(h_coef_8t[sc_ratio][i][j],
982 GSC_HCOEF(i, j, k));
983}
984
985static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
986{
987 int i, j, k, sc_ratio;
988
989 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
990 sc_ratio = 0;
991 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
992 sc_ratio = 1;
993 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
994 sc_ratio = 2;
995 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
996 sc_ratio = 3;
997 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
998 sc_ratio = 4;
999 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
1000 sc_ratio = 5;
1001 else
1002 sc_ratio = 6;
1003
1004 for (i = 0; i < GSC_COEF_PHASE; i++)
1005 for (j = 0; j < GSC_COEF_V_4T; j++)
1006 for (k = 0; k < GSC_COEF_DEPTH; k++)
1007 gsc_write(v_coef_4t[sc_ratio][i][j],
1008 GSC_VCOEF(i, j, k));
1009}
1010
1011static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
1012{
1013 u32 cfg;
1014
cbc4c33d
YC		 1015 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
1016 sc->main_hratio, sc->main_vratio);
f2646380
EK		 1017
1018 gsc_set_h_coef(ctx, sc->main_hratio);
1019 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
1020 gsc_write(cfg, GSC_MAIN_H_RATIO);
1021
1022 gsc_set_v_coef(ctx, sc->main_vratio);
1023 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
1024 gsc_write(cfg, GSC_MAIN_V_RATIO);
1025}
1026
1027static int gsc_dst_set_size(struct device *dev, int swap,
1028 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1029{
1030 struct gsc_context *ctx = get_gsc_context(dev);
1031 struct drm_exynos_pos img_pos = *pos;
1032 struct gsc_scaler *sc = &ctx->sc;
1033 u32 cfg;
1034
cbc4c33d
YC		 1035 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
1036 swap, pos->x, pos->y, pos->w, pos->h);
f2646380
EK		 1037
1038 if (swap) {
1039 img_pos.w = pos->h;
1040 img_pos.h = pos->w;
1041 }
1042
1043 /* pixel offset */
1044 cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
1045 GSC_DSTIMG_OFFSET_Y(pos->y));
1046 gsc_write(cfg, GSC_DSTIMG_OFFSET);
1047
1048 /* scaled size */
1049 cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
1050 gsc_write(cfg, GSC_SCALED_SIZE);
1051
cbc4c33d 1052 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
f2646380
EK		 1053
1054 /* original size */
1055 cfg = gsc_read(GSC_DSTIMG_SIZE);
1056 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
1057 GSC_DSTIMG_WIDTH_MASK);
1058 cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
1059 GSC_DSTIMG_HEIGHT(sz->vsize));
1060 gsc_write(cfg, GSC_DSTIMG_SIZE);
1061
1062 cfg = gsc_read(GSC_OUT_CON);
1063 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
1064
cbc4c33d 1065 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
f2646380
EK		 1066
1067 if (pos->w >= GSC_WIDTH_ITU_709)
1068 if (sc->range)
1069 cfg |= GSC_OUT_RGB_HD_WIDE;
1070 else
1071 cfg |= GSC_OUT_RGB_HD_NARROW;
1072 else
1073 if (sc->range)
1074 cfg |= GSC_OUT_RGB_SD_WIDE;
1075 else
1076 cfg |= GSC_OUT_RGB_SD_NARROW;
1077
1078 gsc_write(cfg, GSC_OUT_CON);
1079
1080 return 0;
1081}
1082
1083static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
1084{
1085 u32 cfg, i, buf_num = GSC_REG_SZ;
1086 u32 mask = 0x00000001;
1087
1088 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1089
1090 for (i = 0; i < GSC_REG_SZ; i++)
1091 if (cfg & (mask << i))
1092 buf_num--;
1093
cbc4c33d 1094 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
f2646380
EK		 1095
1096 return buf_num;
1097}
1098
1099static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
1100 enum drm_exynos_ipp_buf_type buf_type)
1101{
1102 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1103 bool masked;
1104 u32 cfg;
1105 u32 mask = 0x00000001 << buf_id;
1106 int ret = 0;
1107
cbc4c33d 1108 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
f2646380
EK		 1109
1110 mutex_lock(&ctx->lock);
1111
1112 /* mask register set */
1113 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1114
1115 switch (buf_type) {
1116 case IPP_BUF_ENQUEUE:
1117 masked = false;
1118 break;
1119 case IPP_BUF_DEQUEUE:
1120 masked = true;
1121 break;
1122 default:
1123 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1124 ret = -EINVAL;
1125 goto err_unlock;
1126 }
1127
1128 /* sequence id */
1129 cfg &= ~mask;
1130 cfg |= masked << buf_id;
1131 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
1132 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
1133 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
1134
1135 /* interrupt enable */
1136 if (buf_type == IPP_BUF_ENQUEUE &&
1137 gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
1138 gsc_handle_irq(ctx, true, false, true);
1139
1140 /* interrupt disable */
1141 if (buf_type == IPP_BUF_DEQUEUE &&
1142 gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
1143 gsc_handle_irq(ctx, false, false, true);
1144
1145err_unlock:
1146 mutex_unlock(&ctx->lock);
1147 return ret;
1148}
1149
1150static int gsc_dst_set_addr(struct device *dev,
1151 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1152 enum drm_exynos_ipp_buf_type buf_type)
1153{
1154 struct gsc_context *ctx = get_gsc_context(dev);
1155 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
7259c3d6 1156 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
f2646380
EK		 1157 struct drm_exynos_ipp_property *property;
1158
1159 if (!c_node) {
1160 DRM_ERROR("failed to get c_node.\n");
1161 return -EFAULT;
1162 }
1163
1164 property = &c_node->property;
f2646380 1165
cbc4c33d 1166 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
f2646380
EK		 1167 property->prop_id, buf_id, buf_type);
1168
1169 if (buf_id > GSC_MAX_DST) {
1170 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1171 return -EINVAL;
1172 }
1173
1174 /* address register set */
1175 switch (buf_type) {
1176 case IPP_BUF_ENQUEUE:
1177 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1178 GSC_OUT_BASE_ADDR_Y(buf_id));
1179 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1180 GSC_OUT_BASE_ADDR_CB(buf_id));
1181 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1182 GSC_OUT_BASE_ADDR_CR(buf_id));
1183 break;
1184 case IPP_BUF_DEQUEUE:
1185 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
1186 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
1187 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
1188 break;
1189 default:
1190 /* bypass */
1191 break;
1192 }
1193
1194 return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
1195}
1196
1197static struct exynos_drm_ipp_ops gsc_dst_ops = {
1198 .set_fmt = gsc_dst_set_fmt,
1199 .set_transf = gsc_dst_set_transf,
1200 .set_size = gsc_dst_set_size,
1201 .set_addr = gsc_dst_set_addr,
1202};
1203
1204static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable)
1205{
cbc4c33d 1206 DRM_DEBUG_KMS("enable[%d]\n", enable);
f2646380
EK		 1207
1208 if (enable) {
1209 clk_enable(ctx->gsc_clk);
1210 ctx->suspended = false;
1211 } else {
1212 clk_disable(ctx->gsc_clk);
1213 ctx->suspended = true;
1214 }
1215
1216 return 0;
1217}
1218
1219static int gsc_get_src_buf_index(struct gsc_context *ctx)
1220{
1221 u32 cfg, curr_index, i;
1222 u32 buf_id = GSC_MAX_SRC;
1223 int ret;
1224
cbc4c33d 1225 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
f2646380
EK		 1226
1227 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
1228 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
1229
1230 for (i = curr_index; i < GSC_MAX_SRC; i++) {
1231 if (!((cfg >> i) & 0x1)) {
1232 buf_id = i;
1233 break;
1234 }
1235 }
1236
1237 if (buf_id == GSC_MAX_SRC) {
1238 DRM_ERROR("failed to get in buffer index.\n");
1239 return -EINVAL;
1240 }
1241
1242 ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1243 if (ret < 0) {
1244 DRM_ERROR("failed to dequeue.\n");
1245 return ret;
1246 }
1247
cbc4c33d 1248 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
f2646380
EK		 1249 curr_index, buf_id);
1250
1251 return buf_id;
1252}
1253
1254static int gsc_get_dst_buf_index(struct gsc_context *ctx)
1255{
1256 u32 cfg, curr_index, i;
1257 u32 buf_id = GSC_MAX_DST;
1258 int ret;
1259
cbc4c33d 1260 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
f2646380
EK		 1261
1262 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1263 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1264
1265 for (i = curr_index; i < GSC_MAX_DST; i++) {
1266 if (!((cfg >> i) & 0x1)) {
1267 buf_id = i;
1268 break;
1269 }
1270 }
1271
1272 if (buf_id == GSC_MAX_DST) {
1273 DRM_ERROR("failed to get out buffer index.\n");
1274 return -EINVAL;
1275 }
1276
1277 ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1278 if (ret < 0) {
1279 DRM_ERROR("failed to dequeue.\n");
1280 return ret;
1281 }
1282
cbc4c33d 1283 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
f2646380
EK		 1284 curr_index, buf_id);
1285
1286 return buf_id;
1287}
1288
1289static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1290{
1291 struct gsc_context *ctx = dev_id;
1292 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
7259c3d6 1293 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
f2646380
EK		 1294 struct drm_exynos_ipp_event_work *event_work =
1295 c_node->event_work;
1296 u32 status;
1297 int buf_id[EXYNOS_DRM_OPS_MAX];
1298
cbc4c33d 1299 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
f2646380
EK		 1300
1301 status = gsc_read(GSC_IRQ);
1302 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1303 dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n",
1304 ctx->id, status);
1305 return IRQ_NONE;
1306 }
1307
1308 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1309 dev_dbg(ippdrv->dev, "occured frame done at %d, status 0x%x.\n",
1310 ctx->id, status);
1311
1312 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);
1313 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)
1314 return IRQ_HANDLED;
1315
1316 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);
1317 if (buf_id[EXYNOS_DRM_OPS_DST] < 0)
1318 return IRQ_HANDLED;
1319
cbc4c33d 1320 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n",
f2646380
EK		 1321 buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);
1322
1323 event_work->ippdrv = ippdrv;
1324 event_work->buf_id[EXYNOS_DRM_OPS_SRC] =
1325 buf_id[EXYNOS_DRM_OPS_SRC];
1326 event_work->buf_id[EXYNOS_DRM_OPS_DST] =
1327 buf_id[EXYNOS_DRM_OPS_DST];
1328 queue_work(ippdrv->event_workq,
1329 (struct work_struct *)event_work);
1330 }
1331
1332 return IRQ_HANDLED;
1333}
1334
1335static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1336{
1337 struct drm_exynos_ipp_prop_list *prop_list;
1338
f2646380
EK		 1339 prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL);
1340 if (!prop_list) {
1341 DRM_ERROR("failed to alloc property list.\n");
1342 return -ENOMEM;
1343 }
1344
1345 prop_list->version = 1;
1346 prop_list->writeback = 1;
1347 prop_list->refresh_min = GSC_REFRESH_MIN;
1348 prop_list->refresh_max = GSC_REFRESH_MAX;
1349 prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1350 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1351 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1352 (1 << EXYNOS_DRM_DEGREE_90) |
1353 (1 << EXYNOS_DRM_DEGREE_180) |
1354 (1 << EXYNOS_DRM_DEGREE_270);
1355 prop_list->csc = 1;
1356 prop_list->crop = 1;
1357 prop_list->crop_max.hsize = GSC_CROP_MAX;
1358 prop_list->crop_max.vsize = GSC_CROP_MAX;
1359 prop_list->crop_min.hsize = GSC_CROP_MIN;
1360 prop_list->crop_min.vsize = GSC_CROP_MIN;
1361 prop_list->scale = 1;
1362 prop_list->scale_max.hsize = GSC_SCALE_MAX;
1363 prop_list->scale_max.vsize = GSC_SCALE_MAX;
1364 prop_list->scale_min.hsize = GSC_SCALE_MIN;
1365 prop_list->scale_min.vsize = GSC_SCALE_MIN;
1366
1367 ippdrv->prop_list = prop_list;
1368
1369 return 0;
1370}
1371
1372static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
1373{
1374 switch (flip) {
1375 case EXYNOS_DRM_FLIP_NONE:
1376 case EXYNOS_DRM_FLIP_VERTICAL:
1377 case EXYNOS_DRM_FLIP_HORIZONTAL:
4f21877c 1378 case EXYNOS_DRM_FLIP_BOTH:
f2646380
EK		 1379 return true;
1380 default:
cbc4c33d 1381 DRM_DEBUG_KMS("invalid flip\n");
f2646380
EK		 1382 return false;
1383 }
1384}
1385
1386static int gsc_ippdrv_check_property(struct device *dev,
1387 struct drm_exynos_ipp_property *property)
1388{
1389 struct gsc_context *ctx = get_gsc_context(dev);
1390 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1391 struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list;
1392 struct drm_exynos_ipp_config *config;
1393 struct drm_exynos_pos *pos;
1394 struct drm_exynos_sz *sz;
1395 bool swap;
1396 int i;
1397
f2646380
EK		 1398 for_each_ipp_ops(i) {
1399 if ((i == EXYNOS_DRM_OPS_SRC) &&
1400 (property->cmd == IPP_CMD_WB))
1401 continue;
1402
1403 config = &property->config[i];
1404 pos = &config->pos;
1405 sz = &config->sz;
1406
1407 /* check for flip */
1408 if (!gsc_check_drm_flip(config->flip)) {
1409 DRM_ERROR("invalid flip.\n");
1410 goto err_property;
1411 }
1412
1413 /* check for degree */
1414 switch (config->degree) {
1415 case EXYNOS_DRM_DEGREE_90:
1416 case EXYNOS_DRM_DEGREE_270:
1417 swap = true;
1418 break;
1419 case EXYNOS_DRM_DEGREE_0:
1420 case EXYNOS_DRM_DEGREE_180:
1421 swap = false;
1422 break;
1423 default:
1424 DRM_ERROR("invalid degree.\n");
1425 goto err_property;
1426 }
1427
1428 /* check for buffer bound */
1429 if ((pos->x + pos->w > sz->hsize) ||
1430 (pos->y + pos->h > sz->vsize)) {
1431 DRM_ERROR("out of buf bound.\n");
1432 goto err_property;
1433 }
1434
1435 /* check for crop */
1436 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1437 if (swap) {
1438 if ((pos->h < pp->crop_min.hsize) ||
1439 (sz->vsize > pp->crop_max.hsize) ||
1440 (pos->w < pp->crop_min.vsize) ||
1441 (sz->hsize > pp->crop_max.vsize)) {
1442 DRM_ERROR("out of crop size.\n");
1443 goto err_property;
1444 }
1445 } else {
1446 if ((pos->w < pp->crop_min.hsize) ||
1447 (sz->hsize > pp->crop_max.hsize) ||
1448 (pos->h < pp->crop_min.vsize) ||
1449 (sz->vsize > pp->crop_max.vsize)) {
1450 DRM_ERROR("out of crop size.\n");
1451 goto err_property;
1452 }
1453 }
1454 }
1455
1456 /* check for scale */
1457 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1458 if (swap) {
1459 if ((pos->h < pp->scale_min.hsize) ||
1460 (sz->vsize > pp->scale_max.hsize) ||
1461 (pos->w < pp->scale_min.vsize) ||
1462 (sz->hsize > pp->scale_max.vsize)) {
1463 DRM_ERROR("out of scale size.\n");
1464 goto err_property;
1465 }
1466 } else {
1467 if ((pos->w < pp->scale_min.hsize) ||
1468 (sz->hsize > pp->scale_max.hsize) ||
1469 (pos->h < pp->scale_min.vsize) ||
1470 (sz->vsize > pp->scale_max.vsize)) {
1471 DRM_ERROR("out of scale size.\n");
1472 goto err_property;
1473 }
1474 }
1475 }
1476 }
1477
1478 return 0;
1479
1480err_property:
1481 for_each_ipp_ops(i) {
1482 if ((i == EXYNOS_DRM_OPS_SRC) &&
1483 (property->cmd == IPP_CMD_WB))
1484 continue;
1485
1486 config = &property->config[i];
1487 pos = &config->pos;
1488 sz = &config->sz;
1489
1490 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1491 i ? "dst" : "src", config->flip, config->degree,
1492 pos->x, pos->y, pos->w, pos->h,
1493 sz->hsize, sz->vsize);
1494 }
1495
1496 return -EINVAL;
1497}
1498
1499
1500static int gsc_ippdrv_reset(struct device *dev)
1501{
1502 struct gsc_context *ctx = get_gsc_context(dev);
1503 struct gsc_scaler *sc = &ctx->sc;
1504 int ret;
1505
f2646380
EK		 1506 /* reset h/w block */
1507 ret = gsc_sw_reset(ctx);
1508 if (ret < 0) {
1509 dev_err(dev, "failed to reset hardware.\n");
1510 return ret;
1511 }
1512
1513 /* scaler setting */
1514 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1515 sc->range = true;
1516
1517 return 0;
1518}
1519
1520static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1521{
1522 struct gsc_context *ctx = get_gsc_context(dev);
1523 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
7259c3d6 1524 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
f2646380
EK		 1525 struct drm_exynos_ipp_property *property;
1526 struct drm_exynos_ipp_config *config;
1527 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1528 struct drm_exynos_ipp_set_wb set_wb;
1529 u32 cfg;
1530 int ret, i;
1531
cbc4c33d 1532 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
f2646380
EK		 1533
1534 if (!c_node) {
1535 DRM_ERROR("failed to get c_node.\n");
1536 return -EINVAL;
1537 }
1538
1539 property = &c_node->property;
f2646380
EK		 1540
1541 gsc_handle_irq(ctx, true, false, true);
1542
1543 for_each_ipp_ops(i) {
1544 config = &property->config[i];
1545 img_pos[i] = config->pos;
1546 }
1547
1548 switch (cmd) {
1549 case IPP_CMD_M2M:
1550 /* enable one shot */
1551 cfg = gsc_read(GSC_ENABLE);
1552 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1553 GSC_ENABLE_CLK_GATE_MODE_MASK);
1554 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1555 gsc_write(cfg, GSC_ENABLE);
1556
1557 /* src dma memory */
1558 cfg = gsc_read(GSC_IN_CON);
1559 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1560 cfg |= GSC_IN_PATH_MEMORY;
1561 gsc_write(cfg, GSC_IN_CON);
1562
1563 /* dst dma memory */
1564 cfg = gsc_read(GSC_OUT_CON);
1565 cfg |= GSC_OUT_PATH_MEMORY;
1566 gsc_write(cfg, GSC_OUT_CON);
1567 break;
1568 case IPP_CMD_WB:
1569 set_wb.enable = 1;
1570 set_wb.refresh = property->refresh_rate;
1571 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1572 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1573
1574 /* src local path */
5bbea0c4 1575 cfg = gsc_read(GSC_IN_CON);
f2646380
EK		 1576 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1577 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
1578 gsc_write(cfg, GSC_IN_CON);
1579
1580 /* dst dma memory */
1581 cfg = gsc_read(GSC_OUT_CON);
1582 cfg |= GSC_OUT_PATH_MEMORY;
1583 gsc_write(cfg, GSC_OUT_CON);
1584 break;
1585 case IPP_CMD_OUTPUT:
1586 /* src dma memory */
1587 cfg = gsc_read(GSC_IN_CON);
1588 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1589 cfg |= GSC_IN_PATH_MEMORY;
1590 gsc_write(cfg, GSC_IN_CON);
1591
1592 /* dst local path */
1593 cfg = gsc_read(GSC_OUT_CON);
1594 cfg |= GSC_OUT_PATH_MEMORY;
1595 gsc_write(cfg, GSC_OUT_CON);
1596 break;
1597 default:
1598 ret = -EINVAL;
1599 dev_err(dev, "invalid operations.\n");
1600 return ret;
1601 }
1602
1603 ret = gsc_set_prescaler(ctx, &ctx->sc,
1604 &img_pos[EXYNOS_DRM_OPS_SRC],
1605 &img_pos[EXYNOS_DRM_OPS_DST]);
1606 if (ret) {
1607 dev_err(dev, "failed to set precalser.\n");
1608 return ret;
1609 }
1610
1611 gsc_set_scaler(ctx, &ctx->sc);
1612
1613 cfg = gsc_read(GSC_ENABLE);
1614 cfg |= GSC_ENABLE_ON;
1615 gsc_write(cfg, GSC_ENABLE);
1616
1617 return 0;
1618}
1619
1620static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1621{
1622 struct gsc_context *ctx = get_gsc_context(dev);
1623 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1624 u32 cfg;
1625
cbc4c33d 1626 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
f2646380
EK		 1627
1628 switch (cmd) {
1629 case IPP_CMD_M2M:
1630 /* bypass */
1631 break;
1632 case IPP_CMD_WB:
1633 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1634 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1635 break;
1636 case IPP_CMD_OUTPUT:
1637 default:
1638 dev_err(dev, "invalid operations.\n");
1639 break;
1640 }
1641
1642 gsc_handle_irq(ctx, false, false, true);
1643
1644 /* reset sequence */
1645 gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
1646 gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
1647 gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
1648
1649 cfg = gsc_read(GSC_ENABLE);
1650 cfg &= ~GSC_ENABLE_ON;
1651 gsc_write(cfg, GSC_ENABLE);
1652}
1653
56550d94 1654static int gsc_probe(struct platform_device *pdev)
f2646380
EK		 1655{
1656 struct device *dev = &pdev->dev;
1657 struct gsc_context *ctx;
1658 struct resource *res;
1659 struct exynos_drm_ippdrv *ippdrv;
1660 int ret;
1661
1662 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1663 if (!ctx)
1664 return -ENOMEM;
1665
1666 /* clock control */
5cbd419c 1667 ctx->gsc_clk = devm_clk_get(dev, "gscl");
f2646380
EK		 1668 if (IS_ERR(ctx->gsc_clk)) {
1669 dev_err(dev, "failed to get gsc clock.\n");
cfdee8f4 1670 return PTR_ERR(ctx->gsc_clk);
f2646380
EK		 1671 }
1672
1673 /* resource memory */
1674 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1675 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1676 if (IS_ERR(ctx->regs))
1677 return PTR_ERR(ctx->regs);
f2646380
EK		 1678
1679 /* resource irq */
1680 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1681 if (!res) {
1682 dev_err(dev, "failed to request irq resource.\n");
5cbd419c 1683 return -ENOENT;
f2646380
EK		 1684 }
1685
1686 ctx->irq = res->start;
dcb9a7c7 1687 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
f2646380
EK		 1688 IRQF_ONESHOT, "drm_gsc", ctx);
1689 if (ret < 0) {
1690 dev_err(dev, "failed to request irq.\n");
5cbd419c 1691 return ret;
f2646380
EK		 1692 }
1693
1694 /* context initailization */
1695 ctx->id = pdev->id;
1696
1697 ippdrv = &ctx->ippdrv;
1698 ippdrv->dev = dev;
1699 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
1700 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
1701 ippdrv->check_property = gsc_ippdrv_check_property;
1702 ippdrv->reset = gsc_ippdrv_reset;
1703 ippdrv->start = gsc_ippdrv_start;
1704 ippdrv->stop = gsc_ippdrv_stop;
1705 ret = gsc_init_prop_list(ippdrv);
1706 if (ret < 0) {
1707 dev_err(dev, "failed to init property list.\n");
dcb9a7c7 1708 return ret;
f2646380
EK		 1709 }
1710
cbc4c33d 1711 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
f2646380
EK		 1712
1713 mutex_init(&ctx->lock);
1714 platform_set_drvdata(pdev, ctx);
1715
1716 pm_runtime_set_active(dev);
1717 pm_runtime_enable(dev);
1718
1719 ret = exynos_drm_ippdrv_register(ippdrv);
1720 if (ret < 0) {
1721 dev_err(dev, "failed to register drm gsc device.\n");
1722 goto err_ippdrv_register;
1723 }
1724
d873ab99 1725 dev_info(dev, "drm gsc registered successfully.\n");
f2646380
EK		 1726
1727 return 0;
1728
1729err_ippdrv_register:
f2646380 1730 pm_runtime_disable(dev);
f2646380
EK		 1731 return ret;
1732}
1733
56550d94 1734static int gsc_remove(struct platform_device *pdev)
f2646380
EK		 1735{
1736 struct device *dev = &pdev->dev;
1737 struct gsc_context *ctx = get_gsc_context(dev);
1738 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1739
f2646380
EK		 1740 exynos_drm_ippdrv_unregister(ippdrv);
1741 mutex_destroy(&ctx->lock);
1742
1743 pm_runtime_set_suspended(dev);
1744 pm_runtime_disable(dev);
1745
f2646380
EK		 1746 return 0;
1747}
1748
1749#ifdef CONFIG_PM_SLEEP
1750static int gsc_suspend(struct device *dev)
1751{
1752 struct gsc_context *ctx = get_gsc_context(dev);
1753
cbc4c33d 1754 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
f2646380
EK		 1755
1756 if (pm_runtime_suspended(dev))
1757 return 0;
1758
1759 return gsc_clk_ctrl(ctx, false);
1760}
1761
1762static int gsc_resume(struct device *dev)
1763{
1764 struct gsc_context *ctx = get_gsc_context(dev);
1765
cbc4c33d 1766 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
f2646380
EK		 1767
1768 if (!pm_runtime_suspended(dev))
1769 return gsc_clk_ctrl(ctx, true);
1770
1771 return 0;
1772}
1773#endif
1774
1775#ifdef CONFIG_PM_RUNTIME
1776static int gsc_runtime_suspend(struct device *dev)
1777{
1778 struct gsc_context *ctx = get_gsc_context(dev);
1779
cbc4c33d 1780 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
f2646380
EK		 1781
1782 return gsc_clk_ctrl(ctx, false);
1783}
1784
1785static int gsc_runtime_resume(struct device *dev)
1786{
1787 struct gsc_context *ctx = get_gsc_context(dev);
1788
bca34c9a 1789 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
f2646380
EK		 1790
1791 return gsc_clk_ctrl(ctx, true);
1792}
1793#endif
1794
1795static const struct dev_pm_ops gsc_pm_ops = {
1796 SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume)
1797 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1798};
1799
1800struct platform_driver gsc_driver = {
1801 .probe = gsc_probe,
56550d94 1802 .remove = gsc_remove,
f2646380
EK		 1803 .driver = {
1804 .name = "exynos-drm-gsc",
1805 .owner = THIS_MODULE,
1806 .pm = &gsc_pm_ops,
1807 },
1808};
1809
Linux kernel - Deliverables
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