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f2646380 EK |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
3 | * Authors: | |
4 | * Eunchul Kim <chulspro.kim@samsung.com> | |
5 | * Jinyoung Jeon <jy0.jeon@samsung.com> | |
6 | * Sangmin Lee <lsmin.lee@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | #include <linux/kernel.h> | |
f2646380 EK |
15 | #include <linux/platform_device.h> |
16 | #include <linux/clk.h> | |
17 | #include <linux/pm_runtime.h> | |
18 | #include <plat/map-base.h> | |
19 | ||
20 | #include <drm/drmP.h> | |
21 | #include <drm/exynos_drm.h> | |
22 | #include "regs-gsc.h" | |
e30655d0 | 23 | #include "exynos_drm_drv.h" |
f2646380 EK |
24 | #include "exynos_drm_ipp.h" |
25 | #include "exynos_drm_gsc.h" | |
26 | ||
27 | /* | |
6fe891f6 | 28 | * GSC stands for General SCaler and |
f2646380 EK |
29 | * supports image scaler/rotator and input/output DMA operations. |
30 | * input DMA reads image data from the memory. | |
31 | * output DMA writes image data to memory. | |
32 | * GSC supports image rotation and image effect functions. | |
33 | * | |
34 | * M2M operation : supports crop/scale/rotation/csc so on. | |
35 | * Memory ----> GSC H/W ----> Memory. | |
36 | * Writeback operation : supports cloned screen with FIMD. | |
37 | * FIMD ----> GSC H/W ----> Memory. | |
38 | * Output operation : supports direct display using local path. | |
39 | * Memory ----> GSC H/W ----> FIMD, Mixer. | |
40 | */ | |
41 | ||
42 | /* | |
43 | * TODO | |
44 | * 1. check suspend/resume api if needed. | |
45 | * 2. need to check use case platform_device_id. | |
46 | * 3. check src/dst size with, height. | |
47 | * 4. added check_prepare api for right register. | |
48 | * 5. need to add supported list in prop_list. | |
49 | * 6. check prescaler/scaler optimization. | |
50 | */ | |
51 | ||
52 | #define GSC_MAX_DEVS 4 | |
53 | #define GSC_MAX_SRC 4 | |
54 | #define GSC_MAX_DST 16 | |
55 | #define GSC_RESET_TIMEOUT 50 | |
56 | #define GSC_BUF_STOP 1 | |
57 | #define GSC_BUF_START 2 | |
58 | #define GSC_REG_SZ 16 | |
59 | #define GSC_WIDTH_ITU_709 1280 | |
60 | #define GSC_SC_UP_MAX_RATIO 65536 | |
61 | #define GSC_SC_DOWN_RATIO_7_8 74898 | |
62 | #define GSC_SC_DOWN_RATIO_6_8 87381 | |
63 | #define GSC_SC_DOWN_RATIO_5_8 104857 | |
64 | #define GSC_SC_DOWN_RATIO_4_8 131072 | |
65 | #define GSC_SC_DOWN_RATIO_3_8 174762 | |
66 | #define GSC_SC_DOWN_RATIO_2_8 262144 | |
67 | #define GSC_REFRESH_MIN 12 | |
68 | #define GSC_REFRESH_MAX 60 | |
69 | #define GSC_CROP_MAX 8192 | |
70 | #define GSC_CROP_MIN 32 | |
71 | #define GSC_SCALE_MAX 4224 | |
72 | #define GSC_SCALE_MIN 32 | |
73 | #define GSC_COEF_RATIO 7 | |
74 | #define GSC_COEF_PHASE 9 | |
75 | #define GSC_COEF_ATTR 16 | |
76 | #define GSC_COEF_H_8T 8 | |
77 | #define GSC_COEF_V_4T 4 | |
78 | #define GSC_COEF_DEPTH 3 | |
79 | ||
80 | #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev)) | |
81 | #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ | |
82 | struct gsc_context, ippdrv); | |
83 | #define gsc_read(offset) readl(ctx->regs + (offset)) | |
84 | #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) | |
85 | ||
86 | /* | |
87 | * A structure of scaler. | |
88 | * | |
89 | * @range: narrow, wide. | |
90 | * @pre_shfactor: pre sclaer shift factor. | |
91 | * @pre_hratio: horizontal ratio of the prescaler. | |
92 | * @pre_vratio: vertical ratio of the prescaler. | |
93 | * @main_hratio: the main scaler's horizontal ratio. | |
94 | * @main_vratio: the main scaler's vertical ratio. | |
95 | */ | |
96 | struct gsc_scaler { | |
97 | bool range; | |
98 | u32 pre_shfactor; | |
99 | u32 pre_hratio; | |
100 | u32 pre_vratio; | |
101 | unsigned long main_hratio; | |
102 | unsigned long main_vratio; | |
103 | }; | |
104 | ||
105 | /* | |
106 | * A structure of scaler capability. | |
107 | * | |
108 | * find user manual 49.2 features. | |
109 | * @tile_w: tile mode or rotation width. | |
110 | * @tile_h: tile mode or rotation height. | |
111 | * @w: other cases width. | |
112 | * @h: other cases height. | |
113 | */ | |
114 | struct gsc_capability { | |
115 | /* tile or rotation */ | |
116 | u32 tile_w; | |
117 | u32 tile_h; | |
118 | /* other cases */ | |
119 | u32 w; | |
120 | u32 h; | |
121 | }; | |
122 | ||
123 | /* | |
124 | * A structure of gsc context. | |
125 | * | |
126 | * @ippdrv: prepare initialization using ippdrv. | |
127 | * @regs_res: register resources. | |
128 | * @regs: memory mapped io registers. | |
129 | * @lock: locking of operations. | |
130 | * @gsc_clk: gsc gate clock. | |
131 | * @sc: scaler infomations. | |
132 | * @id: gsc id. | |
133 | * @irq: irq number. | |
134 | * @rotation: supports rotation of src. | |
135 | * @suspended: qos operations. | |
136 | */ | |
137 | struct gsc_context { | |
138 | struct exynos_drm_ippdrv ippdrv; | |
139 | struct resource *regs_res; | |
140 | void __iomem *regs; | |
141 | struct mutex lock; | |
142 | struct clk *gsc_clk; | |
143 | struct gsc_scaler sc; | |
144 | int id; | |
145 | int irq; | |
146 | bool rotation; | |
147 | bool suspended; | |
148 | }; | |
149 | ||
150 | /* 8-tap Filter Coefficient */ | |
151 | static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = { | |
152 | { /* Ratio <= 65536 (~8:8) */ | |
153 | { 0, 0, 0, 128, 0, 0, 0, 0 }, | |
154 | { -1, 2, -6, 127, 7, -2, 1, 0 }, | |
155 | { -1, 4, -12, 125, 16, -5, 1, 0 }, | |
156 | { -1, 5, -15, 120, 25, -8, 2, 0 }, | |
157 | { -1, 6, -18, 114, 35, -10, 3, -1 }, | |
158 | { -1, 6, -20, 107, 46, -13, 4, -1 }, | |
159 | { -2, 7, -21, 99, 57, -16, 5, -1 }, | |
160 | { -1, 6, -20, 89, 68, -18, 5, -1 }, | |
161 | { -1, 6, -20, 79, 79, -20, 6, -1 }, | |
162 | { -1, 5, -18, 68, 89, -20, 6, -1 }, | |
163 | { -1, 5, -16, 57, 99, -21, 7, -2 }, | |
164 | { -1, 4, -13, 46, 107, -20, 6, -1 }, | |
165 | { -1, 3, -10, 35, 114, -18, 6, -1 }, | |
166 | { 0, 2, -8, 25, 120, -15, 5, -1 }, | |
167 | { 0, 1, -5, 16, 125, -12, 4, -1 }, | |
168 | { 0, 1, -2, 7, 127, -6, 2, -1 } | |
169 | }, { /* 65536 < Ratio <= 74898 (~8:7) */ | |
170 | { 3, -8, 14, 111, 13, -8, 3, 0 }, | |
171 | { 2, -6, 7, 112, 21, -10, 3, -1 }, | |
172 | { 2, -4, 1, 110, 28, -12, 4, -1 }, | |
173 | { 1, -2, -3, 106, 36, -13, 4, -1 }, | |
174 | { 1, -1, -7, 103, 44, -15, 4, -1 }, | |
175 | { 1, 1, -11, 97, 53, -16, 4, -1 }, | |
176 | { 0, 2, -13, 91, 61, -16, 4, -1 }, | |
177 | { 0, 3, -15, 85, 69, -17, 4, -1 }, | |
178 | { 0, 3, -16, 77, 77, -16, 3, 0 }, | |
179 | { -1, 4, -17, 69, 85, -15, 3, 0 }, | |
180 | { -1, 4, -16, 61, 91, -13, 2, 0 }, | |
181 | { -1, 4, -16, 53, 97, -11, 1, 1 }, | |
182 | { -1, 4, -15, 44, 103, -7, -1, 1 }, | |
183 | { -1, 4, -13, 36, 106, -3, -2, 1 }, | |
184 | { -1, 4, -12, 28, 110, 1, -4, 2 }, | |
185 | { -1, 3, -10, 21, 112, 7, -6, 2 } | |
186 | }, { /* 74898 < Ratio <= 87381 (~8:6) */ | |
187 | { 2, -11, 25, 96, 25, -11, 2, 0 }, | |
188 | { 2, -10, 19, 96, 31, -12, 2, 0 }, | |
189 | { 2, -9, 14, 94, 37, -12, 2, 0 }, | |
190 | { 2, -8, 10, 92, 43, -12, 1, 0 }, | |
191 | { 2, -7, 5, 90, 49, -12, 1, 0 }, | |
192 | { 2, -5, 1, 86, 55, -12, 0, 1 }, | |
193 | { 2, -4, -2, 82, 61, -11, -1, 1 }, | |
194 | { 1, -3, -5, 77, 67, -9, -1, 1 }, | |
195 | { 1, -2, -7, 72, 72, -7, -2, 1 }, | |
196 | { 1, -1, -9, 67, 77, -5, -3, 1 }, | |
197 | { 1, -1, -11, 61, 82, -2, -4, 2 }, | |
198 | { 1, 0, -12, 55, 86, 1, -5, 2 }, | |
199 | { 0, 1, -12, 49, 90, 5, -7, 2 }, | |
200 | { 0, 1, -12, 43, 92, 10, -8, 2 }, | |
201 | { 0, 2, -12, 37, 94, 14, -9, 2 }, | |
202 | { 0, 2, -12, 31, 96, 19, -10, 2 } | |
203 | }, { /* 87381 < Ratio <= 104857 (~8:5) */ | |
204 | { -1, -8, 33, 80, 33, -8, -1, 0 }, | |
205 | { -1, -8, 28, 80, 37, -7, -2, 1 }, | |
206 | { 0, -8, 24, 79, 41, -7, -2, 1 }, | |
207 | { 0, -8, 20, 78, 46, -6, -3, 1 }, | |
208 | { 0, -8, 16, 76, 50, -4, -3, 1 }, | |
209 | { 0, -7, 13, 74, 54, -3, -4, 1 }, | |
210 | { 1, -7, 10, 71, 58, -1, -5, 1 }, | |
211 | { 1, -6, 6, 68, 62, 1, -5, 1 }, | |
212 | { 1, -6, 4, 65, 65, 4, -6, 1 }, | |
213 | { 1, -5, 1, 62, 68, 6, -6, 1 }, | |
214 | { 1, -5, -1, 58, 71, 10, -7, 1 }, | |
215 | { 1, -4, -3, 54, 74, 13, -7, 0 }, | |
216 | { 1, -3, -4, 50, 76, 16, -8, 0 }, | |
217 | { 1, -3, -6, 46, 78, 20, -8, 0 }, | |
218 | { 1, -2, -7, 41, 79, 24, -8, 0 }, | |
219 | { 1, -2, -7, 37, 80, 28, -8, -1 } | |
220 | }, { /* 104857 < Ratio <= 131072 (~8:4) */ | |
221 | { -3, 0, 35, 64, 35, 0, -3, 0 }, | |
222 | { -3, -1, 32, 64, 38, 1, -3, 0 }, | |
223 | { -2, -2, 29, 63, 41, 2, -3, 0 }, | |
224 | { -2, -3, 27, 63, 43, 4, -4, 0 }, | |
225 | { -2, -3, 24, 61, 46, 6, -4, 0 }, | |
226 | { -2, -3, 21, 60, 49, 7, -4, 0 }, | |
227 | { -1, -4, 19, 59, 51, 9, -4, -1 }, | |
228 | { -1, -4, 16, 57, 53, 12, -4, -1 }, | |
229 | { -1, -4, 14, 55, 55, 14, -4, -1 }, | |
230 | { -1, -4, 12, 53, 57, 16, -4, -1 }, | |
231 | { -1, -4, 9, 51, 59, 19, -4, -1 }, | |
232 | { 0, -4, 7, 49, 60, 21, -3, -2 }, | |
233 | { 0, -4, 6, 46, 61, 24, -3, -2 }, | |
234 | { 0, -4, 4, 43, 63, 27, -3, -2 }, | |
235 | { 0, -3, 2, 41, 63, 29, -2, -2 }, | |
236 | { 0, -3, 1, 38, 64, 32, -1, -3 } | |
237 | }, { /* 131072 < Ratio <= 174762 (~8:3) */ | |
238 | { -1, 8, 33, 48, 33, 8, -1, 0 }, | |
239 | { -1, 7, 31, 49, 35, 9, -1, -1 }, | |
240 | { -1, 6, 30, 49, 36, 10, -1, -1 }, | |
241 | { -1, 5, 28, 48, 38, 12, -1, -1 }, | |
242 | { -1, 4, 26, 48, 39, 13, 0, -1 }, | |
243 | { -1, 3, 24, 47, 41, 15, 0, -1 }, | |
244 | { -1, 2, 23, 47, 42, 16, 0, -1 }, | |
245 | { -1, 2, 21, 45, 43, 18, 1, -1 }, | |
246 | { -1, 1, 19, 45, 45, 19, 1, -1 }, | |
247 | { -1, 1, 18, 43, 45, 21, 2, -1 }, | |
248 | { -1, 0, 16, 42, 47, 23, 2, -1 }, | |
249 | { -1, 0, 15, 41, 47, 24, 3, -1 }, | |
250 | { -1, 0, 13, 39, 48, 26, 4, -1 }, | |
251 | { -1, -1, 12, 38, 48, 28, 5, -1 }, | |
252 | { -1, -1, 10, 36, 49, 30, 6, -1 }, | |
253 | { -1, -1, 9, 35, 49, 31, 7, -1 } | |
254 | }, { /* 174762 < Ratio <= 262144 (~8:2) */ | |
255 | { 2, 13, 30, 38, 30, 13, 2, 0 }, | |
256 | { 2, 12, 29, 38, 30, 14, 3, 0 }, | |
257 | { 2, 11, 28, 38, 31, 15, 3, 0 }, | |
258 | { 2, 10, 26, 38, 32, 16, 4, 0 }, | |
259 | { 1, 10, 26, 37, 33, 17, 4, 0 }, | |
260 | { 1, 9, 24, 37, 34, 18, 5, 0 }, | |
261 | { 1, 8, 24, 37, 34, 19, 5, 0 }, | |
262 | { 1, 7, 22, 36, 35, 20, 6, 1 }, | |
263 | { 1, 6, 21, 36, 36, 21, 6, 1 }, | |
264 | { 1, 6, 20, 35, 36, 22, 7, 1 }, | |
265 | { 0, 5, 19, 34, 37, 24, 8, 1 }, | |
266 | { 0, 5, 18, 34, 37, 24, 9, 1 }, | |
267 | { 0, 4, 17, 33, 37, 26, 10, 1 }, | |
268 | { 0, 4, 16, 32, 38, 26, 10, 2 }, | |
269 | { 0, 3, 15, 31, 38, 28, 11, 2 }, | |
270 | { 0, 3, 14, 30, 38, 29, 12, 2 } | |
271 | } | |
272 | }; | |
273 | ||
274 | /* 4-tap Filter Coefficient */ | |
275 | static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = { | |
276 | { /* Ratio <= 65536 (~8:8) */ | |
277 | { 0, 128, 0, 0 }, | |
278 | { -4, 127, 5, 0 }, | |
279 | { -6, 124, 11, -1 }, | |
280 | { -8, 118, 19, -1 }, | |
281 | { -8, 111, 27, -2 }, | |
282 | { -8, 102, 37, -3 }, | |
283 | { -8, 92, 48, -4 }, | |
284 | { -7, 81, 59, -5 }, | |
285 | { -6, 70, 70, -6 }, | |
286 | { -5, 59, 81, -7 }, | |
287 | { -4, 48, 92, -8 }, | |
288 | { -3, 37, 102, -8 }, | |
289 | { -2, 27, 111, -8 }, | |
290 | { -1, 19, 118, -8 }, | |
291 | { -1, 11, 124, -6 }, | |
292 | { 0, 5, 127, -4 } | |
293 | }, { /* 65536 < Ratio <= 74898 (~8:7) */ | |
294 | { 8, 112, 8, 0 }, | |
295 | { 4, 111, 14, -1 }, | |
296 | { 1, 109, 20, -2 }, | |
297 | { -2, 105, 27, -2 }, | |
298 | { -3, 100, 34, -3 }, | |
299 | { -5, 93, 43, -3 }, | |
300 | { -5, 86, 51, -4 }, | |
301 | { -5, 77, 60, -4 }, | |
302 | { -5, 69, 69, -5 }, | |
303 | { -4, 60, 77, -5 }, | |
304 | { -4, 51, 86, -5 }, | |
305 | { -3, 43, 93, -5 }, | |
306 | { -3, 34, 100, -3 }, | |
307 | { -2, 27, 105, -2 }, | |
308 | { -2, 20, 109, 1 }, | |
309 | { -1, 14, 111, 4 } | |
310 | }, { /* 74898 < Ratio <= 87381 (~8:6) */ | |
311 | { 16, 96, 16, 0 }, | |
312 | { 12, 97, 21, -2 }, | |
313 | { 8, 96, 26, -2 }, | |
314 | { 5, 93, 32, -2 }, | |
315 | { 2, 89, 39, -2 }, | |
316 | { 0, 84, 46, -2 }, | |
317 | { -1, 79, 53, -3 }, | |
318 | { -2, 73, 59, -2 }, | |
319 | { -2, 66, 66, -2 }, | |
320 | { -2, 59, 73, -2 }, | |
321 | { -3, 53, 79, -1 }, | |
322 | { -2, 46, 84, 0 }, | |
323 | { -2, 39, 89, 2 }, | |
324 | { -2, 32, 93, 5 }, | |
325 | { -2, 26, 96, 8 }, | |
326 | { -2, 21, 97, 12 } | |
327 | }, { /* 87381 < Ratio <= 104857 (~8:5) */ | |
328 | { 22, 84, 22, 0 }, | |
329 | { 18, 85, 26, -1 }, | |
330 | { 14, 84, 31, -1 }, | |
331 | { 11, 82, 36, -1 }, | |
332 | { 8, 79, 42, -1 }, | |
333 | { 6, 76, 47, -1 }, | |
334 | { 4, 72, 52, 0 }, | |
335 | { 2, 68, 58, 0 }, | |
336 | { 1, 63, 63, 1 }, | |
337 | { 0, 58, 68, 2 }, | |
338 | { 0, 52, 72, 4 }, | |
339 | { -1, 47, 76, 6 }, | |
340 | { -1, 42, 79, 8 }, | |
341 | { -1, 36, 82, 11 }, | |
342 | { -1, 31, 84, 14 }, | |
343 | { -1, 26, 85, 18 } | |
344 | }, { /* 104857 < Ratio <= 131072 (~8:4) */ | |
345 | { 26, 76, 26, 0 }, | |
346 | { 22, 76, 30, 0 }, | |
347 | { 19, 75, 34, 0 }, | |
348 | { 16, 73, 38, 1 }, | |
349 | { 13, 71, 43, 1 }, | |
350 | { 10, 69, 47, 2 }, | |
351 | { 8, 66, 51, 3 }, | |
352 | { 6, 63, 55, 4 }, | |
353 | { 5, 59, 59, 5 }, | |
354 | { 4, 55, 63, 6 }, | |
355 | { 3, 51, 66, 8 }, | |
356 | { 2, 47, 69, 10 }, | |
357 | { 1, 43, 71, 13 }, | |
358 | { 1, 38, 73, 16 }, | |
359 | { 0, 34, 75, 19 }, | |
360 | { 0, 30, 76, 22 } | |
361 | }, { /* 131072 < Ratio <= 174762 (~8:3) */ | |
362 | { 29, 70, 29, 0 }, | |
363 | { 26, 68, 32, 2 }, | |
364 | { 23, 67, 36, 2 }, | |
365 | { 20, 66, 39, 3 }, | |
366 | { 17, 65, 43, 3 }, | |
367 | { 15, 63, 46, 4 }, | |
368 | { 12, 61, 50, 5 }, | |
369 | { 10, 58, 53, 7 }, | |
370 | { 8, 56, 56, 8 }, | |
371 | { 7, 53, 58, 10 }, | |
372 | { 5, 50, 61, 12 }, | |
373 | { 4, 46, 63, 15 }, | |
374 | { 3, 43, 65, 17 }, | |
375 | { 3, 39, 66, 20 }, | |
376 | { 2, 36, 67, 23 }, | |
377 | { 2, 32, 68, 26 } | |
378 | }, { /* 174762 < Ratio <= 262144 (~8:2) */ | |
379 | { 32, 64, 32, 0 }, | |
380 | { 28, 63, 34, 3 }, | |
381 | { 25, 62, 37, 4 }, | |
382 | { 22, 62, 40, 4 }, | |
383 | { 19, 61, 43, 5 }, | |
384 | { 17, 59, 46, 6 }, | |
385 | { 15, 58, 48, 7 }, | |
386 | { 13, 55, 51, 9 }, | |
387 | { 11, 53, 53, 11 }, | |
388 | { 9, 51, 55, 13 }, | |
389 | { 7, 48, 58, 15 }, | |
390 | { 6, 46, 59, 17 }, | |
391 | { 5, 43, 61, 19 }, | |
392 | { 4, 40, 62, 22 }, | |
393 | { 4, 37, 62, 25 }, | |
394 | { 3, 34, 63, 28 } | |
395 | } | |
396 | }; | |
397 | ||
398 | static int gsc_sw_reset(struct gsc_context *ctx) | |
399 | { | |
400 | u32 cfg; | |
401 | int count = GSC_RESET_TIMEOUT; | |
402 | ||
f2646380 EK |
403 | /* s/w reset */ |
404 | cfg = (GSC_SW_RESET_SRESET); | |
405 | gsc_write(cfg, GSC_SW_RESET); | |
406 | ||
407 | /* wait s/w reset complete */ | |
408 | while (count--) { | |
409 | cfg = gsc_read(GSC_SW_RESET); | |
410 | if (!cfg) | |
411 | break; | |
412 | usleep_range(1000, 2000); | |
413 | } | |
414 | ||
415 | if (cfg) { | |
416 | DRM_ERROR("failed to reset gsc h/w.\n"); | |
417 | return -EBUSY; | |
418 | } | |
419 | ||
420 | /* reset sequence */ | |
421 | cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); | |
422 | cfg |= (GSC_IN_BASE_ADDR_MASK | | |
423 | GSC_IN_BASE_ADDR_PINGPONG(0)); | |
424 | gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); | |
425 | gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); | |
426 | gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); | |
427 | ||
428 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); | |
429 | cfg |= (GSC_OUT_BASE_ADDR_MASK | | |
430 | GSC_OUT_BASE_ADDR_PINGPONG(0)); | |
431 | gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); | |
432 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); | |
433 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable) | |
439 | { | |
440 | u32 gscblk_cfg; | |
441 | ||
f2646380 EK |
442 | gscblk_cfg = readl(SYSREG_GSCBLK_CFG1); |
443 | ||
444 | if (enable) | |
445 | gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) | | |
446 | GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) | | |
447 | GSC_BLK_SW_RESET_WB_DEST(ctx->id); | |
448 | else | |
449 | gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id); | |
450 | ||
451 | writel(gscblk_cfg, SYSREG_GSCBLK_CFG1); | |
452 | } | |
453 | ||
454 | static void gsc_handle_irq(struct gsc_context *ctx, bool enable, | |
455 | bool overflow, bool done) | |
456 | { | |
457 | u32 cfg; | |
458 | ||
cbc4c33d | 459 | DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", |
f2646380 EK |
460 | enable, overflow, done); |
461 | ||
462 | cfg = gsc_read(GSC_IRQ); | |
463 | cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK); | |
464 | ||
465 | if (enable) | |
466 | cfg |= GSC_IRQ_ENABLE; | |
467 | else | |
468 | cfg &= ~GSC_IRQ_ENABLE; | |
469 | ||
470 | if (overflow) | |
471 | cfg &= ~GSC_IRQ_OR_MASK; | |
472 | else | |
473 | cfg |= GSC_IRQ_OR_MASK; | |
474 | ||
475 | if (done) | |
476 | cfg &= ~GSC_IRQ_FRMDONE_MASK; | |
477 | else | |
478 | cfg |= GSC_IRQ_FRMDONE_MASK; | |
479 | ||
480 | gsc_write(cfg, GSC_IRQ); | |
481 | } | |
482 | ||
483 | ||
484 | static int gsc_src_set_fmt(struct device *dev, u32 fmt) | |
485 | { | |
486 | struct gsc_context *ctx = get_gsc_context(dev); | |
487 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
488 | u32 cfg; | |
489 | ||
cbc4c33d | 490 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
f2646380 EK |
491 | |
492 | cfg = gsc_read(GSC_IN_CON); | |
493 | cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK | | |
494 | GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK | | |
495 | GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE | | |
496 | GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK); | |
497 | ||
498 | switch (fmt) { | |
499 | case DRM_FORMAT_RGB565: | |
500 | cfg |= GSC_IN_RGB565; | |
501 | break; | |
502 | case DRM_FORMAT_XRGB8888: | |
503 | cfg |= GSC_IN_XRGB8888; | |
504 | break; | |
505 | case DRM_FORMAT_BGRX8888: | |
506 | cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP); | |
507 | break; | |
508 | case DRM_FORMAT_YUYV: | |
509 | cfg |= (GSC_IN_YUV422_1P | | |
510 | GSC_IN_YUV422_1P_ORDER_LSB_Y | | |
511 | GSC_IN_CHROMA_ORDER_CBCR); | |
512 | break; | |
513 | case DRM_FORMAT_YVYU: | |
514 | cfg |= (GSC_IN_YUV422_1P | | |
515 | GSC_IN_YUV422_1P_ORDER_LSB_Y | | |
516 | GSC_IN_CHROMA_ORDER_CRCB); | |
517 | break; | |
518 | case DRM_FORMAT_UYVY: | |
519 | cfg |= (GSC_IN_YUV422_1P | | |
520 | GSC_IN_YUV422_1P_OEDER_LSB_C | | |
521 | GSC_IN_CHROMA_ORDER_CBCR); | |
522 | break; | |
523 | case DRM_FORMAT_VYUY: | |
524 | cfg |= (GSC_IN_YUV422_1P | | |
525 | GSC_IN_YUV422_1P_OEDER_LSB_C | | |
526 | GSC_IN_CHROMA_ORDER_CRCB); | |
527 | break; | |
528 | case DRM_FORMAT_NV21: | |
529 | case DRM_FORMAT_NV61: | |
530 | cfg |= (GSC_IN_CHROMA_ORDER_CRCB | | |
531 | GSC_IN_YUV420_2P); | |
532 | break; | |
533 | case DRM_FORMAT_YUV422: | |
534 | cfg |= GSC_IN_YUV422_3P; | |
535 | break; | |
536 | case DRM_FORMAT_YUV420: | |
537 | case DRM_FORMAT_YVU420: | |
538 | cfg |= GSC_IN_YUV420_3P; | |
539 | break; | |
540 | case DRM_FORMAT_NV12: | |
541 | case DRM_FORMAT_NV16: | |
542 | cfg |= (GSC_IN_CHROMA_ORDER_CBCR | | |
543 | GSC_IN_YUV420_2P); | |
544 | break; | |
545 | case DRM_FORMAT_NV12MT: | |
546 | cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE); | |
547 | break; | |
548 | default: | |
549 | dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
553 | gsc_write(cfg, GSC_IN_CON); | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | static int gsc_src_set_transf(struct device *dev, | |
559 | enum drm_exynos_degree degree, | |
560 | enum drm_exynos_flip flip, bool *swap) | |
561 | { | |
562 | struct gsc_context *ctx = get_gsc_context(dev); | |
563 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
564 | u32 cfg; | |
565 | ||
cbc4c33d | 566 | DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); |
f2646380 EK |
567 | |
568 | cfg = gsc_read(GSC_IN_CON); | |
569 | cfg &= ~GSC_IN_ROT_MASK; | |
570 | ||
571 | switch (degree) { | |
572 | case EXYNOS_DRM_DEGREE_0: | |
573 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) | |
574 | cfg |= GSC_IN_ROT_XFLIP; | |
575 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) | |
576 | cfg |= GSC_IN_ROT_YFLIP; | |
577 | break; | |
578 | case EXYNOS_DRM_DEGREE_90: | |
579 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) | |
580 | cfg |= GSC_IN_ROT_90_XFLIP; | |
581 | else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) | |
582 | cfg |= GSC_IN_ROT_90_YFLIP; | |
583 | else | |
584 | cfg |= GSC_IN_ROT_90; | |
585 | break; | |
586 | case EXYNOS_DRM_DEGREE_180: | |
587 | cfg |= GSC_IN_ROT_180; | |
588 | break; | |
589 | case EXYNOS_DRM_DEGREE_270: | |
590 | cfg |= GSC_IN_ROT_270; | |
591 | break; | |
592 | default: | |
593 | dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); | |
594 | return -EINVAL; | |
595 | } | |
596 | ||
597 | gsc_write(cfg, GSC_IN_CON); | |
598 | ||
599 | ctx->rotation = cfg & | |
600 | (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0; | |
601 | *swap = ctx->rotation; | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | static int gsc_src_set_size(struct device *dev, int swap, | |
607 | struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) | |
608 | { | |
609 | struct gsc_context *ctx = get_gsc_context(dev); | |
610 | struct drm_exynos_pos img_pos = *pos; | |
611 | struct gsc_scaler *sc = &ctx->sc; | |
612 | u32 cfg; | |
613 | ||
cbc4c33d YC |
614 | DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n", |
615 | swap, pos->x, pos->y, pos->w, pos->h); | |
f2646380 EK |
616 | |
617 | if (swap) { | |
618 | img_pos.w = pos->h; | |
619 | img_pos.h = pos->w; | |
620 | } | |
621 | ||
622 | /* pixel offset */ | |
623 | cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) | | |
624 | GSC_SRCIMG_OFFSET_Y(img_pos.y)); | |
625 | gsc_write(cfg, GSC_SRCIMG_OFFSET); | |
626 | ||
627 | /* cropped size */ | |
628 | cfg = (GSC_CROPPED_WIDTH(img_pos.w) | | |
629 | GSC_CROPPED_HEIGHT(img_pos.h)); | |
630 | gsc_write(cfg, GSC_CROPPED_SIZE); | |
631 | ||
cbc4c33d | 632 | DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize); |
f2646380 EK |
633 | |
634 | /* original size */ | |
635 | cfg = gsc_read(GSC_SRCIMG_SIZE); | |
636 | cfg &= ~(GSC_SRCIMG_HEIGHT_MASK | | |
637 | GSC_SRCIMG_WIDTH_MASK); | |
638 | ||
639 | cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) | | |
640 | GSC_SRCIMG_HEIGHT(sz->vsize)); | |
641 | ||
642 | gsc_write(cfg, GSC_SRCIMG_SIZE); | |
643 | ||
644 | cfg = gsc_read(GSC_IN_CON); | |
645 | cfg &= ~GSC_IN_RGB_TYPE_MASK; | |
646 | ||
cbc4c33d | 647 | DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range); |
f2646380 EK |
648 | |
649 | if (pos->w >= GSC_WIDTH_ITU_709) | |
650 | if (sc->range) | |
651 | cfg |= GSC_IN_RGB_HD_WIDE; | |
652 | else | |
653 | cfg |= GSC_IN_RGB_HD_NARROW; | |
654 | else | |
655 | if (sc->range) | |
656 | cfg |= GSC_IN_RGB_SD_WIDE; | |
657 | else | |
658 | cfg |= GSC_IN_RGB_SD_NARROW; | |
659 | ||
660 | gsc_write(cfg, GSC_IN_CON); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id, | |
666 | enum drm_exynos_ipp_buf_type buf_type) | |
667 | { | |
668 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
669 | bool masked; | |
670 | u32 cfg; | |
671 | u32 mask = 0x00000001 << buf_id; | |
672 | ||
cbc4c33d | 673 | DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); |
f2646380 EK |
674 | |
675 | /* mask register set */ | |
676 | cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); | |
677 | ||
678 | switch (buf_type) { | |
679 | case IPP_BUF_ENQUEUE: | |
680 | masked = false; | |
681 | break; | |
682 | case IPP_BUF_DEQUEUE: | |
683 | masked = true; | |
684 | break; | |
685 | default: | |
686 | dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); | |
687 | return -EINVAL; | |
688 | } | |
689 | ||
690 | /* sequence id */ | |
691 | cfg &= ~mask; | |
692 | cfg |= masked << buf_id; | |
693 | gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); | |
694 | gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); | |
695 | gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static int gsc_src_set_addr(struct device *dev, | |
701 | struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, | |
702 | enum drm_exynos_ipp_buf_type buf_type) | |
703 | { | |
704 | struct gsc_context *ctx = get_gsc_context(dev); | |
705 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
7259c3d6 | 706 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
f2646380 EK |
707 | struct drm_exynos_ipp_property *property; |
708 | ||
709 | if (!c_node) { | |
710 | DRM_ERROR("failed to get c_node.\n"); | |
711 | return -EFAULT; | |
712 | } | |
713 | ||
714 | property = &c_node->property; | |
f2646380 | 715 | |
cbc4c33d | 716 | DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", |
f2646380 EK |
717 | property->prop_id, buf_id, buf_type); |
718 | ||
719 | if (buf_id > GSC_MAX_SRC) { | |
720 | dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | /* address register set */ | |
725 | switch (buf_type) { | |
726 | case IPP_BUF_ENQUEUE: | |
727 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], | |
728 | GSC_IN_BASE_ADDR_Y(buf_id)); | |
729 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], | |
730 | GSC_IN_BASE_ADDR_CB(buf_id)); | |
731 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], | |
732 | GSC_IN_BASE_ADDR_CR(buf_id)); | |
733 | break; | |
734 | case IPP_BUF_DEQUEUE: | |
735 | gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id)); | |
736 | gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id)); | |
737 | gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id)); | |
738 | break; | |
739 | default: | |
740 | /* bypass */ | |
741 | break; | |
742 | } | |
743 | ||
744 | return gsc_src_set_buf_seq(ctx, buf_id, buf_type); | |
745 | } | |
746 | ||
747 | static struct exynos_drm_ipp_ops gsc_src_ops = { | |
748 | .set_fmt = gsc_src_set_fmt, | |
749 | .set_transf = gsc_src_set_transf, | |
750 | .set_size = gsc_src_set_size, | |
751 | .set_addr = gsc_src_set_addr, | |
752 | }; | |
753 | ||
754 | static int gsc_dst_set_fmt(struct device *dev, u32 fmt) | |
755 | { | |
756 | struct gsc_context *ctx = get_gsc_context(dev); | |
757 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
758 | u32 cfg; | |
759 | ||
cbc4c33d | 760 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
f2646380 EK |
761 | |
762 | cfg = gsc_read(GSC_OUT_CON); | |
763 | cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK | | |
764 | GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK | | |
765 | GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK | | |
766 | GSC_OUT_GLOBAL_ALPHA_MASK); | |
767 | ||
768 | switch (fmt) { | |
769 | case DRM_FORMAT_RGB565: | |
770 | cfg |= GSC_OUT_RGB565; | |
771 | break; | |
772 | case DRM_FORMAT_XRGB8888: | |
773 | cfg |= GSC_OUT_XRGB8888; | |
774 | break; | |
775 | case DRM_FORMAT_BGRX8888: | |
776 | cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP); | |
777 | break; | |
778 | case DRM_FORMAT_YUYV: | |
779 | cfg |= (GSC_OUT_YUV422_1P | | |
780 | GSC_OUT_YUV422_1P_ORDER_LSB_Y | | |
781 | GSC_OUT_CHROMA_ORDER_CBCR); | |
782 | break; | |
783 | case DRM_FORMAT_YVYU: | |
784 | cfg |= (GSC_OUT_YUV422_1P | | |
785 | GSC_OUT_YUV422_1P_ORDER_LSB_Y | | |
786 | GSC_OUT_CHROMA_ORDER_CRCB); | |
787 | break; | |
788 | case DRM_FORMAT_UYVY: | |
789 | cfg |= (GSC_OUT_YUV422_1P | | |
790 | GSC_OUT_YUV422_1P_OEDER_LSB_C | | |
791 | GSC_OUT_CHROMA_ORDER_CBCR); | |
792 | break; | |
793 | case DRM_FORMAT_VYUY: | |
794 | cfg |= (GSC_OUT_YUV422_1P | | |
795 | GSC_OUT_YUV422_1P_OEDER_LSB_C | | |
796 | GSC_OUT_CHROMA_ORDER_CRCB); | |
797 | break; | |
798 | case DRM_FORMAT_NV21: | |
799 | case DRM_FORMAT_NV61: | |
800 | cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P); | |
801 | break; | |
802 | case DRM_FORMAT_YUV422: | |
803 | case DRM_FORMAT_YUV420: | |
804 | case DRM_FORMAT_YVU420: | |
805 | cfg |= GSC_OUT_YUV420_3P; | |
806 | break; | |
807 | case DRM_FORMAT_NV12: | |
808 | case DRM_FORMAT_NV16: | |
809 | cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | | |
810 | GSC_OUT_YUV420_2P); | |
811 | break; | |
812 | case DRM_FORMAT_NV12MT: | |
813 | cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE); | |
814 | break; | |
815 | default: | |
816 | dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); | |
817 | return -EINVAL; | |
818 | } | |
819 | ||
820 | gsc_write(cfg, GSC_OUT_CON); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int gsc_dst_set_transf(struct device *dev, | |
826 | enum drm_exynos_degree degree, | |
827 | enum drm_exynos_flip flip, bool *swap) | |
828 | { | |
829 | struct gsc_context *ctx = get_gsc_context(dev); | |
830 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
831 | u32 cfg; | |
832 | ||
cbc4c33d | 833 | DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); |
f2646380 EK |
834 | |
835 | cfg = gsc_read(GSC_IN_CON); | |
836 | cfg &= ~GSC_IN_ROT_MASK; | |
837 | ||
838 | switch (degree) { | |
839 | case EXYNOS_DRM_DEGREE_0: | |
840 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) | |
841 | cfg |= GSC_IN_ROT_XFLIP; | |
842 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) | |
843 | cfg |= GSC_IN_ROT_YFLIP; | |
844 | break; | |
845 | case EXYNOS_DRM_DEGREE_90: | |
846 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) | |
847 | cfg |= GSC_IN_ROT_90_XFLIP; | |
848 | else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) | |
849 | cfg |= GSC_IN_ROT_90_YFLIP; | |
850 | else | |
851 | cfg |= GSC_IN_ROT_90; | |
852 | break; | |
853 | case EXYNOS_DRM_DEGREE_180: | |
854 | cfg |= GSC_IN_ROT_180; | |
855 | break; | |
856 | case EXYNOS_DRM_DEGREE_270: | |
857 | cfg |= GSC_IN_ROT_270; | |
858 | break; | |
859 | default: | |
860 | dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); | |
861 | return -EINVAL; | |
862 | } | |
863 | ||
864 | gsc_write(cfg, GSC_IN_CON); | |
865 | ||
866 | ctx->rotation = cfg & | |
867 | (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0; | |
868 | *swap = ctx->rotation; | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio) | |
874 | { | |
cbc4c33d | 875 | DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst); |
f2646380 EK |
876 | |
877 | if (src >= dst * 8) { | |
878 | DRM_ERROR("failed to make ratio and shift.\n"); | |
879 | return -EINVAL; | |
880 | } else if (src >= dst * 4) | |
881 | *ratio = 4; | |
882 | else if (src >= dst * 2) | |
883 | *ratio = 2; | |
884 | else | |
885 | *ratio = 1; | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor) | |
891 | { | |
892 | if (hratio == 4 && vratio == 4) | |
893 | *shfactor = 4; | |
894 | else if ((hratio == 4 && vratio == 2) || | |
895 | (hratio == 2 && vratio == 4)) | |
896 | *shfactor = 3; | |
897 | else if ((hratio == 4 && vratio == 1) || | |
898 | (hratio == 1 && vratio == 4) || | |
899 | (hratio == 2 && vratio == 2)) | |
900 | *shfactor = 2; | |
901 | else if (hratio == 1 && vratio == 1) | |
902 | *shfactor = 0; | |
903 | else | |
904 | *shfactor = 1; | |
905 | } | |
906 | ||
907 | static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc, | |
908 | struct drm_exynos_pos *src, struct drm_exynos_pos *dst) | |
909 | { | |
910 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
911 | u32 cfg; | |
912 | u32 src_w, src_h, dst_w, dst_h; | |
913 | int ret = 0; | |
914 | ||
915 | src_w = src->w; | |
916 | src_h = src->h; | |
917 | ||
918 | if (ctx->rotation) { | |
919 | dst_w = dst->h; | |
920 | dst_h = dst->w; | |
921 | } else { | |
922 | dst_w = dst->w; | |
923 | dst_h = dst->h; | |
924 | } | |
925 | ||
926 | ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio); | |
927 | if (ret) { | |
928 | dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); | |
929 | return ret; | |
930 | } | |
931 | ||
932 | ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio); | |
933 | if (ret) { | |
934 | dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); | |
935 | return ret; | |
936 | } | |
937 | ||
cbc4c33d YC |
938 | DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n", |
939 | sc->pre_hratio, sc->pre_vratio); | |
f2646380 EK |
940 | |
941 | sc->main_hratio = (src_w << 16) / dst_w; | |
942 | sc->main_vratio = (src_h << 16) / dst_h; | |
943 | ||
cbc4c33d YC |
944 | DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", |
945 | sc->main_hratio, sc->main_vratio); | |
f2646380 EK |
946 | |
947 | gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio, | |
948 | &sc->pre_shfactor); | |
949 | ||
cbc4c33d | 950 | DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor); |
f2646380 EK |
951 | |
952 | cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) | | |
953 | GSC_PRESC_H_RATIO(sc->pre_hratio) | | |
954 | GSC_PRESC_V_RATIO(sc->pre_vratio)); | |
955 | gsc_write(cfg, GSC_PRE_SCALE_RATIO); | |
956 | ||
957 | return ret; | |
958 | } | |
959 | ||
960 | static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio) | |
961 | { | |
962 | int i, j, k, sc_ratio; | |
963 | ||
964 | if (main_hratio <= GSC_SC_UP_MAX_RATIO) | |
965 | sc_ratio = 0; | |
966 | else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8) | |
967 | sc_ratio = 1; | |
968 | else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8) | |
969 | sc_ratio = 2; | |
970 | else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8) | |
971 | sc_ratio = 3; | |
972 | else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8) | |
973 | sc_ratio = 4; | |
974 | else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8) | |
975 | sc_ratio = 5; | |
976 | else | |
977 | sc_ratio = 6; | |
978 | ||
979 | for (i = 0; i < GSC_COEF_PHASE; i++) | |
980 | for (j = 0; j < GSC_COEF_H_8T; j++) | |
981 | for (k = 0; k < GSC_COEF_DEPTH; k++) | |
982 | gsc_write(h_coef_8t[sc_ratio][i][j], | |
983 | GSC_HCOEF(i, j, k)); | |
984 | } | |
985 | ||
986 | static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio) | |
987 | { | |
988 | int i, j, k, sc_ratio; | |
989 | ||
990 | if (main_vratio <= GSC_SC_UP_MAX_RATIO) | |
991 | sc_ratio = 0; | |
992 | else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8) | |
993 | sc_ratio = 1; | |
994 | else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8) | |
995 | sc_ratio = 2; | |
996 | else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8) | |
997 | sc_ratio = 3; | |
998 | else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8) | |
999 | sc_ratio = 4; | |
1000 | else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8) | |
1001 | sc_ratio = 5; | |
1002 | else | |
1003 | sc_ratio = 6; | |
1004 | ||
1005 | for (i = 0; i < GSC_COEF_PHASE; i++) | |
1006 | for (j = 0; j < GSC_COEF_V_4T; j++) | |
1007 | for (k = 0; k < GSC_COEF_DEPTH; k++) | |
1008 | gsc_write(v_coef_4t[sc_ratio][i][j], | |
1009 | GSC_VCOEF(i, j, k)); | |
1010 | } | |
1011 | ||
1012 | static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc) | |
1013 | { | |
1014 | u32 cfg; | |
1015 | ||
cbc4c33d YC |
1016 | DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", |
1017 | sc->main_hratio, sc->main_vratio); | |
f2646380 EK |
1018 | |
1019 | gsc_set_h_coef(ctx, sc->main_hratio); | |
1020 | cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio); | |
1021 | gsc_write(cfg, GSC_MAIN_H_RATIO); | |
1022 | ||
1023 | gsc_set_v_coef(ctx, sc->main_vratio); | |
1024 | cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio); | |
1025 | gsc_write(cfg, GSC_MAIN_V_RATIO); | |
1026 | } | |
1027 | ||
1028 | static int gsc_dst_set_size(struct device *dev, int swap, | |
1029 | struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) | |
1030 | { | |
1031 | struct gsc_context *ctx = get_gsc_context(dev); | |
1032 | struct drm_exynos_pos img_pos = *pos; | |
1033 | struct gsc_scaler *sc = &ctx->sc; | |
1034 | u32 cfg; | |
1035 | ||
cbc4c33d YC |
1036 | DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n", |
1037 | swap, pos->x, pos->y, pos->w, pos->h); | |
f2646380 EK |
1038 | |
1039 | if (swap) { | |
1040 | img_pos.w = pos->h; | |
1041 | img_pos.h = pos->w; | |
1042 | } | |
1043 | ||
1044 | /* pixel offset */ | |
1045 | cfg = (GSC_DSTIMG_OFFSET_X(pos->x) | | |
1046 | GSC_DSTIMG_OFFSET_Y(pos->y)); | |
1047 | gsc_write(cfg, GSC_DSTIMG_OFFSET); | |
1048 | ||
1049 | /* scaled size */ | |
1050 | cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h)); | |
1051 | gsc_write(cfg, GSC_SCALED_SIZE); | |
1052 | ||
cbc4c33d | 1053 | DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize); |
f2646380 EK |
1054 | |
1055 | /* original size */ | |
1056 | cfg = gsc_read(GSC_DSTIMG_SIZE); | |
1057 | cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | | |
1058 | GSC_DSTIMG_WIDTH_MASK); | |
1059 | cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) | | |
1060 | GSC_DSTIMG_HEIGHT(sz->vsize)); | |
1061 | gsc_write(cfg, GSC_DSTIMG_SIZE); | |
1062 | ||
1063 | cfg = gsc_read(GSC_OUT_CON); | |
1064 | cfg &= ~GSC_OUT_RGB_TYPE_MASK; | |
1065 | ||
cbc4c33d | 1066 | DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range); |
f2646380 EK |
1067 | |
1068 | if (pos->w >= GSC_WIDTH_ITU_709) | |
1069 | if (sc->range) | |
1070 | cfg |= GSC_OUT_RGB_HD_WIDE; | |
1071 | else | |
1072 | cfg |= GSC_OUT_RGB_HD_NARROW; | |
1073 | else | |
1074 | if (sc->range) | |
1075 | cfg |= GSC_OUT_RGB_SD_WIDE; | |
1076 | else | |
1077 | cfg |= GSC_OUT_RGB_SD_NARROW; | |
1078 | ||
1079 | gsc_write(cfg, GSC_OUT_CON); | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static int gsc_dst_get_buf_seq(struct gsc_context *ctx) | |
1085 | { | |
1086 | u32 cfg, i, buf_num = GSC_REG_SZ; | |
1087 | u32 mask = 0x00000001; | |
1088 | ||
1089 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); | |
1090 | ||
1091 | for (i = 0; i < GSC_REG_SZ; i++) | |
1092 | if (cfg & (mask << i)) | |
1093 | buf_num--; | |
1094 | ||
cbc4c33d | 1095 | DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); |
f2646380 EK |
1096 | |
1097 | return buf_num; | |
1098 | } | |
1099 | ||
1100 | static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id, | |
1101 | enum drm_exynos_ipp_buf_type buf_type) | |
1102 | { | |
1103 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
1104 | bool masked; | |
1105 | u32 cfg; | |
1106 | u32 mask = 0x00000001 << buf_id; | |
1107 | int ret = 0; | |
1108 | ||
cbc4c33d | 1109 | DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); |
f2646380 EK |
1110 | |
1111 | mutex_lock(&ctx->lock); | |
1112 | ||
1113 | /* mask register set */ | |
1114 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); | |
1115 | ||
1116 | switch (buf_type) { | |
1117 | case IPP_BUF_ENQUEUE: | |
1118 | masked = false; | |
1119 | break; | |
1120 | case IPP_BUF_DEQUEUE: | |
1121 | masked = true; | |
1122 | break; | |
1123 | default: | |
1124 | dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); | |
1125 | ret = -EINVAL; | |
1126 | goto err_unlock; | |
1127 | } | |
1128 | ||
1129 | /* sequence id */ | |
1130 | cfg &= ~mask; | |
1131 | cfg |= masked << buf_id; | |
1132 | gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); | |
1133 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); | |
1134 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); | |
1135 | ||
1136 | /* interrupt enable */ | |
1137 | if (buf_type == IPP_BUF_ENQUEUE && | |
1138 | gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START) | |
1139 | gsc_handle_irq(ctx, true, false, true); | |
1140 | ||
1141 | /* interrupt disable */ | |
1142 | if (buf_type == IPP_BUF_DEQUEUE && | |
1143 | gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP) | |
1144 | gsc_handle_irq(ctx, false, false, true); | |
1145 | ||
1146 | err_unlock: | |
1147 | mutex_unlock(&ctx->lock); | |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | static int gsc_dst_set_addr(struct device *dev, | |
1152 | struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, | |
1153 | enum drm_exynos_ipp_buf_type buf_type) | |
1154 | { | |
1155 | struct gsc_context *ctx = get_gsc_context(dev); | |
1156 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
7259c3d6 | 1157 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
f2646380 EK |
1158 | struct drm_exynos_ipp_property *property; |
1159 | ||
1160 | if (!c_node) { | |
1161 | DRM_ERROR("failed to get c_node.\n"); | |
1162 | return -EFAULT; | |
1163 | } | |
1164 | ||
1165 | property = &c_node->property; | |
f2646380 | 1166 | |
cbc4c33d | 1167 | DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", |
f2646380 EK |
1168 | property->prop_id, buf_id, buf_type); |
1169 | ||
1170 | if (buf_id > GSC_MAX_DST) { | |
1171 | dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
1175 | /* address register set */ | |
1176 | switch (buf_type) { | |
1177 | case IPP_BUF_ENQUEUE: | |
1178 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], | |
1179 | GSC_OUT_BASE_ADDR_Y(buf_id)); | |
1180 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], | |
1181 | GSC_OUT_BASE_ADDR_CB(buf_id)); | |
1182 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], | |
1183 | GSC_OUT_BASE_ADDR_CR(buf_id)); | |
1184 | break; | |
1185 | case IPP_BUF_DEQUEUE: | |
1186 | gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id)); | |
1187 | gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id)); | |
1188 | gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id)); | |
1189 | break; | |
1190 | default: | |
1191 | /* bypass */ | |
1192 | break; | |
1193 | } | |
1194 | ||
1195 | return gsc_dst_set_buf_seq(ctx, buf_id, buf_type); | |
1196 | } | |
1197 | ||
1198 | static struct exynos_drm_ipp_ops gsc_dst_ops = { | |
1199 | .set_fmt = gsc_dst_set_fmt, | |
1200 | .set_transf = gsc_dst_set_transf, | |
1201 | .set_size = gsc_dst_set_size, | |
1202 | .set_addr = gsc_dst_set_addr, | |
1203 | }; | |
1204 | ||
1205 | static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable) | |
1206 | { | |
cbc4c33d | 1207 | DRM_DEBUG_KMS("enable[%d]\n", enable); |
f2646380 EK |
1208 | |
1209 | if (enable) { | |
1210 | clk_enable(ctx->gsc_clk); | |
1211 | ctx->suspended = false; | |
1212 | } else { | |
1213 | clk_disable(ctx->gsc_clk); | |
1214 | ctx->suspended = true; | |
1215 | } | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static int gsc_get_src_buf_index(struct gsc_context *ctx) | |
1221 | { | |
1222 | u32 cfg, curr_index, i; | |
1223 | u32 buf_id = GSC_MAX_SRC; | |
1224 | int ret; | |
1225 | ||
cbc4c33d | 1226 | DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); |
f2646380 EK |
1227 | |
1228 | cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); | |
1229 | curr_index = GSC_IN_CURR_GET_INDEX(cfg); | |
1230 | ||
1231 | for (i = curr_index; i < GSC_MAX_SRC; i++) { | |
1232 | if (!((cfg >> i) & 0x1)) { | |
1233 | buf_id = i; | |
1234 | break; | |
1235 | } | |
1236 | } | |
1237 | ||
1238 | if (buf_id == GSC_MAX_SRC) { | |
1239 | DRM_ERROR("failed to get in buffer index.\n"); | |
1240 | return -EINVAL; | |
1241 | } | |
1242 | ||
1243 | ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE); | |
1244 | if (ret < 0) { | |
1245 | DRM_ERROR("failed to dequeue.\n"); | |
1246 | return ret; | |
1247 | } | |
1248 | ||
cbc4c33d | 1249 | DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, |
f2646380 EK |
1250 | curr_index, buf_id); |
1251 | ||
1252 | return buf_id; | |
1253 | } | |
1254 | ||
1255 | static int gsc_get_dst_buf_index(struct gsc_context *ctx) | |
1256 | { | |
1257 | u32 cfg, curr_index, i; | |
1258 | u32 buf_id = GSC_MAX_DST; | |
1259 | int ret; | |
1260 | ||
cbc4c33d | 1261 | DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); |
f2646380 EK |
1262 | |
1263 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); | |
1264 | curr_index = GSC_OUT_CURR_GET_INDEX(cfg); | |
1265 | ||
1266 | for (i = curr_index; i < GSC_MAX_DST; i++) { | |
1267 | if (!((cfg >> i) & 0x1)) { | |
1268 | buf_id = i; | |
1269 | break; | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | if (buf_id == GSC_MAX_DST) { | |
1274 | DRM_ERROR("failed to get out buffer index.\n"); | |
1275 | return -EINVAL; | |
1276 | } | |
1277 | ||
1278 | ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE); | |
1279 | if (ret < 0) { | |
1280 | DRM_ERROR("failed to dequeue.\n"); | |
1281 | return ret; | |
1282 | } | |
1283 | ||
cbc4c33d | 1284 | DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, |
f2646380 EK |
1285 | curr_index, buf_id); |
1286 | ||
1287 | return buf_id; | |
1288 | } | |
1289 | ||
1290 | static irqreturn_t gsc_irq_handler(int irq, void *dev_id) | |
1291 | { | |
1292 | struct gsc_context *ctx = dev_id; | |
1293 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
7259c3d6 | 1294 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
f2646380 EK |
1295 | struct drm_exynos_ipp_event_work *event_work = |
1296 | c_node->event_work; | |
1297 | u32 status; | |
1298 | int buf_id[EXYNOS_DRM_OPS_MAX]; | |
1299 | ||
cbc4c33d | 1300 | DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); |
f2646380 EK |
1301 | |
1302 | status = gsc_read(GSC_IRQ); | |
1303 | if (status & GSC_IRQ_STATUS_OR_IRQ) { | |
1304 | dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n", | |
1305 | ctx->id, status); | |
1306 | return IRQ_NONE; | |
1307 | } | |
1308 | ||
1309 | if (status & GSC_IRQ_STATUS_OR_FRM_DONE) { | |
1310 | dev_dbg(ippdrv->dev, "occured frame done at %d, status 0x%x.\n", | |
1311 | ctx->id, status); | |
1312 | ||
1313 | buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx); | |
1314 | if (buf_id[EXYNOS_DRM_OPS_SRC] < 0) | |
1315 | return IRQ_HANDLED; | |
1316 | ||
1317 | buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx); | |
1318 | if (buf_id[EXYNOS_DRM_OPS_DST] < 0) | |
1319 | return IRQ_HANDLED; | |
1320 | ||
cbc4c33d | 1321 | DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n", |
f2646380 EK |
1322 | buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]); |
1323 | ||
1324 | event_work->ippdrv = ippdrv; | |
1325 | event_work->buf_id[EXYNOS_DRM_OPS_SRC] = | |
1326 | buf_id[EXYNOS_DRM_OPS_SRC]; | |
1327 | event_work->buf_id[EXYNOS_DRM_OPS_DST] = | |
1328 | buf_id[EXYNOS_DRM_OPS_DST]; | |
1329 | queue_work(ippdrv->event_workq, | |
1330 | (struct work_struct *)event_work); | |
1331 | } | |
1332 | ||
1333 | return IRQ_HANDLED; | |
1334 | } | |
1335 | ||
1336 | static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) | |
1337 | { | |
1338 | struct drm_exynos_ipp_prop_list *prop_list; | |
1339 | ||
f2646380 EK |
1340 | prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL); |
1341 | if (!prop_list) { | |
1342 | DRM_ERROR("failed to alloc property list.\n"); | |
1343 | return -ENOMEM; | |
1344 | } | |
1345 | ||
1346 | prop_list->version = 1; | |
1347 | prop_list->writeback = 1; | |
1348 | prop_list->refresh_min = GSC_REFRESH_MIN; | |
1349 | prop_list->refresh_max = GSC_REFRESH_MAX; | |
1350 | prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) | | |
1351 | (1 << EXYNOS_DRM_FLIP_HORIZONTAL); | |
1352 | prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | | |
1353 | (1 << EXYNOS_DRM_DEGREE_90) | | |
1354 | (1 << EXYNOS_DRM_DEGREE_180) | | |
1355 | (1 << EXYNOS_DRM_DEGREE_270); | |
1356 | prop_list->csc = 1; | |
1357 | prop_list->crop = 1; | |
1358 | prop_list->crop_max.hsize = GSC_CROP_MAX; | |
1359 | prop_list->crop_max.vsize = GSC_CROP_MAX; | |
1360 | prop_list->crop_min.hsize = GSC_CROP_MIN; | |
1361 | prop_list->crop_min.vsize = GSC_CROP_MIN; | |
1362 | prop_list->scale = 1; | |
1363 | prop_list->scale_max.hsize = GSC_SCALE_MAX; | |
1364 | prop_list->scale_max.vsize = GSC_SCALE_MAX; | |
1365 | prop_list->scale_min.hsize = GSC_SCALE_MIN; | |
1366 | prop_list->scale_min.vsize = GSC_SCALE_MIN; | |
1367 | ||
1368 | ippdrv->prop_list = prop_list; | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip) | |
1374 | { | |
1375 | switch (flip) { | |
1376 | case EXYNOS_DRM_FLIP_NONE: | |
1377 | case EXYNOS_DRM_FLIP_VERTICAL: | |
1378 | case EXYNOS_DRM_FLIP_HORIZONTAL: | |
4f21877c | 1379 | case EXYNOS_DRM_FLIP_BOTH: |
f2646380 EK |
1380 | return true; |
1381 | default: | |
cbc4c33d | 1382 | DRM_DEBUG_KMS("invalid flip\n"); |
f2646380 EK |
1383 | return false; |
1384 | } | |
1385 | } | |
1386 | ||
1387 | static int gsc_ippdrv_check_property(struct device *dev, | |
1388 | struct drm_exynos_ipp_property *property) | |
1389 | { | |
1390 | struct gsc_context *ctx = get_gsc_context(dev); | |
1391 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
1392 | struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list; | |
1393 | struct drm_exynos_ipp_config *config; | |
1394 | struct drm_exynos_pos *pos; | |
1395 | struct drm_exynos_sz *sz; | |
1396 | bool swap; | |
1397 | int i; | |
1398 | ||
f2646380 EK |
1399 | for_each_ipp_ops(i) { |
1400 | if ((i == EXYNOS_DRM_OPS_SRC) && | |
1401 | (property->cmd == IPP_CMD_WB)) | |
1402 | continue; | |
1403 | ||
1404 | config = &property->config[i]; | |
1405 | pos = &config->pos; | |
1406 | sz = &config->sz; | |
1407 | ||
1408 | /* check for flip */ | |
1409 | if (!gsc_check_drm_flip(config->flip)) { | |
1410 | DRM_ERROR("invalid flip.\n"); | |
1411 | goto err_property; | |
1412 | } | |
1413 | ||
1414 | /* check for degree */ | |
1415 | switch (config->degree) { | |
1416 | case EXYNOS_DRM_DEGREE_90: | |
1417 | case EXYNOS_DRM_DEGREE_270: | |
1418 | swap = true; | |
1419 | break; | |
1420 | case EXYNOS_DRM_DEGREE_0: | |
1421 | case EXYNOS_DRM_DEGREE_180: | |
1422 | swap = false; | |
1423 | break; | |
1424 | default: | |
1425 | DRM_ERROR("invalid degree.\n"); | |
1426 | goto err_property; | |
1427 | } | |
1428 | ||
1429 | /* check for buffer bound */ | |
1430 | if ((pos->x + pos->w > sz->hsize) || | |
1431 | (pos->y + pos->h > sz->vsize)) { | |
1432 | DRM_ERROR("out of buf bound.\n"); | |
1433 | goto err_property; | |
1434 | } | |
1435 | ||
1436 | /* check for crop */ | |
1437 | if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { | |
1438 | if (swap) { | |
1439 | if ((pos->h < pp->crop_min.hsize) || | |
1440 | (sz->vsize > pp->crop_max.hsize) || | |
1441 | (pos->w < pp->crop_min.vsize) || | |
1442 | (sz->hsize > pp->crop_max.vsize)) { | |
1443 | DRM_ERROR("out of crop size.\n"); | |
1444 | goto err_property; | |
1445 | } | |
1446 | } else { | |
1447 | if ((pos->w < pp->crop_min.hsize) || | |
1448 | (sz->hsize > pp->crop_max.hsize) || | |
1449 | (pos->h < pp->crop_min.vsize) || | |
1450 | (sz->vsize > pp->crop_max.vsize)) { | |
1451 | DRM_ERROR("out of crop size.\n"); | |
1452 | goto err_property; | |
1453 | } | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | /* check for scale */ | |
1458 | if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { | |
1459 | if (swap) { | |
1460 | if ((pos->h < pp->scale_min.hsize) || | |
1461 | (sz->vsize > pp->scale_max.hsize) || | |
1462 | (pos->w < pp->scale_min.vsize) || | |
1463 | (sz->hsize > pp->scale_max.vsize)) { | |
1464 | DRM_ERROR("out of scale size.\n"); | |
1465 | goto err_property; | |
1466 | } | |
1467 | } else { | |
1468 | if ((pos->w < pp->scale_min.hsize) || | |
1469 | (sz->hsize > pp->scale_max.hsize) || | |
1470 | (pos->h < pp->scale_min.vsize) || | |
1471 | (sz->vsize > pp->scale_max.vsize)) { | |
1472 | DRM_ERROR("out of scale size.\n"); | |
1473 | goto err_property; | |
1474 | } | |
1475 | } | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | return 0; | |
1480 | ||
1481 | err_property: | |
1482 | for_each_ipp_ops(i) { | |
1483 | if ((i == EXYNOS_DRM_OPS_SRC) && | |
1484 | (property->cmd == IPP_CMD_WB)) | |
1485 | continue; | |
1486 | ||
1487 | config = &property->config[i]; | |
1488 | pos = &config->pos; | |
1489 | sz = &config->sz; | |
1490 | ||
1491 | DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", | |
1492 | i ? "dst" : "src", config->flip, config->degree, | |
1493 | pos->x, pos->y, pos->w, pos->h, | |
1494 | sz->hsize, sz->vsize); | |
1495 | } | |
1496 | ||
1497 | return -EINVAL; | |
1498 | } | |
1499 | ||
1500 | ||
1501 | static int gsc_ippdrv_reset(struct device *dev) | |
1502 | { | |
1503 | struct gsc_context *ctx = get_gsc_context(dev); | |
1504 | struct gsc_scaler *sc = &ctx->sc; | |
1505 | int ret; | |
1506 | ||
f2646380 EK |
1507 | /* reset h/w block */ |
1508 | ret = gsc_sw_reset(ctx); | |
1509 | if (ret < 0) { | |
1510 | dev_err(dev, "failed to reset hardware.\n"); | |
1511 | return ret; | |
1512 | } | |
1513 | ||
1514 | /* scaler setting */ | |
1515 | memset(&ctx->sc, 0x0, sizeof(ctx->sc)); | |
1516 | sc->range = true; | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) | |
1522 | { | |
1523 | struct gsc_context *ctx = get_gsc_context(dev); | |
1524 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
7259c3d6 | 1525 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
f2646380 EK |
1526 | struct drm_exynos_ipp_property *property; |
1527 | struct drm_exynos_ipp_config *config; | |
1528 | struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; | |
1529 | struct drm_exynos_ipp_set_wb set_wb; | |
1530 | u32 cfg; | |
1531 | int ret, i; | |
1532 | ||
cbc4c33d | 1533 | DRM_DEBUG_KMS("cmd[%d]\n", cmd); |
f2646380 EK |
1534 | |
1535 | if (!c_node) { | |
1536 | DRM_ERROR("failed to get c_node.\n"); | |
1537 | return -EINVAL; | |
1538 | } | |
1539 | ||
1540 | property = &c_node->property; | |
f2646380 EK |
1541 | |
1542 | gsc_handle_irq(ctx, true, false, true); | |
1543 | ||
1544 | for_each_ipp_ops(i) { | |
1545 | config = &property->config[i]; | |
1546 | img_pos[i] = config->pos; | |
1547 | } | |
1548 | ||
1549 | switch (cmd) { | |
1550 | case IPP_CMD_M2M: | |
1551 | /* enable one shot */ | |
1552 | cfg = gsc_read(GSC_ENABLE); | |
1553 | cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK | | |
1554 | GSC_ENABLE_CLK_GATE_MODE_MASK); | |
1555 | cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT; | |
1556 | gsc_write(cfg, GSC_ENABLE); | |
1557 | ||
1558 | /* src dma memory */ | |
1559 | cfg = gsc_read(GSC_IN_CON); | |
1560 | cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); | |
1561 | cfg |= GSC_IN_PATH_MEMORY; | |
1562 | gsc_write(cfg, GSC_IN_CON); | |
1563 | ||
1564 | /* dst dma memory */ | |
1565 | cfg = gsc_read(GSC_OUT_CON); | |
1566 | cfg |= GSC_OUT_PATH_MEMORY; | |
1567 | gsc_write(cfg, GSC_OUT_CON); | |
1568 | break; | |
1569 | case IPP_CMD_WB: | |
1570 | set_wb.enable = 1; | |
1571 | set_wb.refresh = property->refresh_rate; | |
1572 | gsc_set_gscblk_fimd_wb(ctx, set_wb.enable); | |
1573 | exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); | |
1574 | ||
1575 | /* src local path */ | |
5bbea0c4 | 1576 | cfg = gsc_read(GSC_IN_CON); |
f2646380 EK |
1577 | cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); |
1578 | cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB); | |
1579 | gsc_write(cfg, GSC_IN_CON); | |
1580 | ||
1581 | /* dst dma memory */ | |
1582 | cfg = gsc_read(GSC_OUT_CON); | |
1583 | cfg |= GSC_OUT_PATH_MEMORY; | |
1584 | gsc_write(cfg, GSC_OUT_CON); | |
1585 | break; | |
1586 | case IPP_CMD_OUTPUT: | |
1587 | /* src dma memory */ | |
1588 | cfg = gsc_read(GSC_IN_CON); | |
1589 | cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); | |
1590 | cfg |= GSC_IN_PATH_MEMORY; | |
1591 | gsc_write(cfg, GSC_IN_CON); | |
1592 | ||
1593 | /* dst local path */ | |
1594 | cfg = gsc_read(GSC_OUT_CON); | |
1595 | cfg |= GSC_OUT_PATH_MEMORY; | |
1596 | gsc_write(cfg, GSC_OUT_CON); | |
1597 | break; | |
1598 | default: | |
1599 | ret = -EINVAL; | |
1600 | dev_err(dev, "invalid operations.\n"); | |
1601 | return ret; | |
1602 | } | |
1603 | ||
1604 | ret = gsc_set_prescaler(ctx, &ctx->sc, | |
1605 | &img_pos[EXYNOS_DRM_OPS_SRC], | |
1606 | &img_pos[EXYNOS_DRM_OPS_DST]); | |
1607 | if (ret) { | |
1608 | dev_err(dev, "failed to set precalser.\n"); | |
1609 | return ret; | |
1610 | } | |
1611 | ||
1612 | gsc_set_scaler(ctx, &ctx->sc); | |
1613 | ||
1614 | cfg = gsc_read(GSC_ENABLE); | |
1615 | cfg |= GSC_ENABLE_ON; | |
1616 | gsc_write(cfg, GSC_ENABLE); | |
1617 | ||
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) | |
1622 | { | |
1623 | struct gsc_context *ctx = get_gsc_context(dev); | |
1624 | struct drm_exynos_ipp_set_wb set_wb = {0, 0}; | |
1625 | u32 cfg; | |
1626 | ||
cbc4c33d | 1627 | DRM_DEBUG_KMS("cmd[%d]\n", cmd); |
f2646380 EK |
1628 | |
1629 | switch (cmd) { | |
1630 | case IPP_CMD_M2M: | |
1631 | /* bypass */ | |
1632 | break; | |
1633 | case IPP_CMD_WB: | |
1634 | gsc_set_gscblk_fimd_wb(ctx, set_wb.enable); | |
1635 | exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); | |
1636 | break; | |
1637 | case IPP_CMD_OUTPUT: | |
1638 | default: | |
1639 | dev_err(dev, "invalid operations.\n"); | |
1640 | break; | |
1641 | } | |
1642 | ||
1643 | gsc_handle_irq(ctx, false, false, true); | |
1644 | ||
1645 | /* reset sequence */ | |
1646 | gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK); | |
1647 | gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK); | |
1648 | gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK); | |
1649 | ||
1650 | cfg = gsc_read(GSC_ENABLE); | |
1651 | cfg &= ~GSC_ENABLE_ON; | |
1652 | gsc_write(cfg, GSC_ENABLE); | |
1653 | } | |
1654 | ||
56550d94 | 1655 | static int gsc_probe(struct platform_device *pdev) |
f2646380 EK |
1656 | { |
1657 | struct device *dev = &pdev->dev; | |
1658 | struct gsc_context *ctx; | |
1659 | struct resource *res; | |
1660 | struct exynos_drm_ippdrv *ippdrv; | |
1661 | int ret; | |
1662 | ||
1663 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
1664 | if (!ctx) | |
1665 | return -ENOMEM; | |
1666 | ||
1667 | /* clock control */ | |
5cbd419c | 1668 | ctx->gsc_clk = devm_clk_get(dev, "gscl"); |
f2646380 EK |
1669 | if (IS_ERR(ctx->gsc_clk)) { |
1670 | dev_err(dev, "failed to get gsc clock.\n"); | |
cfdee8f4 | 1671 | return PTR_ERR(ctx->gsc_clk); |
f2646380 EK |
1672 | } |
1673 | ||
1674 | /* resource memory */ | |
1675 | ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1676 | ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); |
1677 | if (IS_ERR(ctx->regs)) | |
1678 | return PTR_ERR(ctx->regs); | |
f2646380 EK |
1679 | |
1680 | /* resource irq */ | |
1681 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1682 | if (!res) { | |
1683 | dev_err(dev, "failed to request irq resource.\n"); | |
5cbd419c | 1684 | return -ENOENT; |
f2646380 EK |
1685 | } |
1686 | ||
1687 | ctx->irq = res->start; | |
dcb9a7c7 | 1688 | ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler, |
f2646380 EK |
1689 | IRQF_ONESHOT, "drm_gsc", ctx); |
1690 | if (ret < 0) { | |
1691 | dev_err(dev, "failed to request irq.\n"); | |
5cbd419c | 1692 | return ret; |
f2646380 EK |
1693 | } |
1694 | ||
1695 | /* context initailization */ | |
1696 | ctx->id = pdev->id; | |
1697 | ||
1698 | ippdrv = &ctx->ippdrv; | |
1699 | ippdrv->dev = dev; | |
1700 | ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops; | |
1701 | ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops; | |
1702 | ippdrv->check_property = gsc_ippdrv_check_property; | |
1703 | ippdrv->reset = gsc_ippdrv_reset; | |
1704 | ippdrv->start = gsc_ippdrv_start; | |
1705 | ippdrv->stop = gsc_ippdrv_stop; | |
1706 | ret = gsc_init_prop_list(ippdrv); | |
1707 | if (ret < 0) { | |
1708 | dev_err(dev, "failed to init property list.\n"); | |
dcb9a7c7 | 1709 | return ret; |
f2646380 EK |
1710 | } |
1711 | ||
cbc4c33d | 1712 | DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv); |
f2646380 EK |
1713 | |
1714 | mutex_init(&ctx->lock); | |
1715 | platform_set_drvdata(pdev, ctx); | |
1716 | ||
1717 | pm_runtime_set_active(dev); | |
1718 | pm_runtime_enable(dev); | |
1719 | ||
1720 | ret = exynos_drm_ippdrv_register(ippdrv); | |
1721 | if (ret < 0) { | |
1722 | dev_err(dev, "failed to register drm gsc device.\n"); | |
1723 | goto err_ippdrv_register; | |
1724 | } | |
1725 | ||
d873ab99 | 1726 | dev_info(dev, "drm gsc registered successfully.\n"); |
f2646380 EK |
1727 | |
1728 | return 0; | |
1729 | ||
1730 | err_ippdrv_register: | |
f2646380 | 1731 | pm_runtime_disable(dev); |
f2646380 EK |
1732 | return ret; |
1733 | } | |
1734 | ||
56550d94 | 1735 | static int gsc_remove(struct platform_device *pdev) |
f2646380 EK |
1736 | { |
1737 | struct device *dev = &pdev->dev; | |
1738 | struct gsc_context *ctx = get_gsc_context(dev); | |
1739 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; | |
1740 | ||
f2646380 EK |
1741 | exynos_drm_ippdrv_unregister(ippdrv); |
1742 | mutex_destroy(&ctx->lock); | |
1743 | ||
1744 | pm_runtime_set_suspended(dev); | |
1745 | pm_runtime_disable(dev); | |
1746 | ||
f2646380 EK |
1747 | return 0; |
1748 | } | |
1749 | ||
1750 | #ifdef CONFIG_PM_SLEEP | |
1751 | static int gsc_suspend(struct device *dev) | |
1752 | { | |
1753 | struct gsc_context *ctx = get_gsc_context(dev); | |
1754 | ||
cbc4c33d | 1755 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
f2646380 EK |
1756 | |
1757 | if (pm_runtime_suspended(dev)) | |
1758 | return 0; | |
1759 | ||
1760 | return gsc_clk_ctrl(ctx, false); | |
1761 | } | |
1762 | ||
1763 | static int gsc_resume(struct device *dev) | |
1764 | { | |
1765 | struct gsc_context *ctx = get_gsc_context(dev); | |
1766 | ||
cbc4c33d | 1767 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
f2646380 EK |
1768 | |
1769 | if (!pm_runtime_suspended(dev)) | |
1770 | return gsc_clk_ctrl(ctx, true); | |
1771 | ||
1772 | return 0; | |
1773 | } | |
1774 | #endif | |
1775 | ||
1776 | #ifdef CONFIG_PM_RUNTIME | |
1777 | static int gsc_runtime_suspend(struct device *dev) | |
1778 | { | |
1779 | struct gsc_context *ctx = get_gsc_context(dev); | |
1780 | ||
cbc4c33d | 1781 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
f2646380 EK |
1782 | |
1783 | return gsc_clk_ctrl(ctx, false); | |
1784 | } | |
1785 | ||
1786 | static int gsc_runtime_resume(struct device *dev) | |
1787 | { | |
1788 | struct gsc_context *ctx = get_gsc_context(dev); | |
1789 | ||
bca34c9a | 1790 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
f2646380 EK |
1791 | |
1792 | return gsc_clk_ctrl(ctx, true); | |
1793 | } | |
1794 | #endif | |
1795 | ||
1796 | static const struct dev_pm_ops gsc_pm_ops = { | |
1797 | SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume) | |
1798 | SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL) | |
1799 | }; | |
1800 | ||
1801 | struct platform_driver gsc_driver = { | |
1802 | .probe = gsc_probe, | |
56550d94 | 1803 | .remove = gsc_remove, |
f2646380 EK |
1804 | .driver = { |
1805 | .name = "exynos-drm-gsc", | |
1806 | .owner = THIS_MODULE, | |
1807 | .pm = &gsc_pm_ops, | |
1808 | }, | |
1809 | }; | |
1810 |