Commit | Line | Data |
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109eee2f JW |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Freescale DCU drm device driver | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/regmap.h> | |
13 | ||
14 | #include <drm/drmP.h> | |
15 | #include <drm/drm_atomic_helper.h> | |
16 | #include <drm/drm_crtc.h> | |
17 | #include <drm/drm_crtc_helper.h> | |
18 | #include <drm/drm_fb_cma_helper.h> | |
19 | #include <drm/drm_gem_cma_helper.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | ||
22 | #include "fsl_dcu_drm_drv.h" | |
23 | #include "fsl_dcu_drm_plane.h" | |
24 | ||
25 | static int fsl_dcu_drm_plane_index(struct drm_plane *plane) | |
26 | { | |
27 | struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; | |
28 | unsigned int total_layer = fsl_dev->soc->total_layer; | |
29 | unsigned int index; | |
30 | ||
31 | index = drm_plane_index(plane); | |
32 | if (index < total_layer) | |
33 | return total_layer - index - 1; | |
34 | ||
35 | dev_err(fsl_dev->dev, "No more layer left\n"); | |
36 | return -EINVAL; | |
37 | } | |
38 | ||
39 | static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane, | |
40 | struct drm_plane_state *state) | |
41 | { | |
42 | struct drm_framebuffer *fb = state->fb; | |
43 | ||
a36c9867 MY |
44 | if (!state->fb || !state->crtc) |
45 | return 0; | |
46 | ||
109eee2f JW |
47 | switch (fb->pixel_format) { |
48 | case DRM_FORMAT_RGB565: | |
49 | case DRM_FORMAT_RGB888: | |
69855819 | 50 | case DRM_FORMAT_XRGB8888: |
109eee2f | 51 | case DRM_FORMAT_ARGB8888: |
69855819 SA |
52 | case DRM_FORMAT_XRGB4444: |
53 | case DRM_FORMAT_ARGB4444: | |
54 | case DRM_FORMAT_XRGB1555: | |
109eee2f JW |
55 | case DRM_FORMAT_ARGB1555: |
56 | case DRM_FORMAT_YUV422: | |
57 | return 0; | |
58 | default: | |
59 | return -EINVAL; | |
60 | } | |
61 | } | |
62 | ||
63 | static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane, | |
64 | struct drm_plane_state *old_state) | |
65 | { | |
66 | struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; | |
14d11b8d | 67 | unsigned int value; |
e291d298 | 68 | int index; |
109eee2f JW |
69 | |
70 | index = fsl_dcu_drm_plane_index(plane); | |
71 | if (index < 0) | |
72 | return; | |
73 | ||
e291d298 | 74 | regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value); |
109eee2f | 75 | value &= ~DCU_LAYER_EN; |
e291d298 | 76 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value); |
109eee2f JW |
77 | } |
78 | ||
79 | static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, | |
80 | struct drm_plane_state *old_state) | |
81 | ||
82 | { | |
83 | struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; | |
84 | struct drm_plane_state *state = plane->state; | |
85 | struct drm_framebuffer *fb = plane->state->fb; | |
86 | struct drm_gem_cma_object *gem; | |
69855819 | 87 | unsigned int alpha = DCU_LAYER_AB_NONE, bpp; |
e291d298 | 88 | int index; |
109eee2f JW |
89 | |
90 | if (!fb) | |
91 | return; | |
92 | ||
93 | index = fsl_dcu_drm_plane_index(plane); | |
94 | if (index < 0) | |
95 | return; | |
96 | ||
97 | gem = drm_fb_cma_get_gem_obj(fb, 0); | |
98 | ||
99 | switch (fb->pixel_format) { | |
100 | case DRM_FORMAT_RGB565: | |
101 | bpp = FSL_DCU_RGB565; | |
109eee2f JW |
102 | break; |
103 | case DRM_FORMAT_RGB888: | |
104 | bpp = FSL_DCU_RGB888; | |
109eee2f JW |
105 | break; |
106 | case DRM_FORMAT_ARGB8888: | |
69855819 SA |
107 | alpha = DCU_LAYER_AB_WHOLE_FRAME; |
108 | /* fall-through */ | |
109 | case DRM_FORMAT_XRGB8888: | |
109eee2f | 110 | bpp = FSL_DCU_ARGB8888; |
109eee2f | 111 | break; |
69855819 SA |
112 | case DRM_FORMAT_ARGB4444: |
113 | alpha = DCU_LAYER_AB_WHOLE_FRAME; | |
114 | /* fall-through */ | |
115 | case DRM_FORMAT_XRGB4444: | |
109eee2f | 116 | bpp = FSL_DCU_ARGB4444; |
109eee2f JW |
117 | break; |
118 | case DRM_FORMAT_ARGB1555: | |
69855819 SA |
119 | alpha = DCU_LAYER_AB_WHOLE_FRAME; |
120 | /* fall-through */ | |
121 | case DRM_FORMAT_XRGB1555: | |
109eee2f | 122 | bpp = FSL_DCU_ARGB1555; |
109eee2f JW |
123 | break; |
124 | case DRM_FORMAT_YUV422: | |
125 | bpp = FSL_DCU_YUV422; | |
109eee2f JW |
126 | break; |
127 | default: | |
128 | return; | |
129 | } | |
130 | ||
e291d298 SA |
131 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1), |
132 | DCU_LAYER_HEIGHT(state->crtc_h) | | |
133 | DCU_LAYER_WIDTH(state->crtc_w)); | |
134 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2), | |
135 | DCU_LAYER_POSY(state->crtc_y) | | |
136 | DCU_LAYER_POSX(state->crtc_x)); | |
137 | regmap_write(fsl_dev->regmap, | |
138 | DCU_CTRLDESCLN(index, 3), gem->paddr); | |
139 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), | |
140 | DCU_LAYER_EN | | |
69855819 | 141 | DCU_LAYER_TRANS(0xff) | |
e291d298 | 142 | DCU_LAYER_BPP(bpp) | |
69855819 | 143 | alpha); |
e291d298 SA |
144 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5), |
145 | DCU_LAYER_CKMAX_R(0xFF) | | |
146 | DCU_LAYER_CKMAX_G(0xFF) | | |
147 | DCU_LAYER_CKMAX_B(0xFF)); | |
148 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6), | |
149 | DCU_LAYER_CKMIN_R(0) | | |
150 | DCU_LAYER_CKMIN_G(0) | | |
151 | DCU_LAYER_CKMIN_B(0)); | |
152 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0); | |
153 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8), | |
154 | DCU_LAYER_FG_FCOLOR(0)); | |
155 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9), | |
156 | DCU_LAYER_BG_BCOLOR(0)); | |
157 | ||
109eee2f | 158 | if (!strcmp(fsl_dev->soc->name, "ls1021a")) { |
e291d298 SA |
159 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10), |
160 | DCU_LAYER_POST_SKIP(0) | | |
161 | DCU_LAYER_PRE_SKIP(0)); | |
109eee2f | 162 | } |
e291d298 SA |
163 | regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, |
164 | DCU_MODE_DCU_MODE_MASK, | |
165 | DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); | |
166 | regmap_write(fsl_dev->regmap, | |
167 | DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG); | |
109eee2f | 168 | |
e291d298 | 169 | return; |
109eee2f JW |
170 | } |
171 | ||
109eee2f JW |
172 | static const struct drm_plane_helper_funcs fsl_dcu_drm_plane_helper_funcs = { |
173 | .atomic_check = fsl_dcu_drm_plane_atomic_check, | |
174 | .atomic_disable = fsl_dcu_drm_plane_atomic_disable, | |
175 | .atomic_update = fsl_dcu_drm_plane_atomic_update, | |
109eee2f JW |
176 | }; |
177 | ||
178 | static void fsl_dcu_drm_plane_destroy(struct drm_plane *plane) | |
179 | { | |
180 | drm_plane_cleanup(plane); | |
72cc05a5 | 181 | kfree(plane); |
109eee2f JW |
182 | } |
183 | ||
184 | static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = { | |
185 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
186 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
187 | .destroy = fsl_dcu_drm_plane_destroy, | |
188 | .disable_plane = drm_atomic_helper_disable_plane, | |
189 | .reset = drm_atomic_helper_plane_reset, | |
190 | .update_plane = drm_atomic_helper_update_plane, | |
191 | }; | |
192 | ||
193 | static const u32 fsl_dcu_drm_plane_formats[] = { | |
194 | DRM_FORMAT_RGB565, | |
195 | DRM_FORMAT_RGB888, | |
69855819 | 196 | DRM_FORMAT_XRGB8888, |
109eee2f | 197 | DRM_FORMAT_ARGB8888, |
69855819 | 198 | DRM_FORMAT_XRGB4444, |
109eee2f | 199 | DRM_FORMAT_ARGB4444, |
69855819 | 200 | DRM_FORMAT_XRGB1555, |
109eee2f JW |
201 | DRM_FORMAT_ARGB1555, |
202 | DRM_FORMAT_YUV422, | |
203 | }; | |
204 | ||
1277f802 SA |
205 | void fsl_dcu_drm_init_planes(struct drm_device *dev) |
206 | { | |
207 | struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; | |
208 | int i, j; | |
209 | ||
210 | for (i = 0; i < fsl_dev->soc->total_layer; i++) { | |
211 | for (j = 1; j <= fsl_dev->soc->layer_regs; j++) | |
212 | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0); | |
213 | } | |
214 | regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, | |
215 | DCU_MODE_DCU_MODE_MASK, | |
216 | DCU_MODE_DCU_MODE(DCU_MODE_OFF)); | |
217 | regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, | |
218 | DCU_UPDATE_MODE_READREG); | |
219 | } | |
220 | ||
109eee2f JW |
221 | struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev) |
222 | { | |
223 | struct drm_plane *primary; | |
224 | int ret; | |
225 | ||
226 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
227 | if (!primary) { | |
228 | DRM_DEBUG_KMS("Failed to allocate primary plane\n"); | |
229 | return NULL; | |
230 | } | |
231 | ||
232 | /* possible_crtc's will be filled in later by crtc_init */ | |
233 | ret = drm_universal_plane_init(dev, primary, 0, | |
234 | &fsl_dcu_drm_plane_funcs, | |
235 | fsl_dcu_drm_plane_formats, | |
236 | ARRAY_SIZE(fsl_dcu_drm_plane_formats), | |
b0b3b795 | 237 | DRM_PLANE_TYPE_PRIMARY, NULL); |
109eee2f JW |
238 | if (ret) { |
239 | kfree(primary); | |
240 | primary = NULL; | |
241 | } | |
242 | drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs); | |
243 | ||
244 | return primary; | |
245 | } |