[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_device.c

/**************************************************************************
 * Copyright (c) 2011, Intel Corporation.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 **************************************************************************/

#include <linux/backlight.h>
#include <drm/drmP.h>
#include <drm/drm.h>
#include <drm/gma_drm.h>
#include "psb_drv.h"
#include "psb_reg.h"
#include "psb_intel_reg.h"
#include "intel_bios.h"
#include "cdv_device.h"

#define VGA_SR_INDEX		0x3c4
#define VGA_SR_DATA		0x3c5

static void cdv_disable_vga(struct drm_device *dev)
{
	u8 sr1;
	u32 vga_reg;

	vga_reg = VGACNTRL;

	outb(1, VGA_SR_INDEX);
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	udelay(300);

	REG_WRITE(vga_reg, VGA_DISP_DISABLE);
	REG_READ(vga_reg);
}

static int cdv_output_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;

	drm_mode_create_scaling_mode_property(dev);

	cdv_disable_vga(dev);

	cdv_intel_crt_init(dev, &dev_priv->mode_dev);
	cdv_intel_lvds_init(dev, &dev_priv->mode_dev);

	/* These bits indicate HDMI not SDVO on CDV */
	if (REG_READ(SDVOB) & SDVO_DETECTED) {
		cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
		if (REG_READ(DP_B) & DP_DETECTED)
			cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);
	}

	if (REG_READ(SDVOC) & SDVO_DETECTED) {
		cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
		if (REG_READ(DP_C) & DP_DETECTED)
			cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);
	}
	return 0;
}

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE

/*
 *	Cedartrail Backlght Interfaces
 */

static struct backlight_device *cdv_backlight_device;

static int cdv_backlight_combination_mode(struct drm_device *dev)
{
	return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
}

static u32 cdv_get_max_backlight(struct drm_device *dev)
{
	u32 max = REG_READ(BLC_PWM_CTL);

	if (max == 0) {
		DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
		/* i915 does this, I believe which means that we should not
		 * smash PWM control as firmware will take control of it. */
		return 1;
	}

	max >>= 16;
	if (cdv_backlight_combination_mode(dev))
		max *= 0xff;
	return max;
}

static int cdv_get_brightness(struct backlight_device *bd)
{
	struct drm_device *dev = bl_get_data(bd);
	u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

	if (cdv_backlight_combination_mode(dev)) {
		u8 lbpc;

		val &= ~1;
		pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
		val *= lbpc;
	}
	return (val * 100)/cdv_get_max_backlight(dev);

}

static int cdv_set_brightness(struct backlight_device *bd)
{
	struct drm_device *dev = bl_get_data(bd);
	int level = bd->props.brightness;
	u32 blc_pwm_ctl;

	/* Percentage 1-100% being valid */
	if (level < 1)
		level = 1;

	level *= cdv_get_max_backlight(dev);
	level /= 100;

	if (cdv_backlight_combination_mode(dev)) {
		u32 max = cdv_get_max_backlight(dev);
		u8 lbpc;

		lbpc = level * 0xfe / max + 1;
		level /= lbpc;

		pci_write_config_byte(dev->pdev, 0xF4, lbpc);
	}

	blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
	REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
				(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
	return 0;
}

static const struct backlight_ops cdv_ops = {
	.get_brightness = cdv_get_brightness,
	.update_status  = cdv_set_brightness,
};

static int cdv_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct backlight_properties props;

	memset(&props, 0, sizeof(struct backlight_properties));
	props.max_brightness = 100;
	props.type = BACKLIGHT_PLATFORM;

	cdv_backlight_device = backlight_device_register("psb-bl",
					NULL, (void *)dev, &cdv_ops, &props);
	if (IS_ERR(cdv_backlight_device))
		return PTR_ERR(cdv_backlight_device);

	cdv_backlight_device->props.brightness =
			cdv_get_brightness(cdv_backlight_device);
	backlight_update_status(cdv_backlight_device);
	dev_priv->backlight_device = cdv_backlight_device;
	dev_priv->backlight_enabled = true;
	return 0;
}

#endif

/*
 *	Provide the Cedarview specific chip logic and low level methods
 *	for power management
 *
 *	FIXME: we need to implement the apm/ospm base management bits
 *	for this and the MID devices.
 */

static inline u32 CDV_MSG_READ32(uint port, uint offset)
{
	int mcr = (0x10<<24) | (port << 16) | (offset << 8);
	uint32_t ret_val = 0;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	pci_write_config_dword(pci_root, 0xD0, mcr);
	pci_read_config_dword(pci_root, 0xD4, &ret_val);
	pci_dev_put(pci_root);
	return ret_val;
}

static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
{
	int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	pci_write_config_dword(pci_root, 0xD4, value);
	pci_write_config_dword(pci_root, 0xD0, mcr);
	pci_dev_put(pci_root);
}

#define PSB_PM_SSC			0x20
#define PSB_PM_SSS			0x30
#define PSB_PWRGT_GFX_ON		0x02
#define PSB_PWRGT_GFX_OFF		0x01
#define PSB_PWRGT_GFX_D0		0x00
#define PSB_PWRGT_GFX_D3		0x03

static void cdv_init_pm(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt;
	int i;

	dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
							PSB_APMBA) & 0xFFFF;
	dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
							PSB_OSPMBA) & 0xFFFF;

	/* Power status */
	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);

	/* Enable the GPU */
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_ON;
	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	/* Wait for the GPU power */
	for (i = 0; i < 5; i++) {
		u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
			return;
		udelay(10);
	}
	dev_err(dev->dev, "GPU: power management timed out.\n");
}

static void cdv_errata(struct drm_device *dev)
{
	/* Disable bonus launch.
	 *	CPU and GPU competes for memory and display misses updates and
	 *	flickers. Worst with dual core, dual displays.
	 *
	 *	Fixes were done to Win 7 gfx driver to disable a feature called
	 *	Bonus Launch to work around the issue, by degrading
	 *	performance.
	 */
	 CDV_MSG_WRITE32(3, 0x30, 0x08027108);
}

/**
 *	cdv_save_display_registers	-	save registers lost on suspend
 *	@dev: our DRM device
 *
 *	Save the state we need in order to be able to restore the interface
 *	upon resume from suspend
 */
static int cdv_save_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct drm_connector *connector;

	dev_dbg(dev->dev, "Saving GPU registers.\n");

	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);

	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);

	regs->cdv.saveDSPARB = REG_READ(DSPARB);
	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);

	regs->cdv.saveADPA = REG_READ(ADPA);

	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
	regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
	regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
	regs->cdv.saveLVDS = REG_READ(LVDS);

	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);

	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);

	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);

	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);

	return 0;
}

/**
 *	cdv_restore_display_registers	-	restore lost register state
 *	@dev: our DRM device
 *
 *	Restore register state that was lost during suspend and resume.
 *
 *	FIXME: review
 */
static int cdv_restore_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct drm_connector *connector;
	u32 temp;

	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);

	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);

	/* BIOS does below anyway */
	REG_WRITE(DPIO_CFG, 0);
	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);

	temp = REG_READ(DPLL_A);
	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
		REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
		REG_READ(DPLL_A);
	}

	temp = REG_READ(DPLL_B);
	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
		REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
		REG_READ(DPLL_B);
	}

	udelay(500);

	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);

	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
	REG_WRITE(ADPA, regs->cdv.saveADPA);

	REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
	REG_WRITE(LVDS, regs->cdv.saveLVDS);
	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
	REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);

	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);

	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);

	/* Fix arbitration bug */
	cdv_errata(dev);

	drm_mode_config_reset(dev);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);

	/* Resume the modeset for every activated CRTC */
	drm_helper_resume_force_mode(dev);
	return 0;
}

static int cdv_power_down(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt, pwr_mask, pwr_sts;
	int tries = 5;

	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_OFF;
	pwr_mask = PSB_PWRGT_GFX_MASK;

	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	while (tries--) {
		pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
			return 0;
		udelay(10);
	}
	return 0;
}

static int cdv_power_up(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt, pwr_mask, pwr_sts;
	int tries = 5;

	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_ON;
	pwr_mask = PSB_PWRGT_GFX_MASK;

	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	while (tries--) {
		pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
			return 0;
		udelay(10);
	}
	return 0;
}

/* FIXME ? - shared with Poulsbo */
static void cdv_get_core_freq(struct drm_device *dev)
{
	uint32_t clock;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	struct drm_psb_private *dev_priv = dev->dev_private;

	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	pci_read_config_dword(pci_root, 0xD4, &clock);
	pci_dev_put(pci_root);

	switch (clock & 0x07) {
	case 0:
		dev_priv->core_freq = 100;
		break;
	case 1:
		dev_priv->core_freq = 133;
		break;
	case 2:
		dev_priv->core_freq = 150;
		break;
	case 3:
		dev_priv->core_freq = 178;
		break;
	case 4:
		dev_priv->core_freq = 200;
		break;
	case 5:
	case 6:
	case 7:
		dev_priv->core_freq = 266;
		break;
	default:
		dev_priv->core_freq = 0;
	}
}

static void cdv_hotplug_work_func(struct work_struct *work)
{
        struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
							hotplug_work);                 
        struct drm_device *dev = dev_priv->dev;

        /* Just fire off a uevent and let userspace tell us what to do */
        drm_helper_hpd_irq_event(dev);
}                       

/* The core driver has received a hotplug IRQ. We are in IRQ context
   so extract the needed information and kick off queued processing */
   
static int cdv_hotplug_event(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	schedule_work(&dev_priv->hotplug_work);
	REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
	return 1;
}

static void cdv_hotplug_enable(struct drm_device *dev, bool on)
{
	if (on) {
		u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
		hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
			   HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
		REG_WRITE(PORT_HOTPLUG_EN, hotplug);
	}  else {
		REG_WRITE(PORT_HOTPLUG_EN, 0);
		REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
	}	
}

static const char *force_audio_names[] = {
	"off",
	"auto",
	"on",
};

void cdv_intel_attach_force_audio_property(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct drm_property *prop;
	int i;

	prop = dev_priv->force_audio_property;
	if (prop == NULL) {
		prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
					   "audio",
					   ARRAY_SIZE(force_audio_names));
		if (prop == NULL)
			return;

		for (i = 0; i < ARRAY_SIZE(force_audio_names); i++)
			drm_property_add_enum(prop, i, i-1, force_audio_names[i]);

		dev_priv->force_audio_property = prop;
	}
	drm_object_attach_property(&connector->base, prop, 0);
}


static const char *broadcast_rgb_names[] = {
	"Full",
	"Limited 16:235",
};

void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct drm_property *prop;
	int i;

	prop = dev_priv->broadcast_rgb_property;
	if (prop == NULL) {
		prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
					   "Broadcast RGB",
					   ARRAY_SIZE(broadcast_rgb_names));
		if (prop == NULL)
			return;

		for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++)
			drm_property_add_enum(prop, i, i, broadcast_rgb_names[i]);

		dev_priv->broadcast_rgb_property = prop;
	}

	drm_object_attach_property(&connector->base, prop, 0);
}

/* Cedarview */
static const struct psb_offset cdv_regmap[2] = {
	{
		.fp0 = FPA0,
		.fp1 = FPA1,
		.cntr = DSPACNTR,
		.conf = PIPEACONF,
		.src = PIPEASRC,
		.dpll = DPLL_A,
		.dpll_md = DPLL_A_MD,
		.htotal = HTOTAL_A,
		.hblank = HBLANK_A,
		.hsync = HSYNC_A,
		.vtotal = VTOTAL_A,
		.vblank = VBLANK_A,
		.vsync = VSYNC_A,
		.stride = DSPASTRIDE,
		.size = DSPASIZE,
		.pos = DSPAPOS,
		.base = DSPABASE,
		.surf = DSPASURF,
		.addr = DSPABASE,
		.status = PIPEASTAT,
		.linoff = DSPALINOFF,
		.tileoff = DSPATILEOFF,
		.palette = PALETTE_A,
	},
	{
		.fp0 = FPB0,
		.fp1 = FPB1,
		.cntr = DSPBCNTR,
		.conf = PIPEBCONF,
		.src = PIPEBSRC,
		.dpll = DPLL_B,
		.dpll_md = DPLL_B_MD,
		.htotal = HTOTAL_B,
		.hblank = HBLANK_B,
		.hsync = HSYNC_B,
		.vtotal = VTOTAL_B,
		.vblank = VBLANK_B,
		.vsync = VSYNC_B,
		.stride = DSPBSTRIDE,
		.size = DSPBSIZE,
		.pos = DSPBPOS,
		.base = DSPBBASE,
		.surf = DSPBSURF,
		.addr = DSPBBASE,
		.status = PIPEBSTAT,
		.linoff = DSPBLINOFF,
		.tileoff = DSPBTILEOFF,
		.palette = PALETTE_B,
	}
};

static int cdv_chip_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);

	if (pci_enable_msi(dev->pdev))
		dev_warn(dev->dev, "Enabling MSI failed!\n");
	dev_priv->regmap = cdv_regmap;
	cdv_get_core_freq(dev);
	psb_intel_opregion_init(dev);
	psb_intel_init_bios(dev);
	cdv_hotplug_enable(dev, false);
	return 0;
}

/* CDV is much like Poulsbo but has MID like SGX offsets and PM */

const struct psb_ops cdv_chip_ops = {
	.name = "GMA3600/3650",
	.accel_2d = 0,
	.pipes = 2,
	.crtcs = 2,
	.hdmi_mask = (1 << 0) | (1 << 1),
	.lvds_mask = (1 << 1),
	.cursor_needs_phys = 0,
	.sgx_offset = MRST_SGX_OFFSET,
	.chip_setup = cdv_chip_setup,
	.errata = cdv_errata,

	.crtc_helper = &cdv_intel_helper_funcs,
	.crtc_funcs = &cdv_intel_crtc_funcs,

	.output_init = cdv_output_init,
	.hotplug = cdv_hotplug_event,
	.hotplug_enable = cdv_hotplug_enable,

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	.backlight_init = cdv_backlight_init,
#endif

	.init_pm = cdv_init_pm,
	.save_regs = cdv_save_display_registers,
	.restore_regs = cdv_restore_display_registers,
	.power_down = cdv_power_down,
	.power_up = cdv_power_up,
};
Commit	Line	Data
6a227d5f AC	1	/**************************************************************************
	2	* Copyright (c) 2011, Intel Corporation.
	3	* All Rights Reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*
	18	**************************************************************************/
	19
	20	#include <linux/backlight.h>
	21	#include <drm/drmP.h>
	22	#include <drm/drm.h>
760285e7	23	#include <drm/gma_drm.h>
6a227d5f AC	24	#include "psb_drv.h"
	25	#include "psb_reg.h"
	26	#include "psb_intel_reg.h"
	27	#include "intel_bios.h"
	28	#include "cdv_device.h"
	29
	30	#define VGA_SR_INDEX 0x3c4
	31	#define VGA_SR_DATA 0x3c5
	32
6a227d5f AC	33	static void cdv_disable_vga(struct drm_device *dev)
	34	{
	35	u8 sr1;
	36	u32 vga_reg;
	37
	38	vga_reg = VGACNTRL;
	39
	40	outb(1, VGA_SR_INDEX);
	41	sr1 = inb(VGA_SR_DATA);
	42	outb(sr1 \| 1<<5, VGA_SR_DATA);
	43	udelay(300);
	44
	45	REG_WRITE(vga_reg, VGA_DISP_DISABLE);
	46	REG_READ(vga_reg);
	47	}
	48
	49	static int cdv_output_init(struct drm_device *dev)
	50	{
	51	struct drm_psb_private *dev_priv = dev->dev_private;
d235e64a AC	52
	53	drm_mode_create_scaling_mode_property(dev);
	54
6a227d5f AC	55	cdv_disable_vga(dev);
	56
	57	cdv_intel_crt_init(dev, &dev_priv->mode_dev);
	58	cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
	59
9aba9d3a	60	/* These bits indicate HDMI not SDVO on CDV */
35659715	61	if (REG_READ(SDVOB) & SDVO_DETECTED) {
6a227d5f	62	cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
35659715 AC	63	if (REG_READ(DP_B) & DP_DETECTED)
	64	cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);
	65	}
	66
	67	if (REG_READ(SDVOC) & SDVO_DETECTED) {
6a227d5f	68	cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
35659715 AC	69	if (REG_READ(DP_C) & DP_DETECTED)
	70	cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);
	71	}
6a227d5f AC	72	return 0;
	73	}
	74
	75	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	76
	77	/*
9aba9d3a	78	* Cedartrail Backlght Interfaces
6a227d5f AC	79	*/
6a227d5f AC	80
6a227d5f AC	81	static struct backlight_device *cdv_backlight_device;
6a227d5f AC	82
9aba9d3a	83	static int cdv_backlight_combination_mode(struct drm_device *dev)
6a227d5f	84	{
9aba9d3a	85	return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
6a227d5f AC	86	}
6a227d5f AC	87
9aba9d3a AC	88	static u32 cdv_get_max_backlight(struct drm_device *dev)
	89	{
	90	u32 max = REG_READ(BLC_PWM_CTL);
	91
	92	if (max == 0) {
	93	DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
	94	/* i915 does this, I believe which means that we should not
	95	* smash PWM control as firmware will take control of it. */
	96	return 1;
6a227d5f	97	}
9aba9d3a AC	98
	99	max >>= 16;
	100	if (cdv_backlight_combination_mode(dev))
	101	max *= 0xff;
	102	return max;
6a227d5f AC	103	}
6a227d5f AC	104
64691959 AC	105	static int cdv_get_brightness(struct backlight_device *bd)
	106	{
	107	struct drm_device *dev = bl_get_data(bd);
	108	u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
	109
	110	if (cdv_backlight_combination_mode(dev)) {
	111	u8 lbpc;
	112
	113	val &= ~1;
	114	pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
	115	val *= lbpc;
	116	}
	117	return (val * 100)/cdv_get_max_backlight(dev);
	118
	119	}
	120
6a227d5f AC	121	static int cdv_set_brightness(struct backlight_device *bd)
6a227d5f AC	122	{
9aba9d3a	123	struct drm_device *dev = bl_get_data(bd);
6a227d5f	124	int level = bd->props.brightness;
9aba9d3a	125	u32 blc_pwm_ctl;
6a227d5f AC	126
	127	/* Percentage 1-100% being valid */
	128	if (level < 1)
	129	level = 1;
	130
64691959 AC	131	level *= cdv_get_max_backlight(dev);
	132	level /= 100;
	133
9aba9d3a AC	134	if (cdv_backlight_combination_mode(dev)) {
	135	u32 max = cdv_get_max_backlight(dev);
	136	u8 lbpc;
	137
	138	lbpc = level * 0xfe / max + 1;
	139	level /= lbpc;
	140
	141	pci_write_config_byte(dev->pdev, 0xF4, lbpc);
	142	}
	143
	144	blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
	145	REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl \|
	146	(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
6a227d5f AC	147	return 0;
	148	}
	149
	150	static const struct backlight_ops cdv_ops = {
	151	.get_brightness = cdv_get_brightness,
	152	.update_status = cdv_set_brightness,
	153	};
	154
	155	static int cdv_backlight_init(struct drm_device *dev)
	156	{
	157	struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f AC	158	struct backlight_properties props;
	159
	160	memset(&props, 0, sizeof(struct backlight_properties));
	161	props.max_brightness = 100;
	162	props.type = BACKLIGHT_PLATFORM;
	163
	164	cdv_backlight_device = backlight_device_register("psb-bl",
	165	NULL, (void *)dev, &cdv_ops, &props);
	166	if (IS_ERR(cdv_backlight_device))
	167	return PTR_ERR(cdv_backlight_device);
	168
9aba9d3a AC	169	cdv_backlight_device->props.brightness =
9aba9d3a AC	170	cdv_get_brightness(cdv_backlight_device);
6a227d5f AC	171	backlight_update_status(cdv_backlight_device);
6a227d5f AC	172	dev_priv->backlight_device = cdv_backlight_device;
d112a816	173	dev_priv->backlight_enabled = true;
6a227d5f AC	174	return 0;
	175	}
	176
	177	#endif
	178
	179	/*
	180	* Provide the Cedarview specific chip logic and low level methods
	181	* for power management
	182	*
	183	* FIXME: we need to implement the apm/ospm base management bits
	184	* for this and the MID devices.
	185	*/
	186
	187	static inline u32 CDV_MSG_READ32(uint port, uint offset)
	188	{
	189	int mcr = (0x10<<24) \| (port << 16) \| (offset << 8);
	190	uint32_t ret_val = 0;
	191	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	192	pci_write_config_dword(pci_root, 0xD0, mcr);
	193	pci_read_config_dword(pci_root, 0xD4, &ret_val);
	194	pci_dev_put(pci_root);
	195	return ret_val;
	196	}
	197
	198	static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
	199	{
	200	int mcr = (0x11<<24) \| (port << 16) \| (offset << 8) \| 0xF0;
	201	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	202	pci_write_config_dword(pci_root, 0xD4, value);
	203	pci_write_config_dword(pci_root, 0xD0, mcr);
	204	pci_dev_put(pci_root);
	205	}
	206
6a227d5f AC	207	#define PSB_PM_SSC 0x20
6a227d5f AC	208	#define PSB_PM_SSS 0x30
09016a11 AC	209	#define PSB_PWRGT_GFX_ON 0x02
	210	#define PSB_PWRGT_GFX_OFF 0x01
	211	#define PSB_PWRGT_GFX_D0 0x00
	212	#define PSB_PWRGT_GFX_D3 0x03
6a227d5f AC	213
	214	static void cdv_init_pm(struct drm_device *dev)
	215	{
	216	struct drm_psb_private *dev_priv = dev->dev_private;
	217	u32 pwr_cnt;
	218	int i;
	219
	220	dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
	221	PSB_APMBA) & 0xFFFF;
	222	dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
	223	PSB_OSPMBA) & 0xFFFF;
	224
09016a11	225	/* Power status */
6a227d5f	226	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
6a227d5f	227
09016a11 AC	228	/* Enable the GPU */
	229	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	230	pwr_cnt \|= PSB_PWRGT_GFX_ON;
6a227d5f	231	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
09016a11 AC	232
09016a11 AC	233	/* Wait for the GPU power */
6a227d5f AC	234	for (i = 0; i < 5; i++) {
	235	u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	236	if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
09016a11	237	return;
6a227d5f AC	238	udelay(10);
6a227d5f AC	239	}
09016a11	240	dev_err(dev->dev, "GPU: power management timed out.\n");
6a227d5f AC	241	}
6a227d5f AC	242
d235e64a AC	243	static void cdv_errata(struct drm_device *dev)
	244	{
	245	/* Disable bonus launch.
9aba9d3a AC	246	* CPU and GPU competes for memory and display misses updates and
9aba9d3a AC	247	* flickers. Worst with dual core, dual displays.
d235e64a	248	*
9aba9d3a AC	249	* Fixes were done to Win 7 gfx driver to disable a feature called
	250	* Bonus Launch to work around the issue, by degrading
	251	* performance.
d235e64a AC	252	*/
	253	CDV_MSG_WRITE32(3, 0x30, 0x08027108);
	254	}
	255
6a227d5f AC	256	/**
	257	* cdv_save_display_registers - save registers lost on suspend
	258	* @dev: our DRM device
	259	*
	260	* Save the state we need in order to be able to restore the interface
	261	* upon resume from suspend
6a227d5f AC	262	*/
	263	static int cdv_save_display_registers(struct drm_device *dev)
	264	{
09016a11 AC	265	struct drm_psb_private *dev_priv = dev->dev_private;
	266	struct psb_save_area *regs = &dev_priv->regs;
	267	struct drm_connector *connector;
	268
31a0685a	269	dev_dbg(dev->dev, "Saving GPU registers.\n");
09016a11 AC	270
	271	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
	272
	273	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
	274	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
	275
	276	regs->cdv.saveDSPARB = REG_READ(DSPARB);
	277	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
	278	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
	279	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
	280	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
	281	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
	282	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
	283
	284	regs->cdv.saveADPA = REG_READ(ADPA);
	285
	286	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
	287	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
	288	regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
	289	regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
	290	regs->cdv.saveLVDS = REG_READ(LVDS);
	291
	292	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
	293
	294	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
	295	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
	296	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
	297
	298	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
	299
	300	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
	301	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
	302
	303	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
	304	connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
	305
6a227d5f AC	306	return 0;
	307	}
	308
	309	/**
	310	* cdv_restore_display_registers - restore lost register state
	311	* @dev: our DRM device
	312	*
	313	* Restore register state that was lost during suspend and resume.
	314	*
	315	* FIXME: review
	316	*/
	317	static int cdv_restore_display_registers(struct drm_device *dev)
	318	{
09016a11 AC	319	struct drm_psb_private *dev_priv = dev->dev_private;
	320	struct psb_save_area *regs = &dev_priv->regs;
	321	struct drm_connector *connector;
	322	u32 temp;
	323
	324	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
	325
	326	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
	327	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
	328
	329	/* BIOS does below anyway */
	330	REG_WRITE(DPIO_CFG, 0);
	331	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 \| DPIO_CMN_RESET_N);
	332
	333	temp = REG_READ(DPLL_A);
	334	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
	335	REG_WRITE(DPLL_A, temp \| DPLL_SYNCLOCK_ENABLE);
	336	REG_READ(DPLL_A);
	337	}
	338
	339	temp = REG_READ(DPLL_B);
	340	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
	341	REG_WRITE(DPLL_B, temp \| DPLL_SYNCLOCK_ENABLE);
	342	REG_READ(DPLL_B);
	343	}
	344
	345	udelay(500);
	346
	347	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
	348	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
	349	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
	350	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
	351	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
	352	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
	353
	354	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
	355	REG_WRITE(ADPA, regs->cdv.saveADPA);
	356
	357	REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
	358	REG_WRITE(LVDS, regs->cdv.saveLVDS);
	359	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
	360	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
	361	REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
	362	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
	363	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
	364	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
	365	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
	366
	367	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
	368
	369	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
	370	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
	371
	372	/* Fix arbitration bug */
d235e64a	373	cdv_errata(dev);
09016a11 AC	374
	375	drm_mode_config_reset(dev);
	376
	377	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
	378	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
	379
	380	/* Resume the modeset for every activated CRTC */
	381	drm_helper_resume_force_mode(dev);
6a227d5f AC	382	return 0;
	383	}
	384
	385	static int cdv_power_down(struct drm_device *dev)
	386	{
09016a11 AC	387	struct drm_psb_private *dev_priv = dev->dev_private;
	388	u32 pwr_cnt, pwr_mask, pwr_sts;
	389	int tries = 5;
	390
	391	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	392	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	393	pwr_cnt \|= PSB_PWRGT_GFX_OFF;
	394	pwr_mask = PSB_PWRGT_GFX_MASK;
	395
	396	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
	397
	398	while (tries--) {
	399	pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	400	if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
	401	return 0;
	402	udelay(10);
	403	}
6a227d5f AC	404	return 0;
	405	}
	406
	407	static int cdv_power_up(struct drm_device *dev)
	408	{
09016a11 AC	409	struct drm_psb_private *dev_priv = dev->dev_private;
	410	u32 pwr_cnt, pwr_mask, pwr_sts;
	411	int tries = 5;
	412
	413	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	414	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	415	pwr_cnt \|= PSB_PWRGT_GFX_ON;
	416	pwr_mask = PSB_PWRGT_GFX_MASK;
	417
	418	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
	419
	420	while (tries--) {
	421	pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	422	if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
	423	return 0;
	424	udelay(10);
	425	}
6a227d5f AC	426	return 0;
	427	}
	428
	429	/* FIXME ? - shared with Poulsbo */
	430	static void cdv_get_core_freq(struct drm_device *dev)
	431	{
	432	uint32_t clock;
	433	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	434	struct drm_psb_private *dev_priv = dev->dev_private;
	435
	436	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	437	pci_read_config_dword(pci_root, 0xD4, &clock);
	438	pci_dev_put(pci_root);
	439
	440	switch (clock & 0x07) {
	441	case 0:
	442	dev_priv->core_freq = 100;
	443	break;
	444	case 1:
	445	dev_priv->core_freq = 133;
	446	break;
	447	case 2:
	448	dev_priv->core_freq = 150;
	449	break;
	450	case 3:
	451	dev_priv->core_freq = 178;
	452	break;
	453	case 4:
	454	dev_priv->core_freq = 200;
	455	break;
	456	case 5:
	457	case 6:
	458	case 7:
	459	dev_priv->core_freq = 266;
6f314ebb	460	break;
6a227d5f AC	461	default:
	462	dev_priv->core_freq = 0;
	463	}
	464	}
	465
ae0a246a AC	466	static void cdv_hotplug_work_func(struct work_struct *work)
	467	{
	468	struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
	469	hotplug_work);
	470	struct drm_device *dev = dev_priv->dev;
	471
	472	/* Just fire off a uevent and let userspace tell us what to do */
	473	drm_helper_hpd_irq_event(dev);
	474	}
	475
	476	/* The core driver has received a hotplug IRQ. We are in IRQ context
	477	so extract the needed information and kick off queued processing */
	478
	479	static int cdv_hotplug_event(struct drm_device *dev)
	480	{
	481	struct drm_psb_private *dev_priv = dev->dev_private;
	482	schedule_work(&dev_priv->hotplug_work);
	483	REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
	484	return 1;
	485	}
	486
	487	static void cdv_hotplug_enable(struct drm_device *dev, bool on)
	488	{
	489	if (on) {
	490	u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
	491	hotplug \|= HDMIB_HOTPLUG_INT_EN \| HDMIC_HOTPLUG_INT_EN \|
	492	HDMID_HOTPLUG_INT_EN \| CRT_HOTPLUG_INT_EN;
	493	REG_WRITE(PORT_HOTPLUG_EN, hotplug);
	494	} else {
	495	REG_WRITE(PORT_HOTPLUG_EN, 0);
	496	REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
	497	}
	498	}
	499
220801bd AC	500	static const char *force_audio_names[] = {
	501	"off",
	502	"auto",
	503	"on",
	504	};
	505
	506	void cdv_intel_attach_force_audio_property(struct drm_connector *connector)
	507	{
	508	struct drm_device *dev = connector->dev;
	509	struct drm_psb_private *dev_priv = dev->dev_private;
	510	struct drm_property *prop;
	511	int i;
	512
	513	prop = dev_priv->force_audio_property;
	514	if (prop == NULL) {
	515	prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
	516	"audio",
	517	ARRAY_SIZE(force_audio_names));
	518	if (prop == NULL)
	519	return;
	520
	521	for (i = 0; i < ARRAY_SIZE(force_audio_names); i++)
	522	drm_property_add_enum(prop, i, i-1, force_audio_names[i]);
	523
	524	dev_priv->force_audio_property = prop;
	525	}
a69ac9ea	526	drm_object_attach_property(&connector->base, prop, 0);
220801bd AC	527	}
	528
	529
	530	static const char *broadcast_rgb_names[] = {
	531	"Full",
	532	"Limited 16:235",
	533	};
	534
	535	void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector)
	536	{
	537	struct drm_device *dev = connector->dev;
	538	struct drm_psb_private *dev_priv = dev->dev_private;
	539	struct drm_property *prop;
	540	int i;
	541
	542	prop = dev_priv->broadcast_rgb_property;
	543	if (prop == NULL) {
	544	prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
	545	"Broadcast RGB",
	546	ARRAY_SIZE(broadcast_rgb_names));
	547	if (prop == NULL)
	548	return;
	549
	550	for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++)
	551	drm_property_add_enum(prop, i, i, broadcast_rgb_names[i]);
	552
	553	dev_priv->broadcast_rgb_property = prop;
	554	}
	555
a69ac9ea	556	drm_object_attach_property(&connector->base, prop, 0);
220801bd AC	557	}
220801bd AC	558
8512e074 AC	559	/* Cedarview */
	560	static const struct psb_offset cdv_regmap[2] = {
	561	{
	562	.fp0 = FPA0,
	563	.fp1 = FPA1,
	564	.cntr = DSPACNTR,
	565	.conf = PIPEACONF,
	566	.src = PIPEASRC,
	567	.dpll = DPLL_A,
213a8434	568	.dpll_md = DPLL_A_MD,
8512e074 AC	569	.htotal = HTOTAL_A,
	570	.hblank = HBLANK_A,
	571	.hsync = HSYNC_A,
	572	.vtotal = VTOTAL_A,
	573	.vblank = VBLANK_A,
	574	.vsync = VSYNC_A,
	575	.stride = DSPASTRIDE,
	576	.size = DSPASIZE,
	577	.pos = DSPAPOS,
	578	.base = DSPABASE,
	579	.surf = DSPASURF,
	580	.addr = DSPABASE,
	581	.status = PIPEASTAT,
	582	.linoff = DSPALINOFF,
	583	.tileoff = DSPATILEOFF,
	584	.palette = PALETTE_A,
	585	},
	586	{
	587	.fp0 = FPB0,
	588	.fp1 = FPB1,
	589	.cntr = DSPBCNTR,
	590	.conf = PIPEBCONF,
	591	.src = PIPEBSRC,
	592	.dpll = DPLL_B,
213a8434	593	.dpll_md = DPLL_B_MD,
8512e074 AC	594	.htotal = HTOTAL_B,
	595	.hblank = HBLANK_B,
	596	.hsync = HSYNC_B,
	597	.vtotal = VTOTAL_B,
	598	.vblank = VBLANK_B,
	599	.vsync = VSYNC_B,
	600	.stride = DSPBSTRIDE,
	601	.size = DSPBSIZE,
	602	.pos = DSPBPOS,
	603	.base = DSPBBASE,
	604	.surf = DSPBSURF,
	605	.addr = DSPBBASE,
	606	.status = PIPEBSTAT,
	607	.linoff = DSPBLINOFF,
	608	.tileoff = DSPBTILEOFF,
	609	.palette = PALETTE_B,
	610	}
	611	};
	612
6a227d5f AC	613	static int cdv_chip_setup(struct drm_device *dev)
6a227d5f AC	614	{
ae0a246a AC	615	struct drm_psb_private *dev_priv = dev->dev_private;
ae0a246a AC	616	INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
9c0b6fcd AC	617
	618	if (pci_enable_msi(dev->pdev))
	619	dev_warn(dev->dev, "Enabling MSI failed!\n");
8512e074	620	dev_priv->regmap = cdv_regmap;
6a227d5f	621	cdv_get_core_freq(dev);
d839ede4	622	psb_intel_opregion_init(dev);
6a227d5f	623	psb_intel_init_bios(dev);
ae0a246a	624	cdv_hotplug_enable(dev, false);
6a227d5f AC	625	return 0;
	626	}
	627
	628	/* CDV is much like Poulsbo but has MID like SGX offsets and PM */
	629
	630	const struct psb_ops cdv_chip_ops = {
b6195aab	631	.name = "GMA3600/3650",
6a227d5f AC	632	.accel_2d = 0,
6a227d5f AC	633	.pipes = 2,
b6195aab	634	.crtcs = 2,
d235e64a AC	635	.hdmi_mask = (1 << 0) \| (1 << 1),
d235e64a AC	636	.lvds_mask = (1 << 1),
bc794829	637	.cursor_needs_phys = 0,
6a227d5f AC	638	.sgx_offset = MRST_SGX_OFFSET,
6a227d5f AC	639	.chip_setup = cdv_chip_setup,
d235e64a	640	.errata = cdv_errata,
6a227d5f AC	641
	642	.crtc_helper = &cdv_intel_helper_funcs,
	643	.crtc_funcs = &cdv_intel_crtc_funcs,
	644
	645	.output_init = cdv_output_init,
ae0a246a AC	646	.hotplug = cdv_hotplug_event,
ae0a246a AC	647	.hotplug_enable = cdv_hotplug_enable,
6a227d5f AC	648
	649	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	650	.backlight_init = cdv_backlight_init,
	651	#endif
	652
	653	.init_pm = cdv_init_pm,
	654	.save_regs = cdv_save_display_registers,
	655	.restore_regs = cdv_restore_display_registers,
	656	.power_down = cdv_power_down,
	657	.power_up = cdv_power_up,
	658	};