[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_device.c

/**************************************************************************
 * Copyright (c) 2011, Intel Corporation.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 **************************************************************************/

#include <linux/backlight.h>
#include <drm/drmP.h>
#include <drm/drm.h>
#include "gma_drm.h"
#include "psb_drv.h"
#include "psb_reg.h"
#include "psb_intel_reg.h"
#include "intel_bios.h"
#include "cdv_device.h"

#define VGA_SR_INDEX		0x3c4
#define VGA_SR_DATA		0x3c5

static void cdv_disable_vga(struct drm_device *dev)
{
	u8 sr1;
	u32 vga_reg;

	vga_reg = VGACNTRL;

	outb(1, VGA_SR_INDEX);
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	udelay(300);

	REG_WRITE(vga_reg, VGA_DISP_DISABLE);
	REG_READ(vga_reg);
}

static int cdv_output_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	cdv_disable_vga(dev);

	cdv_intel_crt_init(dev, &dev_priv->mode_dev);
	cdv_intel_lvds_init(dev, &dev_priv->mode_dev);

	/* These bits indicate HDMI not SDVO on CDV, but we don't yet support
	   the HDMI interface */
	if (REG_READ(SDVOB) & SDVO_DETECTED)
		cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
	if (REG_READ(SDVOC) & SDVO_DETECTED)
		cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
	return 0;
}

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE

/*
 *	Poulsbo Backlight Interfaces
 */

#define BLC_PWM_PRECISION_FACTOR 100	/* 10000000 */
#define BLC_PWM_FREQ_CALC_CONSTANT 32
#define MHz 1000000

#define PSB_BLC_PWM_PRECISION_FACTOR    10
#define PSB_BLC_MAX_PWM_REG_FREQ        0xFFFE
#define PSB_BLC_MIN_PWM_REG_FREQ        0x2

#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
#define PSB_BACKLIGHT_PWM_CTL_SHIFT	(16)

static int cdv_brightness;
static struct backlight_device *cdv_backlight_device;

static int cdv_get_brightness(struct backlight_device *bd)
{
	/* return locally cached var instead of HW read (due to DPST etc.) */
	/* FIXME: ideally return actual value in case firmware fiddled with
	   it */
	return cdv_brightness;
}


static int cdv_backlight_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	unsigned long core_clock;
	/* u32 bl_max_freq; */
	/* unsigned long value; */
	u16 bl_max_freq;
	uint32_t value;
	uint32_t blc_pwm_precision_factor;

	/* get bl_max_freq and pol from dev_priv*/
	if (!dev_priv->lvds_bl) {
		dev_err(dev->dev, "Has no valid LVDS backlight info\n");
		return -ENOENT;
	}
	bl_max_freq = dev_priv->lvds_bl->freq;
	blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;

	core_clock = dev_priv->core_freq;

	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
	value *= blc_pwm_precision_factor;
	value /= bl_max_freq;
	value /= blc_pwm_precision_factor;

	if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
		 value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
				return -ERANGE;
	else {
		/* FIXME */
	}
	return 0;
}

static int cdv_set_brightness(struct backlight_device *bd)
{
	int level = bd->props.brightness;

	/* Percentage 1-100% being valid */
	if (level < 1)
		level = 1;

	/*cdv_intel_lvds_set_brightness(dev, level); FIXME */
	cdv_brightness = level;
	return 0;
}

static const struct backlight_ops cdv_ops = {
	.get_brightness = cdv_get_brightness,
	.update_status  = cdv_set_brightness,
};

static int cdv_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	int ret;
	struct backlight_properties props;

	memset(&props, 0, sizeof(struct backlight_properties));
	props.max_brightness = 100;
	props.type = BACKLIGHT_PLATFORM;

	cdv_backlight_device = backlight_device_register("psb-bl",
					NULL, (void *)dev, &cdv_ops, &props);
	if (IS_ERR(cdv_backlight_device))
		return PTR_ERR(cdv_backlight_device);

	ret = cdv_backlight_setup(dev);
	if (ret < 0) {
		backlight_device_unregister(cdv_backlight_device);
		cdv_backlight_device = NULL;
		return ret;
	}
	cdv_backlight_device->props.brightness = 100;
	cdv_backlight_device->props.max_brightness = 100;
	backlight_update_status(cdv_backlight_device);
	dev_priv->backlight_device = cdv_backlight_device;
	return 0;
}

#endif

/*
 *	Provide the Cedarview specific chip logic and low level methods
 *	for power management
 *
 *	FIXME: we need to implement the apm/ospm base management bits
 *	for this and the MID devices.
 */

static inline u32 CDV_MSG_READ32(uint port, uint offset)
{
	int mcr = (0x10<<24) | (port << 16) | (offset << 8);
	uint32_t ret_val = 0;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	pci_write_config_dword(pci_root, 0xD0, mcr);
	pci_read_config_dword(pci_root, 0xD4, &ret_val);
	pci_dev_put(pci_root);
	return ret_val;
}

static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
{
	int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	pci_write_config_dword(pci_root, 0xD4, value);
	pci_write_config_dword(pci_root, 0xD0, mcr);
	pci_dev_put(pci_root);
}

#define PSB_PM_SSC			0x20
#define PSB_PM_SSS			0x30
#define PSB_PWRGT_GFX_ON		0x02
#define PSB_PWRGT_GFX_OFF		0x01
#define PSB_PWRGT_GFX_D0		0x00
#define PSB_PWRGT_GFX_D3		0x03

static void cdv_init_pm(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt;
	int i;

	dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
							PSB_APMBA) & 0xFFFF;
	dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
							PSB_OSPMBA) & 0xFFFF;

	/* Power status */
	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);

	/* Enable the GPU */
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_ON;
	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	/* Wait for the GPU power */
	for (i = 0; i < 5; i++) {
		u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
			return;
		udelay(10);
	}
	dev_err(dev->dev, "GPU: power management timed out.\n");
}

/**
 *	cdv_save_display_registers	-	save registers lost on suspend
 *	@dev: our DRM device
 *
 *	Save the state we need in order to be able to restore the interface
 *	upon resume from suspend
 */
static int cdv_save_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct drm_connector *connector;

	dev_info(dev->dev, "Saving GPU registers.\n");

	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);

	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);

	regs->cdv.saveDSPARB = REG_READ(DSPARB);
	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);

	regs->cdv.saveADPA = REG_READ(ADPA);

	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
	regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
	regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
	regs->cdv.saveLVDS = REG_READ(LVDS);

	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);

	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);

	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);

	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);

	return 0;
}

/**
 *	cdv_restore_display_registers	-	restore lost register state
 *	@dev: our DRM device
 *
 *	Restore register state that was lost during suspend and resume.
 *
 *	FIXME: review
 */
static int cdv_restore_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct drm_connector *connector;
	u32 temp;

	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);

	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);

	/* BIOS does below anyway */
	REG_WRITE(DPIO_CFG, 0);
	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);

	temp = REG_READ(DPLL_A);
	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
		REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
		REG_READ(DPLL_A);
	}

	temp = REG_READ(DPLL_B);
	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
		REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
		REG_READ(DPLL_B);
	}

	udelay(500);

	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);

	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
	REG_WRITE(ADPA, regs->cdv.saveADPA);

	REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
	REG_WRITE(LVDS, regs->cdv.saveLVDS);
	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
	REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);

	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);

	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);

	/* Fix arbitration bug */
	CDV_MSG_WRITE32(3, 0x30, 0x08027108);

	drm_mode_config_reset(dev);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);

	/* Resume the modeset for every activated CRTC */
	drm_helper_resume_force_mode(dev);
	return 0;
}

static int cdv_power_down(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt, pwr_mask, pwr_sts;
	int tries = 5;

	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_OFF;
	pwr_mask = PSB_PWRGT_GFX_MASK;

	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	while (tries--) {
		pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
			return 0;
		udelay(10);
	}
	return 0;
}

static int cdv_power_up(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt, pwr_mask, pwr_sts;
	int tries = 5;

	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_ON;
	pwr_mask = PSB_PWRGT_GFX_MASK;

	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	while (tries--) {
		pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
			return 0;
		udelay(10);
	}
	return 0;
}

/* FIXME ? - shared with Poulsbo */
static void cdv_get_core_freq(struct drm_device *dev)
{
	uint32_t clock;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	struct drm_psb_private *dev_priv = dev->dev_private;

	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	pci_read_config_dword(pci_root, 0xD4, &clock);
	pci_dev_put(pci_root);

	switch (clock & 0x07) {
	case 0:
		dev_priv->core_freq = 100;
		break;
	case 1:
		dev_priv->core_freq = 133;
		break;
	case 2:
		dev_priv->core_freq = 150;
		break;
	case 3:
		dev_priv->core_freq = 178;
		break;
	case 4:
		dev_priv->core_freq = 200;
		break;
	case 5:
	case 6:
	case 7:
		dev_priv->core_freq = 266;
	default:
		dev_priv->core_freq = 0;
	}
}

static int cdv_chip_setup(struct drm_device *dev)
{
	cdv_get_core_freq(dev);
	gma_intel_opregion_init(dev);
	psb_intel_init_bios(dev);
	return 0;
}

/* CDV is much like Poulsbo but has MID like SGX offsets and PM */

const struct psb_ops cdv_chip_ops = {
	.name = "GMA3600/3650",
	.accel_2d = 0,
	.pipes = 2,
	.crtcs = 2,
	.sgx_offset = MRST_SGX_OFFSET,
	.chip_setup = cdv_chip_setup,

	.crtc_helper = &cdv_intel_helper_funcs,
	.crtc_funcs = &cdv_intel_crtc_funcs,

	.output_init = cdv_output_init,

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	.backlight_init = cdv_backlight_init,
#endif

	.init_pm = cdv_init_pm,
	.save_regs = cdv_save_display_registers,
	.restore_regs = cdv_restore_display_registers,
	.power_down = cdv_power_down,
	.power_up = cdv_power_up,
};
Commit	Line	Data
6a227d5f AC	1	/**************************************************************************
	2	* Copyright (c) 2011, Intel Corporation.
	3	* All Rights Reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*
	18	**************************************************************************/
	19
	20	#include <linux/backlight.h>
	21	#include <drm/drmP.h>
	22	#include <drm/drm.h>
838fa588	23	#include "gma_drm.h"
6a227d5f AC	24	#include "psb_drv.h"
	25	#include "psb_reg.h"
	26	#include "psb_intel_reg.h"
	27	#include "intel_bios.h"
	28	#include "cdv_device.h"
	29
	30	#define VGA_SR_INDEX 0x3c4
	31	#define VGA_SR_DATA 0x3c5
	32
6a227d5f AC	33	static void cdv_disable_vga(struct drm_device *dev)
	34	{
	35	u8 sr1;
	36	u32 vga_reg;
	37
	38	vga_reg = VGACNTRL;
	39
	40	outb(1, VGA_SR_INDEX);
	41	sr1 = inb(VGA_SR_DATA);
	42	outb(sr1 \| 1<<5, VGA_SR_DATA);
	43	udelay(300);
	44
	45	REG_WRITE(vga_reg, VGA_DISP_DISABLE);
	46	REG_READ(vga_reg);
	47	}
	48
	49	static int cdv_output_init(struct drm_device *dev)
	50	{
	51	struct drm_psb_private *dev_priv = dev->dev_private;
	52	cdv_disable_vga(dev);
	53
	54	cdv_intel_crt_init(dev, &dev_priv->mode_dev);
	55	cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
	56
	57	/* These bits indicate HDMI not SDVO on CDV, but we don't yet support
	58	the HDMI interface */
	59	if (REG_READ(SDVOB) & SDVO_DETECTED)
	60	cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
	61	if (REG_READ(SDVOC) & SDVO_DETECTED)
	62	cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
	63	return 0;
	64	}
	65
	66	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	67
	68	/*
	69	* Poulsbo Backlight Interfaces
	70	*/
	71
	72	#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
	73	#define BLC_PWM_FREQ_CALC_CONSTANT 32
	74	#define MHz 1000000
	75
	76	#define PSB_BLC_PWM_PRECISION_FACTOR 10
	77	#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
	78	#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
	79
	80	#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
	81	#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
	82
	83	static int cdv_brightness;
	84	static struct backlight_device *cdv_backlight_device;
	85
	86	static int cdv_get_brightness(struct backlight_device *bd)
	87	{
	88	/* return locally cached var instead of HW read (due to DPST etc.) */
	89	/* FIXME: ideally return actual value in case firmware fiddled with
	90	it */
	91	return cdv_brightness;
	92	}
	93
	94
	95	static int cdv_backlight_setup(struct drm_device *dev)
	96	{
97	struct drm_psb_private *dev_priv = dev->dev_private;
98	unsigned long core_clock;
99	/* u32 bl_max_freq; */
100	/* unsigned long value; */
101	u16 bl_max_freq;
102	uint32_t value;
103	uint32_t blc_pwm_precision_factor;
104
105	/* get bl_max_freq and pol from dev_priv*/
106	if (!dev_priv->lvds_bl) {
107	dev_err(dev->dev, "Has no valid LVDS backlight info\n");
108	return -ENOENT;
109	}
110	bl_max_freq = dev_priv->lvds_bl->freq;
111	blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
112
113	core_clock = dev_priv->core_freq;
114
115	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
116	value *= blc_pwm_precision_factor;
117	value /= bl_max_freq;
118	value /= blc_pwm_precision_factor;
119
120	if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ \|\|
121	value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
122	return -ERANGE;
123	else {
124	/* FIXME */
125	}
126	return 0;
127	}
128
129	static int cdv_set_brightness(struct backlight_device *bd)
130	{
131	int level = bd->props.brightness;
132
133	/* Percentage 1-100% being valid */
134	if (level < 1)
135	level = 1;
136
137	/cdv_intel_lvds_set_brightness(dev, level); FIXME /
138	cdv_brightness = level;
139	return 0;
140	}
141
142	static const struct backlight_ops cdv_ops = {
143	.get_brightness = cdv_get_brightness,
144	.update_status = cdv_set_brightness,
145	};
146
147	static int cdv_backlight_init(struct drm_device *dev)
148	{
149	struct drm_psb_private *dev_priv = dev->dev_private;
150	int ret;
151	struct backlight_properties props;
152
153	memset(&props, 0, sizeof(struct backlight_properties));
154	props.max_brightness = 100;
155	props.type = BACKLIGHT_PLATFORM;
156
157	cdv_backlight_device = backlight_device_register("psb-bl",
158	NULL, (void *)dev, &cdv_ops, &props);
159	if (IS_ERR(cdv_backlight_device))
160	return PTR_ERR(cdv_backlight_device);
161
162	ret = cdv_backlight_setup(dev);
163	if (ret < 0) {
164	backlight_device_unregister(cdv_backlight_device);
165	cdv_backlight_device = NULL;
166	return ret;
167	}
168	cdv_backlight_device->props.brightness = 100;
169	cdv_backlight_device->props.max_brightness = 100;
170	backlight_update_status(cdv_backlight_device);
171	dev_priv->backlight_device = cdv_backlight_device;
172	return 0;
173	}
174
175	#endif
176
177	/*
178	* Provide the Cedarview specific chip logic and low level methods
179	* for power management
180	*
181	* FIXME: we need to implement the apm/ospm base management bits
182	* for this and the MID devices.
183	*/
184
185	static inline u32 CDV_MSG_READ32(uint port, uint offset)
186	{
187	int mcr = (0x10<<24) \| (port << 16) \| (offset << 8);
188	uint32_t ret_val = 0;
189	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
190	pci_write_config_dword(pci_root, 0xD0, mcr);
191	pci_read_config_dword(pci_root, 0xD4, &ret_val);
192	pci_dev_put(pci_root);
193	return ret_val;
194	}
195
196	static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
197	{
198	int mcr = (0x11<<24) \| (port << 16) \| (offset << 8) \| 0xF0;
199	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
200	pci_write_config_dword(pci_root, 0xD4, value);
201	pci_write_config_dword(pci_root, 0xD0, mcr);
202	pci_dev_put(pci_root);
203	}
204
6a227d5f AC	205	#define PSB_PM_SSC 0x20
6a227d5f AC	206	#define PSB_PM_SSS 0x30
09016a11 AC	207	#define PSB_PWRGT_GFX_ON 0x02
	208	#define PSB_PWRGT_GFX_OFF 0x01
	209	#define PSB_PWRGT_GFX_D0 0x00
	210	#define PSB_PWRGT_GFX_D3 0x03
6a227d5f AC	211
	212	static void cdv_init_pm(struct drm_device *dev)
	213	{
	214	struct drm_psb_private *dev_priv = dev->dev_private;
	215	u32 pwr_cnt;
	216	int i;
	217
	218	dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
	219	PSB_APMBA) & 0xFFFF;
	220	dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
	221	PSB_OSPMBA) & 0xFFFF;
	222
09016a11	223	/* Power status */
6a227d5f	224	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
6a227d5f	225
09016a11 AC	226	/* Enable the GPU */
	227	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	228	pwr_cnt \|= PSB_PWRGT_GFX_ON;
6a227d5f	229	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
09016a11 AC	230
09016a11 AC	231	/* Wait for the GPU power */
6a227d5f AC	232	for (i = 0; i < 5; i++) {
	233	u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	234	if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
09016a11	235	return;
6a227d5f AC	236	udelay(10);
6a227d5f AC	237	}
09016a11	238	dev_err(dev->dev, "GPU: power management timed out.\n");
6a227d5f AC	239	}
	240
	241	/**
	242	* cdv_save_display_registers - save registers lost on suspend
	243	* @dev: our DRM device
	244	*
	245	* Save the state we need in order to be able to restore the interface
	246	* upon resume from suspend
6a227d5f AC	247	*/
	248	static int cdv_save_display_registers(struct drm_device *dev)
	249	{
09016a11 AC	250	struct drm_psb_private *dev_priv = dev->dev_private;
	251	struct psb_save_area *regs = &dev_priv->regs;
	252	struct drm_connector *connector;
	253
	254	dev_info(dev->dev, "Saving GPU registers.\n");
	255
	256	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
	257
	258	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
	259	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
	260
	261	regs->cdv.saveDSPARB = REG_READ(DSPARB);
	262	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
	263	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
	264	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
	265	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
	266	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
	267	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
	268
	269	regs->cdv.saveADPA = REG_READ(ADPA);
	270
	271	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
	272	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
	273	regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
	274	regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
	275	regs->cdv.saveLVDS = REG_READ(LVDS);
	276
	277	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
	278
	279	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
	280	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
	281	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
	282
	283	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
	284
	285	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
	286	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
	287
	288	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
	289	connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
	290
6a227d5f AC	291	return 0;
	292	}
	293
	294	/**
	295	* cdv_restore_display_registers - restore lost register state
	296	* @dev: our DRM device
	297	*
	298	* Restore register state that was lost during suspend and resume.
	299	*
	300	* FIXME: review
	301	*/
	302	static int cdv_restore_display_registers(struct drm_device *dev)
	303	{
09016a11 AC	304	struct drm_psb_private *dev_priv = dev->dev_private;
	305	struct psb_save_area *regs = &dev_priv->regs;
	306	struct drm_connector *connector;
	307	u32 temp;
	308
	309	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
	310
	311	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
	312	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
	313
	314	/* BIOS does below anyway */
	315	REG_WRITE(DPIO_CFG, 0);
	316	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 \| DPIO_CMN_RESET_N);
	317
	318	temp = REG_READ(DPLL_A);
	319	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
	320	REG_WRITE(DPLL_A, temp \| DPLL_SYNCLOCK_ENABLE);
	321	REG_READ(DPLL_A);
	322	}
	323
	324	temp = REG_READ(DPLL_B);
	325	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
	326	REG_WRITE(DPLL_B, temp \| DPLL_SYNCLOCK_ENABLE);
	327	REG_READ(DPLL_B);
	328	}
	329
	330	udelay(500);
	331
	332	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
	333	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
	334	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
	335	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
	336	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
	337	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
	338
	339	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
	340	REG_WRITE(ADPA, regs->cdv.saveADPA);
	341
	342	REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
	343	REG_WRITE(LVDS, regs->cdv.saveLVDS);
	344	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
	345	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
	346	REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
	347	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
	348	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
	349	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
	350	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
	351
	352	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
	353
	354	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
	355	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
	356
	357	/* Fix arbitration bug */
	358	CDV_MSG_WRITE32(3, 0x30, 0x08027108);
	359
	360	drm_mode_config_reset(dev);
	361
	362	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
	363	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
	364
	365	/* Resume the modeset for every activated CRTC */
	366	drm_helper_resume_force_mode(dev);
6a227d5f AC	367	return 0;
	368	}
	369
	370	static int cdv_power_down(struct drm_device *dev)
	371	{
09016a11 AC	372	struct drm_psb_private *dev_priv = dev->dev_private;
	373	u32 pwr_cnt, pwr_mask, pwr_sts;
	374	int tries = 5;
	375
	376	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	377	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	378	pwr_cnt \|= PSB_PWRGT_GFX_OFF;
	379	pwr_mask = PSB_PWRGT_GFX_MASK;
	380
	381	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
	382
	383	while (tries--) {
	384	pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	385	if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
	386	return 0;
	387	udelay(10);
	388	}
6a227d5f AC	389	return 0;
	390	}
	391
	392	static int cdv_power_up(struct drm_device *dev)
	393	{
09016a11 AC	394	struct drm_psb_private *dev_priv = dev->dev_private;
	395	u32 pwr_cnt, pwr_mask, pwr_sts;
	396	int tries = 5;
	397
	398	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	399	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	400	pwr_cnt \|= PSB_PWRGT_GFX_ON;
	401	pwr_mask = PSB_PWRGT_GFX_MASK;
	402
	403	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
	404
	405	while (tries--) {
	406	pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	407	if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
	408	return 0;
	409	udelay(10);
	410	}
6a227d5f AC	411	return 0;
	412	}
	413
	414	/* FIXME ? - shared with Poulsbo */
	415	static void cdv_get_core_freq(struct drm_device *dev)
	416	{
	417	uint32_t clock;
	418	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	419	struct drm_psb_private *dev_priv = dev->dev_private;
	420
	421	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	422	pci_read_config_dword(pci_root, 0xD4, &clock);
	423	pci_dev_put(pci_root);
	424
	425	switch (clock & 0x07) {
	426	case 0:
	427	dev_priv->core_freq = 100;
	428	break;
	429	case 1:
	430	dev_priv->core_freq = 133;
	431	break;
	432	case 2:
	433	dev_priv->core_freq = 150;
	434	break;
	435	case 3:
	436	dev_priv->core_freq = 178;
	437	break;
	438	case 4:
	439	dev_priv->core_freq = 200;
	440	break;
	441	case 5:
	442	case 6:
	443	case 7:
	444	dev_priv->core_freq = 266;
	445	default:
	446	dev_priv->core_freq = 0;
	447	}
	448	}
	449
	450	static int cdv_chip_setup(struct drm_device *dev)
	451	{
	452	cdv_get_core_freq(dev);
	453	gma_intel_opregion_init(dev);
	454	psb_intel_init_bios(dev);
	455	return 0;
	456	}
	457
	458	/* CDV is much like Poulsbo but has MID like SGX offsets and PM */
	459
	460	const struct psb_ops cdv_chip_ops = {
b6195aab	461	.name = "GMA3600/3650",
6a227d5f AC	462	.accel_2d = 0,
6a227d5f AC	463	.pipes = 2,
b6195aab	464	.crtcs = 2,
6a227d5f AC	465	.sgx_offset = MRST_SGX_OFFSET,
	466	.chip_setup = cdv_chip_setup,
	467
	468	.crtc_helper = &cdv_intel_helper_funcs,
	469	.crtc_funcs = &cdv_intel_crtc_funcs,
	470
	471	.output_init = cdv_output_init,
	472
	473	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	474	.backlight_init = cdv_backlight_init,
	475	#endif
	476
	477	.init_pm = cdv_init_pm,
	478	.save_regs = cdv_save_display_registers,
	479	.restore_regs = cdv_restore_display_registers,
	480	.power_down = cdv_power_down,
	481	.power_up = cdv_power_up,
	482	};