[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_device.c

/**************************************************************************
 * Copyright (c) 2011, Intel Corporation.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 **************************************************************************/

#include <linux/backlight.h>
#include <drm/drmP.h>
#include <drm/drm.h>
#include "gma_drm.h"
#include "psb_drv.h"
#include "psb_reg.h"
#include "psb_intel_reg.h"
#include "intel_bios.h"
#include "cdv_device.h"

#define VGA_SR_INDEX		0x3c4
#define VGA_SR_DATA		0x3c5

static void cdv_disable_vga(struct drm_device *dev)
{
	u8 sr1;
	u32 vga_reg;

	vga_reg = VGACNTRL;

	outb(1, VGA_SR_INDEX);
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	udelay(300);

	REG_WRITE(vga_reg, VGA_DISP_DISABLE);
	REG_READ(vga_reg);
}

static int cdv_output_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;

	drm_mode_create_scaling_mode_property(dev);

	cdv_disable_vga(dev);

	cdv_intel_crt_init(dev, &dev_priv->mode_dev);
	cdv_intel_lvds_init(dev, &dev_priv->mode_dev);

	/* These bits indicate HDMI not SDVO on CDV, but we don't yet support
	   the HDMI interface */
	if (REG_READ(SDVOB) & SDVO_DETECTED)
		cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
	if (REG_READ(SDVOC) & SDVO_DETECTED)
		cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
	return 0;
}

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE

/*
 *	Poulsbo Backlight Interfaces
 */

#define BLC_PWM_PRECISION_FACTOR 100	/* 10000000 */
#define BLC_PWM_FREQ_CALC_CONSTANT 32
#define MHz 1000000

#define PSB_BLC_PWM_PRECISION_FACTOR    10
#define PSB_BLC_MAX_PWM_REG_FREQ        0xFFFE
#define PSB_BLC_MIN_PWM_REG_FREQ        0x2

#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
#define PSB_BACKLIGHT_PWM_CTL_SHIFT	(16)

static int cdv_brightness;
static struct backlight_device *cdv_backlight_device;

static int cdv_get_brightness(struct backlight_device *bd)
{
	/* return locally cached var instead of HW read (due to DPST etc.) */
	/* FIXME: ideally return actual value in case firmware fiddled with
	   it */
	return cdv_brightness;
}


static int cdv_backlight_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	unsigned long core_clock;
	/* u32 bl_max_freq; */
	/* unsigned long value; */
	u16 bl_max_freq;
	uint32_t value;
	uint32_t blc_pwm_precision_factor;

	/* get bl_max_freq and pol from dev_priv*/
	if (!dev_priv->lvds_bl) {
		dev_err(dev->dev, "Has no valid LVDS backlight info\n");
		return -ENOENT;
	}
	bl_max_freq = dev_priv->lvds_bl->freq;
	blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;

	core_clock = dev_priv->core_freq;

	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
	value *= blc_pwm_precision_factor;
	value /= bl_max_freq;
	value /= blc_pwm_precision_factor;

	if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
		 value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
				return -ERANGE;
	else {
		/* FIXME */
	}
	return 0;
}

static int cdv_set_brightness(struct backlight_device *bd)
{
	int level = bd->props.brightness;

	/* Percentage 1-100% being valid */
	if (level < 1)
		level = 1;

	/*cdv_intel_lvds_set_brightness(dev, level); FIXME */
	cdv_brightness = level;
	return 0;
}

static const struct backlight_ops cdv_ops = {
	.get_brightness = cdv_get_brightness,
	.update_status  = cdv_set_brightness,
};

static int cdv_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	int ret;
	struct backlight_properties props;

	memset(&props, 0, sizeof(struct backlight_properties));
	props.max_brightness = 100;
	props.type = BACKLIGHT_PLATFORM;

	cdv_backlight_device = backlight_device_register("psb-bl",
					NULL, (void *)dev, &cdv_ops, &props);
	if (IS_ERR(cdv_backlight_device))
		return PTR_ERR(cdv_backlight_device);

	ret = cdv_backlight_setup(dev);
	if (ret < 0) {
		backlight_device_unregister(cdv_backlight_device);
		cdv_backlight_device = NULL;
		return ret;
	}
	cdv_backlight_device->props.brightness = 100;
	cdv_backlight_device->props.max_brightness = 100;
	backlight_update_status(cdv_backlight_device);
	dev_priv->backlight_device = cdv_backlight_device;
	return 0;
}

#endif

/*
 *	Provide the Cedarview specific chip logic and low level methods
 *	for power management
 *
 *	FIXME: we need to implement the apm/ospm base management bits
 *	for this and the MID devices.
 */

static inline u32 CDV_MSG_READ32(uint port, uint offset)
{
	int mcr = (0x10<<24) | (port << 16) | (offset << 8);
	uint32_t ret_val = 0;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	pci_write_config_dword(pci_root, 0xD0, mcr);
	pci_read_config_dword(pci_root, 0xD4, &ret_val);
	pci_dev_put(pci_root);
	return ret_val;
}

static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
{
	int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	pci_write_config_dword(pci_root, 0xD4, value);
	pci_write_config_dword(pci_root, 0xD0, mcr);
	pci_dev_put(pci_root);
}

#define PSB_PM_SSC			0x20
#define PSB_PM_SSS			0x30
#define PSB_PWRGT_GFX_ON		0x02
#define PSB_PWRGT_GFX_OFF		0x01
#define PSB_PWRGT_GFX_D0		0x00
#define PSB_PWRGT_GFX_D3		0x03

static void cdv_init_pm(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt;
	int i;

	dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
							PSB_APMBA) & 0xFFFF;
	dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
							PSB_OSPMBA) & 0xFFFF;

	/* Power status */
	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);

	/* Enable the GPU */
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_ON;
	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	/* Wait for the GPU power */
	for (i = 0; i < 5; i++) {
		u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
			return;
		udelay(10);
	}
	dev_err(dev->dev, "GPU: power management timed out.\n");
}

static void cdv_errata(struct drm_device *dev)
{
	/* Disable bonus launch.
	 *	CPU and GPU competes for memory and display misses updates and flickers.
	 *	Worst with dual core, dual displays.
	 *
	 *	Fixes were done to Win 7 gfx driver to disable a feature called Bonus
	 *	Launch to work around the issue, by degrading performance.
	 */
	 CDV_MSG_WRITE32(3, 0x30, 0x08027108);
}

/**
 *	cdv_save_display_registers	-	save registers lost on suspend
 *	@dev: our DRM device
 *
 *	Save the state we need in order to be able to restore the interface
 *	upon resume from suspend
 */
static int cdv_save_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct drm_connector *connector;

	dev_info(dev->dev, "Saving GPU registers.\n");

	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);

	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);

	regs->cdv.saveDSPARB = REG_READ(DSPARB);
	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);

	regs->cdv.saveADPA = REG_READ(ADPA);

	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
	regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
	regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
	regs->cdv.saveLVDS = REG_READ(LVDS);

	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);

	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);

	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);

	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);

	return 0;
}

/**
 *	cdv_restore_display_registers	-	restore lost register state
 *	@dev: our DRM device
 *
 *	Restore register state that was lost during suspend and resume.
 *
 *	FIXME: review
 */
static int cdv_restore_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct drm_connector *connector;
	u32 temp;

	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);

	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);

	/* BIOS does below anyway */
	REG_WRITE(DPIO_CFG, 0);
	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);

	temp = REG_READ(DPLL_A);
	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
		REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
		REG_READ(DPLL_A);
	}

	temp = REG_READ(DPLL_B);
	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
		REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
		REG_READ(DPLL_B);
	}

	udelay(500);

	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);

	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
	REG_WRITE(ADPA, regs->cdv.saveADPA);

	REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
	REG_WRITE(LVDS, regs->cdv.saveLVDS);
	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
	REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);

	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);

	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);

	/* Fix arbitration bug */
	cdv_errata(dev);

	drm_mode_config_reset(dev);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);

	/* Resume the modeset for every activated CRTC */
	drm_helper_resume_force_mode(dev);
	return 0;
}

static int cdv_power_down(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt, pwr_mask, pwr_sts;
	int tries = 5;

	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_OFF;
	pwr_mask = PSB_PWRGT_GFX_MASK;

	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	while (tries--) {
		pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
			return 0;
		udelay(10);
	}
	return 0;
}

static int cdv_power_up(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_cnt, pwr_mask, pwr_sts;
	int tries = 5;

	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	pwr_cnt |= PSB_PWRGT_GFX_ON;
	pwr_mask = PSB_PWRGT_GFX_MASK;

	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);

	while (tries--) {
		pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
		if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
			return 0;
		udelay(10);
	}
	return 0;
}

/* FIXME ? - shared with Poulsbo */
static void cdv_get_core_freq(struct drm_device *dev)
{
	uint32_t clock;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	struct drm_psb_private *dev_priv = dev->dev_private;

	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	pci_read_config_dword(pci_root, 0xD4, &clock);
	pci_dev_put(pci_root);

	switch (clock & 0x07) {
	case 0:
		dev_priv->core_freq = 100;
		break;
	case 1:
		dev_priv->core_freq = 133;
		break;
	case 2:
		dev_priv->core_freq = 150;
		break;
	case 3:
		dev_priv->core_freq = 178;
		break;
	case 4:
		dev_priv->core_freq = 200;
		break;
	case 5:
	case 6:
	case 7:
		dev_priv->core_freq = 266;
	default:
		dev_priv->core_freq = 0;
	}
}

static int cdv_chip_setup(struct drm_device *dev)
{
	cdv_get_core_freq(dev);
	gma_intel_opregion_init(dev);
	psb_intel_init_bios(dev);
	REG_WRITE(PORT_HOTPLUG_EN, 0);
	REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
	return 0;
}

/* CDV is much like Poulsbo but has MID like SGX offsets and PM */

const struct psb_ops cdv_chip_ops = {
	.name = "GMA3600/3650",
	.accel_2d = 0,
	.pipes = 2,
	.crtcs = 2,
	.hdmi_mask = (1 << 0) | (1 << 1),
	.lvds_mask = (1 << 1),
	.sgx_offset = MRST_SGX_OFFSET,
	.chip_setup = cdv_chip_setup,
	.errata = cdv_errata,

	.crtc_helper = &cdv_intel_helper_funcs,
	.crtc_funcs = &cdv_intel_crtc_funcs,

	.output_init = cdv_output_init,

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	.backlight_init = cdv_backlight_init,
#endif

	.init_pm = cdv_init_pm,
	.save_regs = cdv_save_display_registers,
	.restore_regs = cdv_restore_display_registers,
	.power_down = cdv_power_down,
	.power_up = cdv_power_up,
};
Commit	Line	Data
6a227d5f AC	1	/**************************************************************************
	2	* Copyright (c) 2011, Intel Corporation.
	3	* All Rights Reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*
	18	**************************************************************************/
	19
	20	#include <linux/backlight.h>
	21	#include <drm/drmP.h>
	22	#include <drm/drm.h>
838fa588	23	#include "gma_drm.h"
6a227d5f AC	24	#include "psb_drv.h"
	25	#include "psb_reg.h"
	26	#include "psb_intel_reg.h"
	27	#include "intel_bios.h"
	28	#include "cdv_device.h"
	29
	30	#define VGA_SR_INDEX 0x3c4
	31	#define VGA_SR_DATA 0x3c5
	32
6a227d5f AC	33	static void cdv_disable_vga(struct drm_device *dev)
	34	{
	35	u8 sr1;
	36	u32 vga_reg;
	37
	38	vga_reg = VGACNTRL;
	39
	40	outb(1, VGA_SR_INDEX);
	41	sr1 = inb(VGA_SR_DATA);
	42	outb(sr1 \| 1<<5, VGA_SR_DATA);
	43	udelay(300);
	44
	45	REG_WRITE(vga_reg, VGA_DISP_DISABLE);
	46	REG_READ(vga_reg);
	47	}
	48
	49	static int cdv_output_init(struct drm_device *dev)
	50	{
	51	struct drm_psb_private *dev_priv = dev->dev_private;
d235e64a AC	52
	53	drm_mode_create_scaling_mode_property(dev);
	54
6a227d5f AC	55	cdv_disable_vga(dev);
	56
	57	cdv_intel_crt_init(dev, &dev_priv->mode_dev);
	58	cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
	59
	60	/* These bits indicate HDMI not SDVO on CDV, but we don't yet support
	61	the HDMI interface */
	62	if (REG_READ(SDVOB) & SDVO_DETECTED)
	63	cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
	64	if (REG_READ(SDVOC) & SDVO_DETECTED)
	65	cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
	66	return 0;
	67	}
	68
	69	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	70
	71	/*
	72	* Poulsbo Backlight Interfaces
	73	*/
	74
	75	#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
	76	#define BLC_PWM_FREQ_CALC_CONSTANT 32
	77	#define MHz 1000000
	78
	79	#define PSB_BLC_PWM_PRECISION_FACTOR 10
	80	#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
	81	#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
	82
	83	#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
	84	#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
	85
	86	static int cdv_brightness;
	87	static struct backlight_device *cdv_backlight_device;
	88
	89	static int cdv_get_brightness(struct backlight_device *bd)
	90	{
	91	/* return locally cached var instead of HW read (due to DPST etc.) */
	92	/* FIXME: ideally return actual value in case firmware fiddled with
	93	it */
	94	return cdv_brightness;
	95	}
	96
	97
	98	static int cdv_backlight_setup(struct drm_device *dev)
	99	{
	100	struct drm_psb_private *dev_priv = dev->dev_private;
	101	unsigned long core_clock;
	102	/* u32 bl_max_freq; */
	103	/* unsigned long value; */
	104	u16 bl_max_freq;
	105	uint32_t value;
	106	uint32_t blc_pwm_precision_factor;
	107
	108	/* get bl_max_freq and pol from dev_priv*/
	109	if (!dev_priv->lvds_bl) {
	110	dev_err(dev->dev, "Has no valid LVDS backlight info\n");
	111	return -ENOENT;
	112	}
	113	bl_max_freq = dev_priv->lvds_bl->freq;
	114	blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
	115
	116	core_clock = dev_priv->core_freq;
	117
	118	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
119	value *= blc_pwm_precision_factor;
120	value /= bl_max_freq;
121	value /= blc_pwm_precision_factor;
122
123	if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ \|\|
124	value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
125	return -ERANGE;
126	else {
127	/* FIXME */
128	}
129	return 0;
130	}
131
132	static int cdv_set_brightness(struct backlight_device *bd)
133	{
134	int level = bd->props.brightness;
135
136	/* Percentage 1-100% being valid */
137	if (level < 1)
138	level = 1;
139
140	/cdv_intel_lvds_set_brightness(dev, level); FIXME /
141	cdv_brightness = level;
142	return 0;
143	}
144
145	static const struct backlight_ops cdv_ops = {
146	.get_brightness = cdv_get_brightness,
147	.update_status = cdv_set_brightness,
148	};
149
150	static int cdv_backlight_init(struct drm_device *dev)
151	{
152	struct drm_psb_private *dev_priv = dev->dev_private;
153	int ret;
154	struct backlight_properties props;
155
156	memset(&props, 0, sizeof(struct backlight_properties));
157	props.max_brightness = 100;
158	props.type = BACKLIGHT_PLATFORM;
159
160	cdv_backlight_device = backlight_device_register("psb-bl",
161	NULL, (void *)dev, &cdv_ops, &props);
162	if (IS_ERR(cdv_backlight_device))
163	return PTR_ERR(cdv_backlight_device);
164
165	ret = cdv_backlight_setup(dev);
166	if (ret < 0) {
167	backlight_device_unregister(cdv_backlight_device);
168	cdv_backlight_device = NULL;
169	return ret;
170	}
171	cdv_backlight_device->props.brightness = 100;
172	cdv_backlight_device->props.max_brightness = 100;
173	backlight_update_status(cdv_backlight_device);
174	dev_priv->backlight_device = cdv_backlight_device;
175	return 0;
176	}
177
178	#endif
179
180	/*
181	* Provide the Cedarview specific chip logic and low level methods
182	* for power management
183	*
184	* FIXME: we need to implement the apm/ospm base management bits
185	* for this and the MID devices.
186	*/
187
188	static inline u32 CDV_MSG_READ32(uint port, uint offset)
189	{
190	int mcr = (0x10<<24) \| (port << 16) \| (offset << 8);
191	uint32_t ret_val = 0;
192	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
193	pci_write_config_dword(pci_root, 0xD0, mcr);
194	pci_read_config_dword(pci_root, 0xD4, &ret_val);
195	pci_dev_put(pci_root);
196	return ret_val;
197	}
198
199	static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
200	{
201	int mcr = (0x11<<24) \| (port << 16) \| (offset << 8) \| 0xF0;
202	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
203	pci_write_config_dword(pci_root, 0xD4, value);
204	pci_write_config_dword(pci_root, 0xD0, mcr);
205	pci_dev_put(pci_root);
206	}
207
6a227d5f AC	208	#define PSB_PM_SSC 0x20
6a227d5f AC	209	#define PSB_PM_SSS 0x30
09016a11 AC	210	#define PSB_PWRGT_GFX_ON 0x02
	211	#define PSB_PWRGT_GFX_OFF 0x01
	212	#define PSB_PWRGT_GFX_D0 0x00
	213	#define PSB_PWRGT_GFX_D3 0x03
6a227d5f AC	214
	215	static void cdv_init_pm(struct drm_device *dev)
	216	{
	217	struct drm_psb_private *dev_priv = dev->dev_private;
	218	u32 pwr_cnt;
	219	int i;
	220
	221	dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
	222	PSB_APMBA) & 0xFFFF;
	223	dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
	224	PSB_OSPMBA) & 0xFFFF;
	225
09016a11	226	/* Power status */
6a227d5f	227	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
6a227d5f	228
09016a11 AC	229	/* Enable the GPU */
	230	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	231	pwr_cnt \|= PSB_PWRGT_GFX_ON;
6a227d5f	232	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
09016a11 AC	233
09016a11 AC	234	/* Wait for the GPU power */
6a227d5f AC	235	for (i = 0; i < 5; i++) {
	236	u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	237	if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
09016a11	238	return;
6a227d5f AC	239	udelay(10);
6a227d5f AC	240	}
09016a11	241	dev_err(dev->dev, "GPU: power management timed out.\n");
6a227d5f AC	242	}
6a227d5f AC	243
d235e64a AC	244	static void cdv_errata(struct drm_device *dev)
	245	{
	246	/* Disable bonus launch.
	247	* CPU and GPU competes for memory and display misses updates and flickers.
	248	* Worst with dual core, dual displays.
	249	*
	250	* Fixes were done to Win 7 gfx driver to disable a feature called Bonus
	251	* Launch to work around the issue, by degrading performance.
	252	*/
	253	CDV_MSG_WRITE32(3, 0x30, 0x08027108);
	254	}
	255
6a227d5f AC	256	/**
	257	* cdv_save_display_registers - save registers lost on suspend
	258	* @dev: our DRM device
	259	*
	260	* Save the state we need in order to be able to restore the interface
	261	* upon resume from suspend
6a227d5f AC	262	*/
	263	static int cdv_save_display_registers(struct drm_device *dev)
	264	{
09016a11 AC	265	struct drm_psb_private *dev_priv = dev->dev_private;
	266	struct psb_save_area *regs = &dev_priv->regs;
	267	struct drm_connector *connector;
	268
	269	dev_info(dev->dev, "Saving GPU registers.\n");
	270
	271	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
	272
	273	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
	274	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
	275
	276	regs->cdv.saveDSPARB = REG_READ(DSPARB);
	277	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
	278	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
	279	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
	280	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
	281	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
	282	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
	283
	284	regs->cdv.saveADPA = REG_READ(ADPA);
	285
	286	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
	287	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
	288	regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
	289	regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
	290	regs->cdv.saveLVDS = REG_READ(LVDS);
	291
	292	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
	293
	294	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
	295	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
	296	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
	297
	298	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
	299
	300	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
	301	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
	302
	303	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
	304	connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
	305
6a227d5f AC	306	return 0;
	307	}
	308
	309	/**
	310	* cdv_restore_display_registers - restore lost register state
	311	* @dev: our DRM device
	312	*
	313	* Restore register state that was lost during suspend and resume.
	314	*
	315	* FIXME: review
	316	*/
	317	static int cdv_restore_display_registers(struct drm_device *dev)
	318	{
09016a11 AC	319	struct drm_psb_private *dev_priv = dev->dev_private;
	320	struct psb_save_area *regs = &dev_priv->regs;
	321	struct drm_connector *connector;
	322	u32 temp;
	323
	324	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
	325
	326	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
	327	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
	328
	329	/* BIOS does below anyway */
	330	REG_WRITE(DPIO_CFG, 0);
	331	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 \| DPIO_CMN_RESET_N);
	332
	333	temp = REG_READ(DPLL_A);
	334	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
	335	REG_WRITE(DPLL_A, temp \| DPLL_SYNCLOCK_ENABLE);
	336	REG_READ(DPLL_A);
	337	}
	338
	339	temp = REG_READ(DPLL_B);
	340	if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
	341	REG_WRITE(DPLL_B, temp \| DPLL_SYNCLOCK_ENABLE);
	342	REG_READ(DPLL_B);
	343	}
	344
	345	udelay(500);
	346
	347	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
	348	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
	349	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
	350	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
	351	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
	352	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
	353
	354	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
	355	REG_WRITE(ADPA, regs->cdv.saveADPA);
	356
	357	REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
	358	REG_WRITE(LVDS, regs->cdv.saveLVDS);
	359	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
	360	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
	361	REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
	362	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
	363	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
	364	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
	365	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
	366
	367	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
	368
	369	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
	370	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
	371
	372	/* Fix arbitration bug */
d235e64a	373	cdv_errata(dev);
09016a11 AC	374
	375	drm_mode_config_reset(dev);
	376
	377	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
	378	connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
	379
	380	/* Resume the modeset for every activated CRTC */
	381	drm_helper_resume_force_mode(dev);
6a227d5f AC	382	return 0;
	383	}
	384
	385	static int cdv_power_down(struct drm_device *dev)
	386	{
09016a11 AC	387	struct drm_psb_private *dev_priv = dev->dev_private;
	388	u32 pwr_cnt, pwr_mask, pwr_sts;
	389	int tries = 5;
	390
	391	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	392	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	393	pwr_cnt \|= PSB_PWRGT_GFX_OFF;
	394	pwr_mask = PSB_PWRGT_GFX_MASK;
	395
	396	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
	397
	398	while (tries--) {
	399	pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	400	if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
	401	return 0;
	402	udelay(10);
	403	}
6a227d5f AC	404	return 0;
	405	}
	406
	407	static int cdv_power_up(struct drm_device *dev)
	408	{
09016a11 AC	409	struct drm_psb_private *dev_priv = dev->dev_private;
	410	u32 pwr_cnt, pwr_mask, pwr_sts;
	411	int tries = 5;
	412
	413	pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
	414	pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
	415	pwr_cnt \|= PSB_PWRGT_GFX_ON;
	416	pwr_mask = PSB_PWRGT_GFX_MASK;
	417
	418	outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
	419
	420	while (tries--) {
	421	pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
	422	if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
	423	return 0;
	424	udelay(10);
	425	}
6a227d5f AC	426	return 0;
	427	}
	428
	429	/* FIXME ? - shared with Poulsbo */
	430	static void cdv_get_core_freq(struct drm_device *dev)
	431	{
	432	uint32_t clock;
	433	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	434	struct drm_psb_private *dev_priv = dev->dev_private;
	435
	436	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	437	pci_read_config_dword(pci_root, 0xD4, &clock);
	438	pci_dev_put(pci_root);
	439
	440	switch (clock & 0x07) {
	441	case 0:
	442	dev_priv->core_freq = 100;
	443	break;
	444	case 1:
	445	dev_priv->core_freq = 133;
	446	break;
	447	case 2:
	448	dev_priv->core_freq = 150;
	449	break;
	450	case 3:
	451	dev_priv->core_freq = 178;
	452	break;
	453	case 4:
	454	dev_priv->core_freq = 200;
	455	break;
	456	case 5:
	457	case 6:
	458	case 7:
	459	dev_priv->core_freq = 266;
	460	default:
	461	dev_priv->core_freq = 0;
	462	}
	463	}
	464
	465	static int cdv_chip_setup(struct drm_device *dev)
	466	{
	467	cdv_get_core_freq(dev);
	468	gma_intel_opregion_init(dev);
	469	psb_intel_init_bios(dev);
055bf38d AC	470	REG_WRITE(PORT_HOTPLUG_EN, 0);
055bf38d AC	471	REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
6a227d5f AC	472	return 0;
	473	}
	474
	475	/* CDV is much like Poulsbo but has MID like SGX offsets and PM */
	476
	477	const struct psb_ops cdv_chip_ops = {
b6195aab	478	.name = "GMA3600/3650",
6a227d5f AC	479	.accel_2d = 0,
6a227d5f AC	480	.pipes = 2,
b6195aab	481	.crtcs = 2,
d235e64a AC	482	.hdmi_mask = (1 << 0) \| (1 << 1),
d235e64a AC	483	.lvds_mask = (1 << 1),
6a227d5f AC	484	.sgx_offset = MRST_SGX_OFFSET,
6a227d5f AC	485	.chip_setup = cdv_chip_setup,
d235e64a	486	.errata = cdv_errata,
6a227d5f AC	487
	488	.crtc_helper = &cdv_intel_helper_funcs,
	489	.crtc_funcs = &cdv_intel_crtc_funcs,
	490
	491	.output_init = cdv_output_init,
	492
	493	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	494	.backlight_init = cdv_backlight_init,
	495	#endif
	496
	497	.init_pm = cdv_init_pm,
	498	.save_regs = cdv_save_display_registers,
	499	.restore_regs = cdv_restore_display_registers,
	500	.power_down = cdv_power_down,
	501	.power_up = cdv_power_up,
	502	};